Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor in which an external electrode does not readily peel away from the multilayer body. Provided is a multilayer ceramic capacitor 1 provided with a multilayer body 2 that has an inner layer part 11 in which a plurality of dielectric layers 14 and internal electrodes 15 are alternately stacked and outer layer parts 12 which are disposed on one side and on the other side of the inner layer part 11 in the stacking direction, and external electrodes 3, 4 that are provided on at least one surface of the multilayer body 2 in a direction intersecting the stacking direction and include main-surface-side folded-back sections 3A, 4A covering a portion of the outer layer parts 12, wherein a mixture layer 12A of a dielectric and a metal is provided in covered sections 16 of the outer layer parts 12 that are covered by the main-surface-side folded-back sections 3A, 4A.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Recently, reducing the impedance of electronic circuit lines has become increasingly important, particularly in mobile device products. To achieve this, three-terminal multilayer ceramic capacitors are widely used for decoupling purposes. A three-terminal multilayer ceramic capacitor includes a laminate having an inner layer portion formed by alternating multiple dielectric layers each having an end-exposed internal electrode exposed at an end surface and a side-surface internal electrode exposed at a side surface, and outer layer portions disposed on one side and the other side of the inner layer portion in the stacking direction. The laminate also includes external electrodes disposed on the end surfaces and connected to the end-exposed internal electrodes, and external electrodes disposed on the side surfaces and connected to the side-surface internal electrodes (see Patent Document 1). Miniaturization of a three-terminal multilayer ceramic capacitor enables further reduction in impedance at high frequencies. The reduction in impedance due to miniaturization is due to a reduction in the equivalent series inductance (ESL) of the multilayer ceramic capacitor.

[0003] Japanese Patent Application Laid-Open No. 2013-201417

[0004] However, as multilayer ceramic capacitors become smaller, the contact area between the external electrodes and the internal electrodes decreases. This reduces the adhesive strength of the external electrodes to the laminate, making the external electrodes more likely to peel off from the laminate. An object of the present invention is to provide a multilayer ceramic capacitor in which the external electrodes are less likely to peel off from the laminate.

[0005] In order to solve the above problems, the present invention provides a multilayer ceramic capacitor comprising: a laminate having inner layer portions in which dielectric layers and internal electrodes are alternately stacked multiple times; and outer layer portions arranged on one side and the other side in the stacking direction of the inner layer portions; and an external electrode provided on at least one surface of the laminate in a direction intersecting the stacking direction and including a main surface side folded portion covering a part of the outer layer portions, wherein a mixed layer of dielectric and metal is provided in a covering portion of the outer layer portions that is covered by the main surface side folded portion.

[0006] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which external electrodes are less likely to peel off from the laminate.

[0007] 1 is a schematic perspective view of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view of an embodiment of the multilayer ceramic capacitor 1 cut in the II-II direction in FIG. 1. FIG. 3 is a cross-sectional view of an embodiment of the multilayer ceramic capacitor 1 cut in the III-III direction in FIG. 1. FIG. 4 is a cross-sectional view taken along an end face exposed internal electrode 15A of the multilayer ceramic capacitor 1. FIG. 5 is a cross-sectional view taken along a side face exposed internal electrode 15B of the multilayer ceramic capacitor 1. FIG. 6 is a cross-sectional view of an embodiment of the multilayer ceramic capacitor 1 cut in the IV-IV direction at the outer layer portion 12 in FIG. 1. FIG. 7 is a diagram illustrating a manufacturing process of a laminate 2 in a manufacturing method of the multilayer ceramic capacitor 1. FIG. 8 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1.

[0008] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present invention will be described. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along the II-II direction in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along the III-III direction in Fig. 1.

[0009] (Multilayer ceramic capacitor 1) The multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 with a three-terminal structure, including a laminate 2, end surface external electrodes 3 provided on both end surfaces C of the laminate 2 in the length direction L, and side surface external electrodes 4 provided on both side surfaces B of the laminate 2 in the width direction W. The laminate 2 includes an inner layer portion 11 in which dielectric layers 14 and internal electrodes 15 are stacked, and an outer layer portion 12.

[0010] In this specification, the term indicating the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 as the stacking direction T. The direction that intersects with the stacking direction T and in which the pair of end face external electrodes 3 are provided is referred to as the length direction L. The direction that intersects with both the length direction L and the stacking direction T is referred to as the width direction W. In the embodiment, the stacking direction T, the length direction L, and the width direction W are perpendicular to one another.

[0011] In the following description, of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides of the stacking direction T will be referred to as main surfaces A, a pair of outer surfaces extending in the stacking direction T and on both sides of the width direction W will be referred to as side surfaces B, and a pair of outer surfaces extending in the stacking direction T and on both sides of the length direction L will be referred to as end surfaces C.

[0012] As shown in FIG. 2 or 3, the multilayer ceramic capacitor 1 has a length L dimension LC of 0.10 mm or more and 0.70 mm or less, a width W dimension WC of 0.05 mm or more and 0.40 mm or less, and a stacking direction T dimension TC of 0.10 mm or more and 0.55 mm or less.

[0013] Furthermore, the capacitance of the multilayer ceramic capacitor 1 is 0.022 μF to 10 μF, and preferably 1.0 μF to 2.2 μF. The ESL of the multilayer ceramic capacitor 1 is preferably 65 pH or less at 100 MHz, and preferably 50 pH or less at 1 GHz.

[0014] The capacitance of the multilayer ceramic capacitor 1 can be measured using an LCR meter (manufactured by Agilent Technologies, model number: E4980A) under conditions of 1 kHz and 0.5 Vrms. The ESL of the multilayer ceramic capacitor 1 can be calculated from the measured impedance value at a predetermined frequency using a network analyzer (manufactured by Agilent Technologies, model number: E5080A).

[0015] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate 2 intersect, and a ridge is a portion where two surfaces of the laminate 2 intersect.

[0016] The dimensions of the laminate 2 are as shown in Figure 2 or Figure 3: the length direction L dimension LL is 0.09 mm or more and 0.69 mm or less, the width direction W dimension WL is 0.04 mm or more and 0.39 mm or less, and the stacking direction T dimension TL is 0.09 mm or more and 0.54 mm or less.

[0017] (Inner Layer Portion 11) The inner layer portion 11 is formed by laminating a plurality of dielectric layers 14 and internal electrodes 15 along the lamination direction T.

[0018] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material. The ceramic material is mainly composed of a ceramic material containing at least one of Ca, Zr, and Ti. Specifically, for example, a ceramic material containing Ca and Zr and having the general formula ABO ３ The ceramic material having such a perovskite structure is mainly composed of a ceramic material having a perovskite structure represented by the formula: BaTiO ３ (barium titanate) and CaZrO ３ However, the ceramic material forming the dielectric layer 14 may contain all of Ca, Zr, and Ti as its main components.

[0019] (Internal Electrode 15) The internal electrode 15 is preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.

[0020] The internal electrode 15 has a plurality of end-exposed internal electrodes 15A and a plurality of side-exposed internal electrodes 15B arranged alternately. When there is no need to particularly distinguish between the end-exposed internal electrodes 15A and the side-exposed internal electrodes 15B, they will be collectively referred to as the internal electrode 15.

[0021] Fig. 4 is a cross-sectional view taken along an end surface exposed internal electrode 15A of the multilayer ceramic capacitor 1. Fig. 5 is a cross-sectional view taken along a side surface exposed internal electrode 15B of the multilayer ceramic capacitor 1.

[0022] (End-face-exposed internal electrode 15A) As shown in Fig. 4, the end-face-exposed internal electrode 15A extends between both end faces C in the length direction L of the laminate 2 and is spaced a certain distance from both side faces B in the width direction W. The end-face-exposed internal electrode 15A has an end-face facing portion 15Aa located in the center between both end faces C and end-face drawn portions 15Ab extending from the end-face facing portion 15Aa to both end faces C. In the embodiment, the end-face facing portion 15Aa and the end-face drawn portions 15Ab have the same dimension in the width direction W, and the end-face-exposed internal electrode 15A, including the end-face facing portion 15Aa and the end-face drawn portions 15Ab, has a substantially rectangular shape as a whole. The end-face drawn portions 15Ab extending from the end-face facing portion 15Aa to both end faces C extend to both end faces C on both sides, are exposed at the end faces C of the laminate 2, and are connected to the end-face external electrodes 3 provided on both end faces C in the length direction L of the laminate 2.

[0023] 5, the side surface exposed internal electrode 15B has a side surface facing portion 15Ba located in the center between both side surfaces B, and side surface drawn-out portions 15Bb extending from the side surface facing portion 15Ba to both side surfaces B. The side surface facing portion 15Ba is a substantially rectangular shape slightly smaller than the laminate 2, and is spaced a certain distance from both side surfaces B in the width direction W.

[0024] The dimension of the side lead portion 15Bb in the length direction L is smaller than the dimension of the side facing portion 15Ba in the length direction L. The side lead portion 15Bb extends to both side surfaces B, is exposed at the side surfaces B of the laminate 2, and is connected to the side surface external electrodes 4 provided on both side surfaces of the laminate 2 in the width direction W.

[0025] The end surface facing portion 15Aa and the side surface facing portion 15Ba face each other to form a capacitor portion.

[0026] The dielectric layer 14 is formed by alternately stacking multiple layers of a first dielectric layer 14A on which an end-face-exposed internal electrode 15A exposed on the end face C is arranged, and a second dielectric layer 14B on which a side-face-exposed internal electrode 15B exposed on a portion of the side face B is arranged.

[0027] 2 and 3 , the outer layer portion 12 is a dielectric layer disposed on the main surface A side of the inner layer portion 11. The outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11.

[0028] (End Face External Electrodes 3) End face external electrodes 3 are arranged on both end faces C of the laminate 2. To the end face external electrodes 3, end face drawn portions 15Ab of the end face exposed internal electrodes 15A are connected.

[0029] (Side Surface External Electrodes 4) Side surface external electrodes 4 are arranged on both side surfaces B of the laminate 2. To the side surface external electrodes 4, side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B are connected.

[0030] The end surface external electrode 3 and the side surface external electrode 4 include a base electrode layer 31 and a plating layer 32 disposed on the base electrode layer 31. The plating layer 32 includes a Ni (nickel) plating layer 321 disposed on the base electrode layer 31, and a Sn (tin) plating layer 322 disposed on the Ni plating layer 321. However, without being limited thereto, the end surface external electrode 3 and the side surface external electrode 4 may have a structure in which, for example, the base electrode layer 31 is made of Ni, and a Cu plating layer, a Ni plating layer, and a Sn plating layer are disposed thereon in this order.

[0031] (Folded portion) The end surface external electrode 3 includes an end surface electrode main surface side folded portion 3A that covers not only the end surface C but also part of the main surface A, and an end surface electrode side surface side folded portion 3B that covers part of the side surface B. The side surface external electrode 4 includes a side surface electrode main surface side folded portion 4A that covers not only the side surface B but also part of the main surface A. When it is not necessary to distinguish between the end surface electrode main surface side folded portion 3A and the side surface electrode main surface side folded portion 4A, they will be collectively referred to as a folded portion.

[0032] 6 is a cross-sectional view of an embodiment of the multilayer ceramic capacitor 1 taken in the IV-IV direction at the outer layer portion 12 in FIG. 1. In the outer layer portion 12, an end surface side mixed layer 12Aa is provided in the end surface side covering portion 16a that is covered by the end surface electrode main surface side folded portion 3A of the end surface external electrode 3. In the outer layer portion 12, a side surface side mixed layer 12Ab is provided in the side surface side covering portion 16b that is covered by the side surface electrode main surface side folded portion 4A of the side surface external electrode 4.

[0033] In this specification, when it is not necessary to distinguish between end surface-side covering portion 16a and side surface-side covering portion 16b, they will be collectively referred to as covering portion 16. When it is not necessary to distinguish between end surface-side mixed layer 12Aa and side surface-side mixed layer 12Ab, they will be collectively referred to as mixed layer 12A.

[0034] The mixed layer 12A includes a dielectric and a metal. In this embodiment, the dielectric is the same as the dielectric constituting the outer layer portion 12, and the metal is preferably the same as the metal, such as Cu or Ni, constituting the external electrode.

[0035] The ratio of the metal to the dielectric in the mixed layer 12A is 0.001 mol % or more and 50 mol % or less. The ratio of the metal to the dielectric in the mixed layer 12A can be measured, for example, by polishing a cross section of the mixed layer 12A to expose it, performing a composition analysis using EDX (Energy Dispersive X-ray Spectroscopy), and calculating the ratio from the quantitative calculation values ​​of each composition obtained from the analysis results.

[0036] In a cross section passing through the stacking direction T and the length direction L at the center of the width direction W shown in Fig. 2 and in a cross section passing through the stacking direction T and the width direction W at the center of the length direction L shown in Fig. 3, the area occupied by the mixed layer 12A is 1% to 99% of the total area of ​​the coating portion in the outer layer portion 12. Note that Figs. 2 and 3 illustrate the case where the area occupied by the mixed layer 12A is about 50% of the total area of ​​the coating portion in the outer layer portion 12.

[0037] In this specification, the "covered portion in the outer layer portion 12" refers to the end surface side covered portion 16a, which is the region of the outer layer portion 12 covered by the end surface electrode main surface side folded portion 3A of the end surface external electrode 3, and the side surface side covered portion 16b, which is the region covered by the side surface electrode main surface side folded portion 4A of the side surface external electrode 4, shown in Figures 2 and 3.

[0038] 2 , the dimension L1 in the length direction L, which is perpendicular to the end face C where the end face external electrode 3 is connected to the end face exposed internal electrode 15A, on the main surface A of the end face electrode main surface side folded portion 3A of the end face external electrode 3, is 0.05 mm or more and 0.20 mm or less. The dimension W1 in the width direction W, which is perpendicular to the side face B where the side face external electrode 4 is connected to the side face exposed internal electrode 15B, on the main surface A of the side face electrode main surface side folded portion 4A of the side face external electrode 4, is 0.05 mm or more and 0.20 mm or less.

[0039] (Method of Manufacturing Multilayer Ceramic Capacitor 1) Next, a method of manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described. Fig. 7 is a diagram illustrating the steps of manufacturing the laminate 2 in the method of manufacturing the multilayer ceramic capacitor 1. Fig. 8 is a flowchart illustrating the method of manufacturing the multilayer ceramic capacitor 1.

[0040] (Inner layer sheet forming step S1) An end-face exposed internal electrode 15A is formed with a conductive paste on a ceramic green sheet 14A' that will become the first dielectric layer 14A. Similarly, a side-face exposed internal electrode 15B is formed with a conductive paste on a ceramic green sheet 14B' that will become the second dielectric layer 14B.

[0041] The ceramic green sheets 14A' and 14B' are strip-shaped sheets formed by forming a ceramic slurry containing ceramic powder, a binder, and a solvent onto a carrier film using a die coater, gravure coater, microgravure coater, or the like.

[0042] The end-face exposed internal electrodes 15A and side-face exposed internal electrodes 15B are formed by printing, such as screen printing, gravure printing, or letterpress printing.

[0043] (Outer layer portion sheet forming process S2) A small amount of metal powder is printed, for example by inkjet printing, on the portion 16a' that will become the end face side covering portion 16a and the portion 16b' that will become the side face side covering portion 16b of the ceramic green sheet that will become the outer layer portion 12, to prepare the ceramic green sheet 12' for the outer layer portion before lamination.

[0044] (Stacking step S3) Ceramic green sheets 14A' to become the first dielectric layers 14A on which the end-face exposed internal electrodes 15A are arranged and ceramic green sheets 14B' to become the second dielectric layers 14B on which the side-face exposed internal electrodes 15B are arranged are stacked alternately.

[0045] Next, the ceramic green sheets 12' for outer layers are arranged on top and bottom with the surfaces printed with the metal powder facing outwards, and are thermocompression bonded to form a mother block.

[0046] (Mother Block Cutting Step S4) Next, the mother block is cut and divided in the length direction L and width direction W to manufacture a plurality of rectangular parallelepiped laminates 2.

[0047] (External electrode forming process S5) Next, side surface external electrodes 4 are formed on both side surfaces B of the laminate 2. The side surface drawn portions 15Bb of the side surface exposed internal electrodes 15B are connected to the side surface external electrodes 4. The side surface external electrodes 4 are formed so as to cover not only the side surfaces B but also part of the side surface B side of the main surface A. At this time, the portions 16b' on the laminate 2 where the metal powder is printed are covered by the side surface electrode main surface side folded portions 4A of the side surface external electrodes 4, becoming the side surface side covering portions 16b.

[0048] Then, end surface external electrodes 3 are formed on both end surfaces C of the laminate 2. End surface drawn portions 15Ab of the end surface exposed internal electrodes 15A are connected to the end surface external electrodes 3. The end surface external electrodes 3 are formed so as to cover not only the end surfaces C but also parts of the end surface C sides of the main surfaces A and side surfaces B. At this time, the portions 16a' on the laminate 2 where the metal powder is printed are covered by the end surface electrode main surface side folded portions 3A of the end surface external electrodes 3 to form end surface side covering portions 16a.

[0049] (Firing step S6) The laminate is then heated in a nitrogen atmosphere for a predetermined time at the set firing temperature. When the end surface external electrodes 3 and the side surface external electrodes 4 are baked onto the laminate 2, the metal powder printed on the end surface side covering portions 16a and the side surface side covering portions 16b in the outer layer ceramic green sheets 12' diffuses into the outer layer portions 12. As a result, end surface side mixed layers 12Aa are formed in the end surface side covering portions 16a, and side surface side mixed layers 12Ab are formed in the side surface side covering portions 16b, thereby producing the multilayer ceramic capacitor 1 of the embodiment.

[0050] Effect of the embodiment According to the multilayer ceramic capacitor 1 of the present embodiment, an end surface side mixed layer 12Aa is formed in the end surface side covering portion of the outer layer portion 12 that is covered by the end surface electrode main surface side folded portion 3A of the end surface external electrode 3. A side surface side mixed layer 12Ab is formed in the side surface side covering portion of the outer layer portion 12 that is covered by the side surface electrode main surface side folded portion 4A of the side surface external electrode 4.

[0051] In this way, when the end surface side mixed layer 12Aa, which is a mixture of dielectric and metal, is formed, the metal contained in the end surface side mixed layer 12Aa bonds with the metal contained in the end surface external electrode 3, improving the adhesion strength between the end surface electrode main surface side folded portion 3A of the end surface external electrode 3 and the outer layer portion 12, thereby improving the strength resistance of the multilayer ceramic capacitor 1 against external stress.

[0052] When the side-side mixed layer 12Ab, which is a mixture of a dielectric and a metal, is formed, the metal contained in the side-side mixed layer 12Ab bonds with the metal contained in the side-side external electrode 4, improving the adhesion strength between the side-electrode main surface-side folded portion 4A of the side-side external electrode 4 and the outer layer portion 12, thereby improving the strength resistance of the multilayer ceramic capacitor 1 against external stress.

[0053] This makes it possible to provide a multilayer ceramic capacitor 1 in which the end surface external electrodes 3 and the side surface external electrodes 4 are less likely to peel off from the laminate 2 .

[0054] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0055] For example, in the embodiment, an example has been described in which the three-terminal multilayer ceramic capacitor 1 has the mixed layer 12A provided in four locations on each of the two main surfaces A, namely, on the two end surface external electrodes 3 sides and the two side surface external electrodes 4 sides, for a total of eight locations. However, the present invention is not limited to this, and the mixed layer 12A may be provided on only one of the two main surfaces A sides. Furthermore, the mixed layer 12A may be provided in some, but not all, of the four locations on the two end surface external electrodes 3 sides and the two side surface external electrodes 4 sides.

[0056] Furthermore, a two-terminal multilayer ceramic capacitor may be used instead of the three-terminal multilayer ceramic capacitor 1. That is, a multilayer ceramic capacitor may include the end surface external electrodes 3, the end surface electrode main surface side folded portions 3A, and the end surface side mixed layers 12Aa, but not the side surface external electrodes 4, the side surface electrode main surface side folded portions 4A, and the side surface side mixed layers 12Ab.

[0057] In addition, in the embodiment, the mixed layer 12A is described as being provided in the outer layer portion 12, but the mixed layer may also be formed in the portion of the inner layer portion 11 that is covered by the folded portion of the dielectric layer 14.

[0058] The present invention also includes the following: <1> A multilayer ceramic capacitor comprising: a laminate having inner layer portions in which a plurality of dielectric layers and internal electrodes are alternately laminated, and outer layer portions arranged on one side and the other side in a lamination direction of the inner layer portions; and an external electrode provided on at least one surface of the laminate in a direction intersecting the lamination direction and including a main surface side folded portion covering a part of the outer layer portions, wherein a mixed layer of a dielectric and a metal is provided in a covering portion of the outer layer portion that is covered by the main surface side folded portion.

[0059] <2> The multilayer ceramic capacitor according to <1>, wherein the laminate is a three-terminal type having, when a direction intersecting the stacking direction is defined as a length direction and a direction intersecting the stacking direction and the length direction is defined as a width direction, the internal electrodes include end-face-exposed internal electrodes exposed on end faces that are one and the other of the length direction faces of the laminate, and side-face-exposed internal electrodes exposed on side faces that are one and the other of the width direction faces of the laminate, and the external electrodes include end-face external electrodes provided on the end faces of the laminate and connected to the end-face-exposed internal electrodes, and side-face external electrodes provided on the side faces of the laminate and connected to the side-face-exposed internal electrodes.

[0060] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the ratio of the metal to the dielectric in the mixed layer is 0.001 mol % or more and 50 mol % or less.

[0061] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein, in the laminate, a direction intersecting the stacking direction is defined as a length direction, and a direction intersecting the stacking direction and the length direction is defined as a width direction, an area occupied by the mixed layer in each of a cross section passing through the stacking direction and the length direction, a cross section passing through the stacking direction and the width direction, and a cross section passing through the length direction and the width direction is 1% or more and 99% or less of an entire area of ​​the covering portion.

[0062] <5> When the direction intersecting the stacking direction of the laminate is defined as the length direction and the direction intersecting the stacking direction and the length direction is defined as the width direction of the laminate, the internal electrodes comprise end surface exposed internal electrodes exposed on end surfaces that are one and the other surfaces in the length direction of the laminate, and side surface exposed internal electrodes exposed on side surfaces that are one and the other surfaces in the width direction of the laminate, the external electrodes are a three-terminal type that comprises end surface external electrodes that are provided on the end surfaces of the laminate and connected to the end surface exposed internal electrodes, and side surface external electrodes that are provided on the side surfaces of the laminate and connected to the side surface exposed internal electrodes, the main surface side folded portion comprises an end surface electrode main surface side folded portion included in the end surface external electrode, and a side surface electrode main surface side folded portion included in the side surface external electrode, the covering portion comprises an end surface side covering portion covered by the end surface electrode main surface side folded portion, and a side surface side covering portion covered by the side surface electrode main surface side folded portion, The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the mixed layer is provided on both the end face side covering portion and the side face side covering portion.

[0063] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein the main surface side folded portion of the external electrode has a dimension of 0.05 to 0.20 mm in a direction perpendicular to a surface on the main surface where the external electrode is connected to the internal electrode.

[0064] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the dimension in the lamination direction is 0.55 mm or less.

[0065] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein a dimension in a length direction intersecting the stacking direction is 0.10 mm or more and 0.70 mm or less, and a dimension in a width direction intersecting the stacking direction and the length direction is 0.05 mm or more and 0.40 mm or less.

[0066] <9> The multilayer ceramic capacitor according to any one of <1> to <8>, wherein the external electrodes contain Ni.

[0067] <10> The multilayer ceramic capacitor according to any one of <1> to <9>, having a capacitance of 0.022 μF or more and 10 μF or less.

[0068] <11> The multilayer ceramic capacitor according to any one of <1> to <10>, wherein the equivalent series inductance is 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

[0069] 1 Multilayer ceramic capacitor 3 End surface external electrode 3A End surface electrode main surface side folded portion 3B End surface electrode side surface side folded portion 4 Side surface external electrode 4A Side surface electrode main surface side folded portion 11 Inner layer portion 12 Outer layer portion 12A Mixed layer 12Aa End surface side mixed layer 12Ab Side side mixed layer 14 Dielectric layer 14A First dielectric layer 14B Second dielectric layer 15 Internal electrode 15A End face exposed internal electrode 15Aa End face opposing part 15Ab End face drawn part 15B Side surface exposed internal electrode 15Ba Side face opposing part 15Bb Side face drawn part 16 Covering part 16a End face side covering part 16b Side face side covering part

Claims

1. A multilayer ceramic capacitor comprising: a laminate having inner layer portions in which dielectric layers and internal electrodes are alternately laminated in a plurality of layers, and outer layer portions arranged on one side and the other side of a lamination direction of the inner layer portions; and an external electrode provided on at least one surface of the laminate in a direction intersecting the lamination direction and including a main surface side folded portion covering a part of the outer layer portions, wherein a mixed layer of dielectric and metal is provided in a covering portion of the outer layer portions that is covered by the main surface side folded portion.

2. The multilayer ceramic capacitor according to claim 1, wherein, when a direction in said laminate that intersects with the stacking direction is defined as a length direction and a direction that intersects with the stacking direction and the length direction is defined as a width direction, said internal electrodes comprise end face exposed internal electrodes exposed on end faces that are one and the other of the faces in the length direction of said laminate, and side face exposed internal electrodes exposed on side faces that are one and the other of the faces in the width direction of said laminate, and said external electrodes are of a three-terminal type comprising end face external electrodes provided on said end faces of said laminate and connected to said end face exposed internal electrodes, and side face external electrodes provided on said side faces of said laminate and connected to said side face exposed internal electrodes.

3. The multilayer ceramic capacitor according to claim 1, wherein the ratio of the metal to the dielectric in the mixed layer is 0.001 mol % or more and 50 mol % or less.

4. A multilayer ceramic capacitor as claimed in any one of claims 1 to 3, wherein, in the laminate, a direction intersecting the stacking direction is defined as a length direction, and a direction intersecting the stacking direction and the length direction is defined as a width direction, and an area occupied by the mixed layer in each of a cross section passing through the stacking direction and the length direction, a cross section passing through the stacking direction and the width direction, and a cross section passing through the length direction and the width direction is 1% or more and 99% or less of a total area of ​​the covering portion.

5. In the laminate, when a direction intersecting the stacking direction is defined as a length direction and a direction intersecting the stacking direction and the length direction is defined as a width direction, the internal electrodes comprise end face exposed internal electrodes exposed at end faces, which are one and the other faces in the length direction of the laminate, and side face exposed internal electrodes exposed at side faces, which are one and the other faces in the width direction of the laminate, the external electrodes are a three-terminal type comprising end face external electrodes provided on the end faces of the laminate and connected to the end face exposed internal electrodes, and side face external electrodes provided on the side faces of the laminate and connected to the side face exposed internal electrodes, the main surface side folded portion comprises an end face electrode main surface side folded portion included in the end face external electrode and a side face electrode main surface side folded portion included in the side face external electrode, the covering portion comprises an end face side covering portion covered by the end face electrode main surface side folded portion, and a side face side covering portion covered by the side face electrode main surface side folded portion, The multilayer ceramic capacitor according to claim 1 , wherein the mixed layer is provided on both the end surface side covering portion and the side surface side covering portion.

6. A multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the main surface side folded portion of the external electrode has a dimension on the main surface perpendicular to the surface where the external electrode is connected to the internal electrode of 0.05 mm or more and 0.20 mm or less.

7. The multilayer ceramic capacitor according to claim 1, wherein the dimension in the lamination direction is 0.10 mm or more and 0.55 mm or less.

8. A multilayer ceramic capacitor according to any one of claims 1 to 7, wherein the dimension in a length direction intersecting the lamination direction is 0.10 mm or more and 0.70 mm or less, and the dimension in a width direction intersecting the lamination direction and the length direction is 0.05 mm or more and 0.40 mm or less.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein the external electrodes contain Ni.

10. The multilayer ceramic capacitor according to any one of claims 1 to 9, having a capacitance of 0.022 μF or more and 10 μF or less.

11. The multilayer ceramic capacitor according to any one of claims 1 to 10, having an equivalent series inductance of 65 pH or less at 100 MHz and 50 pH or less at 1 GHz.

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