Integrated circuit

Abstract

Provided is an integrated circuit capable of maintaining high reliability even under a severe environment such as a high radiation environment.　An integrated circuit 1 comprises: a master latch 3 for receiving an input of an input signal, and outputting a signal at a timing based on a master clock signal; and N (N is an odd number of 3 or more) slave latches 4 for receiving an input of the signal outputted from the master latch 3, and outputting an output signal at a timing based on a slave clock signal. The master latch 3 outputs, to the slave latches 4, a signal of a value determined on the basis of the input signal and the input of the outputted signal. Each of the slave latches 4 is configured to output an output signal of a value determined on the basis of a majority decision result of signals respectively outputted from the N slave latches 4 or a majority decision result of signals, which the slave latches 4 have respectively received, as inputs, from the master latch 3.

Description

Integrated Circuits

[0001] The present invention relates to an integrated circuit comprising a master latch and a slave latch.

[0002] Various flip-flop circuits synchronized by a clock signal and equipped with a master latch and a slave latch have been proposed as semiconductor integrated circuits (see, for example, Patent Document 1). Integrated circuits such as flip-flop circuits are used as circuits that meet various requirements, such as FPGAs (Field Programmable Gate Arrays), programmable devices, radiation-hardened integrated circuits, and highly reliable integrated circuits. Furthermore, integrated circuits are increasingly being used in technical fields that require high reliability, such as the nuclear reactor field, nuclear fusion field, space field, high-energy accelerators, and highly reliable systems.

[0003] For example, while the total dose tolerance of a general integrated circuit available on the market is about 50 krad, a specially designed radiation-hardened integrated circuit is designed with high reliability of 300 krad to 2 Mrad.

[0004] JP 2017-022500 A

[0005] However, even for radiation-hardened integrated circuits with high reliability of 300 krad to 2 Mrad, the lifespan of the integrated circuit is only 10 to 20 hours, for example, at a decommissioning site. The reason for this is that when radiation is incident on an integrated circuit, the transistors deteriorate, increasing the propagation delay of each gate on the integrated circuit. Furthermore, if radiation continues to be incident, the drive capability of the transistors in the integrated circuit will decrease significantly, and they will become inoperable and reach the end of their lifespan.

[0006] Therefore, for example, in various devices used in high radiation environments, there is a demand for the development of integrated circuits that have a long life and high reliability.

[0007] The present invention has been made in view of the above circumstances, and has as its object to provide an integrated circuit that is more reliable even in a high level radiation environment.

[0008] In order to solve the above problem, the integrated circuit disclosed in the present application comprises a master latch that receives an input signal and outputs a signal at a timing based on a master clock signal, and N (N is an integer greater than or equal to 3) slave latches that receive an input signal output from the master latch and output an output signal at a timing based on a slave clock signal, wherein the master latch outputs a signal to the slave latches whose value is determined based on the input signal and the output signal, and each of the slave latches outputs an output signal whose value is determined based on the result of a majority vote of the signals output from the N slave latches or the result of a majority vote of the signals each of the slave latches receives as input from the master latch.

[0009] The integrated circuit is also characterized in that it comprises M master latches (M is an integer equal to or greater than 3), and each master latch outputs to the slave latch a signal whose value is determined based on the majority vote result of the signals output from the M master latches or the majority vote result of the input signals received by each master latch.

[0010] In the integrated circuit, when the slave latch performs majority voting and signals of different values ​​are included, the cycle of the slave clock signal is lengthened.

[0011] In addition, in the integrated circuit, when the master latch performs majority voting and signals of different values ​​are included, the cycle of the master clock signal is lengthened.

[0012] In the integrated circuit, the master clock signal and the slave clock signal are clock signals branched from an original clock signal and having different phases.

[0013] In the integrated circuit, the slave clock signal is a first-phase slave clock signal and a second-phase slave clock signal which are branched from an original clock signal and have different phases, and the slave latch outputs an output signal having a value determined based on a majority decision result of the signals input from the master latch to each of the slave latches at a timing based on the first-phase slave clock signal, and outputs an output signal having a value determined based on a majority decision result of the signals output from the slave latches at a timing based on the second-phase slave clock signal.

[0014] The integrated circuit is also characterized in that it comprises a detection circuit for detecting a deterioration state, and when the detection circuit detects deterioration, it lengthens the period of the slave clock signal.

[0015] In the integrated circuit, the detection circuit detects the deterioration state based on the discharge time of the electric charge stored in a diode formed by joining a p-type semiconductor and an n-type semiconductor.

[0016] In the integrated circuit, the detection circuit is a ring oscillator in which an odd number of NOT circuits are connected in series in a ring to form an oscillation circuit.

[0017] The integrated circuit disclosed herein includes a master latch controlled by a master clock signal and a slave latch controlled by a slave clock signal, and at least the slave latch includes a majority circuit, thereby providing excellent effects such as improved reliability.

[0018] FIG. 1 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 2 is a circuit diagram showing an example of a majority circuit included in the integrated circuit disclosed herein. FIG. 3 is a circuit diagram showing an example of a clock circuit included in the integrated circuit disclosed herein. FIG. 4 is a circuit diagram showing an example of a circuit in which the integrated circuit disclosed herein is configured as an FPGA. FIG. 5 is a timing chart showing an example of signal processing in the integrated circuit disclosed herein. FIG. 6 is a timing chart showing an example of signal processing in the integrated circuit disclosed herein. FIG. 7 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 8 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 9 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 10 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 11 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 12 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 13 is a circuit diagram showing an example of an integrated circuit disclosed herein. FIG. 14 is a timing chart showing an example of signal processing in the integrated circuit disclosed herein. 1 is a circuit diagram showing an experimental circuit using the integrated circuit disclosed in the present application.

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0020] <Application Examples> The integrated circuit disclosed herein is used, for example, as a field programmable gate array (FPGA), a programmable device, a radiation-hardened integrated circuit, a high-reliability integrated circuit, and the like. The integrated circuit disclosed herein is also used in technical fields such as nuclear reactors and nuclear fusion, specifically in technical fields such as systems used in decommissioning work, robots, nuclear reactor control systems, nuclear reactor monitoring systems, and nuclear reactor maintenance robots. The integrated circuit disclosed herein is also used in technical fields such as space and high-energy accelerators, specifically in technical fields such as rockets, satellites, and radiation-hardened measurement systems. Furthermore, the integrated circuit disclosed herein is used in systems requiring high reliability, such as embedded systems for automobiles and aircraft. An integrated circuit 1 disclosed herein, illustrated by way of example in the drawings, will be described below with reference to the drawings.

[0021] <Circuit Configuration Example> Fig. 1 is a circuit diagram showing an example of an integrated circuit 1 disclosed herein. The integrated circuit 1 disclosed herein can be realized as an N-multiplexed (N is an integer equal to or greater than 3) flip-flop circuit 2, and Fig. 1 shows an example of an equivalent circuit of the integrated circuit 1 disclosed herein realized as a tripled flip-flop. Note that N is defined as an integer equal to or greater than 3, but is preferably an odd number when considering implementation as a majority circuit. For convenience of explanation, when describing the tripled flip-flop circuit 2 individually, the circuits will be described below as a first flip-flop 2A, a second flip-flop 2B, and a third flip-flop 2C from the top of the figure.

[0022] The first flip-flop 2A receives a first input signal D1 and outputs a first output signal Q1. The second flip-flop 2B receives a second input signal D2 and outputs a second output signal Q2. The third flip-flop 2C receives a third input signal D3 and outputs a third output signal Q3.

[0023] Each flip-flop circuit 2 includes a master latch 3 and a slave latch 4 .

[0024] Each master latch 3 is a circuit that receives an input signal (first input signal D1, second input signal D2, third input signal D3) and outputs an intermediate signal to a slave latch 4 at a timing based on a master clock signal with a predetermined cycle. In FIG. 1 , the intermediate signal output from the master latch 3 of the first flip-flop 2A to the corresponding slave latch 4 is indicated as a first intermediate signal IQ1. The intermediate signal of the second flip-flop 2B is indicated as a second intermediate signal IQ2, and the intermediate signal of the third flip-flop 2C is indicated as a third intermediate signal IQ3. Furthermore, in FIG. 1 , the master clock signals input to the first flip-flop 2A, second flip-flop 2B, and third flip-flop 2C are indicated as a first master clock signal MCLK1, second master clock signal MCLK2, and third master clock signal MCLK3.

[0025] Each slave latch 4 is a circuit that receives the intermediate signal output from the master latch 3 and outputs an output signal (first output signal Q1, second output signal Q2, third output signal Q3) at a timing based on a slave clock signal with a set predetermined cycle. In Fig. 1, the slave clock signals input to the first flip-flop 2A, second flip-flop 2B, and third flip-flop 2C are shown as a first slave clock signal SCLK1, a second slave clock signal SCLK2, and a third slave clock signal SCLK3.

[0026] Each master latch 3 includes a master majority circuit 30, an input inverter 31, a master inverter 32, a master input gate 33, and a master feedback gate .

[0027] The master majority circuit 30 receives input signals input to each master latch 3 and intermediate signals output from each master latch 3. Each master majority circuit 30 then outputs an intermediate signal whose value is determined by the majority decision result of the input input signals or the majority decision result of the input intermediate signals. The master majority circuit 30 of each master latch 3 receives as input signals a first input signal D1, a second input signal D2, and a third input signal D3. The master majority circuit 30 of each master latch 3 also receives as input intermediate signals (first intermediate signal IQ1, second intermediate signal IQ2, and third intermediate signal IQ3) output from each master latch 3. A specific configuration example of the master majority circuit 30 will be described later.

[0028] The input inverter 31 receives input signals (first input signal D1, second input signal D2, third input signal D3), inverts the signal values, and outputs the input signals to the master majority circuit 30 of each master latch 3 via the master input gate 33.

[0029] The master inverter 32 receives the intermediate signals (first intermediate signal IQ1, second intermediate signal IQ2, third intermediate signal IQ3) output from the master majority circuit 30, inverts the signal values, and outputs the intermediate signals to the master majority circuit 30 of each master latch 3 via the master feedback gate 34.

[0030] The master input gate 33 receives the input signal output from the input inverter 31 and outputs the input signal to the master majority circuit 30. The master input gate 33 outputs the input signal at a timing based on two systems of master clock signals that are periodically input. The two systems of master clock signals are input to the master input gate 33 alternately at a predetermined cycle. In FIG. 1 , the master clock signal input to the first flip-flop 2A is shown as a first master clock signal MCLK1. The master clock signals input to the second flip-flop 2B and the third flip-flop 2C are shown as a second master clock signal MCLK2 and a third master clock signal MCLK3, respectively.

[0031] The master feedback gate 34 receives the intermediate signal output from the master inverter 32 and outputs the input intermediate signal to the master majority circuit 30. The master feedback gate 34 outputs the intermediate signal at a timing based on two systems of master clock signals that are periodically input. The two systems of master clock signals are input alternately to the master feedback gate 34 at a predetermined cycle.

[0032] The master input gate 33 and the master feedback gate 34 receive the same master clock signal with the same period and phase, and alternately output signals at timing based on the master clock signal.

[0033] For example, the master majority circuit 30 of the first flip-flop 2A receives a first input signal D1 from the input inverter 31 of the first flip-flop 2A at a timing based on the first master clock signal MCLK1. The master majority circuit 30 of the first flip-flop 2A also receives a second input signal D2 and a third input signal D3 from the input inverters 31 of the second flip-flop 2B and the third flip-flop 2C at a timing based on the second master clock signal MCLK2 and the third master clock signal MCLK3, respectively. The master majority circuit 30 of the first flip-flop 2A outputs a first intermediate signal IQ1 based on the majority decision result of the first input signal D1, the second input signal D2, and the third input signal D3.

[0034] For example, the master majority circuit 30 of the first flip-flop 2A receives the first intermediate signal IQ1 output from the master latch 3 of the first flip-flop 2A from the master inverter 32 of the first flip-flop 2A at a timing based on the first master clock signal MCLK1. The master majority circuit 30 of the first flip-flop 2A also receives the second intermediate signal IQ2 and the third intermediate signal IQ3 from the master inverters 32 of the second flip-flop 2B and the third flip-flop 2C at a timing based on the second master clock signal MCLK2 and the third master clock signal MCLK3, respectively. The master majority circuit 30 of the first flip-flop 2A outputs the first intermediate signal IQ1 based on the majority decision result of the first intermediate signal IQ1, the second intermediate signal IQ2, and the third intermediate signal IQ3.

[0035] As described above, the master majority circuit 30 of the first flip-flop 2A alternately receives the input signal and the intermediate signal at a timing based on the master clock signal, and outputs the intermediate signal. Substantially the same processing is performed in the second flip-flop 2B and the third flip-flop 2C.

[0036] Each slave latch 4 includes a slave majority circuit 40 , an output inverter 41 , a slave inverter 42 , a slave input gate 43 , and a slave feedback gate 44 .

[0037] The slave majority circuit 40 receives as input intermediate signals input to each slave latch 4 and output signals output from each slave latch 4. Each slave majority circuit 40 then outputs an output signal whose value is determined by the majority decision result of the input intermediate signals or the majority decision result of the input output signals. The slave majority circuit 40 of each slave latch 4 receives as input the first intermediate signal IQ1, the second intermediate signal IQ2, and the third intermediate signal IQ3 as intermediate signals. The slave majority circuit 40 of each slave latch 4 also receives as input the output signals output from each slave latch 4. A specific configuration example of the slave majority circuit 40 will be described later.

[0038] The output inverter 41 receives the output signal output from the slave majority circuit 40, inverts the signal value, and outputs the output signal.

[0039] The slave inverter 42 receives the output signal output from the slave majority circuit 40 , inverts the signal value, and outputs the output signal to the slave majority circuit 40 of each slave latch 4 via the slave feedback gate 44 .

[0040] The slave input gate 43 receives an intermediate signal output from the corresponding master latch 3 and outputs the input intermediate signal to the slave majority circuit 40. The slave input gate 43 outputs the intermediate signal at a timing based on two slave clock signals that are periodically input. The two slave clock signals are input to the slave input gate 43 alternately at a predetermined cycle. In FIG. 1 , the slave clock signal input to the first flip-flop 2A is shown as a first slave clock signal SCLK1. The slave clock signals input to the second flip-flop 2B and the third flip-flop 2C are shown as a second slave clock signal SCLK2 and a third slave clock signal SCLK3, respectively.

[0041] The slave feedback gate 44 receives the output signal output from the slave inverter 42 and outputs the input output signal to the slave majority circuit 40. The slave feedback gate 44 outputs the output signal at a timing based on two systems of slave clock signals that are periodically input. The two systems of slave clock signals are input alternately to the slave feedback gate 44 at a predetermined cycle.

[0042] The slave input gate 43 and the slave feedback gate 44 receive the same slave clock signal with the same period and phase, and alternately output signals at timing based on the slave clock signal.

[0043] For example, the slave majority circuit 40 of the first flip-flop 2A receives a first intermediate signal IQ1 from the master latch 3 of the first flip-flop 2A at a timing based on the first slave clock signal SCLK1. The slave majority circuit 40 of the first flip-flop 2A also receives a second intermediate signal IQ2 and a third intermediate signal IQ3 from the master latch 3 of the second flip-flop 2B and the third flip-flop 2C at a timing based on the second slave clock signal SCLK2 and the third slave clock signal SCLK3, respectively. The slave majority circuit 40 of the first flip-flop 2A outputs a first output signal Q1 based on the majority decision result of the first intermediate signal IQ1, the second intermediate signal IQ2, and the third intermediate signal IQ3.

[0044] For example, the slave majority circuit 40 of the first flip-flop 2A receives the first intermediate signal IQ1 output from the first flip-flop 2A from the slave inverter 42 of the slave latch 4 of the first flip-flop 2A at a timing based on the first slave clock signal SCLK1. The slave majority circuit 40 of the first flip-flop 2A also receives the second output signal Q2 and the third output signal Q3 from the slave inverters 42 of the second flip-flop 2B and the third flip-flop 2C at a timing based on the second slave clock signal SCLK2 and the third slave clock signal SCLK3, respectively. The slave majority circuit 40 of the first flip-flop 2A outputs the first output signal Q1 based on the majority decision result of the first output signal Q1, the second output signal Q2, and the third output signal Q3.

[0045] As described above, the slave majority circuit 40 of the first flip-flop 2A alternately receives the intermediate signal and the output signal at a timing based on the slave clock signal, and outputs the output signal. Substantially the same processing is performed in the second flip-flop 2B and the third flip-flop 2C.

[0046] FIG. 2 is a circuit diagram showing an example of a majority circuit included in the integrated circuit 1 disclosed herein. The integrated circuit 1 disclosed herein includes a master majority circuit 30 and a slave majority circuit 40. The master majority circuit 30 and the slave majority circuit 40 can be configured using substantially similar circuits. FIG. 2 shows an example of an equivalent circuit of a majority circuit applied as the triplexed master majority circuit 30 and slave majority circuit 40. In FIG. 2, VDD is connected to the positive side of the power supply, and VSS is connected to the negative side. In FIG. 2, A, B, and C indicate input signals. In the case of the master majority circuit 30, A, B, and C indicate the first input signal D1 (or the first intermediate signal IQ1), the second input signal D2 (or the second intermediate signal IQ2), and the third input signal D3 (or the third intermediate signal IQ3). In the case of the slave majority circuit 40, A, B, and C represent the first intermediate signal IQ1 (or the first output signal Q1), the second intermediate signal IQ2 (or the second output signal Q2), and the third intermediate signal IQ3 (or the third output signal Q3). Furthermore, in Fig. 2, Y represents an output signal, and in the case of the master majority circuit 30, Y represents an intermediate signal, and in the case of the slave majority circuit 40, Y represents an output signal.

[0047] The majority circuit has two transistors, such as P-channel MOSFETs, connected in series to the positive side of a signal line that outputs signal Y. The majority circuit also has two transistors, such as N-channel MOSFETs, connected in series to the negative side of the signal line that outputs signal Y. The majority circuit has three sets of signals that are input to the gate terminals of the two series-connected transistors, and therefore three sets of signal lines connected to the electrode sides are connected in series to the positive and negative sides.

[0048] 2, when two or three of the input signals A, B, and C have a value of High "1," the negative side becomes conductive, and the value of the output signal Y becomes Low "0." Furthermore, when two or three of the input signals A, B, and C have a value of Low "0," the positive side becomes conductive, and the value of the output signal Y becomes High "1."

[0049] That is, the majority circuit shown in FIG. 2 is a circuit that inverts the value that is the majority of the input signal values ​​and outputs it.

[0050] FIG. 3 is a circuit diagram showing an example of a clock circuit 5 included in the integrated circuit 1 disclosed herein. The integrated circuit 1 disclosed herein operates at a timing defined by a two-phase clock signal. FIG. 3 shows an example of an equivalent circuit of the clock circuit 5 that outputs a clock signal input to the circuit illustrated in FIG. 1. The integrated circuit 1 can be implemented so that a clock circuit 5 is provided for each flip-flop circuit 2 to which the clock signal is output. FIG. 3 shows an example in which a clock circuit 5 is provided corresponding to a first flip-flop 2A, a second flip-flop 2B, and a third flip-flop 2C. For convenience of explanation, when multiple clock circuits 5 are individually described below, they will be described as a first clock circuit 5A, a second clock circuit 5B, and a third clock circuit 5C, respectively, corresponding to each flip-flop circuit 2.

[0051] The first clock circuit 5A receives a first clock signal CLK1 as an input from an oscillator circuit (not shown) as an original clock signal. The first clock circuit 5A then outputs a first master clock signal MCLK1 and a first slave clock signal SCLK1. Similarly, the second clock circuit 5B receives a second clock signal and outputs a second master clock signal MCLK2 and a second slave clock signal SCLK2. The third clock circuit 5C receives a third clock signal and outputs a third master clock signal MCLK3 and a third slave clock signal SCLK3.

[0052] Each clock circuit 5 includes various circuits such as a delay 50, a selector 51, a master gate 52, and a slave gate 53. A clock signal input to the clock circuit 5 is branched to the delay 50, the master gate 52, and the slave gate 53. The clock signal input to the delay 50 is output to the selector 51, and is then output from the selector 51 to the master gate 52 and the slave gate 53.

[0053] The delay 50 is a circuit in which multiple buffers are connected in series and delays the input clock signal. FIG. 3 illustrates a circuit in which n buffers, denoted by 1 to n (n is a natural number greater than or equal to 2), are connected in series. The selector 51 selects a signal to accept as input from the signals output from each buffer and determines the delay time provided by the delay 50. If the master majority circuit 30 or the slave majority circuit 40 does not receive all of the input signals with the same value, the selector 51 operates to lengthen the delay time. The operation of the selector 51 is controlled by a program signal output from the control circuit 6, which controls the operation of the integrated circuit 1. The operation of the selector 51 is controlled for each clock circuit 5, so that a first program signal PRG1 is input to the first clock circuit 5A. Similarly, a second program signal PRG2 is input to the second clock circuit 5B, and a third program signal PRG3 is input to the third clock circuit 5C. Therefore, when the master latch 3 or the slave latch 4 performs a majority vote and the input signals contain signals with different values, the integrated circuit 1 of the present disclosure controls to increase the clock skew and / or lengthen the period of the external clock signal (resulting in lengthening the periods of the master clock signal and the slave clock signal). For example, in the clock circuit 5 illustrated in FIG. 3 , the selector 51 initially selects the signal output from buffer 0 of the delay 50 (set to maximize the skew between the master clock signal MCLK and the slave clock signal SCLK). Then, if there is a margin for clock skew (or whenever the majority vote is split), the selector 51 is configured to switch between the signal output from buffer 1 and the signal output from buffer 2, and so on up to buffer n-1. Additionally, the integrated circuit 1 is configured to be able to switch the frequency of the external clock signal. This allows the integrated circuit 1 to optimally select the frequency of the external clock signal and, therefore, the clock skew margin.

[0054] The master gate 52 is configured using an AND gate. The master gate 52 receives as input the clock signal and the signal output from the selector 51, functions as an AND gate, and outputs a master clock signal. The master gate 52 included in the first clock circuit 5A receives as input the first clock signal CLK1 and the signal from the selector 51, and outputs a first master clock signal MCLK1 to the master latch 3 of the first flip-flop 2A. Similarly, the second clock circuit 5B and the third clock circuit 5C output a second master clock signal MCLK2 based on the second clock signal and a third master clock signal MCLK3 based on the third clock signal to their corresponding master latches 3, respectively.

[0055] The slave gate 53 is composed of two NOT gates and an AND gate. The slave gate 53 receives inputs of a clock signal inverted by the NOT gate and a signal output from the selector 51 and inverted by the NOT gate, functions as an AND gate, and outputs a slave clock signal. By inverting the input signal, the master clock signal and the slave clock signal have different phases. The slave gate 53 included in the first clock circuit 5A receives inputs of the first clock signal CLK1 and the signal from the selector 51, and outputs a first slave clock signal SCLK1 to the slave latch 4 of the first flip-flop 2A. Similarly, the second clock circuit 5B and the third clock circuit 5C output a second slave clock signal SCLK2 based on the second clock signal and a third slave clock signal SCLK3 based on the third clock signal to their corresponding slave latches 4, respectively.

[0056] 4 is a circuit diagram showing an example of a circuit in which the integrated circuit 1 disclosed herein is configured as an FPGA. Fig. 4 shows an example in which the integrated circuits 1 disclosed herein are connected in cascade to form a triplexed shift register circuit, realizing an FPGA circuit. By configuring the integrated circuit 1 disclosed herein as a multiplexed shift register circuit, it is possible to dramatically improve resistance to permanent faults.

[0057] 1 to 4, the integrated circuit 1 disclosed herein uses a majority circuit to configure the flip-flop circuit 2. This allows the integrated circuit 1 disclosed herein to maintain reliability even if, for example, some transistors experience an abnormality such as a failure or delay, causing a decrease in drive capability.

[0058] <Signal Processing Example> Next, an example of signal processing by the integrated circuit 1 disclosed herein will be described. FIG. 5 is a timing chart showing an example of signal processing by the integrated circuit 1 disclosed herein. FIG. 5 shows an example of a timing chart for the integrated circuit 1 disclosed herein illustrated in FIG. 1. FIG. 5 shows the time variation of each signal with the horizontal axis representing time and the vertical axis representing the value of each signal. The signals shown on the horizontal axis are, from top to bottom, the first to third master clock signals MCLK1, MCLK2, and MCLK3, the first to third slave clock signals SCLK1, SCLK2, and SCLK3, the first to third input signals D1, D2, and D3, the first to third intermediate signals IQ1, IQ2, and IQ3, and the first to third output signals Q1, Q2, and Q3.

[0059] As illustrated in FIG. 5 , the integrated circuit 1 disclosed herein operates as a flip-flop circuit 2 in which a two-phase clock signal is input to the master latch 3 and the slave latch 4, and the signal value is inverted at the timing defined by the clock signal.

[0060] Fig. 6 is a timing chart showing an example of signal processing by the integrated circuit 1 disclosed herein. Fig. 6 illustrates a timing chart in the case where a delay occurs in the clock signal in Fig. 5. In Fig. 6, the interval shown by the vertical dashed dotted line is the clock skew margin, which is determined by the distance from the slowest master clock signal (third master clock signal MCLK3) to the fastest slave clock signal (second slave clock signal SCLK2).

[0061] For example, if delays occur in some transistors due to the effects of radiation, errors may occur in signal processing. The integrated circuit 1 disclosed herein operates normally as a whole if a majority of the master latches 3 (three or more odd numbers) operate normally. The same applies to the slave latches 4. Therefore, reliability can be improved by ensuring a sufficient clock skew margin, as illustrated in FIG. 6 . Furthermore, the integrated circuit 1 disclosed herein can change the clock skew margin depending on the voting situation by using the clock circuit 5 illustrated in FIG. 3 . In a high-radiation environment, as illustrated in FIG. 6 , each clock buffer constituting the clock tree deteriorates due to radiation, and differences in the deterioration speed of each clock buffer occur during the deterioration process. This increases clock skew, potentially rendering the sequential circuit inoperable. However, the integrated circuit 1 disclosed herein uses a majority voting circuit and controls the clock skew margin to an appropriate value, thereby achieving excellent effects such as improved reliability.

[0062] 7 is a timing chart showing an example of signal processing by the integrated circuit 1 disclosed herein. Fig. 7 illustrates a state in which the first input signal D1 is not inverted and remains constant at a high value such as "1" due to an abnormality such as a failure in Fig. 5. Even if an abnormality such as that illustrated in Fig. 7 occurs, the integrated circuit 1 disclosed herein can maintain normal overall operation as long as the second input signal D2 and the third input signal D3 are normal.

[0063] For example, a radiation-hard environment device equipped with the integrated circuit 1 disclosed herein can increase total dose tolerance to approximately 730 Mrad, and can be used for 300 days or more even in a high radiation environment such as a decommissioning site, providing excellent effects. In other words, the integrated circuit 1 disclosed herein can be said to have dramatically improved reliability in a radiation environment, even compared to conventional, specifically designed radiation-hard integrated circuits, which have a total dose tolerance of 300 krad to 2 Mrad and become unusable in approximately 10 to 20 hours.

[0064] Taking advantage of its excellent radiation resistance, the integrated circuit 1 disclosed herein can be implemented in a radiation-hard environment device. The radiation-hard environment device can be realized, for example, as a detection device that operates in a strong radiation environment, various work robots, an unmanned aerial vehicle, or the like. For example, in a radiation-hard environment device realized as an unmanned aerial vehicle, or so-called drone, the integrated circuit 1 disclosed herein can be used for a drive unit for a lift propeller, a propulsion propeller, or the like, and its control; a detection unit for an image sensor, a radiation detection element, or the like, and its control; and a communication unit for transmitting and receiving information obtained by the detection unit and information such as control commands from other control devices, and its control.

[0065] For example, conventional unmanned aerial vehicles equipped with conventional radiation-resistant integrated circuits rapidly deteriorate in high-radiation environments, quickly becoming unusable, such as being unable to be controlled or fly. To prevent this from happening, conventional unmanned aerial vehicles must be equipped with thick shielding, but the addition of such shielding increases the vehicle's weight, making flight itself difficult. The unmanned aerial vehicle equipped with the integrated circuit 1 disclosed herein solves this problem and can be realized as a radiation-resistant device that can be used stably even in high-radiation environments.

[0066] <Other Circuit Configuration Examples> The integrated circuit 1 disclosed herein can be realized as a circuit with various configurations, not limited to the circuit configuration exemplified in Fig. 1. Below, other configuration examples that are modifications of the configuration example of the integrated circuit 1 exemplified in Fig. 1 will be described.

[0067] FIG. 8 is a circuit diagram showing an example of an integrated circuit 1 disclosed herein. The integrated circuit 1 illustrated in FIG. 8 shows an equivalent circuit having a configuration in which the position of the majority circuit is changed. Specifically, the integrated circuit 1 illustrated in FIG. 8 has a configuration in which the master majority circuit 30 and the master inverter 32 are interchanged, and the slave majority circuit 40 and the slave inverter 42 are interchanged. As illustrated in FIG. 8, the integrated circuit 1 disclosed herein can be realized with a variety of highly reliable circuit configurations.

[0068] Fig. 9 is a circuit diagram showing an example of the integrated circuit 1 disclosed herein. The integrated circuit 1 illustrated in Fig. 9 shows an equivalent circuit having a configuration in which the input inverter 31 and the output inverter 41 are omitted. As illustrated in Fig. 9, the integrated circuit 1 disclosed herein can omit the input inverter 31 and the output inverter 41, thereby simplifying the circuit configuration.

[0069] Fig. 10 is a circuit diagram showing an example of the integrated circuit 1 disclosed herein. The integrated circuit 1 illustrated in Fig. 10 shows an equivalent circuit having a configuration in which the position of the majority circuit is changed and the input inverter 31 and the output inverter 41 are omitted. The integrated circuit 1 illustrated in Fig. 9 combines the features of the circuit illustrated in Fig. 8 and the circuit illustrated in Fig. 9. As illustrated in Fig. 9, the integrated circuit 1 disclosed herein can be realized in various modified forms.

[0070] FIG. 11 is a circuit diagram showing an example of an integrated circuit 1 disclosed herein. The integrated circuit 1 illustrated in FIG. 11 shows an example of an equivalent circuit of the integrated circuit 1 in which only the master majority circuit 30 of the majority circuits is omitted. Specifically, an intermediate inverter 35 is disposed in the position of the master majority circuit 30, and a signal inverted by the intermediate inverter 35 is output as an intermediate signal to the slave latch 4. The integrated circuit 1 disclosed herein can omit the master majority circuit 30, thereby simplifying the circuit configuration. Note that the integrated circuit 1 disclosed herein can be realized in various modified configurations, such as by replacing only the slave majority circuit 40 of the majority circuits with an inverter.

[0071] FIG. 12 is a circuit diagram showing an example of an integrated circuit 1 disclosed in the present application. The integrated circuit 1 shown in FIG. 12 shows an example of an equivalent circuit of an integrated circuit 1 in which a clock signal is four-phased. The integrated circuit 1 described above is shown as having a configuration in which the clock signal is two-phased, as a master clock signal and a slave clock signal. In contrast to this configuration, the integrated circuit 1 shown in FIG. 12 is configured such that a master high clock signal is input to the master input gate 33, a master low clock signal is input to the master feedback gate 34, a slave high clock signal is input to the slave input gate 43, and a slave low clock signal is input to the slave feedback gate 44. In other words, the integrated circuit 1 shown in FIG. 12 is configured such that the clock signal is four-phased.

[0072] 12, the master high clock signal, master low clock signal, slave high clock signal (first-phase slave clock signal), and slave low clock signal (second-phase slave clock signal) input to the first flip-flop 2A are respectively indicated as MGCLK1, MLCLK1, SGCLK1, and SLCLK1. The master high clock signal, master low clock signal, slave high clock signal, and slave low clock signal input to the second flip-flop 2B are respectively indicated as MGCLK2, MLCLK2, SGCLK2, and SLCLK2. The master high clock signal, master low clock signal, slave high clock signal, and slave low clock signal input to the third flip-flop 2C are respectively indicated as MGCLK3, MLCLK3, SGCLK3, and SLCLK3.

[0073] Fig. 13 is a circuit diagram showing an example of a clock circuit 5 included in the integrated circuit 1 disclosed herein. The clock circuit 5 shown in Fig. 13 is an equivalent circuit having a configuration in which the clock signal is four-phased by converting the clock circuit 5 shown in Fig. 3 into a four-phase circuit. Fig. 13 shows an example of a first clock circuit 5A corresponding to the first flip-flop 2A. The clock circuit 5 includes one parent clock circuit 5AA, and a master slave clock circuit 5AB and a slave slave clock circuit 5AC branching from the parent clock circuit 5AA.

[0074] The parent clock circuit 5AA includes various circuits such as a delay 50 and a selector 51. The parent clock circuit 5AA receives an input of a first clock signal CLK1, which is an original clock signal. The parent clock circuit 5AA selects a signal to accept as input from the signals output from each buffer included in the delay 50 using the selector 51. The parent clock circuit 5AA then outputs the selected signal to the master slave clock circuit 5AB and the slave slave clock circuit 5AC.

[0075] The master-use slave clock circuit 5AB includes a master gate 52, a delay 50, a selector 51, and an inverting gate 54. The master gate 52 is configured using an AND gate. The inverting gate 54 is configured using a NOT gate. The master gate 52 receives the first clock signal CLK1 and a signal output from the selector 51 of the master clock circuit 5AA, functions as an AND gate, and outputs a signal to the delay 50 and the inverting gate 54. The master-use slave clock circuit 5AB selects an input signal from the signals output from each buffer included in the delay 50 using the selector 51. The master-use slave clock circuit 5AB then outputs the selected signal as a master high clock signal to the integrated circuit 1 illustrated in FIG. 12. The inverting gate 54 also receives the signal output from the master gate 52 and inverts it. The master-use slave clock circuit 5AB then outputs the inverted signal as a master low clock signal to the integrated circuit 1 illustrated in FIG. 12.

[0076] The slave-use slave clock circuit 5AC includes a slave gate 53, a delay 50, a selector 51, and an inverting gate 54. The slave gate 53 is configured using two NOT gates and an AND gate. The slave gate 53 receives inputs of a signal obtained by inverting the first clock signal CLK1 using a NOT gate and a signal output from the selector 51 of the parent clock circuit 5AA and inverted using a NOT gate. The slave gate 53 functions as an AND gate and outputs signals to the delay 50 and the inverting gate 54. The slave-use slave clock circuit 5AC selects a signal to accept as input from the signals output from each buffer included in the delay 50 using the selector 51. The slave-use slave clock circuit 5AC then outputs the selected signal as a slave high clock signal to the integrated circuit 1 illustrated in FIG. 12. The inverting gate 54 also receives an input of the signal output from the slave gate 53 and inverts the signal. The slave-use slave clock circuit 5AC then outputs the inverted signal as a slave low clock signal to the integrated circuit 1 illustrated in FIG. 12. Although FIG. 13 shows a configuration in which the clock circuit 5 illustrated in FIG. 3 is four-phased, the integrated circuit 1 disclosed in the present application is not limited to this, and can be realized in various ways, such as by implementing multiple clock circuits 5 illustrated in FIG. 3 .

[0077] FIG. 14 is a timing chart showing an example of signal processing in the integrated circuit 1 disclosed herein. FIG. 14 shows an example of a timing chart for the integrated circuit 1 disclosed herein, as exemplified in FIG. 12. FIG. 14 shows time on the horizontal axis and the value of each signal on the vertical axis, indicating changes in each signal over time. The signal values ​​shown on the horizontal axis, from top to bottom, are the master high clock signals MGCLK1, MGCLK2, and MGCLK3 of the first to third flip-flops 2C, the master low clock signals MLCLK1, MLCLK2, and MLCLK3, the slave high clock signals SGCLK1, SGCLK2, and SGCLK3, and the slave low clock signals SLCLK1, SLCLK2, and SLCLK3. As exemplified in FIGS. 11 and 12, the integrated circuit 1 disclosed herein can be configured with appropriately multi-phased clock signals.

[0078] 15 is a circuit diagram showing an example of a clock circuit 5 included in the integrated circuit 1 disclosed herein. The clock circuit 5 shown in FIG. 15 has an equivalent circuit configuration including a delay adjustment circuit 7 in a stage preceding a delay 50 and a selector 51. FIG. 15 illustrates a first clock circuit 5A corresponding to a first flip-flop 2A. The clock circuit 5 includes the delay adjustment circuit 7, and further includes various circuits such as a delay 50, a selector 51, a master gate 52, and a slave gate 53. The delay adjustment circuit 7 includes an adjustment delay 70 and an adjustment selector 71. The configurations of the adjustment delay 70 and the adjustment selector 71 are substantially the same as those of the delay 50 and the selector 51.

[0079] The clock circuit 5 receives an input of a first clock signal CLK1, which is an original clock signal, and the first clock signal CLK1 is input to an adjustment delay 70. An adjustment selector 71 selects a signal to accept as input from the signals output from each buffer included in the adjustment delay 70, and outputs the selected signal to the delay 50, the master gate 52, and the slave gate 53. The operation of the adjustment selector 71 is controlled by an adjustment program signal PRGA output from the control circuit 6.

[0080] The selector 51 selects a signal to accept input from the signals output from each buffer included in the delay 50, and outputs the selected signal to the master gate 52 and the slave gate 53. The operation of the selector 51 is controlled by a first program signal PRG1 output from the control circuit 6. A second clock circuit 5B corresponding to the second flip-flop 2B and a third clock circuit 5C corresponding to the third flip-flop 2C are also implemented with a similar configuration.

[0081] The adjusted program signal PRGA is a signal output from the control circuit 6 that detects a delay when the delay time of the clock circuit 5 corresponding to another flip-flop 2 becomes longer. For example, assume that the buffer included in the delay 50 of the first clock circuit 5A corresponding to the first flip-flop 2A suddenly deteriorates, causing the delay time to become relatively longer compared to the second clock circuit 5B and the third clock circuit 5C. The control circuit 6, upon detecting this situation, outputs the adjusted program signal PRGA to the second clock circuit 5B and the third clock circuit 5C. Upon receiving the adjusted program signal PRGA, the second clock circuit 5B and the third clock circuit 5C lengthen their delay times using the adjustment delay 70 and adjustment selector 71 of the delay adjustment circuit 7. This allows the integrated circuit 1 disclosed herein to operate while maintaining a low clock skew margin of the clock circuit 5.

[0082] The integrated circuit 1 disclosed herein may be provided with another detection circuit 8 that detects a degradation state in combination with processing by the majority circuit. In this case, the integrated circuit 1 executes processing such as lengthening the period of the master clock signal and / or the slave high clock signal even when degradation is detected by the other detection circuit 8.

[0083] FIG. 16 is a circuit diagram showing an example of the detection circuit 8 included in the integrated circuit 1 disclosed herein. FIG. 16 also shows an example of a circuit combining a diode and a transistor as an equivalent circuit of another detection circuit 8. The diode is formed by joining a p-type semiconductor and an n-type semiconductor, for example, in a structure such as Nwell-Psubstrate or n-type diffusion layer-Psubstrate. The anode terminal A on the p-type semiconductor side is connected to VSS, and the cathode terminal C on the n-type semiconductor side is connected to a transistor and a detection terminal for voltage detection. Therefore, the detection circuit 8 can detect the cathode voltage as the detection voltage Vα from the detection terminal. For example, a P-channel junction FET is used as the transistor. When a P-channel junction FET is used, the source terminal S of the transistor is connected to the cathode terminal C of the diode. Furthermore, the drain terminal D of the transistor is connected to VDD, and the gate terminal G is connected to a switch signal CN.

[0084] FIG. 17 is a timing chart showing an example of the operation of the detection circuit 8 included in the integrated circuit 1 disclosed herein. FIG. 17 shows the time-dependent changes in the switch signal CN and detection voltage Vα of the detection circuit 8 illustrated in FIG. 16 , with the horizontal axis representing time and the vertical axis representing the switch signal CN applied to the transistor and the detection voltage Vα detected at the detection terminal. In the timing chart of FIG. 17 , the upper part shows the switch signal CN, the middle part shows the detection voltage Vα (Vα#n) in a normal state, and the lower part shows the detection voltage Vα (Vα#d) in a degraded state. When the switch signal CN goes LOW, the transistor turns on, charging the diode junction capacitance, causing the detection voltage Vα to rise to VDD. If the transistor is then negated and left alone, the charge accumulated up to the diode junction capacitance is gradually discharged as a leakage current, causing the detection voltage Vα to drop from VDD to VCC, indicated by the dotted line in FIG. 17 . As degradation due to radiation progresses, the detection circuit 8 included in the integrated circuit 1 experiences increased leakage current, resulting in a rapid drop in the detection voltage Vα. As illustrated in FIG. 17 , the normal detection voltage Vα#n and the degraded detection voltage Vα#d differ in the rate at which they drop from VDD to VCC, resulting in a difference in the time it takes for the detection voltage Vα to reach VCC after the switch signal CN goes LOW. In other words, the detection circuit 8 included in the integrated circuit 1 can estimate the total dose by measuring the time it takes for the potential based on the charge stored in the detection voltage Vα to drop from VDD to VCC. Therefore, the control circuit 6 of the integrated circuit 1 outputs a clock signal to control the clock skew margin and clock frequency based on the time it takes for the detection voltage Vα to drop.

[0085] As described above, the integrated circuit 1 disclosed in the present application has excellent effects such as being able to control the clock circuit 5 by the detection circuit 8 used in combination with the majority circuit, thereby improving reliability.

[0086] FIG. 18 is a circuit diagram illustrating an example of a detection circuit 8 included in the integrated circuit 1 disclosed herein. FIG. 18 also illustrates an example of a circuit using a ring oscillator as an equivalent circuit of another detection circuit 8. A ring oscillator is an oscillation circuit in which an odd number of NOT circuits are connected in a series ring. The oscillation frequency of a ring oscillator changes due to degradation caused by radiation. Specifically, the oscillation frequency of a ring oscillator transitions from a high frequency to a low frequency due to degradation caused by radiation. In other words, the detection circuit 8 included in the integrated circuit 1 can estimate the total dose by measuring the oscillation frequency. Therefore, the control circuit 6 of the integrated circuit 1 outputs a clock signal to control the clock skew margin and clock frequency based on the decrease in oscillation frequency. Note that while FIG. 18 illustrates an oscillation circuit in which three NOT circuits are connected in a series ring, any odd number of NOT circuits, such as one, five, or seven, can be appropriately designed.

[0087] 16 and 18, depending on the chip size, theoretically one to four detection circuits 8 can be distributed throughout the circuit to provide sufficient functionality. For example, when one detection circuit 8 is disposed, the detection circuit 8 is disposed near the center. Furthermore, when four detection circuits 8 are disposed, the chip is divided into four sections, and the detection circuits 8 are disposed near the center of each section. Note that five or more detection circuits 8 can also be disposed depending on the chip size and the required reliability.

[0088] As described above, the integrated circuit 1 disclosed in the present application has excellent effects such as being able to control the clock circuit 5 by the detection circuit 8 used in combination with the majority circuit, thereby improving reliability.

[0089] Next, experimental results using the integrated circuit 1 disclosed herein will be described. FIGS. 19 and 20 are circuit diagrams showing an experimental circuit using the integrated circuit 1 disclosed herein. For convenience of illustration, FIGS. 19 and 20 show one circuit diagram across two drawings, with FIG. 19 at the top and FIG. 20 at the bottom. In FIGS. 19 and 20, wires labeled with the same alphanumeric characters are connected. The experimental circuit shown in FIGS. 19 and 20 is a circuit in which the radiation-hardened FPGA illustrated in FIG. 4 is configured using the two-phase clock triplexed latch illustrated in FIG. 1 and the majority circuit illustrated in FIG. 2. For convenience of illustration, FIGS. 19 and 20 show two integrated circuits 1 one above the other so that their connection relationships can be seen. When implementing the circuit, the number of integrated circuits 1 is determined, for example, by the number of configurable logic blocks (CLBs) that make up the FPGA, and the connection relationships of the integrated circuits 1 are determined, for example, by a switching matrix. The experimental circuit using the exemplified integrated circuit 1 disclosed herein was found to have a radiation tolerance of 7.3 MGy, which is 365 to 7,300 times that of a correspondingly configured existing radiation-tolerant VLSI. Note that although the experimental circuit in this case does not include a phase / period adjustment circuit in the master-slave block, further improvements in radiation tolerance are expected by incorporating and adjusting a phase / period adjustment circuit in the master-slave block.

[0090] The present invention is not limited to the above-described embodiments, and can be embodied in various other forms. Therefore, the above-described embodiments are merely illustrative in all respects and should not be interpreted as limiting. The technical scope of the present invention is defined by the claims and is not limited in any way by the text of the specification. Furthermore, all modifications and variations within the equivalent scope of the claims are within the scope of the present invention.

[0091] For example, while the embodiment described above is implemented as a triplex flip-flop circuit, the integrated circuit 1 disclosed herein is not limited to this configuration and can be configured with an odd number of flip-flops (three or more), such as quintuple or septuple, which can implement a majority circuit. Furthermore, the integrated circuit 1 disclosed herein can be configured with an N-multiplexed slave latch 4 (N is an integer greater than or equal to three) and an M-multiplexed master latch 3 (M is an integer greater than or equal to three), where N=M or N≠M. Because the slave latch 4 and the master latch 3 are implemented as majority circuits, N and M are preferably odd numbers greater than or equal to three, but may also be integers greater than or equal to three. Furthermore, the integrated circuit 1 disclosed herein can be implemented in various ways, such as by not employing a majority circuit in the master latch 3 (M=1) and configuring only the slave latch 4 as a majority circuit.

[0092] 1 Integrated circuit 2 Flip-flop circuit 2A First flip-flop 2B Second flip-flop 2C Third flip-flop 3 Master latch 30 Master majority circuit 31 Input inverter 32 Master inverter 33 Master input gate 34 Master feedback gate 35 Intermediate inverter 4 Slave latch 40 Slave majority circuit 41 Output inverter 42 Slave inverter 43 Slave input gate 44 Slave feedback gate 5 Clock circuit 5A First clock circuit 5B Second clock circuit 5C Third clock circuit 5AA Parent clock circuit 5AB Master slave clock circuit 5AC Slave slave clock circuit 50 Delay 500 Adjustable delay 51 Selector 510 Adjustable selector 52 Master gate 53 Slave gate 54 Inverting gate 6 Control circuit 7 Delay adjustment circuit 70 Adjustable delay 71 Adjustable selector 8 Detection circuit D1 First input signal D2 Second input signal D3 Third input signal IQ1 First intermediate signal IQ2 Second intermediate signal IQ3 Third intermediate signal Q1 First output signal Q2 Second output signal Q3 Third output signal MCLK1 First master clock signal MCLK2 Second master clock signal MCLK3 Third master clock signal SCLK1 First slave clock signal SCLK2 Second slave clock signal SCLK3 Third slave clock signal CLK1 First clock signal CLK2 Second clock signal CLK3 Third clock signal PRG1 First program signal PRG2 Second program signal PRG3 Third program signal PRGA Adjusted program signal MGCLK1, MGCLK2,MGCLK3: Master high clock signal MLCLK1, MLCLK2, MLCLK3: Master low clock signal SGCLK1, SGCLK2, SGCLK3: Slave high clock signal (first phase slave clock signal) SLCLK1, SLCLK2, SLCLK3: Slave low clock signal (second phase slave clock signal)

Claims

1. An integrated circuit comprising: a master latch which receives an input signal and outputs a signal at a timing based on a master clock signal; and N slave latches (N is an integer equal to or greater than 3) which receive an input signal output from said master latch and output an output signal at a timing based on a slave clock signal, wherein said master latch outputs to said slave latch a signal whose value is determined based on the input signal and the output signal, and each of said slave latches outputs an output signal whose value is determined based on a majority vote of the signals output from each of said N slave latches, or a majority vote of the signals each of said slave latches receives as input from the master latch.

2. An integrated circuit as claimed in claim 1, comprising M master latches (M is an integer equal to or greater than 3), each of which is adapted to output to said slave latch a signal whose value is determined based on the result of a majority vote of signals output from each of said M master latches, or the result of a majority vote of each of the input signals received by said each master latch.

3. An integrated circuit according to claim 1 or 2, characterized in that, when the slave latch performs a majority vote and signals of different values ​​are included, the period of the slave clock signal is lengthened.

4. An integrated circuit according to claim 2, characterized in that when the master latch performs a majority vote and signals of different values ​​are included, the period of the master clock signal is lengthened.

5. An integrated circuit according to claim 1 or 2, characterized in that the master clock signal and the slave clock signal are clock signals branched off from an original clock signal and have different phases.

6. An integrated circuit as claimed in claim 1 or 2, wherein the slave clock signal is a first-phase slave clock signal and a second-phase slave clock signal which are branched from an original clock signal and have different phases, and the slave latch is adapted to output an output signal whose value is determined based on a majority decision result of each signal input to each of the slave latches from the master latch at a timing based on the first-phase slave clock signal, and to output an output signal whose value is determined based on a majority decision result of the signals respectively output from the slave latches at a timing based on the second-phase slave clock signal.

7. An integrated circuit as claimed in claim 1 or 2, further comprising a detection circuit for detecting a deterioration state, and wherein when said detection circuit detects deterioration, the period of the slave clock signal is lengthened.

8. An integrated circuit according to claim 7, characterized in that the detection circuit detects the deterioration state based on the discharge time of the electric charge stored in a diode formed by joining a p-type semiconductor and an n-type semiconductor.

9. An integrated circuit according to claim 7, wherein the detection circuit is a ring oscillator formed by connecting an odd number of NOT circuits in series in a ring shape to form an oscillation circuit.

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