Semiconductor device and manufacturing method therefor, and storage system

Abstract

A semiconductor device and a manufacturing method therefor, and a storage system. The semiconductor device comprises a stack structure (10), and at least one semiconductor structure (20) running through the stack structure (10), wherein the semiconductor structure (20) comprises a capacitor structure (210), a first transistor structure (310) and a second transistor structure (410) which extend in the stack structure (10) in a first direction; and the second and first transistor structures (410, 310) and the capacitor structure (210) in the same semiconductor structure (20) are sequentially arranged and connected in the first direction, thereby realizing the vertical arrangement of transistors and a storage capacitor and improving the storage density.

Description

Semiconductor device, manufacturing method thereof, and storage system Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and a storage system. Background Art

[0002] Ferroelectric random access memory (FeRAM), as a new type of memory, is increasingly being used due to its advantages over traditional dynamic random access memory (DRAM), such as non-volatility, high speed, and low power consumption.

[0003] Currently, the storage density of ferroelectric memory is not high and needs to be improved.

[0004] Summary of the Invention

[0005] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and a storage system, which can improve the storage density of the semiconductor device.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising:

[0007] A stacked structure comprising conductor layers and dielectric layers stacked alternately along a first direction;

[0008] At least one semiconductor structure extending through the stacked structure; the semiconductor structure comprising:

[0009] a capacitor structure, a first transistor structure, and a second transistor structure extending in the stacked structure along the first direction;

[0010] The second transistor structure, the first transistor structure and the capacitor structure in the same semiconductor structure are sequentially arranged and connected along the first direction.

[0011] In a second aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor device, the method comprising:

[0012] forming a stacked structure comprising alternating conductor layers and dielectric layers;

[0013] forming at least one semiconductor structure penetrating the stack structure; the semiconductor structure comprising a capacitor structure, a first transistor structure, and a second transistor structure extending in the stack structure along the first direction;

[0014] The second transistor structure, the first transistor structure and the capacitor structure in the same semiconductor structure are sequentially arranged and connected along the first direction.

[0015] In a third aspect, an embodiment of the present application further provides a storage system comprising: a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory comprises the semiconductor device described in the first aspect.

[0016] An embodiment of the present application provides a semiconductor device, a manufacturing method thereof, and a storage system; the semiconductor structure in the semiconductor device includes a capacitor structure, a first transistor structure, and a second transistor structure extending sequentially in a stacked structure along the first direction, and the second transistor structure, the first transistor structure, and the capacitor structure in the same semiconductor structure are sequentially arranged and connected along the first direction, thereby realizing the vertical arrangement of each transistor structure and each capacitor structure in the semiconductor structure, greatly realizing the improvement of storage capacitance density, and improving the storage density of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] FIG1 is an equivalent circuit diagram of a memory cell in a semiconductor device according to some embodiments;

[0019] 2 to 28 are schematic structural diagrams of a semiconductor device at multiple stages according to an embodiment of the present application;

[0020] FIG29 is a schematic structural diagram of a semiconductor structure in a semiconductor device provided in an embodiment of the present application;

[0021] FIG30 is an equivalent circuit diagram of a memory cell in a semiconductor device according to an embodiment of the present application;

[0022] FIG31 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0023] FIG32 is a schematic diagram of the structure of the storage system provided in the embodiment of the application. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0025] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0026] In the description of the present application, “at least one of A, B, and C” and “at least one of A, B, or C” have the same meaning, and both include the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. “A and / or B” includes the following three combinations: only A, only B, and a combination of A and B.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0028] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0029] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0030] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0031] Some embodiments of the present disclosure provide an electronic device, which may include a storage system configured to implement data storage as described below, and may also include at least one of a central processing unit (CPU) and a cache. Exemplarily, the electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, and the like.

[0032] As used in this application, the term "layer" refers to a material portion comprising a region with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire lower layer or superstructure, or can have a scope that is less than the lower layer or superstructure scope. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be between the top surface and the bottom surface of the continuous structure or between any one group of horizontal planes at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, which can comprise one or more layers, and / or can have one or more layers thereon, above and / or below. The layer can comprise multiple layers. For example, an interconnect layer can comprise one or more gate line layers and a contact layer (wherein contacts, interconnects and one or more dielectric layers are formed).

[0033] It should be noted that the illustrations provided in the embodiments of the present application are only schematic illustrations of the basic concept of the present application. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated.

[0034] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0035] Transistors are used as switches or selection devices in memory cells of some memory devices, such as DRAM, PCM, and ferroelectric DRAM (Fe RAM). However, planar transistors commonly used in memory cells generally have a horizontal structure, in which the buried word line is in the substrate and the bit line is above the substrate. The memory cell of a semiconductor device can be a 1T1C cell consisting of a transistor and a storage capacitor. It should be understood that the memory cell can also be any suitable structure XTYC, such as a 1T2C cell, a 1T3C cell, a 2T1C cell, a 3T1C cell, a 2T3C cell, etc., where X and Y are both positive integers. Wherein, T is the abbreviation of transistor, and C is the abbreviation of storage capacitor.

[0036] In one implementation, referring to FIG1 , the memory cell has a 2T3C structure, wherein two transistors are placed horizontally side by side, and three storage capacitors C are placed vertically side by side. The first electrode of the first transistor T1 is connected to the plate line (PL), the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2, the second electrode of the second transistor T2 is connected to the bit line (BL), the gate of the first transistor T1 is connected to the first plates of the first storage capacitor C1, the second storage capacitor C2, and the third storage capacitor C3, and the gate of the second transistor T2 is connected to the word line (WL). In addition, the second plates of the three storage capacitors are respectively connected to the plate line PL. The density of multiple storage capacitors arranged vertically on a horizontal plane reduces the density of 2T3C.

[0037] In order to improve the above-mentioned problems, with reference to Figures 2 to 32, an embodiment of the present application provides a semiconductor device 1000, a method for manufacturing the same, and a storage system. The semiconductor structure 20 formed in the present application includes a capacitor structure 210, a first transistor structure 310, and a second transistor structure 410 extending in the stacking direction (Z direction) in the stacking structure 10. The second transistor structure 410, the first transistor structure 310, and the capacitor structure 210 in the same semiconductor structure 20 are arranged and connected in sequence along the first direction Z. In this way, multiple transistor structures and multiple storage capacitors 214 are arranged vertically, which can reduce the occupied area of ​​the transistor structure and the storage capacitor 214, thereby improving the storage density and miniaturization of the three-dimensional memory device. The design of vertically arranging transistors also simplifies the arrangement of the interconnect structure (e.g., word lines and bit lines) coupled to the memory cell, reduces the spacing restrictions of the word lines and / or bit lines, and reduces the influence of the vertically arranged storage capacitor 214 on the extraction of the vertically arranged transistor structure, thereby reducing manufacturing complexity and improving product yield.

[0038] Please refer to FIG. 23 , which is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application. FIG. 2 to FIG. 22 are schematic diagrams of the structure of multiple stages of forming the semiconductor device shown in FIG. 23 . The semiconductor device includes:

[0039] The stacked structure 10 includes conductor layers and dielectric layers stacked alternately along a first direction Z;

[0040] At least one semiconductor structure 20 extending through the stacked structure 10; the semiconductor structure 20 includes:

[0041] a capacitor structure 210 , a first transistor structure 310 , and a second transistor structure 410 extending in the stack structure 10 along the first direction Z (Z direction);

[0042] The second transistor structure 410 , the first transistor structure 310 , and the capacitor structure 210 in the same semiconductor structure 20 are sequentially arranged along the first direction Z and connected.

[0043] In some examples, the stacked structure 10 shown in Figures 2 to 28 includes dielectric layers and conductor layers that are staggered in a first direction Z and extend along a second direction and a third direction. The second direction intersects the first direction Z, and the third direction intersects the first direction Z and the second direction. Here, the second direction intersecting the first direction Z can be understood as the angle between the second direction and the first direction Z being less than or equal to 90 degrees, and the third direction intersecting the first direction Z and the second direction can be understood as the angle between the third direction and the plane containing the first direction Z and the second direction being less than or equal to 90 degrees. In some specific examples of the present application, the angle between the second direction and the first direction Z is equal to 90 degrees, and the angle between the third direction and the plane containing the first direction Z and the second direction is equal to 90 degrees.

[0044] In some specific examples, the first direction Z can be understood as the Z-axis direction shown in Figures 2-29, the second direction can be understood as the X-axis direction shown in Figures 2-29, and the third direction can be understood as the Y-axis direction shown in Figures 2-29.

[0045] For example, referring to Figures 2 to 28, the stacked structure 10 includes a first stacked layer 200, a second stacked layer 300, and a third stacked layer 400, which are sequentially stacked along a first direction Z. The first stacked layer 200 includes a first conductor layer 201 and a first dielectric layer 202, which are alternately stacked along the first direction Z. The second stacked layer 300 includes a second conductor layer 301 and a second dielectric layer 302, which are alternately stacked along the first direction Z. The third stacked layer 400 includes a third conductor layer 401 and a third dielectric layer 402, which are alternately stacked along the first direction Z. Of course, the first stacked layer 200 may further include a fourth dielectric layer 203 located between the substrate 100 and the first conductor layer 201.

[0046] Specifically, a substrate 100 is first provided. The substrate 100 extends in a second direction X and a third direction Y to form a stacking surface, and a stacking layer is formed on the stacking surface. As an example, the substrate 100 can be selected according to the actual needs of the device, for example, it can include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate. Preferably, in this embodiment, the substrate 100 includes a single crystal silicon substrate.

[0047] In some examples, substrate 100 is a semiconductor substrate. For example, the substrate can be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate. It should be noted that the substrate can be an ion-doped substrate, specifically, a P-type doped substrate or an N-type doped substrate. A suitable material can be selected as the substrate according to actual needs, and this application does not impose specific restrictions on this. Of course, in other embodiments, the substrate material can also be a semiconductor or compound containing other elements. For example, the substrate can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, or a silicon carbide (SiC) substrate. In other examples, the substrate is made of a non-conductive material, which can include, for example, glass, plastic, or a sapphire wafer.

[0048] In some examples, a deposition method is selected based on actual needs to form a stacked structure 10 having a multi-layer structure on a stacking surface. The number of stacked layers in the stacked structure 10 shown in Figures 2 to 23 is merely an example, and the number of layers in the stacked layer is also merely an example. For example, the number of first dielectric layers 202 and first conductor layers 201 in the first stacked layer 200 may include 32 layers, 64 layers, 96 layers, or 128 layers, etc. Specifically, the number of dielectric layers and conductor layers included in different stacked layers in the stacked structure 10 can be set based on actual needs, that is, the number of layers in the stacked structure 10 is not limited.

[0049] In some examples, the first dielectric layer 202 to the fourth dielectric layer 203 can all be made of insulating materials, including but not limited to any one of silicon nitride, silicon oxide, and aluminum oxide, or any combination thereof. Silicon oxide herein refers to a silicon oxide compound, such as SixOy, and silicon nitride refers to a silicon nitrogen compound, such as SixNy. The first conductor layer 201 to the third conductor layer 401 can be made of conductive materials, including but not limited to any one of poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), or any combination thereof.

[0050] It should be noted that the conductor layer and the dielectric layer have different etching selectivities, and the deposition methods of the conductor layer and the dielectric layer may include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal-organic MOCVD, and atomic layer deposition (ALD).

[0051] In some examples, the semiconductor device 1000 is further provided with at least one semiconductor structure 20 extending through the stacked structure 10. For example, referring to FIG. 23 , the semiconductor device 1000 is provided with three semiconductor structures 20 extending through the stacked structure 10, wherein the same semiconductor structure 20 includes a capacitor structure 210, a first transistor structure 310, and a second transistor structure 410 extending in the stacked structure 10 along the first direction Z, wherein the second transistor structure 410, the first transistor structure 310, and the capacitor structure 210 in the same semiconductor structure 20 are sequentially arranged and connected along the first direction Z.

[0052] In some embodiments, the capacitor structure 210 includes: a plurality of storage capacitors 214 , and the plurality of storage capacitors 214 are arranged along the first direction Z at intervals.

[0053] In some examples, the same capacitor structure 210 corresponds to multiple storage capacitors 214 , and the multiple storage capacitors 214 are arranged along the stacking direction, i.e., the first direction Z. For example, referring to FIG. 23 , a capacitor structure 210 of the same semiconductor structure 20 includes three storage capacitors 214 .

[0054] It should be noted that the number of semiconductor structures 20 in the semiconductor device shown in FIG23 is merely an example, and the number of transistor structures and the number of capacitor structures 210 arranged and connected along the first direction Z contained in each semiconductor structure 20 shown in FIG23 are also merely examples. For example, the number of semiconductor structures 20 in the semiconductor device may include 1, 2, 3, 4, 5, etc., the number of storage capacitors 214 included in the capacitor structure 210 in the same semiconductor structure 20 may include 1, 2, 3, 4, 5, etc., and the number of transistors included in the capacitor structure 210 in the same semiconductor structure 20 may include at least two, for example, 2, 3, 4, 5, etc. The transistor structures and capacitor structures 210 arranged and connected along the first direction Z in the same semiconductor structure 20 can be any suitable structure XTYC, such as a 2T1C structure, a 2T2C structure, a 2T3C structure, a 2T4C structure, a 2T5C structure, a 3T1C structure, a 3T2C structure, etc., where X is a positive integer greater than 1, Y is a positive integer, T represents the transistor structure, and C represents the capacitor structure 210. Multiple storage capacitors 214 and the first transistor structure 310 and the second transistor structure 410 corresponding to the same semiconductor structure 20 can constitute the aforementioned memory cell.

[0055] In some embodiments, the storage capacitor 214 includes a first electrode 212 and a dielectric layer 211 . The dielectric layer 211 is connected to the first conductor layer 201 and is disposed between the first electrode 212 and the first conductor layer 201 .

[0056] In some examples, referring to Figures 7 to 23, the capacitor structure 210 includes a dielectric layer 211 and a first electrode 212 arranged in sequence from the outside to the inside, and the dielectric layer 211 is used to enable the semiconductor device 1000 to realize a storage function. The dielectric layer 211 is located between the plurality of first conductor layers 201 and the first electrode 212, and the dielectric layer 211 is connected to the first conductor layer 201 corresponding to the first preset depth in the stacked structure 10 along the first direction Z. The dielectric layer 211 and the first electrode 212 both extend along the first direction Z. The portions of the dielectric layer 211 and the first electrode 212 that are opposite to the first conductor layer 201 form a storage capacitor 214 with the first conductor layer 201. The portion of each first conductor layer 201 surrounding the dielectric layer 211 constitutes the second electrode of the storage capacitor 214.

[0057] Exemplarily, the number of first conductive layers 201 is multiple, and the portion of each first conductive layer 201 surrounding the dielectric layer 211, as well as the portion of the dielectric layer 211 and the first electrode 212 opposite the first conductive layer 201, form a storage capacitor 214. Multiple storage capacitors 214 corresponding to the same semiconductor structure 20 share the first electrode 212 and the dielectric layer 211, and both the first electrode 212 and the dielectric layer 211 extend along the first direction Z, thereby allowing the multiple storage capacitors 214 to be arranged along the first direction Z.

[0058] In some embodiments, the material of the dielectric layer 211 includes any one or more of ferroelectric materials and antiferroelectric materials.

[0059] In some examples, the material of dielectric layer 211 can include multiple materials, as long as dielectric layer 211 can achieve a storage effect. The embodiments of the present disclosure are not limited to this. For example, dielectric layer 211 can be a ferroelectric layer, which can include a high-k (i.e., high dielectric constant) dielectric material, which can include transition metal oxides such as hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof. On this basis, the high-k dielectric material can also be doped. For example, dielectric layer 211 can be HfO2 doped with silicon (Si), yttrium (Y), gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof.

[0060] Exemplarily, the dielectric layer 211 can be a ferroelectric layer, and the portion of the first conductor layer 201 surrounding the dielectric layer 211, and the portion of the dielectric layer 211 and the first electrode 212 opposite to the first conductor layer 201 form a ferroelectric capacitor, which is also a type of the above-mentioned storage capacitor 214. At this time, the three-dimensional memory 320 including the semiconductor device 1000 is a ferroelectric memory. As a new type of memory, ferroelectric memory has the advantages of non-volatility, high speed, low power consumption, etc., and is being used more and more widely. Ferroelectric memory mainly includes ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistor (FeFET) memory.

[0061] In some embodiments, the first electrode 212 includes multiple layers of sub-electrodes along a radial direction (X direction) of the capacitor structure 210 , and the radial direction intersects the first direction Z.

[0062] In some examples, the first electrode 212 includes at least one layer of sub-electrodes along the radial direction of the capacitor structure 210. For example, as shown in Figures 9 to 23, along the radial direction of the capacitor structure 210, the first electrode 212 includes a first sub-electrode 2121 and a second sub-electrode 2122 surrounding the first sub-electrode 2121. The material of the multi-layer sub-electrodes can be a conductive material, which includes but is not limited to one or more combinations of conductive materials such as TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), Pt (platinum), polysilicon, etc.

[0063] It should be noted that the materials of the multi-layer sub-electrodes, such as the first sub-electrode 2121 and the second sub-electrode 2122, can be the same or different. When the materials of the multi-layer sub-electrodes are the same, the densities of the sub-electrodes can be different. Exemplarily, the materials of the sub-electrodes include any one or more of titanium nitride (TiN) and polysilicon.

[0064] In some embodiments, please continue to refer to Figures 7 and 23. The capacitor structure 210 further includes: a support column 213 extending along the first direction Z, the second sub-electrode 2122 is arranged around the support column 213, the support column 213 can be cylindrical, and the second sub-electrode 2122 surrounds the support column 213. Exemplarily, the support column 213 can be made of an insulating material, and the insulating material can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. By providing the support column 213, a support function can be provided for forming the first transistor structure 310 and the second transistor structure 410 in the subsequent embodiments such as Figures 24 to 29.

[0065] In some embodiments, the first transistor structure 310 includes:

[0066] A first gate structure 313 connected to the first surface 220 of the capacitor structure 210 along the first direction Z.

[0067] In some examples, referring to Figures 16 to 29, the first transistor structure 310 includes a first gate structure 313, and the capacitor structure 210 includes a first surface 220 (i.e., an upper surface or top surface) away from the substrate 100 along the first direction Z and a second surface (i.e., a lower surface or bottom surface, not shown in the figures) closer to the substrate 100 along the first direction Z. The first gate structure 313 includes a first side 3139 (i.e., an upper surface or top surface) away from the substrate 100 or the capacitor structure 210 along the first direction Z and a second side 3130 (i.e., a lower surface or bottom surface) closer to the substrate 100 or the capacitor structure 210 along the first direction Z. The first surface 220 (i.e., an upper surface or top surface) of the capacitor structure 210 shown in Figures 7 to 29 along the first direction Z is in contact with the second side 3130 (i.e., a lower surface or bottom surface) of the first gate structure 313 along the first direction Z. The capacitor structure 210 shown in Figures 7 to 29 is in contact with the substrate 100 along the second surface (i.e., a lower surface or bottom surface) along the first direction Z. It should be noted that the size of the first gate structure 313 along the second direction X may be greater than or equal to the size of the capacitor structure 210 along the second direction X. The material of the first gate structure 313 includes a conductive material, which includes but is not limited to polysilicon or a metal silicide, such as a metal silicide selected from cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), W, and titanium (Ti).

[0068] A first isolation structure 314 connected to a first side 3139 of the first gate structure 313 along the first direction Z.

[0069] In some examples, referring to Figures 16 to 29 , the first transistor structure 310 further includes a first isolation structure 314, wherein the first isolation structure 314 is located on a side of the capacitor structure 210 shown in Figures 7 to 29 away from the substrate. The first isolation structure 314 includes a first end 3149 (i.e., an upper surface or top surface) away from the substrate 100 or the capacitor structure 210 along the first direction Z and a second end 3140 (i.e., a lower surface or bottom surface) closer to the substrate 100 or the capacitor structure 210 along the first direction Z. The second side 3130 (i.e., a lower surface or bottom surface) of the first gate structure 313 along the first direction Z is in contact with the first surface 220 (i.e., an upper surface or top surface) of the capacitor structure 210 along the first direction Z, and the first side 3139 (i.e., an upper surface or top surface) of the first gate structure 313 along the first direction Z is in contact with the second end 3140 (i.e., a lower surface or bottom surface) of the first isolation structure 314 along the first direction Z. It should be noted that the size of the first isolation structure 314 along the second direction X may be greater than or equal to the size of the first gate structure 313 along the second direction X. The first isolation structure 314 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0070] A first spacer structure 312 surrounds the first gate structure 313 and the first isolation structure 314 .

[0071] In some examples, referring to Figures 16 to 29 , the first transistor structure 310 further includes a first spacer structure 312, wherein the first spacer structure 312 is located on a side of the capacitor structure 210 shown in Figures 7 to 29 away from the substrate, and the first spacer structure 312 is disposed around the first gate structure 313 and the first isolation structure 314 in the second direction X. In other words, the first spacer structure 312 includes a first cavity Q1, so that the first spacer structure 312 is a hollow cylindrical structure, the hollow cylindrical first spacer structure 312 includes two portions arranged opposite to each other along the second direction X, the two portions extending along the first direction Z, and the first gate structure 313 and the first isolation structure 314 are located within the first cavity Q1 of the first spacer structure 312, that is, the first gate structure 313 and the first isolation structure 314 are located between the two portions of the hollow cylindrical first spacer structure 312. It should be noted that the size of the first gate structure 313 along the second direction X can be greater than or equal to the size of the capacitor structure 210 along the second direction X. The material of the first spacer may be an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0072] A first drain structure 315 connected to a first end 3149 of the first isolation structure 314 along the first direction Z and a first surface 3129 of the first spacing structure 312 along the first direction Z.

[0073] In some examples, referring to Figures 16 to 29 , the first transistor structure 310 further includes a first drain structure 315 , wherein the first drain structure 315 is located on a side of the first isolation structure 314 shown in Figures 7 to 29 away from the substrate along the first direction Z. The first spacer structure 312 includes a first surface 3129 (i.e., an upper surface or top surface) away from the substrate 100 or the capacitor structure 210 along the first direction Z and a second surface 3120 (i.e., a lower surface or bottom surface) closer to the substrate 100 or the capacitor structure 210 along the first direction Z. The first drain structure 315 includes a first end surface 3159 (i.e., an upper surface or top surface) away from the substrate 100 or the capacitor structure 210 along the first direction Z and a second end surface 3150 (i.e., a lower surface or bottom surface) closer to the substrate 100 or the capacitor structure 210 along the first direction Z. The second end 3140 (i.e., the lower surface or bottom surface) of the first isolation structure 314 along the first direction Z is in contact with and connected to the first side 3139 (i.e., the upper surface or top surface) of the first gate structure 313 along the first direction Z. Furthermore, the first end 3149 (i.e., the upper surface or top surface) of the first isolation structure 314 along the first direction Z is in contact with and connected to the second end surface 3150 (i.e., the lower surface or bottom surface) of the first drain structure 315 along the first direction Z. Furthermore, the second end surface 3150 (i.e., the lower surface or bottom surface) of the first drain structure 315 along the first direction Z is also connected to the first surface 3129 of the first spacer structure 312 along the first direction Z. It should be noted that the dimension of the first drain structure 315 along the second direction X can be greater than or equal to the sum of the dimension of the first isolation structure 314 along the second direction X and the dimension of the first spacer structure 312 along the second direction X. In other words, the projections of the first isolation structure 314 and the first spacer structure 312 along the second direction X are located within the projection of the first drain structure 315 along the second direction X. The material of the first drain structure 315 may include a conductive material, and the conductive material may include single crystal silicon, polycrystalline silicon, etc.

[0074] a first channel structure 311 surrounding the first spacer structure 312 and the first drain structure 315;

[0075] The first channel structure 311 is connected to the second conductor layer 301 , and the portion where the second conductor layer 301 is connected to the first channel structure 311 serves as a first source structure of the first transistor structure 310 .

[0076] In some examples, referring to Figures 16 to 29 , the first transistor structure 310 further includes a first channel structure 311, wherein the first channel structure 311 is located on a side of the capacitor structure 210 shown in Figures 7 to 29 away from the substrate, and the first channel structure 311 is disposed around the first spacer structure 312 and the first drain structure 315. In other words, the first channel structure 311 includes a second cavity Q2, such that the first channel structure 311 is a hollow cylindrical structure. The hollow cylindrical first channel structure 311 includes two portions disposed opposite each other along the second direction X, and the two portions extend along the first direction Z. The first spacer structure 312 and the first drain structure 315 are located within the second cavity Q2 of the first channel structure 311, that is, the first spacer structure 312 and the first drain structure 315 are located between the two portions of the hollow cylindrical first channel structure 311. The first channel structure 311 is also connected to the second conductor layer 301 having a second preset depth in the stacked structure 10 along the first direction Z. As shown in Figures 16 to 29, the multiple layers of first conductor layers 201 and the multiple layers of second conductor layers 301 are arranged in sequence along the first direction Z and away from the substrate, and the second preset depth is less than the first preset depth. That is, as shown in Figures 16 to 29, any layer of the second conductor layer 301 is located above any layer of the first conductor layer 201 along the first direction Z.

[0077] In some examples, the first channel structure 311 may be made of a conductive material, which may include single crystal silicon, polycrystalline silicon, etc., such as N-type doped polycrystalline silicon, P-type doped polycrystalline silicon.

[0078] In some embodiments, a dimension CD1 of the first channel structure 311 along a second direction X is greater than a dimension CD2 of the capacitor structure 210 along the first direction Z, and the second direction X intersects the first direction Z.

[0079] In some examples, as shown in FIG12 , a dimension CD1 of the first channel structure 311 along the second direction X is larger than a dimension CD2 of the capacitor structure 210 along the first direction Z. This ensures a certain safety distance between the first channel structure 311 and the dielectric layer 211 of each storage capacitor 214 in the capacitor structure 210 to prevent electrical breakdown.

[0080] In some embodiments, a dimension H1 of the first gate structure 313 in the first direction Z is greater than a dimension H2 of the second conductor layer 301 to which the first gate structure 313 is connected in the first direction Z.

[0081] In some examples, as shown in FIG17 , the dimension of the first gate structure 313 in the first direction Z is greater than the dimension of the second conductor layer 301 connected to the first gate structure 313 in the first direction Z. The first channel structure 311 can be divided into three parts along the first direction Z. The first part 4151 to the third part 4153 are sequentially arranged along the first direction Z in a direction close to the capacitor structure 210, that is, the first part 4151 is located above the second part 4152 along the first direction Z, and the second part 4152 is located above the third part 4153 along the first direction Z. The first part 41513111 of the first channel structure 311 is connected to the first drain structure 315. Thus, the first part 41513111 of the first channel structure 311 can serve as part of the first drain structure 315. The second portion 41523112 of the first channel structure 311 is connected to the second dielectric layer 302. In this way, a certain fixed voltage can be applied to the first gate structure 313 connected thereto via the plate line PL (PL), so that holes can be kept in the first channel structure 311 during storage (write) operations, thereby reducing hole leakage when the voltage of the first gate structure 313 changes.

[0082] The third portion 41533113 of the first channel structure 311 is connected to the first conductor layer 201. As shown in FIG17 , the first conductor layer 201 can serve as a first source structure 600 commonly used by two first transistor structures 310 in adjacent semiconductor structures 20 arranged along the second direction X. In other words, the two first transistor structures 310 in adjacent semiconductor structures 20 arranged along the second direction X share a common source. For example, as shown in FIG16 to FIG29 , the leftmost first transistor structure 310 shares a common source with the middle first transistor structure 310, and the sidemost first transistor structure 310 shares a common source with the middle first transistor structure 310.

[0083] It should be noted that Figures 2 to 29 are part of the structural schematic diagram of the semiconductor device of the present application. Therefore, as shown in Figures 16 to 29, in addition to the adjacent first transistors sharing the first source structure, the first source structure in the semiconductor device can serve as the common source of all first transistors in the semiconductor device.

[0084] In some embodiments, the first isolation structure 314 includes an isolation groove structure 3141 and a dielectric material layer 3142 located in the isolation groove structure 3141 , and a size of the first drain structure 315 along the second direction X is larger than a size of the dielectric material layer 3142 along the second direction X.

[0085] In some examples, as shown in FIG. 14 to FIG. 29 , the first isolation structure 314 includes an isolation groove structure 3141 and a dielectric material layer 3142. The dielectric material layer 3142 is located within the isolation groove structure 3141. Both the isolation groove structure 3141 and the dielectric material layer 3142 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the isolation groove structure 3141 may be made of silicon nitride, and the dielectric material layer 3142 may be made of silicon oxide and / or silicon oxynitride.

[0086] In some embodiments, the second transistor structure 410 includes:

[0087] A second source structure 411 connected to the first end surface 3159 of the first drain structure 315 along the first direction Z.

[0088] In some examples, as shown in Figures 23 to 29, the second transistor structure 410 includes a second source structure 411. The second source structure 411 includes a first side 4119 (i.e., an upper surface or top surface) away from the substrate 100 along the first direction Z and a second side 4110 (i.e., a lower surface or bottom surface) closer to the substrate 100 along the first direction Z. The second side 4110 (i.e., a lower surface or bottom surface) along the first direction Z of the second source structure 411 is in contact with and connected to the first end surface (i.e., an upper surface or top surface) of the first drain structure 315 in the first transistor structure 310 shown in Figures 16 to 29 along the first direction Z. It should be noted that the size of the second source structure 411 along the second direction X is smaller than the size of the first drain structure 315 along the second direction X. The material of the second source structure 411 may include a conductive material, and the conductive material may include single crystal silicon, polycrystalline silicon, etc.

[0089] A second isolation structure 413 connected to a first side 4119 of the second source structure 411 along the first direction Z.

[0090] In some examples, please continue to refer to Figures 23 to 29, the second transistor structure 410 also includes a second isolation structure 413, and the second isolation structure 413 includes a first sidewall 4139 (i.e., upper surface or top surface) away from the substrate 100 along the first direction Z and a second sidewall 4130 (i.e., lower surface or bottom surface) close to the substrate 100 along the first direction Z. The second isolation structure 413 is located on the side of the first transistor structure 310 shown in Figures 16 to 29 away from the substrate 100 or the capacitor structure 210, and the first side edge 4119 (i.e., upper surface or top surface) of the second source structure 411 along the first direction Z is in contact with the second sidewall 4130 (i.e., lower surface or bottom surface) of the second isolation structure 413 along the first direction Z. It should be noted that the size of the second isolation structure 413 along the second direction X can be less than or equal to the size of the second source structure 411 along the second direction X. The second isolation structure 413 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0091] A second drain structure 414 connected to the first sidewall 4139 of the second isolation structure 413 along the first direction Z.

[0092] In some examples, referring to Figures 23 to 29 , the second transistor structure 410 further includes a second drain structure 414, which includes a first end 4149 (i.e., an upper surface or top surface) away from the substrate 100 along the first direction Z and a second end 4140 (i.e., a lower surface or bottom surface) closer to the substrate 100 along the first direction Z. The second drain structure 414 is located on a side of the second isolation structure 413 shown in Figures 7 to 29 that is away from the substrate along the first direction Z, and a first sidewall 4139 (i.e., an upper surface or top surface) of the second isolation structure 413 along the first direction Z is in contact with the second end 4140 (i.e., a lower surface or bottom surface) of the second drain structure 414 along the first direction Z. It should be noted that the dimension of the second drain structure 414 along the second direction X can be less than or equal to the dimension of the second isolation structure 413 along the second direction X. The material of the second drain structure 414 may include a conductive material, such as single crystal silicon, polycrystalline silicon, or the like.

[0093] a second channel structure 415 surrounding the second source structure 411 , the second isolation structure 413 and the second drain structure 414 .

[0094] In some examples, referring to Figures 23 to 29 , the second transistor structure 410 further includes a second channel structure 415 , wherein the second channel structure 415 is located on a side of the first transistor structure 310 shown in Figures 7 to 29 away from the substrate, and the second channel structure 415 is arranged around the second source structure 411 , the second isolation structure 413 , and the second drain structure 414 . That is to say, the second channel structure 415 includes a third cavity Q3, so that the second channel structure 415 is a hollow columnar structure, the hollow columnar second channel structure 415 includes two parts arranged opposite to each other along the second direction X, the two parts extend along the first direction Z, and the second source structure 411, the second isolation structure 413 and the second drain structure 414 are located within the third cavity Q3 of the second channel structure 415, that is, the second source structure 411, the second isolation structure 413 and the second drain structure 414 are located between the two parts of the hollow columnar second channel structure 415, and the sum of the projection sizes of the second source structure 411 along the first direction Z, the projection of the second isolation structure 413 along the first direction Z and the projection size of the second drain structure 414 along the first direction Z is located within the projection range of the second channel structure 415 along the first direction Z. In some examples, the second channel structure 415 may be made of a conductive material, which may include single crystal silicon, polycrystalline silicon, etc., such as N-type doped polycrystalline silicon, P-type doped polycrystalline silicon.

[0095] The second spacer structure 412 surrounds the second channel structure 415 . The second spacer structure 412 is connected to the third conductor layer 401 . The portion of the third conductor layer 401 connected to the second spacer structure 412 serves as a second gate structure of the second transistor structure 410 .

[0096] In some examples, referring to Figures 23 to 29 , the second transistor structure 410 further includes a second spacer structure 412, wherein the second spacer structure 412 is located on a side of the first transistor structure 310 shown in Figures 7 to 29 away from the substrate, and the second spacer structure 412 is disposed around the second channel structure 415. Specifically, the second spacer structure 412 includes a fourth cavity Q4, such that the second channel structure 415 is a hollow columnar structure. The hollow columnar second spacer structure 412 includes two portions disposed opposite each other along the second direction X, both portions extending along the first direction Z. The second channel structure 415 is located within the fourth cavity Q4 of the second spacer structure 412, i.e., the second channel structure 415 is located between the two portions of the hollow columnar second spacer structure 412. It should be noted that the dimension of the second spacer structure 412 along the second direction X can be smaller than the dimension of the first drain structure 315 along the second direction X, and even smaller than the dimension of the first isolation structure 314 along the second direction X. The second spacer structure 412 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0097] In some examples, the second spacing structure 412 is also connected to the third conductor layer 401 having a third preset depth in the stacked structure 10 along the first direction Z. As shown in Figures 23 to 29, the multi-layer first conductor layer 201, the multi-layer second conductor layer 301 and the multi-layer third conductor layer 401 are arranged in sequence along the first direction Z and away from the substrate. The third preset depth is less than the second preset depth, and the second preset depth is less than the first preset depth. That is, with reference to Figures 23 to 29, any layer of the third conductor layer 401 is located above any layer of the second conductor layer 301 along the first direction Z.

[0098] In some examples, as shown in FIG23 , the second channel structure 415 can be divided into three portions along the first direction Z. The first portion 4151 to the third portion 4153 are sequentially arranged along the first direction Z in a direction close to the first transistor structure 310. That is, the first portion 4151 is located above the second portion 4152 along the first direction Z, and the second portion 4152 is located above the third portion 4153 along the first direction Z. The first portion 4151 of the second channel structure 415 is connected to the second drain structure 414. Thus, the first portion 4151 of the second channel structure 415 can serve as part of the second drain structure 414. The second portion 4152 of the second channel structure 415 is connected to the third dielectric layer 402. Thus, when a certain voltage is applied to the first gate structure 313 via a word line, the second channel structure 415 can be turned on, thus achieving a gating function. The third portion 4153 of the second channel structure 415 is connected to the third conductor layer 401. As shown in FIG23 , the third conductor layer 401 can serve as a second gate structure 700 commonly used by two second transistor structures 410 in adjacent semiconductor structures 20 arranged along the second direction X. In other words, the two second transistor structures 410 in adjacent semiconductor structures 20 arranged along the second direction X share a common gate. For example, as shown in FIG23 to FIG29 , the leftmost second transistor structure 410 shares a common gate with the middle second transistor structure 410, and the sidemost second transistor structure 410 shares a common gate with the middle second transistor structure 410.

[0099] In some embodiments, the orthographic projection of the second spacer structure 412 on the stacked structure 10 is located within the area surrounded by the outer side surface of the first channel structure 311 , and the outer side surface of the second spacer structure 412 is spaced a preset distance from the outer side surface of the first channel structure 311 .

[0100] In some examples, the orthographic projection of the second spacer structure 412 on the stacked structure 10 is located within the area enclosed by the outer side surface of the first channel structure 311. That is, the dimension of the second spacer structure 412 along the second direction X is smaller than the spacing between the two parts of the first channel structure 311 along the second direction X. In addition, the outer side surface of the second spacer structure 412 is spaced a preset distance from the outer side surface of the first channel structure 311, so that the dimension of the first channel structure 311102 of the first transistor structure 310 along the second direction X is set to the dimension of the second channel structure 415 of the second transistor structure 410 along the second direction X. In this way, not only can the gating rate of the second gate structure in the second transistor structure 410 be improved, but also the hole storage capacity of the first channel structure 311 in the first transistor structure 310 can be increased, thereby improving the storage capacity of the semiconductor device.

[0101] In some embodiments, the semiconductor device includes a core region A and a connection region T arranged along a second direction X, the semiconductor structure 20 is located in the core region A, the second direction X intersects the first direction Z; the connection region T includes:

[0102] a plurality of first lead-out structures 504 extending in the stacked structure 10 along the first direction Z, wherein the plurality of first lead-out structures 504 are arranged at intervals in the second direction X;

[0103] Each of the first lead-out structures 504 is respectively connected to the conductor layer at a preset depth.

[0104] In some examples, as shown in FIG. 26 , the semiconductor device includes a core region A and a connection region T arranged along a second direction X, wherein the plurality of semiconductor structures 20 in the above-described embodiment are located in the core region A, and the spacing between the plurality of semiconductor structures 20 arranged along the second direction X in the core region A can be the same or different. The connection region T includes a plurality of first lead-out structures 504, wherein the first lead-out structures 504 extend along the first direction Z in the connection region T of the stacked structure 10, and the plurality of first lead-out structures 504 are spaced apart in the second direction X, and the spacing between the plurality of first lead-out structures 504 arranged along the second direction X in the connection region T can be the same or different. Each of the first lead-out structures 504 is respectively connected to the plurality of first conductor layers 201, the plurality of second conductor layers 301, and the plurality of third conductor layers 401.

[0105] In some embodiments, the first lead-out structure 504 includes:

[0106] a conductive contact portion 541 extending along the first direction Z; and

[0107] An insulating barrier layer 542 surrounds the conductive contact portion 541 .

[0108] In some examples, please continue to refer to FIG. 26 , the material of the first lead-out structure 504 may include a conductive contact portion 541 extending along the first direction Z and an insulating barrier layer 542 extending along the first direction Z, wherein the insulating barrier layer 542 is disposed around the conductive contact portion 541 .

[0109] In some examples, the conductive contact portion 541 can be made of a conductive material, including but not limited to poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and any combination thereof. The insulating barrier layer 542 can be made of an insulating material, including but not limited to silicon nitride, silicon oxide, and aluminum oxide, and any combination thereof.

[0110] In some embodiments, the semiconductor device further comprises:

[0111] a protective layer 500 covering one side of the stacked structure 10 along the first direction Z;

[0112] A third lead-out structure 501 extends in the protection layer 500 along the first direction Z and is connected to the second drain structure 414 in the second transistor structure 410 .

[0113] In some examples, as shown in Figures 25 and 26 , a protective layer 500 is provided on a surface of the stacked structure 10 facing away from the substrate along the first direction Z. The protective layer 500 can be made of an insulating material, which can include, but is not limited to, any one of silicon nitride, silicon oxide, and aluminum oxide, or any combination thereof. The semiconductor device further includes a third lead-out structure 501 located on each second drain structure 414, i.e., multiple third lead-out structures 501 are connected to a corresponding number of second drain structures 414 in a one-to-one correspondence.

[0114] In an embodiment of the present application, as shown in FIG. 26 , the semiconductor device includes a third lead-out structure 501 extending along a first direction Z and connected to each second drain structure 414 in the core region A, and a first lead-out structure 504 extending along the first direction Z and connected to each conductor layer (e.g., including multiple first conductor layers 201, second conductor layer 301, and third conductor layer 401) in the connection region T. Each second drain structure 414 is connected to a bit line BL via a third lead-out structure 501, thereby connecting each semiconductor structure 20 to a bit line BL. The bottoms of the first channel structures 311 of the first transistor structures 310 in the multiple semiconductor structures 20 are commonly connected to the second conductor layer 301, which serves as the first source structure. In other words, they share a common source layer. The first lead-out structure 504 connected to the second conductor layer 301 can be connected to a land line PL. Thus, the multiple first transistor structures 310 are connected to a land line PL via the first lead-out structure 504 connected to the second conductor layer 301. The bottoms of the second channel structures 415 of the second transistor structures 410 in the multiple semiconductor structures 20 are commonly connected to the third conductor layer 401 serving as the second gate structure, i.e., they share a common gate layer. The first lead-out structure 504 connected to the third conductor layer 401 can be connected to a word line. In this way, the multiple second transistor structures 410 are connected to a word line via the first lead-out structure 504 connected to the third conductor layer 401, thereby achieving better gate control capability and improving switching speed.

[0115] In some embodiments, the semiconductor device includes a core area A and a step area SS arranged along a second direction X, the semiconductor structure 20 is located in the core area A, the second direction X intersects the first direction Z; the step area SS includes a plurality of step structures 800;

[0116] The lengths of the plurality of step structures 800 along the second direction X vary gradually; the step structures 800 include at least one conductor layer and at least one dielectric layer;

[0117] a plurality of second lead-out structures 502 extending along the first direction Z, wherein the plurality of second lead-out structures 502 are arranged at intervals in the second direction X;

[0118] Each of the second lead-out structures 502 is respectively connected to the conductor layer in the step structure 800 of a preset depth.

[0119] In some examples, as shown in FIG. 29 , a semiconductor device includes a core region A and a step region SS arranged along a second direction X. The plurality of semiconductor structures 20 described in the above embodiments are located in the core region A, and the spacing between the plurality of semiconductor structures 20 arranged along the second direction X in the core region A can be the same or different. The step region SS includes a plurality of second lead-out structures 502, wherein the first lead-out structure 504 extends along the first direction Z in the step region SS of the stacked structure 10, and the plurality of second lead-out structures 502 are spaced apart in the second direction X. The spacing between the plurality of second lead-out structures 502 arranged along the second direction X in the step region SS can be the same or different. Each second lead-out structure 502 is connected to the plurality of first conductor layers 201, the plurality of second conductor layers 301, and the plurality of third conductor layers 401, respectively.

[0120] In some examples, the second lead-out structure 502 can be made of a conductive material, which may include but is not limited to poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and any other conductive materials, or any combination of multiple materials.

[0121] In some embodiments, the semiconductor device further comprises:

[0122] a protective layer 500 covering one side of the stacked structure 10 along the first direction Z and a predetermined area within the step region SS; the predetermined area includes an area within the step region SS excluding the step structure 800 and the second lead-out structure 502;

[0123] A third lead-out structure 501 extends in the protection layer 500 along the first direction Z and is connected to the second drain structure 414 in the second transistor structure 410 .

[0124] In some examples, as shown in Figures 27 and 29, a protective layer 500 is provided on a surface of the stacked structure 10 facing away from the substrate along the first direction Z. Furthermore, a protective layer 500 is also provided on the area within the step region SS excluding the step structure 800 and the second lead structure 502. The protective layer 500 can be made of an insulating material, which can include, but is not limited to, any one of silicon nitride, silicon oxide, and aluminum oxide, or any combination thereof. The semiconductor device further includes a third lead structure 501 located on each second drain structure 414, i.e., multiple third lead structures 501 are connected to a corresponding number of second drain structures 414 in a one-to-one correspondence.

[0125] In an embodiment of the present application, as shown in FIG. 29 , the semiconductor device includes a third lead-out structure 501 extending along a first direction Z and connected to each second drain structure 414 in the core region A, and a second lead-out structure 502 extending along the first direction Z and connected to each conductor layer (e.g., including multiple first conductor layers 201, second conductor layer 301, and third conductor layer 401) in the step region SS. Each second drain structure 414 is connected to a bit line BL via a third lead-out structure 501, thereby connecting each semiconductor structure 20 to a bit line BL. The bottoms of the first channel structures 311 of the first transistor structures 310 in the multiple semiconductor structures 20 are commonly connected to the second conductor layer 301, which serves as the first source structure. In other words, they share a common source layer. The second lead-out structure 502 connected to the second conductor layer 301 can be connected to a land line PL. Thus, the multiple first transistor structures 310 are connected to a land line PL via the second lead-out structure 502 connected to the second conductor layer 301. The bottoms of the second channel structures 415 of the second transistor structures 410 in the multiple semiconductor structures 20 are commonly connected to the third conductor layer 401 serving as the second gate structure, i.e., they share a common gate layer. The second lead-out structure 502 connected to the third conductor layer 401 can be connected to a word line. In this way, the multiple second transistor structures 410 are connected to a word line through the second lead-out structure 502 connected to the third conductor layer 401, thereby achieving better gate control capability and improving switching speed.

[0126] Please refer to Figure 29, which shows an equivalent circuit diagram of multiple storage capacitors 214, a first transistor structure 310, and a second transistor structure 410 in a storage unit in Figure 26 or Figure 29 of the above-mentioned embodiment of the present application. Figure 29 exemplarily shows three storage capacitors 214. Of course, it can also include two storage capacitors 214, or more storage capacitors 214. Exemplarily, the first transistor structure 310 is connected to one end of the multiple storage capacitors 214 (for example, the first electrode 212 of the storage capacitor 214), and the other end of each storage capacitor 214 (for example, the dielectric layer 211 of the storage capacitor 214) is electrically connected to the first conductor layer 201.

[0127] It should be noted that, in the embodiment of the present application, the stacked structure 10 may include a plurality of stacked layers sequentially stacked along the first direction Z, such as the first stacked layer 200, the second stacked layer 300, and the third stacked layer 400 shown in Figures 26 and 29. The first stacked layer 200 may include a plurality of first conductor layers 201 and a plurality of first dielectric layers 202 alternately connected along the first direction Z, the second stacked layer 300 may include a second conductor layer 301 and a second dielectric layer 302 alternately connected along the first direction Z, and the third stacked layer 400 may include a third conductor layer 401 and a third dielectric layer 402 alternately connected along the first direction Z. The thicknesses of the multiple first dielectric layers 202 in the first stack 200 (i.e., the extension along the first direction Z, hereinafter referred to as thickness) can be substantially the same or different; the thicknesses of the multiple first conductor layers 201 in the first stack 200 can be substantially the same or different; the thicknesses of the first conductor layer 201, the second conductor layer 301, and the third conductor layer 401 can be substantially the same or different; similarly, the thicknesses of the first dielectric layer 202, the second dielectric layer 302, and the third dielectric layer 402 can be substantially the same or different, and can be selected based on actual needs. In addition, the number of stacked layers of the first conductor layers 201 in the first stack 200 determines the number of storage capacitors 214 corresponding to the same semiconductor structure 20 described in the above embodiment; the number of stacked layers of the first stack 200 can be, for example, 32 layers, 64 layers, 96 layers, 128 layers, etc. The more stacked layers of the first stack 200, the higher the integration level, i.e., the greater the number of storage capacitors 214. The number of stacking layers and the stacking height of the first conductor layer 201 in the first stacking layer 200 can be designed according to actual storage requirements, and this application does not impose any specific restrictions on this.

[0128] By providing multiple stacked first conductive layers 201, a portion of each first conductive layer 201 surrounding the dielectric layer 211, and a portion of the dielectric layer 211 and the first electrode 212 opposite the first conductive layer 201 form a storage capacitor 214, thereby obtaining a memory cell comprising multiple storage capacitors 214, a first transistor structure 310, and a second transistor structure 410. One storage capacitor 214 can be used to store one bit of data, while multiple storage capacitors 214 can be used to store multiple bits of data. Thus, compared to the memory cell of the 1T1C structure in the prior art, the storage capacity of the semiconductor device 1000 is improved. On the other hand, in the embodiment of the present application, the second transistor structure 410, the first transistor structure 310, and the capacitor structure 210 (multiple storage capacitors 214) in the same semiconductor structure 20 are sequentially arranged and connected along the first direction Z, thereby achieving a vertical arrangement of the transistor structures and the capacitor structures 210 in the semiconductor structure 20, greatly improving the density of the storage capacitors 214, and improving the storage density of the semiconductor device.

[0129] FIG31 is a flow chart of a method for manufacturing a semiconductor device 1000 according to an embodiment of the present application. The specific flow chart, referring to the structural diagrams of FIG2 to FIG30 , may include the following steps:

[0130] S100 , forming a stacked structure 10 ; the stacked structure 10 includes alternatingly stacked conductor layers and dielectric layers.

[0131] A stacked structure 10 is provided as shown in Figures 26 and 28. The materials and number of layers of the conductor and dielectric layers included in the stacked structure 10 can be found in the descriptions of the aforementioned embodiments and will not be repeated here. For ease of description, the stacked structure 10 of the semiconductor device in the following embodiments includes the first stacked layer 200, the second stacked layer 300, and the third stacked layer 400 as described in Figures 2 to 28.

[0132] S200, forming at least one semiconductor structure 20 penetrating the stacked structure 10; the semiconductor structure 20 includes a capacitor structure 210, a first transistor structure 310, and a second transistor structure 410 extending in the stacked structure 10 along the first direction Z;

[0133] The second transistor structure 410 , the first transistor structure 310 , and the capacitor structure 210 in the same semiconductor structure 20 are sequentially arranged along the first direction Z and connected.

[0134] In some embodiments, the step S200 of forming at least one semiconductor structure 20 penetrating the stacked structure 10 specifically includes:

[0135] S210: Forming a capacitor structure 210 extending along the first direction Z in the stacked structure 10. As shown in Figures 2 to 7, a capacitor structure 210 extending along the first direction Z is formed in the first stacked layer 200 of the stacked structure 10. It should be noted that the number of first stacked layers 200 shown in the figures is only an example, and first stacked layers 200 with other numbers of layers are also within the scope of protection of this application.

[0136] In some embodiments, the step of forming the capacitor structure 210 extending along the first direction Z in the stacked structure 10 includes:

[0137] S211 , as shown in FIG. 2 to FIG. 4 , at least one first through hole K1 extending along the first direction Z is formed in the stack structure 10 .

[0138] In some examples, as shown in Figures 2 to 3, a first stacked layer 200 is formed on one side of the substrate 100 along the first direction Z. The first stacked layer 200 includes a plurality of first conductor layers 201 and a plurality of first dielectric layers 202 arranged alternately. In some examples, the first stacked layer 200 can be formed on the substrate 100 using a thin film deposition process. For example, the thin film deposition process can include a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Of course, the first stacked layer 200 can also include a fourth dielectric layer 203 located between the substrate and the first conductor layer 201. For relevant descriptions of the materials of the first conductor layer 201, the first dielectric layer 202, and the fourth dielectric layer 203, please refer to the descriptions in some of the above embodiments and will not be repeated here.

[0139] 4 , the plurality of first through holes K1 may be formed by a dry etching process or a wet etching process. The first through holes K1 may extend along the first direction Z toward the substrate 100 .

[0140] S212. As shown in Figures 5 to 7, a dielectric layer 211 and a first electrode 212 are formed in the first through hole K1 and arranged in sequence from the inside to the outside along the second direction X (X) to form the capacitor structure 210 extending along the first direction Z; the second direction X intersects the first direction Z; the dielectric layer 211 is connected to the first conductor layer 201 and is arranged between the first electrode 212 and the first conductor layer 201; the capacitor structure 210 includes a plurality of storage capacitors 214 arranged at intervals along the first direction Z; the third surface 2119 of the dielectric layer 211 along the first direction Z and the fourth surface 2129 of the first electrode 212 along the first direction Z are flush.

[0141] The description of the materials of the dielectric layer 211 and the first electrode 212 in the capacitor structure 210 and the multiple storage capacitors 214 can refer to the description in the above embodiments and will not be repeated here.

[0142] In some examples, both the dielectric layer 211 and the first electrode 212 can be formed by chemical vapor deposition (CVD), such as metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc. The dielectric layer 211 and the first electrode 212 can also be formed by atomic layer deposition (ALD), sputtering, evaporation, or any combination thereof.

[0143] S220 , forming a first transistor structure 310 in the stacked structure 10 , the first transistor structure 310 extending along the first direction Z and being in contact with the first surface 220 of the capacitor structure 210 along the first direction Z.

[0144] In some examples, as shown in Figures 8 to 16, a second stacked layer 300 is formed on a side of the first stacked layer 200 away from the capacitor structure 210 along the first direction Z. Then, a first transistor structure 310 connected to the capacitor structure 210 is formed in the third stacked layer 400. For a detailed process of forming the first transistor structure 310, see steps S221 to S226 in the embodiments below.

[0145] In some embodiments, the step of forming the first transistor structure 310 in the stacked structure 10 , which extends along the first direction Z and is in contact with the first surface 220 of the capacitor structure 210 along the first direction Z, includes:

[0146] S221 . Form at least one second through hole K2 extending along the first direction Z in the stack structure 10 .

[0147] In some examples, as shown in FIG8 , a second stacked layer 300 is formed on a side of the first stacked layer 200 away from the substrate along the first direction Z. The second stacked layer 300 includes alternating second conductor layers 301 and second dielectric layers 302. In some examples, the second stacked layer 300 can be formed on the first stacked layer 200 using a thin film deposition process. For example, the thin film deposition process can include a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). For details about the materials of the second conductor layer 301 and the second dielectric layer 302, refer to the descriptions in the aforementioned embodiments and are not further elaborated here.

[0148] 9 , the plurality of second through holes K2 may be formed by a dry etching process or a wet etching process. The second through holes K2 may extend along the first direction Z toward the substrate 100 .

[0149] S222. As shown in FIG10 , a first channel structure 311, a first spacer structure 312, and a first gate structure 313 are formed in the second through hole K2, which are arranged sequentially from the outside to the inside along the second direction X; the second direction X intersects the first direction Z; and the first gate structure 313 is in contact and connected with the first surface 220 of the capacitor structure 210 along the first direction Z.

[0150] In some examples, the first channel structure 311, the first spacer structure 312, and the first gate structure 313 can all be formed by chemical vapor deposition (CVD) (e.g., metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc.). The first channel structure 311, the first spacer structure 312, and the first gate structure 313 can also be formed by atomic layer deposition (ALD), sputtering, evaporation, or any combination thereof.

[0151] S223: As shown in FIG11 , remove a portion of the first gate structure 313. In some examples, a dry etching process or a wet etching process may be used to remove a portion of the first gate structure 313.

[0152] S224 , as shown in FIG. 11 , forming a first isolation structure 314 covering the first gate structure 313 .

[0153] In some examples, a thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof can be used to deposit the first isolation structure 314 in the groove formed after a portion of the first gate structure 313 is removed as shown in FIG. 11 .

[0154] S225. Remove a portion of the first spacer structure 312 so that a first surface 3129 of the first spacer structure 312 away from the capacitor structure 210 along the first direction Z is flush with a first end 3149 of the first isolation structure 314 away from the capacitor structure 210 along the first direction Z. In some examples, a dry etching process or a wet etching process can be used to remove a portion of the first spacer structure 312 away from the substrate along the first direction Z so that a first surface 3129 of the first spacer structure 312 away from the capacitor structure 210 along the first direction Z is flush with a first end 3149 of the first isolation structure 314 away from the capacitor structure 210 along the first direction Z.

[0155] S226. As shown in FIG12 , a first drain structure 315 is formed covering the first isolation structure 314 and the first spacer structure 312. A first end surface 3159 of the first drain structure 315 away from the capacitor structure 210 along the first direction Z is flush with a seventh surface 3119 of the first channel structure 311 away from the capacitor structure 210 along the first direction Z.

[0156] In which, the first channel structure 311 is connected to the second conductor layer 301, and the part of the second conductor layer 301 connected to the first channel structure 311 serves as the first source structure of the first transistor structure 310; the first spacer structure 312 is close to the second surface 3120 of the capacitor structure 210 along the first direction Z, the first channel structure 311 is close to the sixth surface 3110 of the capacitor structure 210 along the first direction Z, and the first gate structure 313 is close to the second side 3130 of the capacitor structure 210 along the first direction Z and is flush with the first surface 220 of the capacitor structure 210 along the first direction Z.

[0157] In some examples, the hollow cylindrical first channel structure 311 includes a sixth surface 3110 and a seventh surface 3119 arranged opposite to each other along the first direction Z, and the side of the first transistor structure 310 away from the capacitor structure 210 along the first direction Z is flush with the first surface 220 of the capacitor structure 210 along the first direction Z.

[0158] In some embodiments, the step of forming the first isolation structure 314 covering the first gate structure 313 includes:

[0159] forming a first isolation layer 3241 covering the stacked structure 10 and the first gate structure 313;

[0160] forming a second isolation layer 3242 on the first isolation layer;

[0161] removing a portion of the second isolation layer 3242 located in the stacked structure 10 and a portion of the second isolation layer 3242 located between the first spacing structures 312 and away from the stacked structure 10 ;

[0162] A portion of the first isolation layer 3241 located in the stacked structure 10 and a portion of the first isolation layer 3241 located between the first spacing structures 312 are removed.

[0163] In some examples, as shown in FIG13 , the first isolation layer 3241 and the second isolation layer 3242 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof, and portions of the first isolation layer 3241 and the second isolation layer 3242 may be removed by a dry etching process or a wet etching process.

[0164] S230 , forming a second transistor structure 410 in the stacked structure 10 , the second transistor structure 410 extending along the first direction Z and being in contact with a surface of the first transistor structure 310 away from the capacitor 210 structure along the first direction Z.

[0165] In some examples, as shown in Figures 17 to 23, a third stacked layer 400 is formed on a side of the second stacked layer 300 away from the capacitor structure 210 along the first direction Z, and then a second transistor structure 410 connected to the first transistor structure 310 is formed in the third stacked layer 400. The specific process of forming the first transistor structure 310 is described in steps S231 to S235 in the embodiments below.

[0166] In some embodiments, the step of forming the second transistor structure 410 in the stacked structure 10 in S230, which extends along the first direction Z and is in contact with a surface of the first transistor structure 310 away from the capacitor structure 210 along the first direction Z, includes:

[0167] S231 . Form at least one third through hole K6 extending along the first direction Z in the stack structure 10 .

[0168] In some examples, as shown in Figures 17 and 18, a third stacked layer 400 is formed on a side of the second stacked layer 300 away from the substrate along the first direction Z. The third stacked layer 400 includes alternating third plate line layers and third dielectric layers 402. In some examples, a thin film deposition process can be used to form the third stacked layer 400 on the second stacked layer 300. For example, the thin film deposition process can include a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). For details about the materials of the third plate line layer and the third dielectric layer 402, refer to the descriptions in the above embodiments and will not be repeated here.

[0169] 19 , the plurality of third through holes K6 may be formed by a dry etching process or a wet etching process. The third through holes K6 may extend along the first direction Z toward the substrate 100 .

[0170] S232. As shown in FIG20 , a second spacing structure 412 extending along the first direction Z is formed in the third through hole K6; the second spacing structure 412 is in contact and connected with the ninth surface 4120 of the capacitor structure 210 along the first direction Z and the first end surface 3159 of the first drain structure 315 away from the capacitor structure 210 along the first direction Z.

[0171] In some examples, the second spacer structure 412 can be formed by chemical vapor deposition (CVD) (e.g., metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc.).

[0172] S233. As shown in FIG21 , a second source structure 411 and a second channel structure 415 surrounding the second source structure 411 are formed between the two second spacing structures 412; the second source structure 411 is in contact and connected with the first end face 3159 of the first drain structure 315 away from the capacitor structure 210 along the first direction Z, close to the second side edge 4110 of the capacitor structure 210 along the first direction Z.

[0173] In some examples, the second source structure 411 and the second channel structure 415 can be formed by chemical vapor deposition (CVD) (e.g., metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc.).

[0174] S234. As shown in FIG22 , a second isolation structure 413 is formed between the second channel structures 415 ; the second isolation structure 413 is connected to the second sidewall 4130 of the capacitor structure 210 along the first direction Z and the first side edge 4119 of the second source structure 411 away from the capacitor structure 210 along the first direction Z.

[0175] In some examples, the second isolation structure 413 can be formed by chemical vapor deposition (CVD) (e.g., metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc.).

[0176] S235. As shown in FIG. 23 , a second drain structure 414 is formed between the second channel structures 415 . The second drain structure 414 is connected to a second end 4140 of the second drain structure 414 close to the capacitor structure 210 along the first direction Z and to a first sidewall 4139 of the second isolation structure 413 away from the capacitor structure 210 along the first direction Z.

[0177] Among them, the second spacing structure 412 is flush with the tenth surface 4129 of the capacitor structure 210 along the first direction Z, the second channel structure 415 is flush with the thirteenth surface 4159 of the capacitor structure 210 along the first direction Z, and the second drain structure 414 is flush with the first end 4149 of the capacitor structure 210 along the first direction Z.

[0178] In some embodiments, the stacked structure 10 includes a core region A and a connection region T arranged along a second direction X, where the second direction X intersects the first direction Z; and the method further includes:

[0179] forming a plurality of fifth through holes K8 in the connection area T;

[0180] A first lead-out structure 504 is formed in the fifth through hole K8; the first lead-out structure 504 extends in the stacked structure 10 along the first direction Z, and the multiple first lead-out structures 504 are arranged at intervals in the second direction X, and each of the first lead-out structures 504 is respectively connected to the conductor layer of a preset depth.

[0181] Specifically, as shown in Figures 24, 25, and 26, a thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof can be used to form a protective layer 500 on one surface of the third stacked layer 400 in the stacked structure 10 along the first direction Z. A dry or wet etching process can be used to remove a portion of the protective layer 500 within the connection region T of the stacked structure 10 along the first direction Z, as well as a portion of the conductor layer and the dielectric layer within the connection region T of the stacked structure 10, to form a plurality of fifth through holes K8 arranged in a stair-like pattern and spaced apart in synchronization with both the first direction Z and the second direction X. A thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof is used to deposit a first lead structure 504 extending in the first direction Z within each of the fifth through holes K8. Because each first lead structure 504 is connected to the conductor layer in the connection region T at a predetermined depth, the plurality of first lead structures 504 formed within the connection region T are arranged in a stair-like pattern and spaced apart in synchronization with both the first direction Z and the second direction X.

[0182] In some embodiments, the stacked structure 10 includes a core area A and a step area SS arranged along the second direction X, and the method further includes:

[0183] Removing part of the conductor layer and part of the dielectric layer in the stacked structure 10 to form a plurality of step structures 800, such that the dimensions of the plurality of step structures 800 along the first direction Z and the second direction X vary in a step-like manner;

[0184] A sixth through hole K9 is formed above the step structure 800;

[0185] A second lead-out structure 502 is formed in the sixth through hole K9 . The second lead-out structure 502 extends in the stacked structure 10 along the first direction Z, and the plurality of second lead-out structures 502 are arranged at intervals in the second direction X.

[0186] Specifically, as shown in Figures 24, 27 and 28, a thin film deposition process such as chemical vapor deposition CVD, PVD, ALD or any combination thereof can be used to form a protective layer 500 on one side of the third stacking layer 400 in the stacking structure 10 along the first direction Z, and then a dry etching process or a wet etching process is used to remove part of the conductor layer and part of the dielectric layer in the step area SS in the stacking structure 10 along the first direction Z to form a plurality of step structures 800.

[0187] A dry or wet etching process can be used to remove a portion of the step structure 800 and a portion of the protective layer 500 covering the step structure 800, thereby forming a plurality of sixth through holes K9 that are synchronously spaced and arranged in a stair-like distribution along the first direction Z and the second direction X. A thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof is used to deposit a second lead-out structure 502 extending along the first direction Z in each of the sixth through holes K9. Because each second lead-out structure 502 is respectively connected to the conductor layer in the step structure 800 at a predetermined depth, the plurality of second lead-out structures 502 formed in the step region SS are synchronously spaced and arranged in a stair-like distribution along the first direction Z and the second direction X.

[0188] In some embodiments, the method further comprises:

[0189] forming a protective layer 500 on one side of the stacked structure 10 along the first direction Z;

[0190] forming a plurality of fourth through holes K7 in the protection layer 500 above the second transistor structure 410;

[0191] A third lead-out structure 501 is formed in the fourth through hole K7 . The third lead-out structure 501 extends along the first direction Z and is connected to the second drain structure 414 in the second transistor structure 410 .

[0192] Specifically, as shown in Figures 24 and 25, or as shown in Figures 24 and 27, a thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof can be used to form a protective layer 500 on one side of the third stacked layer 400 in the stacked structure 10 along the first direction Z. A dry etching process or a wet etching process can be used to remove a portion of the protective layer 500 above the second transistor structure 410 along the first direction Z to form a seventh through hole K7, and the orthographic projection of the seventh through hole K7 along the second direction X is located within the range of the orthographic projection of the second transistor structure 410 along the second direction X. A thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof is used to form a third lead structure 501 in the fourth through hole K7.

[0193] The semiconductor device 1000 can be a three-dimensional memory (3D NAND Flash), and the semiconductor device 1000 can also be a part of a three-dimensional memory. When the semiconductor device 1000 is a three-dimensional memory, it also includes an array storage structure (Array) and a peripheral circuit (Periphery Circuit). The semiconductor device 1000 of any of the above items is located in the array storage structure. The array storage structure is used to store information, and the peripheral circuit can be located above or below the array storage structure, or can be located around the array storage structure. The peripheral circuit is used to control the corresponding array storage structure. In addition, the semiconductor device 1000 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation. In addition, the semiconductor device 1000 of the embodiment of the present invention can be a three-dimensional memory, or can be a part of a peripheral memory, without special limitation.

[0194] As shown in FIG32 , an embodiment of the present invention further provides a storage system including a controller 330 and a three-dimensional memory 320 . The controller 330 is coupled to the three-dimensional memory 320 and is used to control the three-dimensional memory 320 to store data. The three-dimensional memory 320 includes any one of the semiconductor devices 1000 described above.

[0195] Specifically, as shown in FIG32 , the storage system 30 includes a controller 330 and one or more three-dimensional memories 320, wherein the three-dimensional memories 320 include one or more array storage structures 321 and peripheral circuits 322. The storage system 30 can communicate with the host 40 via the controller 330, wherein the controller 330 can be connected to the one or more three-dimensional memories 320 via channels in the one or more three-dimensional memories 320. Each three-dimensional memory 320 can be managed by the controller 330 via the channels in the three-dimensional memory 320.

[0196] The storage system 30 can be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 30 can be applied to and packaged into the above-mentioned electronic devices. The storage system 30 can be integrated into a memory card, for example, or into a solid-state drive (SSD).

[0197] Among them, the memory card includes one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0198] In some examples, in the storage system 30, the controller 330 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0199] In other examples, in the storage system 30 , the controller 330 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0200] In some examples, the controller 330 may be configured to manage data stored in the three-dimensional memory 320 and communicate with an external device (eg, a host).

[0201] In some examples, the controller 330 may also be configured to control operations of the three-dimensional memory 320 , such as read, erase, and program operations.

[0202] In some examples, the controller 330 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 320 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0203] In some examples, the controller 330 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 320 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0204] In some examples, the controller 330 is also configured to process error correction codes on data read from or written to the three-dimensional memory 320 .

[0205] It is easy to understand that the controller 330 can also perform any other suitable functions, such as formatting the 3D memory 320. For another example, the controller 330 can communicate with an external device (eg, a host) via at least one of various interface protocols.

[0206] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0207] The controller 330 may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0208] It should be noted that the above-mentioned peripheral circuit 322 includes one or more peripheral devices. Specifically, the above-mentioned peripheral devices may include, for example, a page buffer, a decoder (for example, a row decoder and a column decoder), a read amplifier, a driver (for example, a word line driver) and at least one of any active (or passive) components of the circuit (for example, transistors, diodes, resistors and storage capacitors 214, etc.).

[0209] The peripheral devices may also include any other circuits compatible with advanced logic processes. Exemplarily, the peripheral devices include logic circuits (eg, processors and programmable logic devices) and / or storage circuits (eg, static random access memories).

[0210] The above is a detailed introduction to a semiconductor device 1000 and its manufacturing method, and a storage system 30 provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor device, wherein: include: Stacked structure; The stacked structure comprises conductor layers and dielectric layers alternately stacked along a first direction; at least one semiconductor structure extending through the stacked structure; The semiconductor structure comprises: a capacitor structure, a first transistor structure, and a second transistor structure extending in the stacked structure along the first direction; The second transistor structure, the first transistor structure and the capacitor structure in the same semiconductor structure are sequentially arranged and connected along the first direction.

2. The semiconductor device according to claim 1, wherein The capacitor structure includes: a plurality of storage capacitors, and the plurality of storage capacitors are arranged at intervals along the first direction.

3. The semiconductor device according to claim 2, wherein: The storage capacitor includes: a first electrode and a dielectric layer, wherein the dielectric layer is connected to the first conductor layer and is arranged between the first electrode and the first conductor layer.

4. The semiconductor device according to claim 3, wherein: The first electrode includes multiple layers of sub-electrodes along a radial direction of the capacitor structure, and the radial direction intersects with the first direction.

5. The semiconductor device according to claim 1, wherein The first transistor structure comprises: a first gate structure connected to a first surface of the capacitor structure along the first direction; a first isolation structure connected to a first side of the first gate structure along the first direction; a first spacing structure surrounding the first gate structure and the first isolation structure; a first drain structure connected to a first end of the first isolation structure along the first direction and a first surface of the first spacing structure along the first direction; a first channel structure surrounding the first spacer structure and the first drain structure; The first channel structure is connected to the second conductor layer, and a portion of the second conductor layer connected to the first channel structure serves as a first source structure of the first transistor structure.

6. The semiconductor device according to claim 5, wherein: A size of the first channel structure along a second direction is greater than a size of the capacitor structure along the first direction, and the second direction intersects the first direction.

7. The semiconductor device according to claim 5, wherein: A size of the first gate structure in the first direction is greater than a size of a second conductor layer connected to the first gate structure in the first direction.

8. The semiconductor device according to claim 6, wherein: The first isolation structure includes an isolation groove structure and a dielectric material layer located in the isolation groove structure. The size of the first drain structure along the second direction is greater than the size of the dielectric material layer along the second direction.

9. The semiconductor device according to claim 5, wherein: The second transistor structure comprises: a second source structure connected to a first end surface of the first drain structure along the first direction; a second isolation structure connected to a first side of the second source structure along the first direction; a second drain structure connected to a first sidewall of the second isolation structure along the first direction; a second channel structure surrounding the second source structure, the second isolation structure and the second drain structure; A second spacing structure surrounds the second channel structure, the second spacing structure is connected to a third conductor layer, and a portion of the third conductor layer connected to the second spacing structure serves as a second gate structure of the second transistor structure.

10. The semiconductor device according to claim 9, wherein The orthographic projection of the second spacing structure on the stacked structure is located in a region surrounded by an outer side surface of the first channel structure, and the outer side surface of the second spacing structure is spaced apart from the outer side surface of the first channel structure by a preset distance.

11. The semiconductor device according to claim 3, wherein: The material of the dielectric layer includes any one or more of ferroelectric materials and antiferroelectric materials.

12. The semiconductor device according to claim 4, wherein: The material of the sub-electrode includes any one or more of titanium nitride and polysilicon.

13. The semiconductor device according to any one of claims 1 to 12, wherein: The semiconductor device comprises a core region and a connection region arranged along a second direction, the semiconductor structure is located in the core region, the second direction intersects the first direction; the connection region comprises: a plurality of first lead-out structures extending in the stacked structure along the first direction, and the plurality of first lead-out structures are arranged at intervals in the second direction; Each of the first lead-out structures is respectively connected to the conductor layer at a preset depth.

14. The semiconductor device according to claim 13, wherein: The first lead-out structure comprises: a conductive contact portion extending along the first direction; and An insulating barrier layer surrounds the conductive contact.

15. The semiconductor device according to claim 14, wherein: Also includes: a protective layer covering one side of the stacked structure along the first direction; A third lead-out structure extends in the protection layer along the first direction and is connected to the second drain structure in the second transistor structure.

16. The semiconductor device according to any one of claims 1 to 12, wherein: The semiconductor device comprises a core region and a step region arranged along a second direction, the semiconductor structure is located in the core region, the second direction intersects the first direction; the step region comprises a plurality of step structures; The lengths of the plurality of step structures along the second direction vary gradually; the step structures include at least one conductor layer and at least one dielectric layer; a plurality of second lead-out structures extending along the first direction, and the plurality of second lead-out structures are arranged at intervals in the second direction; Each of the second lead-out structures is respectively connected to the conductor layer in the step structure of a preset depth.

17. The semiconductor device according to claim 16, wherein: Also includes: A protective layer covering one side of the stacked structure along the first direction and a preset area within the step area; The preset area includes an area in the step area except the step structure and the second lead-out structure; A third lead-out structure extends in the protection layer along the first direction and is connected to the second drain structure in the second transistor structure.

18. A method for manufacturing a semiconductor device, wherein: The method comprises: Forming a stacked structure; the stacked structure includes staggered and stacked conductor layers and dielectric layers; forming at least one semiconductor structure penetrating the stacked structure; the semiconductor structure comprising a capacitor structure, a first transistor structure, and a second transistor structure extending in the stacked structure along the first direction; The second transistor structure, the first transistor structure and the capacitor structure in the same semiconductor structure are sequentially arranged and connected along the first direction.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The forming of at least one semiconductor structure penetrating the stacked structure comprises: forming a capacitor structure extending along the first direction in the stacked structure; forming a first transistor structure in the stacked structure, the first transistor structure extending along the first direction and being in contact with a first surface of the capacitor structure along the first direction; A second transistor structure is formed in the stack structure, extending along the first direction and contacting and connected to a side of the first transistor structure away from the capacitor structure along the first direction.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The step of forming a capacitor structure extending along the first direction in the stacked structure includes: forming at least one first through hole extending along the first direction in the stacked structure; A dielectric layer and a first electrode are sequentially arranged from inside to outside along a second direction in the first through hole to form the capacitor structure extending along the first direction; the second direction intersects the first direction; the dielectric layer is connected to the first conductor layer and is arranged between the first electrode and the first conductor layer; The capacitor structure includes a plurality of storage capacitors arranged at intervals along the first direction; a third surface of the dielectric layer along the first direction and a fourth surface of the first electrode along the first direction are flush.

21. The method for manufacturing a semiconductor device according to claim 19, wherein: The step of forming a first transistor structure in the stacked structure, the first transistor structure extending along the first direction and being in contact with the first surface of the capacitor structure along the first direction, comprises: forming at least one second through hole extending along the first direction in the stacked structure; A first channel structure, a first spacing structure and a first gate structure are sequentially arranged from outside to inside along a second direction in the second through hole; the second direction intersects the first direction; the second side of the first gate structure along the first direction is in contact and connected with the first surface of the capacitor structure along the first direction; removing a portion of the first gate structure; forming a first isolation structure covering the first gate structure; Removing a portion of the first spacing structure so that a first surface of the first spacing structure away from the capacitor structure along the first direction is flush with a first end of the first isolation structure away from the capacitor structure along the first direction; forming a first drain structure covering the first isolation structure and the first spacing structure; a first end surface of the first drain structure away from the capacitor structure along the first direction is flush with a seventh surface of the first channel structure away from the capacitor structure along the first direction; Among them, the first channel structure is connected to the second conductor layer, and the part of the second conductor layer connected to the first channel structure serves as the first source structure of the first transistor structure; the first spacing structure is close to the second surface of the capacitor structure along the first direction, the first channel structure is close to the sixth surface of the capacitor structure along the first direction, and the first gate structure is close to the second side of the capacitor structure along the first direction and is flush with the first surface of the capacitor structure along the first direction.

22. The method for manufacturing a semiconductor device according to claim 21, wherein: The step of forming a first isolation structure covering the first gate structure includes: forming a first isolation layer covering the stacked structure and the first gate structure; forming a second isolation layer on the first isolation layer; removing a portion of the second isolation layer located in the stacked structure and a portion of the second isolation layer located between the first spacing structures and away from the stacked structure; A portion of the first isolation layer located in the stacked structure and a portion of the first isolation layer located between the first spacing structures are removed.

23. The method for manufacturing a semiconductor device according to claim 22, wherein: The step of forming a second transistor structure in the stacked structure extending along the first direction and contacting and connecting with a side of the first transistor structure away from the capacitor structure along the first direction comprises: forming at least one third through hole extending along the first direction in the stacked structure; A second spacing structure extending along the first direction is formed in the third through hole; a ninth surface of the second spacing structure close to the capacitor structure along the first direction is in contact and connected with a first end surface of the first drain structure away from the capacitor structure along the first direction; A second source structure and a second channel structure surrounding the second source structure are formed between the second spacing structures; the second source structure is in contact and connected with a second side edge of the capacitor structure along the first direction and close to the capacitor structure, and a first end surface of the first drain structure is away from the capacitor structure along the first direction; A second isolation structure is formed between the second channel structures; a second sidewall of the second isolation structure close to the capacitor structure along the first direction is connected to a first side edge of the second source structure away from the capacitor structure along the first direction; A second drain structure is formed between the second channel structures; a second end of the second drain structure close to the capacitor structure along the first direction is connected to a first sidewall of the second isolation structure away from the capacitor structure along the first direction; The second spacing structure is flush with the tenth surface of the capacitor structure along the first direction, the second channel structure is flush with the thirteenth surface of the capacitor structure along the first direction, and the second drain structure is flush with the first end of the capacitor structure along the first direction.

24. The method for manufacturing a semiconductor device according to claim 23, wherein: The stacked structure includes a core area and a connection area arranged along a second direction, and the second direction intersects the first direction; the method further includes: forming a plurality of fifth through holes in the connection area; A first lead-out structure is formed in the fifth through hole; the first lead-out structure extends in the stacked structure along the first direction, and the plurality of first lead-out structures are arranged at intervals in the second direction, Each of the first lead-out structures is respectively connected to the conductor layer at a preset depth.

25. The method for manufacturing a semiconductor device according to claim 23, wherein: The stacked structure includes a core area and a step area arranged along the second direction, and the method further includes: Removing part of the conductor layer and part of the dielectric layer in the stacked structure to form a plurality of step structures, so that the dimensions of the plurality of step structures along the first direction and the dimensions of the second direction change in a step-wise manner; forming a sixth through hole above the step structure; A second lead-out structure is formed in the sixth through hole; the second lead-out structure extends in the stacked structure along the first direction, and the multiple second lead-out structures are arranged at intervals in the second direction, and each of the second lead-out structures is respectively connected to the conductor layer in the step structure of a preset depth.

26. The method for manufacturing a semiconductor device according to claim 24 or 25, wherein: Also includes: forming a protective layer on one side of the stacked structure along the first direction; forming a plurality of fourth through holes in the protection layer above the second transistor structure; A third lead-out structure is formed in the fourth through hole, and the third lead-out structure extends along the first direction and is connected to the second drain structure in the second transistor structure.

27. A storage system, wherein: include: A controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes the semiconductor device according to any one of claims 1 to 17.

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