Hardware acceleration circuit used for binarizing grayscale image partitions

Abstract

Disclosed in the present invention is a hardware acceleration circuit used for binarizing grayscale image partitions. The hardware acceleration circuit comprises a register module, a threshold value array calculation module, a convolution filtering module, a binarization calculation module and a memory module, wherein the register module is used for preconfiguring the hardware acceleration circuit for binarizing grayscale image partitions; the threshold value array calculation module is used for acquiring a corresponding grayscale image after partitioning is performed, and calculating an initial threshold value array of the grayscale image partition; the convolution filtering module is used for filtering the initial threshold value array to obtain a filtered threshold value array; the binarization calculation module is used for comparing the grayscale image with the filtered threshold value array to obtain a binarized image; and the memory module is used for storing data that is involved in the threshold value array calculation module, the convolution filtering module and the binarization calculation module.

Description

A hardware acceleration circuit for grayscale image binarization Technical Field

[0001] The present invention relates to the technical field of image binarization, and in particular to a hardware acceleration circuit for grayscale image block binarization. Background Art

[0002] Image segmentation is a key research topic in the field of image processing. It refers to the process of dividing an image into internally consistent but externally distinct regions based on features such as grayscale, color, texture, or shape. As the most critical step in image processing, image segmentation lays the foundation for subsequent image analysis and understanding, such as target extraction and feature recognition. Therefore, in-depth research on image segmentation is of great significance. Image binarization is a fundamental method in image segmentation. Object recognition, character recognition, and edge extraction, among other tasks, all require image binarization. Most binarization methods are based on thresholds, so selecting an accurate threshold is a critical step in the binarization process. Currently, threshold-based binarization methods include global thresholding and local thresholding.

[0003] Global thresholding applies the same threshold to every pixel in the entire image. In production line environments, where lighting conditions are known, a fixed value is often used as the global threshold. However, in natural light environments like outdoors, lighting conditions are often more complex. For example, the camera may see different images of chocolate ice cream during the day and at night, and global thresholding cannot adapt to both conditions. Therefore, global thresholding has many limitations.

[0004] The local threshold, also known as the adaptive threshold, refers to the selection of different thresholds for different areas of the image based on the ambient light conditions. In the image binarization of various scenes, the applicability of the local threshold method is greatly improved compared to the global threshold method. For example, under natural light conditions with relatively complex lighting conditions, a certain area of ​​the image is relatively dark, and a relatively low threshold is required. For example, setting the threshold to 50 can clearly separate the black and white colors of this area of ​​the image. However, another area of ​​the image is relatively well-lit. At this time, the threshold can be set higher, such as 172, so that the black and white colors can be smoothly separated in the area with sufficient lighting conditions. The present invention is a hardware acceleration circuit for grayscale image block binarization based on the local threshold method.

[0005] Summary of the Invention

[0006] The purpose of the present invention is to address the defects of the prior art and provide a hardware acceleration circuit for grayscale image block binarization.

[0007] In order to achieve the above objectives, the present invention adopts the following technical solutions:

[0008] A hardware acceleration circuit for grayscale image block binarization includes a register module, a threshold array calculation module, a convolution filter module, a binarization calculation module, and a memory module; the register module is respectively connected to the threshold array calculation module, the convolution filter module, and the binarization calculation module; the memory module is respectively connected to the threshold array calculation module, the convolution filter module, and the binarization calculation module;

[0009] A register module is used to pre-configure a hardware acceleration circuit for grayscale image binarization;

[0010] The threshold array calculation module is used to obtain the grayscale image corresponding to the block and calculate the initial threshold array of the grayscale image block;

[0011] A convolution filter module is used to filter the initial threshold array to obtain a filtered threshold array;

[0012] A binarization calculation module is used to compare the grayscale image with the filtered threshold array to obtain a binarized image;

[0013] The memory module is used to store data involved in the threshold array calculation module, the convolution filter module, and the binarization calculation module.

[0014] Furthermore, the pre-configuration in the register module includes: configuring the width of the grayscale image, configuring the height of the grayscale image, configuring the starting address of the grayscale image stored in the memory module, configuring the starting address of the threshold array stored in the memory module, configuring the starting address of the binarized image stored in the memory module, and configuring the convolution filter module parameters.

[0015] Furthermore, the initial threshold array of the grayscale image calculated in the threshold array calculation module specifically includes:

[0016] Read M*N pixels of the current pixel block from the memory module, calculate and store the maximum pixel value, minimum pixel value and cumulative sum of the pixel values;

[0017] Calculate the maximum pixel difference and the average value of the cumulative sum of the pixels according to the maximum pixel value, the minimum pixel value and the cumulative sum of the pixel values;

[0018] Determine whether the maximum pixel difference is greater than the preset judgment condition value. If so, use the accumulated average value as the threshold of the current pixel block; if not, determine whether the current pixel block is the leftmost or topmost block of the grayscale image. If so, use the minimum pixel value / 2 as the threshold of the current pixel block; if not, calculate the special threshold of the pixel block.

[0019] Furthermore, the step of calculating the special threshold of the pixel block further includes:

[0020] Determine whether the minimum pixel value of the current pixel block is less than the special threshold. If so, use the special threshold as the threshold of the current pixel block; if not, use the minimum pixel value / 2 as the threshold of the current pixel block.

[0021] Furthermore, the maximum pixel difference is calculated as follows: maximum pixel difference = maximum pixel value - minimum pixel value;

[0022] The calculation method of the cumulative sum average is: cumulative sum average = cumulative sum of pixel values / (M×N).

[0023] Furthermore, the special threshold is calculated as follows: special threshold = {threshold of the block above the current pixel block + threshold of the block to the left of the current pixel block × 2 + threshold of the block at the upper left corner of the current pixel block} / 4.

[0024] Furthermore, the convolution filter module performs filtering on the initial threshold array as follows:

[0025] Read P×P data of the initial threshold array in the memory module, perform convolution filtering on the P×P data of the initial threshold array to obtain a threshold array after convolution filtering, and store the filtered threshold array in the memory module.

[0026] Furthermore, the binarization calculation module compares the grayscale image with the filtered threshold array as follows:

[0027] Read the filtered threshold of the current pixel block, compare the filtered threshold corresponding to the current pixel block with each pixel value, if the pixel value is less than or equal to the filtered threshold, update the pixel grayscale value to 0; if the pixel value is greater than the filtered threshold, update the pixel grayscale value to 255.

[0028] Compared with the existing technology, the present invention implements a block-based binarization hardware acceleration circuit structure that divides the grayscale image to be processed into blocks through a threshold array calculation module, calculates the threshold value in each block after the block division, filters the obtained initial threshold value through a convolution filter module, and finally compares the grayscale image pixel value with the filtered threshold array value through a binarization calculation module to obtain the binarization of the grayscale image to be processed. This greatly improves the efficiency of grayscale image block binarization. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a system structure diagram of a hardware acceleration circuit for grayscale image block binarization provided by Example 1;

[0030] FIG2 is a schematic diagram of grayscale image segmentation provided by Example 1;

[0031] FIG3 is a flow chart of calculating an initial threshold array of a grayscale image provided by Example 1;

[0032] FIG4 is a schematic diagram of a method for calculating an initial threshold array of a current block provided by Example 1;

[0033] FIG5 is a schematic diagram of pixel block position division provided by Example 1;

[0034] FIG6 is a flow chart of performing convolution filtering on an initial threshold array provided in Example 1;

[0035] FIG7 is a schematic diagram of performing convolution filtering on an initial threshold array provided by Example 1;

[0036] FIG8 is a schematic diagram of binarization of a grayscale image of a current block provided by Example 1;

[0037] FIG9 is a flowchart of image binarization provided by Example 1. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0039] The purpose of the present invention is to address the defects of the prior art and provide a hardware acceleration circuit for grayscale image block binarization.

[0040] Example 1

[0041] This embodiment provides a hardware acceleration circuit for grayscale image block binarization, as shown in Figure 1-9, including a register module 11, a threshold array calculation module 12, a convolution filter module 13, a binarization calculation module 14, and a memory module 15; the register module 11 is respectively connected to the threshold array calculation module 12, the convolution filter module 13, and the binarization calculation module 14, and the memory module 15 is respectively connected to the threshold array calculation module 12, the convolution filter module 13, and the binarization calculation module 14.

[0042] Register module 11, used for pre-configuring the hardware acceleration circuit for grayscale image block binarization;

[0043] The threshold array calculation module 12 is used to obtain the grayscale image corresponding to the block and calculate the initial threshold array of the grayscale image block;

[0044] The convolution filter module 13 is used to filter the initial threshold array to obtain a filtered threshold array;

[0045] A binarization calculation module 14 is used to compare the grayscale image with the filtered threshold array to obtain a binarized image;

[0046] The memory module 15 is used to store data involved in the threshold array calculation module, the convolution filter module, and the binarization calculation module.

[0047] Grayscale images are generally represented in the field of image processing using matrices. That is, no matter how complex or colorful the input image is, it's nothing more than a matrix to the computer. Each element in this matrix is ​​a pixel. For a single-channel grayscale image, this element is a number, most commonly represented by an 8-bit binary number (which can represent a value from 0 to 255). The size of the number represents the brightness of the image at that pixel. The larger the number, the brighter the pixel. 0 represents complete black, and 255 represents complete white.

[0048] Image binarization refers to setting the grayscale values ​​of image pixels to 0 or 255, essentially rendering the entire image visually distinct in black and white. An image consists of a target object, background, and noise. To directly extract the target object from a multi-valued digital image, a common approach is to set a threshold T and use it to divide the image data into two parts: groups of pixels greater than T and groups of pixels less than T. This fundamental method for studying image grayscale transformations is called image binarization. Image binarization is a fundamental image processing technique, often tied to specific algorithms. Many algorithms require binary data as input, such as decoding a QR code, which requires distinguishing between black and white blocks.

[0049] This embodiment provides a hardware acceleration circuit for grayscale image block binarization for a single-channel grayscale image.

[0050] In the register module 11, the hardware acceleration circuit for grayscale image block binarization is preconfigured.

[0051] Pre-configuration specifically includes:

[0052] (1) Configure the width of the grayscale image;

[0053] (2) Configure the height of the grayscale image;

[0054] (3) configuring the starting address of the grayscale image stored in the memory module;

[0055] (4) configuring the threshold array to be stored at the starting address in the memory module;

[0056] (5) configuring the starting address of the binary image stored in the memory module;

[0057] (6) Configure the convolution filter module parameters.

[0058] In the threshold array calculation module 12, the grayscale image corresponding to the block is obtained, and the initial threshold array of the grayscale image block is calculated.

[0059] In this embodiment, grayscale image segmentation can be implemented according to existing technologies, which will not be described in detail in this embodiment. FIG2 is a schematic diagram of grayscale image segmentation.

[0060] As shown in Figure 3, the initial threshold array of the grayscale image is calculated as follows:

[0061] (1) Read the first row of M pixels from the memory module 15 and temporarily store them in the internal cache of the threshold array calculation module 12.

[0062] Then, the second row of M pixels are read from the memory module 15 and temporarily stored in the internal cache of the threshold array calculation module 12. At this time, while reading the second row of M pixels, the maximum pixel value (max_pixel), the minimum pixel value (min_pixel) and the cumulative sum of the pixel values ​​(sum_pixel) in the first row of M pixels are calculated, and the first calculation result is temporarily stored in the internal cache of the threshold array calculation module 12.

[0063] Then, the third row of M pixels is read from the memory module 15 and temporarily stored in the internal cache of the threshold array calculation module 12. At this time, while reading the third row of M pixels, the maximum pixel value (max_pixel), the minimum pixel value (min_pixel) and the cumulative sum of the pixel values ​​(sum_pixel) of the second row of M pixels are calculated, and the maximum pixel value (max_pixel) and the minimum pixel value (min_pixel) of the second row of M pixels are added to the maximum pixel value (max_pixel) of the first row of M pixels stored in the internal cache of the threshold array calculation module 12. xel) and the minimum pixel value (min_pixel) are compared to obtain the maximum pixel value (max_pixel) and the minimum pixel value (min_pixel) in the first two rows of pixels, and the cumulative sum (sum_pixel) of the pixel values ​​of the M pixels in the second row is added to the cumulative sum (sum_pixel) of the pixel values ​​of the M pixels in the first row stored in the internal cache of the threshold array calculation module 12 to obtain the cumulative sum (sum_pixel) of the pixel values ​​of the first two rows of pixels, to obtain a second calculation result, and the second calculation result is updated to the internal cache of the threshold array calculation module 12.

[0064] Similarly, the M pixels in the Nth row are read from the memory module 15 and temporarily stored in the internal cache of the threshold array calculation module 12, and calculation is performed according to the above calculation method to finally obtain the maximum pixel value (max_pixel), minimum pixel value (min_pixel) and cumulative sum of pixel values ​​(sum_pixel) in the first N rows of M pixels, and obtain the final calculation result. The data in the internal cache of the threshold array calculation module 12 is updated, and the final calculation result is written into the memory module 15.

[0065] FIG4 is a schematic diagram of a method for calculating the initial threshold array of the current block.

[0066] a means reading the pixels of the shadow part of the first row, and subsequently calculating the maximum pixel value, minimum pixel value and cumulative sum of the pixel values ​​of the first row, and caching the first result; b means reading the pixels of the shadow part of the second row, and subsequently calculating the maximum pixel value, minimum pixel value and cumulative sum of the pixel values ​​of the second row, comparing the maximum pixel value and minimum pixel value of the second row with the maximum pixel value and minimum pixel value in the cache, adding the cumulative sum of the pixel values ​​of the second row to the cumulative sum of the pixel values ​​in the cache to obtain the second result, and updating the data in the cache according to the second result; c means reading the pixels of the shadow part of the third row, and subsequently calculating the maximum pixel value, minimum pixel value and cumulative sum of the pixel values ​​of the third row, and comparing the maximum pixel value and minimum pixel value of the third row with the maximum pixel value and minimum pixel value in the cache, and adding the cumulative sum of the pixel values ​​of the second row to the cumulative sum of the pixel values ​​in the cache to obtain the second result, and updating the data in the cache according to the second result. The pixel value and the minimum pixel value are compared with the maximum pixel value and the minimum pixel value in the cache (the updated result), the cumulative sum of the pixel values ​​in the third row is added to the cumulative sum of the pixel values ​​in the cache (the updated result) to obtain a third result, and the data in the cache is updated according to the third result; similarly, d represents reading the pixel points in the shadow part of the Nth row, and subsequently calculating the maximum pixel value, the minimum pixel value and the cumulative sum of the pixel values ​​in the Nth row, comparing the maximum pixel value and the minimum pixel value in the Nth row with the maximum pixel value and the minimum pixel value in the cache (the updated result), adding the cumulative sum of the pixel values ​​in the Nth row to the cumulative sum of the pixel values ​​in the cache (the updated result) to obtain the Nth result, and updating the data in the cache according to the Nth result.

[0067] The data of the current block is obtained according to the above method, and finally the data of all blocks are obtained according to the above method.

[0068] (2) Parameter value calculation:

[0069] Maximum pixel difference (diff_pixel) = maximum pixel value (max_pixel) - minimum pixel value (min_pixel);

[0070] Cumulative sum average (avg_pixel) = cumulative sum of pixel values ​​(sum_pixel) / (M×N);

[0071] Special threshold (special_range) = {block threshold above the current pixel block (top_threshold) + block threshold to the left of the current pixel block (left_threshold) × 2 + block threshold at the upper left corner of the current pixel block (lefttop_threshold)} / 4.

[0072] FIG5 is a schematic diagram of pixel block position division; it should be noted that the block threshold above the pixel block, the block threshold to the left of the pixel block, and the block threshold in the upper left corner of the pixel block are similar to the method of calculating the initial threshold array, but they belong to thresholds of different divisions, and will not be elaborated in this embodiment.

[0073] (3) Calculation method of the initial threshold array of the current block.

[0074] Determine whether the maximum pixel difference (diff_pixel) among the N rows of M×N pixels finally calculated in the current block is greater than the preset algorithm judgment condition value (IMG_range); the preset algorithm judgment condition value can be set according to actual conditions or can be an industry standard.

[0075] If the maximum pixel difference (differ_pixel) > the preset algorithm judgment condition value (IMG_range), then according to the conventional processing method, the accumulated average value (avg_pixel) is used as the threshold of the current pixel block, and the threshold result is written to the threshold array storage address of the memory module 15.

[0076] If the maximum pixel difference (diff_pixel) is less than or equal to the preset algorithm judgment condition value (IMG_range), further judgment is required:

[0077] Determine whether the current image block is the leftmost block or the topmost block of the image;

[0078] If the current image block is the leftmost block or the topmost block of the image, the current image block is a boundary condition and requires special processing. At this time, the minimum pixel value (min_pixel) / 2 is used as the threshold of the current pixel block, and the threshold result is written to the threshold array storage address of the memory module 15.

[0079] If the current image block is not the leftmost or topmost block of the image, a special threshold (special_range) needs to be calculated, and then the conditional judgment is continued:

[0080] If the minimum pixel value (min_pixel) of the current block is less than the special threshold (special_range), the special threshold (special_range) is used as the threshold of the current block, and the threshold result is written into the threshold array storage address of the memory module 15.

[0081] If the minimum pixel value (min_pixel) of the current pixel block ≥ the special threshold (special_range), the minimum pixel value (min_pixel) / 2 of the current pixel block is used as the threshold of the current pixel block, and the threshold result is written to the threshold array storage address of the memory module 15.

[0082] According to the above method, the initial threshold array of the current block is obtained, and finally the initial threshold array of all blocks is obtained according to the above method.

[0083] In the convolution filter module 13, the initial threshold array is filtered to obtain a filtered threshold array; specifically:

[0084] The hardware or software system of the hardware acceleration circuit is called so that the software configures P×P convolution kernel matrix data according to the actual light environment conditions and the learning results of the convolution neural network algorithm, calls the convolution filter module, and performs a P×P convolution operation on the obtained initial threshold array, that is, as shown in Figure 6, reads the P×P convolution window data corresponding to the initial threshold array in the memory module 15 and caches them; reads the P×P convolution kernel data corresponding to the current row and caches them, performs a convolution operation on the initial threshold array in the current window to obtain a filtered threshold array, and rewrites the filtered threshold array result to the threshold array storage address of the memory module 15; then the column count is increased by 1, and it is determined whether the column is the last column of the initial threshold array. If not, the window is shifted right and the convolution operation is continued; if so, the row count is increased by 1, and it is determined whether the row is the last row of the initial threshold array. If not, the window is shifted down and the convolution operation is continued; if so, the process ends and the final filtered result is obtained.

[0085] FIG7 is a schematic diagram of performing convolution filtering on the initial threshold array.

[0086] This embodiment is described using a 5×5 convolution kernel as an example.

[0087] The process of filtering the initial threshold value represented by the black square within the dashed box (a) is essentially a convolution of the surrounding 5×5 matrix. To calculate the filtered value, a 5×5 register resource is used to cache the matrix. The filtered threshold value for the point at the location of the black square in a is then calculated and written back to the threshold array in the memory module 15.

[0088] b represents the matrix with the black square in a shifted right. The five threshold values ​​on the leftmost side of the matrix are discarded. The matrix is ​​shifted right, and the five threshold values ​​on the rightmost side of the matrix are read from the memory module and cached in a register. The filtered threshold value at the location of the black square in b is calculated and written back to the threshold array in the storage space of the memory module 15. This process is repeated in this way to obtain the final filtered threshold array.

[0089] In this embodiment, due to the characteristics of convolution calculation, the points in the outermost P / 2 rows and P / 2 columns within the initial threshold array range need to be filled, copied, or other special processing when performing convolution filtering.

[0090] In the binarization calculation module 14, the grayscale image is compared with the filtered threshold array to obtain a binarized image.

[0091] In the first clock cycle, the read enable signal of the memory module 15 is turned on to read the first row of M pixels from the memory module 15;

[0092] In the second clock cycle, the M pixels of the first row are cached in the internal cache of the binarization calculation module 14, and the address of the memory module 15 is switched to the threshold array storage address to read the threshold of the current pixel block;

[0093] In the third clock cycle, the threshold of the current pixel block is cached in the internal cache of the binarization calculation module 14;

[0094] In the fourth clock cycle, the M pixel values ​​in the currently cached row are binarized in parallel. That is, the grayscale values ​​of pixels whose values ​​are less than or equal to the threshold are updated to 0, and the grayscale values ​​of pixels whose values ​​are greater than the threshold are updated to 255.

[0095] In the fifth clock cycle, the write enable signal of the memory module 15 is turned on, and the updated binary pixel value is written from the binarization calculation module 14 into the binary image storage address space of the memory module 15 .

[0096] The pixel binarization process of the subsequent N rows of pixels and other pixel blocks is similar.

[0097] FIG8 is a schematic diagram of the binarization of the grayscale image of the current block.

[0098] a means reading the first row of pixel values ​​of the current block (shown in the shaded part), reading the filtered threshold of the current block, comparing each pixel value with the filtered threshold, and updating its value to 0 if the pixel value is less than or equal to the threshold; if the pixel value is greater than the threshold, updating its value to 255.

[0099] b means reading the second row of pixel values ​​of the current block (shown in the shaded part), comparing each pixel value with the filtered threshold, and updating its value to 0 if the pixel value is less than or equal to the threshold; if the pixel value is greater than the threshold, updating its value to 255.

[0100] Figure 9 is a schematic diagram of the image binarization process. According to the method in Figure 7, the image binarization result of the current block can be obtained. Similarly, the remaining blocks are operated according to this method until the calculation of all blocks is completed and the binarized value of the entire grayscale image is obtained.

[0101] The memory module 15 is used to store the grayscale image, the initial threshold array, the filtered threshold array and the binarized image.

[0102] The present embodiment implements the method of dividing the grayscale image to be processed into blocks through the threshold array calculation module, calculating the threshold value in each block after the block division, filtering the obtained initial threshold value through the convolution filter module, and finally comparing the grayscale image pixel value with the filtered threshold array value through the binarization calculation module to obtain a binarized image of the grayscale image to be processed.

[0103] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A hardware acceleration circuit for grayscale image block binarization, characterized in that: It includes a register module, a threshold array calculation module, a convolution filtering module, a binarization calculation module, and a memory module; the register module is respectively connected to the threshold array calculation module, the convolution filtering module, and the binarization calculation module, and the memory module is respectively connected to the threshold array calculation module, the convolution filtering module, and the binarization calculation module; A register module, used for pre-configuring a hardware acceleration circuit for grayscale image block binarization; The threshold array calculation module is used to obtain the grayscale image corresponding to the block and calculate the initial threshold array of the grayscale image block; A convolution filter module is used to filter the initial threshold array to obtain a filtered threshold array; A binarization calculation module is used to compare the grayscale image with the filtered threshold array to obtain a binarized image; The memory module is used to store the data involved in the threshold array calculation module, the convolution filter module, and the binarization calculation module.

2. The hardware acceleration circuit for grayscale image block binarization according to claim 1, characterized in that: The pre-configuration in the register module includes: configuring the width of the grayscale image, configuring the height of the grayscale image, configuring the starting address of the grayscale image stored in the memory module, configuring the starting address of the threshold array stored in the memory module, configuring the starting address of the binary image stored in the memory module, and configuring the convolution filter module parameters.

3. The hardware acceleration circuit for grayscale image block binarization according to claim 1, characterized in that: The initial threshold array of the grayscale image calculated in the threshold array calculation module specifically includes: Read M*N pixels of the current pixel block from the memory module, calculate and store the maximum pixel value, the minimum pixel value and the accumulated sum of the pixel values ​​among the pixels; Calculate the maximum pixel difference and the average value of the pixel points based on the maximum pixel value, the minimum pixel value and the cumulative sum of the pixel values; Determine whether the maximum pixel difference is greater than the preset judgment condition value. If so, use the accumulated and averaged value as the threshold of the current pixel block; if not, determine whether the current pixel block is the leftmost or topmost block of the grayscale image. If so, use the minimum pixel value / 2 as the threshold of the current pixel block; if not, calculate the image Special thresholds for chunks.

4. The hardware acceleration circuit for grayscale image block binarization according to claim 3, characterized in that: The calculation of the special threshold of the pixel block also includes: Determine whether the minimum pixel value of the current pixel block is less than the special threshold. If so, use the special threshold as the threshold of the current pixel block; if not, use the minimum pixel value / 2 as the threshold of the current pixel block.

5. The hardware acceleration circuit for grayscale image block binarization according to claim 4, characterized in that: The maximum pixel difference is calculated as follows: maximum pixel difference = maximum pixel value - minimum pixel value; The calculation method of the cumulative sum average is: cumulative sum average = cumulative sum of pixel values / (M×N).

6. The hardware acceleration circuit for grayscale image block binarization according to claim 5, characterized in that: The special threshold is calculated as follows: special threshold={threshold of the upper block of the current pixel block+threshold of the left block of the current pixel block×2+threshold of the upper left corner block of the current pixel block} / 4.

7. The hardware acceleration circuit for grayscale image block binarization according to claim 1, characterized in that: The filtering process of the initial threshold array in the convolution filtering module is specifically as follows: Read P×P data of the initial threshold array in the memory module, perform convolution filtering on the P×P data of the initial threshold array to obtain a threshold array after convolution filtering, and store the filtered threshold array in the memory module.

8. The hardware acceleration circuit for grayscale image block binarization according to claim 1, characterized in that: The binarization calculation module compares the grayscale image with the filtered threshold array as follows: Read the filtered threshold of the current pixel block, compare the filtered threshold corresponding to the current pixel block with each pixel value, if the pixel value is less than or equal to the filtered threshold, update the pixel gray value to 0; if the pixel value is greater than the filtered threshold, update the pixel gray value to 255.

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