Resonance method and apparatus

Abstract

Disclosed in the present application are a resonance suppression method and apparatus, a device, and a storage medium. The method comprises: upon determining, on the basis of the topology and structure of a system circuit, that a circuit having CLC topology is present, determining the inherent resonant frequency point of the circuit having CLC topology; determining that the full-wave effective value of the current of a capacitor in the circuit having CLC topology is greater than a current threshold value; determining that the frequency of the primary subharmonic in the system circuit coincides with the inherent resonant frequency point; and on the basis of the frequency band distribution of the primary subharmonic and the inherent resonant frequency point, determining an optimization scheme for the system circuit, so as to reduce the full-wave effective value of the current of the capacitor in the circuit having CLC topology.

Description

A resonance method and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application with application number 202310999453.9, application date August 9, 2023, and application name “A resonance suppression method and device”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into the present disclosure by introduction. Technical Field

[0003] The present disclosure relates to, but is not limited to, a resonance suppression method and apparatus. Background Art

[0004] The ripple current of the DC bus support capacitors in the intermediate circuit of a traction converter is one of the key factors affecting the converter's product life. Traction converters often use an AC / DC / AC main circuit topology. When the main circuit adopts a multi-rectifier, multi-motor topology, the converter usually adopts a common DC bus structure to reduce the four-quadrant switching frequency and expand the converter capacity. In a shared DC bus topology, there are two or more support capacitors on the DC side connected by a busbar or copper busbar. Due to unreasonable device selection and / or system layout design, the stray inductance distribution of the DC bus side line is improper, which will generate an inherent electrical resonant frequency, causing the system to generate a large resonant current at a fixed frequency point. This will cause the two capacitors to generate a current several times that of the externally injected harmonics between the busbar or copper busbar connected to them, resulting in an increase in the operating current of the capacitors and an excessive current in the connecting copper busbar, resulting in an excessive temperature rise of the copper busbar, thus affecting the product life.

[0005] Currently, designers only focus on the feasibility of the structural layout of two capacitors C sharing a common DC bus in the main circuit topology and CLC structure design. In the electrical selection of capacitors, they only consider the current size and ripple of the capacitors under normal operating conditions, and do not consider capacitor failure or damage caused by excessive capacitor current due to CLC resonance. In the selection of two capacitor connection banks, they only consider the structural layout and low-inductance structural design.

[0006] The disadvantage of this structural design is that if resonance is not considered in a CLC circuit, the current flowing through the capacitor at the resonant point will be very high, resulting in high ripple. This can have a significant impact on the capacitor, causing failure or severely shortening its lifespan. If the selection of the connecting bar between capacitors focuses solely on structural layout and low inductance without considering the changes in parasitic inductance caused by the structural design, the connecting bar can also overheat and cause system failure.

[0007] Summary of the Invention

[0008] In view of this, embodiments of the present disclosure provide a resonance suppression method, apparatus, device, and storage medium.

[0009] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0010] In a first aspect, an embodiment of the present disclosure provides a resonance suppression method, the method comprising:

[0011] In the case where a CLC topology circuit is determined to exist based on the topology and structure of the system circuit, determining the inherent resonant frequency of the CLC topology circuit;

[0012] Determining that a full-wave effective value of a current of a capacitor in the CLC topology circuit is greater than a current threshold;

[0013] Determining whether the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency point;

[0014] An optimization scheme for the system circuit is determined based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit.

[0015] In one embodiment, determining the inherent resonant frequency of the CLC topology circuit includes: determining a CLC resonant equivalent circuit corresponding to the CLC topology circuit; using Kirchhoff's law to determine the current relationship between the branch current and the total current in the CLC resonant equivalent circuit; and using the current relationship to determine the inherent frequency, wherein the inherent frequency is the frequency when the branch current is maximum.

[0016] In one embodiment, determining that the full-wave effective value of the current of the capacitor in the CLC topology circuit is greater than the current threshold includes: bringing the parameters in the CLC topology circuit into the system circuit to perform system simulation to determine the full-wave effective value of the current of the capacitor in the CLC topology circuit; and comparing the full-wave effective value of the current with the current threshold to determine that the full-wave effective value of the current is greater than the current threshold.

[0017] In one embodiment, the optimization scheme for the system circuit is determined based on the frequency band distribution of the main subharmonics and the inherent resonant frequency, including: determining that the main subharmonics are not distributed in a first frequency region, increasing the inductance value in the system circuit, and moving the inherent resonant frequency to the first frequency region, wherein the frequency value of the first frequency region is less than a preset first frequency.

[0018] In one embodiment, the optimization scheme for the system circuit is determined based on the frequency band distribution of the main subharmonics and the inherent resonant frequency, including: when determining that the main subharmonics are not distributed in a first frequency region, increasing the capacitance value in the system circuit and moving the inherent resonant frequency to the first frequency region, wherein the frequency value of the first frequency region is less than a preset first frequency.

[0019] In one embodiment, the optimization scheme for the system circuit is determined based on the frequency band distribution of the main subharmonics and the inherent resonant frequency, including: when determining that the distribution of the main subharmonics in the second frequency region is less than a preset distribution rate requirement, reducing the inductance value in the system circuit and increasing the loop resistance value in the system circuit, and moving the inherent resonant frequency to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

[0020] In one embodiment, the optimization scheme for the system circuit is determined based on the frequency band distribution of the main subharmonics and the inherent resonant frequency, including: determining that the distribution of the main subharmonics in the second frequency region is less than a preset distribution rate requirement, reducing the capacitance value in the system circuit, and moving the inherent resonant frequency to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

[0021] In a second aspect, an embodiment of the present disclosure provides a resonance suppression device, the device comprising:

[0022] A first determining module is configured to determine, based on the topology and structure of the system circuit, a natural resonant frequency of the CLC topology circuit when determining that a CLC topology circuit exists;

[0023] A second determining module is configured to determine whether a full-wave effective value of a current of a capacitor in the CLC topology circuit is greater than a current threshold;

[0024] A third determining module is used to determine whether the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency point;

[0025] The fourth determination module is used to determine an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point, so as to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit.

[0026] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor implements the above method when executing the program.

[0027] In a fourth aspect, an embodiment of the present disclosure provides a storage medium storing executable instructions for implementing the above method when executed by a processor.

[0028] In the embodiment of the present disclosure, first, based on the topology and structure of the system circuit, it is determined that there is a CLC topology circuit, and the inherent resonant frequency of the CLC topology circuit is determined; then, it is determined that the full-wave effective value of the current of the capacitor in the CLC topology circuit is greater than the current threshold; it is determined that the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency; finally, based on the frequency band distribution of the main subharmonic and the inherent resonant frequency, an optimization scheme for the system circuit is determined to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit. In this way, it is possible to determine that there is a CLC topology circuit in the system circuit, analyze the cause of the heating of the system circuit connection row, and determine the optimization scheme for the system circuit based on the frequency band distribution of the main subharmonic and the inherent resonant frequency, so as to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit and achieve the effect of reducing the heating of the system circuit connection row. This method can be applied to the design stage of the product, and the system component selection and structural design can be completed through simulation design, effectively saving production and time costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1A is a schematic diagram of a flow chart of a method for implementing resonance suppression according to an embodiment of the present disclosure;

[0030] FIG1B is a topological diagram of a system circuit provided in an embodiment of the present disclosure;

[0031] FIG1C is a schematic diagram of a system CLC resonant equivalent circuit provided by an embodiment of the present disclosure;

[0032] FIG1D is a diagram showing parasitic parameter extraction results using ANSYS Q3D according to an embodiment of the present disclosure;

[0033] FIG1E is a graph showing the capacitance current spectrum and full-wave effective value results provided by an embodiment of the present disclosure;

[0034] FIG1F is a diagram showing parasitic parameter extraction results using ANSYS Q3D according to an embodiment of the present disclosure;

[0035] FIG1G is a graph showing the spectrum of the capacitor current and the full-wave effective value of the capacitor current according to an embodiment of the present disclosure;

[0036] FIG2 is a schematic diagram of an implementation flow of a system circuit optimization solution provided by an embodiment of the present disclosure;

[0037] FIG3 shows two technical means of providing a resonance suppression method according to an embodiment of the present disclosure;

[0038] FIG4 is a flow chart of a method for simulating and analyzing resonance suppression of a CLC circuit in a traction converter according to an embodiment of the present disclosure;

[0039] FIG5 is a schematic diagram of the structure of a resonance suppression device provided by an embodiment of the present disclosure;

[0040] FIG6 is a schematic diagram of a hardware entity of an electronic device provided by an embodiment of the present disclosure.

[0041] Implementation Method

[0042] To make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the specific technical solutions of the embodiments of the present disclosure will be further described in detail below in conjunction with the drawings in the embodiments of the present disclosure. The following embodiments are used to illustrate the present disclosure but are not intended to limit the scope of the present disclosure.

[0043] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] In the following description, the terms "first\second\third" are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with the specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0046] The present disclosure provides a resonance suppression method, as shown in FIG1A , comprising:

[0047] Step S110: If a CLC topology circuit is determined to exist based on the topology and structure of the system circuit, determine the inherent resonant frequency of the CLC topology circuit;

[0048] Here, the CLC topology circuit is a circuit structure consisting of three cascaded filters, namely a capacitor filter, an inductor filter and a capacitor filter.

[0049] During implementation, the presence of a CLC topology circuit can be determined based on the topology and structure of the system circuit. FIG1B is a schematic diagram of the topology of a system circuit provided by an embodiment of the present disclosure. As shown in FIG1B , two capacitors C connected to a busbar 11 can form a CLC topology circuit, indicating that the system circuit shown in FIG1B has a CLC topology circuit.

[0050] After determining that a CLC topology circuit exists, a system resonance point mechanism analysis can be performed on the CLC topology circuit, and the inherent resonance frequency of the CLC topology circuit can be determined using finite element simulation software, which can be Ansys Q3D.

[0051] Step S120: determining whether the full-wave effective value of the current of the capacitor in the CLC topology circuit is greater than a current threshold;

[0052] Here, the current threshold can be set according to actual needs.

[0053] During the implementation process, the main circuit can be system simulated, the current waveform on the capacitor can be collected, and the full-wave effective value of the current can be calculated.

[0054] Step S130, determining whether the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency point;

[0055] Here, while performing system simulation on the main circuit, a spectrum analysis can be performed on the current to obtain a spectrum diagram of the capacitor current I. Based on the spectrum diagram of the capacitor current I, the frequency of the main subharmonics in the system circuit can be determined.

[0056] During implementation, the acquired primary harmonics can be compared with the natural resonant frequency to determine whether the primary harmonics and the natural resonant frequency coincide. If it is determined that the primary harmonics and the natural resonant frequency coincide, step S140 is executed. If it is determined that the primary harmonics and the natural resonant frequency do not coincide, it can be determined that the capacitor current (full-wave effective value of the capacitor current) does not meet system requirements and is not caused by the CLC resonant circuit, and other causes need to be analyzed.

[0057] Step S140: determining an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point, so as to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit.

[0058] In the embodiment of the present disclosure, first, based on the topology and structure of the system circuit, it is determined that there is a CLC topology circuit, and the inherent resonant frequency of the CLC topology circuit is determined; then, it is determined that the full-wave effective value of the current of the capacitor in the CLC topology circuit is greater than the current threshold; it is determined that the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency; finally, based on the frequency band distribution of the main subharmonic and the inherent resonant frequency, an optimization scheme for the system circuit is determined to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit. In this way, it is possible to determine that there is a CLC topology circuit in the system circuit, analyze the cause of the heating of the system circuit connection row, and determine the optimization scheme for the system circuit based on the frequency band distribution of the main subharmonic and the inherent resonant frequency, so as to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit and achieve the effect of reducing the heating of the system circuit connection row. This method can be applied to the design stage of the product, and the system component selection and structural design can be completed through simulation design, effectively saving production and time costs.

[0059] In some embodiments, the above step S110 of “determining the inherent resonant frequency of the CLC topology circuit” can be implemented by the following steps:

[0060] Step 111: Determine a CLC resonant equivalent circuit corresponding to the CLC topology circuit;

[0061] For example, the main circuit topology of the system is shown in Figure 1B. In the intermediate DC link, two supporting capacitors C are connected together through busbar 11, and a CLC resonant circuit exists. Figure 1C is a schematic diagram of a system CLC resonant equivalent circuit provided by an embodiment of the present disclosure. As shown in Figure 1C, AC is an AC current source used to simulate the ripple current introduced by the converter, and I is the current value output by the AC current source; C1 and C2 are the DC capacitors of branches 1 and 2, L2 and R2 are the line inductance and resistance of branch 2, and I1 and I2 are the currents flowing through branches 1 and 2.

[0062] Step 112: Using Kirchhoff's law, determine the current relationship between the branch current and the total current in the CLC resonant equivalent circuit;

[0063] During implementation, after determining the existence of a CLC resonant circuit in the circuit shown in FIG1B , the system resonance point mechanism analysis can be performed, and the correlation formula between the system's inherent resonant point f1 and the capacitors C1 and C2, as well as the parasitic inductance L2 and internal resistance R2 of the busbar or copper busbar connecting the two capacitors, can be derived.

[0064] According to Kirchhoff's law, the relationship between the currents I1 and I2 in branches 1 and 2 in Figure 1C and the total current I is as follows:

[0065] Here, ω is equal to 2πf.

[0066] Step 113: Determine the natural frequency point using the current relationship, wherein the natural frequency point is the frequency point when the branch current is maximum.

[0067] During implementation, when it is determined that In the case of , I1 and I2 reach their maximum, then the natural resonant frequency point f1 can be obtained using the following formula (3):

[0068] Here, in the CLC equivalent circuit, the capacitance value C is known. The parasitic inductance L2 and internal resistance R2 of the busbar or copper busbar connecting the two capacitors C1 and C2 can be extracted using the finite element simulation software Ansys Q3D. Substituting them into the above formula (3) yields the system's inherent resonant frequency. FIG1D is a diagram of the parasitic parameter extraction results of ANSYS Q3D provided in an embodiment of the present disclosure. As shown in FIG1D , FIG1D is a diagram of the parasitic parameter extraction results of ANSYS Q3D provided in an embodiment of the present disclosure. As shown in FIG1D , the two copper buses in the figure are the positive and negative busbars. The simulation results show that the internal resistance R of the positive and negative copper busbar loop is 0.6 milliohms (mΩ), and the parasitic inductance L of the loop is 605 nanohenries (nH).

[0069] As shown in Figure 1D, the parasitic inductance L of the busbar or copper busbar connecting the two capacitors C is 605nH and the internal resistance R is 0.6mΩ. Substituting the inductance parameters into Equation (3) yields the system's natural resonant frequency of 3700 Hz. The internal resistance can be used to determine the full-wave effective value of the current.

[0070] In the disclosed embodiment, the CLC resonant equivalent circuit corresponding to the CLC topology circuit is first determined; then, Kirchhoff's law is used to determine the current relationship between the branch current and the total current in the CLC resonant equivalent circuit; and finally, the natural frequency is determined using this current relationship, where the natural frequency is the frequency at which the branch current is at its maximum. In this way, the natural frequency can be obtained.

[0071] In some embodiments, the above step S120 of "determining that the full-wave effective value of the current of the capacitor in the CLC topology circuit is greater than the current threshold" can be implemented by the following steps:

[0072] Step 121: bring the parameters of the CLC topology circuit into the system circuit to perform system simulation, and determine the full-wave effective value of the current of the capacitor in the CLC topology circuit;

[0073] Here, the obtained CLC parameters can be brought into the main circuit in MATLAB for system simulation, the current waveform on capacitor C1 can be collected, the full-wave RMS value can be calculated, and the current spectrum can be analyzed. Figure 1E shows the capacitor current spectrum and full-wave RMS results provided by an embodiment of the present disclosure. As shown in Figure 1E, the system has a relatively large harmonic current around 3700Hz, with a full-wave RMS value of 381 amperes (A).

[0074] Step 122 : Compare the full-wave effective value of the current with the current threshold to determine whether the full-wave effective value of the current is greater than the current threshold.

[0075] Here, the current threshold can be set according to actual usage. For example, the current threshold can be set to 300 A. As shown in FIG1E , the full-wave effective value of the current is 381 A, which is greater than 300 A and does not meet the system requirements.

[0076] In the disclosed embodiment, the parameters of the CLC topology circuit are first introduced into the system circuit for system simulation to determine the full-wave effective value of the current of the capacitor in the CLC topology circuit. The full-wave effective value of the current is then compared with the current threshold to determine whether the full-wave effective value of the current is greater than the current threshold. In this way, it can be determined whether the full-wave effective value of the current of the capacitor meets the system design requirements.

[0077] In some embodiments, as shown in FIG2 , the above step S140 of “determining an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency” can be implemented by the following steps:

[0078] Step S210: When it is determined that the main subharmonics are not distributed in the first frequency region, increase the inductance value in the system circuit and move the natural resonant frequency point to the first frequency region, wherein the frequency value of the first frequency region is less than the preset first frequency.

[0079] Step S220: When it is determined that the main subharmonics are not distributed in the first frequency region, increase the capacitance value in the system circuit to move the natural resonant frequency point to the first frequency region, wherein the frequency value of the first frequency region is less than the preset first frequency.

[0080] Step S230: When it is determined that the distribution of the main subharmonics in the second frequency region is less than a preset distribution rate requirement, the inductance value in the system circuit is reduced, and the loop resistance value in the system circuit is increased, so as to move the natural resonant frequency point to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

[0081] Step S240: When it is determined that the distribution of the main subharmonics in the second frequency region is less than a preset distribution rate requirement, the capacitance value in the system circuit is reduced, and the inherent resonant frequency point is moved to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

[0082] For example, the system's inherent resonance point is 3700 Hz. In the system's harmonic spectrum, the current at the 3700 Hz harmonic frequency point is the highest, indicating that resonance has occurred at 3700 Hz and that the system's primary sub-resonance point has overlapped the inherent resonance point. From the system spectrum, the system's primary sub-harmonics are relatively low in the high-frequency region, so either step S230 or step S240 is used. If, based on the system selection requirements, it is determined that the solution provided by step S230 is superior, then step S230 is executed.

[0083] In the Q3D software, by modifying the structure of the connecting bar between the two capacitors, the effect of reducing L and increasing R is achieved. Figure 1F is the ANSYS Q3D parasitic parameter extraction result diagram provided by the embodiment of the present disclosure. As shown in Figure 1F, in the Q3D software, the two copper bars in the figure are the positive and negative copper bars of the busbar. The simulation results show that the internal resistance R of the positive and negative copper bars loop is 0.61mΩ, and the parasitic inductance L of the loop is 280.1nH. That is, the parasitic inductance L2 of the modified connecting bar can be 280.1nH and the internal resistance R2 is 0.61mΩ without changing the length of the connecting bar. The effect of reducing the line inductance L and increasing the internal resistance R of the loop is achieved. The inherent resonance point is calculated to be f1=5400Hz. Referring to the system current spectrum, the harmonic distribution of the system at 5400Hz is very small. Figure 1G is the capacitor current spectrum and full-wave effective value result diagram provided by the embodiment of the present disclosure. Specifically, a system simulation was performed, and the results are shown in Figure 1G. The current spectrum resonated at 5400 Hz, but because the main subharmonics of the input current did not cover the inherent resonance point f1 = 5400 Hz, the resonant current value was very small. The full-wave effective value (RMS) of the capacitor current was 250 A, which was less than the system requirement of 300 A, verifying the feasibility of the optimization scheme.

[0084] In the embodiments of the present disclosure, four effective optimization methods are provided to ensure that the circuit obtained through device selection and / or structural design meets all the effective values ​​of the current required by the design, effectively avoiding excessive capacitor current and heating of the connecting row due to CLC resonance.

[0085] FIG3 shows two technical means for providing a resonance suppression method according to an embodiment of the present disclosure. As shown in FIG3 , the two technical means are as follows:

[0086] Technical means 1. Analysis method of the CLC inherent resonance point of the main circuit.

[0087] During implementation, the presence of a CLC topology circuit in the intermediate DC link can be determined based on the system's main circuit topology and structure. Once the presence of a CLC resonant circuit is confirmed, the system's resonance point mechanism is analyzed, and a formula correlating the system's inherent resonance point, f, with L and C is derived. In a CLC circuit, the capacitance value, C, is known. Using the finite element simulation software AnsysQ3D, the parasitic inductance, L, and internal resistance, R, of the busbar or copper busbar connecting the two capacitors, C, are extracted. These are then substituted into the formula for the system's inherent resonance point, f, to calculate the system's CLC inherent resonant frequency.

[0088] Technical means 2: Solution to suppress excessive current caused by CLC resonance.

[0089] During the implementation process, the system can be simulated in MATLAB, the current I on the two capacitors can be collected and the spectrum analysis can be performed to obtain the current I spectrum diagram, and the main subharmonic frequencies of the system can be analyzed; it can be determined whether the main subharmonics of the system cover the inherent resonance point obtained by technical means 1, and a current suppression scheme for the capacitor current caused by CLC resonance can be proposed based on the actual situation; rectification can be carried out in the design stage according to the suppression scheme, and finally the system simulation can be carried out to obtain the full-wave effective value and spectrum distribution diagram of the capacitor current to verify the rectification effect.

[0090] By combining Technical Methods 1 and 2, the disclosed embodiments can provide a simulation analysis of excessive capacitive current caused by system CLC resonance and a system main circuit optimization solution for suppressing excessive current. The simulation environment is closer to the actual environment, and the simulation results are more valuable for design reference.

[0091] FIG4 is a flow chart of a simulation analysis method for suppressing resonance of a CLC circuit in a traction converter provided by an embodiment of the present disclosure. As shown in FIG4 , the method includes the following steps:

[0092] Step S401, product structure design stage;

[0093] Step S402, Q3D extracts the parasitic inductance parameters of the parallel arrangement between the capacitors in the main circuit;

[0094] During implementation, the presence of a CLC topology circuit in the intermediate DC link can be determined based on the system's main circuit topology and structure. Once the presence of a CLC resonant circuit is confirmed, the system's resonance point mechanism is analyzed, and formulas are derived to correlate the system's inherent resonance point, f, with the capacitors C1 and C2, as well as the parasitic inductance L2 and internal resistance R2 of the busbar or copper busbar connecting the two capacitors. In the CLC circuit, the capacitance C is known, and the parasitic inductance L2 and internal resistance R2 of the busbar or copper busbar connecting the two capacitors, C1 and C2, are extracted using the finite element simulation software Ansys Q3D.

[0095] Step S403, calculating the main circuit resonance point (natural resonance frequency f);

[0096] Substitute the parasitic inductance L2 and internal resistance R2 of the busbar or copper busbar of the two capacitors C1 and C2 into the formula to calculate the system's inherent resonant frequency point f.

[0097] Step S404: Analyze the main harmonics of the input and output of the main circuit;

[0098] During implementation, a spectrum analysis is performed on the current to obtain a spectrum diagram of the capacitor current I. The main subharmonics can be determined based on the spectrum diagram.

[0099] Step S405: Matlab system simulation outputs capacitor current spectrum analysis;

[0100] During the implementation process, the obtained CLC parameters are brought into the main circuit for system simulation in MATLAB, the current waveform on the capacitor is collected and the full-wave effective value of the current is calculated.

[0101] Step S406: Verify whether the capacitor current (full-wave effective value) meets the system requirements;

[0102] During implementation, the current threshold can be set according to actual needs. If it is determined that the full-wave effective value of the current is greater than the current threshold, step S407 is executed; if it is determined that the full-wave effective value of the current is less than or equal to the current threshold, step S411 is executed.

[0103] Step S407: The main subharmonics are covered at the CLC resonance point (natural resonance frequency f);

[0104] If it is determined that the natural resonant frequency covers the main subharmonics, step S409 is executed; if it is determined that the natural resonant frequency does not cover the main subharmonics, step S408 is executed.

[0105] Step S408: Analyze other reasons;

[0106] Step S409: executing the optimization plan;

[0107] Based on the actual situation and the coverage relationship between the current spectrum and the system's inherent resonance points, select one of the following optimization solutions:

[0108] Optimization 1: If the system's main subharmonics are not distributed in the low-frequency region, increase the line inductance L to move the system's inherent resonance point forward to the low-frequency region where the system's main subharmonics are not distributed; execute step S410 and then perform system simulation to evaluate whether the capacitor and current values ​​meet the requirements;

[0109] Optimization 2: If the system's main subharmonics are not distributed in the low-frequency region, increase the capacitance C to move the system's inherent resonance point forward to the low-frequency region where the system's main subharmonics are not distributed; execute step S410 and perform system simulation again to evaluate whether the capacitor current value meets the requirements;

[0110] Optimization 3: If the system's main subharmonics have a low harmonic distribution in the high-frequency region, reduce the line inductance L and increase the loop internal resistance R; move the system's inherent resonance point back to the high-frequency region where the system's main subharmonics have a low distribution; execute step S410 and perform system simulation again to evaluate whether the capacitor and current values ​​meet the requirements;

[0111] Optimization 4: If the system's main subharmonics have a low harmonic distribution in the high-frequency region, reduce the capacitance value C; move the system's inherent resonance point back to the high-frequency region where the system's main subharmonics have a low distribution; execute step S410 and then perform system simulation to evaluate whether the capacitor current value meets the requirements.

[0112] Step S410: Verify whether the capacitor current meets the system requirements;

[0113] During implementation, after selecting an optimization solution based on actual conditions, system simulation can be performed to obtain the capacitor current spectrum and full-wave effective value of the capacitor to assess whether the capacitor current value meets the requirements. If the requirements are met, the main circuit CLC circuit is optimized according to the selected solution. If the system requirements are not met, step S409 is executed to continue optimization.

[0114] Step S411: Complete design optimization.

[0115] In the disclosed embodiment, a simulation method combining system simulation and structure-based finite element simulation is used to make the system simulation closer to reality, providing a new approach for system device selection and structural design. CLC resonance analysis simulation forward design: Before the prototype is produced, CLC resonance analysis simulation forward design is carried out, and the simulation method is used to guide the design, avoiding the design defects caused by CLC resonance, and providing optimization solutions for excessive capacitor current and severe heating of the connecting bar due to CLC resonance, saving production and time costs. During product operation, capacitor life attenuation occurs and severe heating of the connecting bar occurs, providing a clear analysis method for such problems. The intermediate DC circuit CLC resonance suppression simulation analysis method in the scheme is not limited to application in traction auxiliary converter topology, but can also be applied to all application circuits where the capacitor current is excessive due to CLC.

[0116] Based on the foregoing embodiments, the embodiments of the present disclosure provide a resonance suppression device, which includes modules, each module includes sub-modules, each sub-module includes a unit, and can be implemented by a processor in an electronic device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0117] FIG5 is a schematic diagram of the structure of a resonance suppression device provided in an embodiment of the present disclosure. As shown in FIG5 , the device 500 includes:

[0118] A first determining module 510 is configured to determine a natural resonant frequency of a CLC topology circuit when determining the existence of the CLC topology circuit based on the topology and structure of the system circuit;

[0119] A second determining module 520 is configured to determine whether a full-wave effective value of a current of a capacitor in the CLC topology circuit is greater than a current threshold;

[0120] A third determining module 530 is configured to determine whether the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency point;

[0121] The fourth determination module 540 is configured to determine an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point, so as to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit.

[0122] In some embodiments, the first determination module 510 includes a first determination submodule, a second determination submodule, and a third determination submodule, wherein the first determination submodule is used to determine the CLC resonant equivalent circuit corresponding to the CLC topology circuit; the second determination submodule is used to determine the current relationship between the branch current and the total current in the CLC resonant equivalent circuit using Kirchhoff's law; and the third determination submodule is used to determine the natural frequency point using the current relationship, wherein the natural frequency point is the frequency point when the branch current is maximum.

[0123] In some embodiments, the fourth determination module 540 is further used to determine that when the main subharmonics are not distributed in the first frequency region, increase the inductance value in the system circuit and move the inherent resonant frequency point to the first frequency region, wherein the frequency value of the first frequency region is less than the preset first frequency.

[0124] In some embodiments, the fourth determination module 540 is used to determine that when the main subharmonics are not distributed in the first frequency region, increase the inductance value in the system circuit and move the inherent resonant frequency point to the first frequency region, wherein the frequency value of the first frequency region is less than the preset first frequency.

[0125] In some embodiments, the fourth determination module 540 is further used to determine that when the distribution of the main harmonics in the second frequency region is less than a preset distribution rate requirement, reduce the inductance value in the system circuit and increase the loop resistance value in the system circuit to move the inherent resonant frequency point to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

[0126] In some embodiments, the fourth determination module 540 is also used to determine that when the distribution of the main harmonics in the second frequency region is less than the preset distribution rate requirement, reduce the capacitance value in the system circuit and move the inherent resonant frequency point to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

[0127] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0128] It should be noted that, in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable an electronic device (which can be a mobile phone, tablet computer, laptop computer, desktop computer, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

[0129] Correspondingly, an embodiment of the present disclosure provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the resonance suppression method provided in the above embodiment are implemented.

[0130] Correspondingly, an embodiment of the present disclosure provides an electronic device. Figure 6 is a schematic diagram of a hardware entity of the electronic device provided by an embodiment of the present disclosure. As shown in Figure 6, the hardware entity of the device 600 includes: a memory 601 and a processor 602, the memory 601 stores a computer program that can be run on the processor 602, and when the processor 602 executes the program, the steps in the resonance suppression method provided in the above embodiment are implemented.

[0131] The memory 601 is configured to store instructions and applications executable by the processor 602, and can also cache data to be processed or processed by the processor 602 and various modules in the electronic device 600 (for example, image data, audio data, voice communication data and video communication data), which can be implemented through flash memory (FLASH) or random access memory (RAM).

[0132] It should be noted that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0133] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0134] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0135] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0136] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0137] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0138] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0139] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling an electronic device (which can be a mobile phone, tablet computer, laptop computer, desktop computer, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, magnetic disks or optical disks.

[0140] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0142] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0143] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A resonance suppression method, the method comprising: In the case where a CLC topology circuit is determined based on the topology and structure of the system circuit, determining the inherent resonant frequency of the CLC topology circuit; Determining that a full-wave effective value of a current of a capacitor in the CLC topology circuit is greater than a current threshold; Determine whether the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency point; An optimization scheme for the system circuit is determined based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit.

2. The method of claim 1, wherein: The determining of the inherent resonant frequency of the CLC topology circuit comprises: Determine a CLC resonant equivalent circuit corresponding to the CLC topology circuit; Using Kirchhoff's law, determining the current relationship between the branch current and the total current in the CLC resonant equivalent circuit; The natural frequency point is determined by using the current relationship, wherein the natural frequency point is the frequency point when the branch current is maximum.

3. The method of claim 1, wherein: Determining that the full-wave effective value of the current of the capacitor in the CLC topology circuit is greater than the current threshold comprises: Bringing the parameters in the CLC topology circuit into the system circuit to perform system simulation, and determining the full-wave effective value of the current of the capacitor in the CLC topology circuit; The current full-wave effective value is compared with the current threshold to determine whether the current full-wave effective value is greater than the current threshold.

4. The method according to any one of claims 1 to 3, wherein: The step of determining an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point includes: When it is determined that the main subharmonics are not distributed in the first frequency region, the inductance value in the system circuit is increased to move the inherent resonant frequency point to the first frequency region, wherein the frequency value of the first frequency region is less than the preset first frequency.

5. The method according to any one of claims 1 to 3, wherein: The determining of an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point includes: When it is determined that the main harmonics are not distributed in the first frequency region, the capacitance value in the system circuit is increased to move the inherent resonant frequency point to the first frequency region, wherein the frequency value of the first frequency region is less than at a preset first frequency.

6. The method according to any one of claims 1 to 3, wherein: The step of determining an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point includes: When it is determined that the distribution of the main harmonics in the second frequency region is less than a preset distribution rate requirement, the inductance value in the system circuit is reduced and the loop resistance value in the system circuit is increased to move the inherent resonant frequency point to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

7. The method according to any one of claims 1 to 3, wherein: The step of determining an optimization scheme for the system circuit based on the frequency band distribution of the main subharmonics and the inherent resonant frequency point includes: When it is determined that the distribution of the main harmonics in the second frequency region is less than a preset distribution rate requirement, the capacitance value in the system circuit is reduced, and the inherent resonant frequency point is moved to the second frequency region, wherein the frequency value of the second frequency region is greater than the preset second frequency.

8. A resonance suppression device, wherein: The device comprises: A first determination module is used to determine the inherent resonant frequency of the CLC topology circuit when determining that there is a CLC topology circuit based on the topology and structure of the system circuit; A second determination module is used to determine that the full-wave effective value of the current of the capacitor in the CLC topology circuit is greater than a current threshold; A third determination module is used to determine whether the frequency of the main subharmonic in the system circuit coincides with the inherent resonant frequency point; The fourth determination module is used to determine an optimization scheme for the system circuit based on the frequency band distribution of the main harmonics and the inherent resonant frequency point to reduce the full-wave effective value of the current of the capacitor in the CLC topology circuit.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, wherein: When the processor executes the program, the steps in the method according to any one of claims 1 to 7 are implemented.

10. A storage medium, wherein: Executable instructions are stored, which are used to cause a processor to execute and implement the steps in any one of the methods described in claims 1 to 7.

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