Solar cell sheet and preparation method, battery assembly and photovoltaic system

Abstract

The present application applies to the technical field of solar cells, and provides a solar cell sheet (100) and a preparation method, a battery assembly (200) and a photovoltaic system (1000). In the solar cell sheet (100), a P-type silicon substrate (10) has a first surface (11) and a second surface (12) opposite the first surface (11); the first surface (11) is a surface facing light; the second surface (12) is a surface facing away from light; the first surface (11) is provided with several first regions (111) and second regions(112), which are alternately disposed in sequence; the second surface (12) is provided with several third regions (121) and fourth regions (122), which are alternately disposed in sequence; P-type doped layers (20) are disposed on the first regions (111) and do not cover the second regions (112); N-type doped layers (40) are disposed on the third regions (121) and do not cover the fourth regions (122); and the sum of the areas of all the third regions (121) is greater than the sum of the areas of all the first regions (112).

Description

Solar cell and preparation method, battery assembly and photovoltaic system

[0001] Priority information

[0002] This application claims priority and benefits of patent applications with patent application numbers 202310996449.7 and 202322129692.7 filed with the State Intellectual Property Office of China on August 8, 2023, and the entire text of which is incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, a solar cell assembly and a photovoltaic system. Background Art

[0004] Solar cell power generation is a sustainable source of clean energy. It uses the photovoltaic effect of semiconductor pn junction to convert sunlight into electrical energy.

[0005] In related technologies, a front emitter region is typically formed on the entire front surface of a silicon wafer, while a back emitter region is formed on the back surface. Passivation films and electrodes are then applied to create a double-sided solar cell that can receive light. However, in this solution, the entire front and back surfaces are covered by doped layers that form emitter or back field regions. These doped layers have a high parasitic absorption of light, resulting in low conversion efficiency for the solar cell.

[0006] To address the problem of high parasitic absorption, a local contact solution can be used. However, the existing local passivation contact technology does not consider how to balance the relationship between parasitic absorption and the area of ​​the PN junction. Although it effectively reduces parasitic absorption, it can easily lead to a PN junction area that is too small, affecting efficiency. In particular, in the technical solution using a P-type silicon substrate, the P-type polysilicon layer has a poor passivation effect on the P-type silicon substrate. If the P-type doped layer is arranged on the entire front side and the N-type doped layer is arranged on the entire back side, it will lead to large parasitic absorption and poor passivation effect. If the P-type polysilicon is arranged on the entire back side and the N-type doped layer is arranged on the front side, on the one hand, the area of ​​the P-type polysilicon is relatively large, resulting in poor passivation effect of the battery and thus low efficiency. On the other hand, the N-type doped layer is arranged on the front side, which has high parasitic absorption of light, which also leads to a decrease in conversion efficiency. At the same time, if the N-type doped layer on the front side and the P-type doped layer on the back side are arranged in a local contact, it can easily lead to a PN junction area that is too small, resulting in reduced efficiency.

[0007] Therefore, how to reduce parasitic absorption while ensuring the efficiency of solar cells has become a technical problem studied by technicians. Summary of the Invention

[0008] The present application provides a solar cell and a preparation method thereof, a cell assembly and a photovoltaic system, aiming to solve the technical problem of how to reduce parasitic absorption while ensuring the efficiency of the solar cell.

[0009] The present application is implemented as follows: the solar cell of the embodiment of the present application comprises:

[0010] A P-type silicon substrate having a first surface and a second surface opposite to the first surface, the first surface being a light-facing surface and the second surface being a light-backed surface, the first surface having a plurality of first and second regions alternately arranged in sequence, and the second surface having a plurality of third and fourth regions alternately arranged in sequence;

[0011] a P-type doped layer disposed on the first region and not covering the second region;

[0012] a first dielectric layer disposed between the P-type doped layer and the first surface;

[0013] an N-type doped layer disposed on the third region and not covering the fourth region, wherein the sum of areas of all the third regions is greater than the sum of areas of all the first regions;

[0014] a second dielectric layer disposed between the N-type doped layer and the second surface; and

[0015] A first electrode and a second electrode, wherein the first electrode contacts the P-type doping layer, and the second electrode contacts the N-type doping layer.

[0016] The present application also provides a method for preparing a solar cell, comprising:

[0017] A P-type silicon substrate is provided, the P-type silicon substrate having a first surface and a second surface opposite to the first surface, the first surface being a light-facing surface and the second surface being a light-backed surface, the first surface having a plurality of first regions and second regions alternately arranged in sequence, and the second surface having a plurality of third regions and fourth regions alternately arranged in sequence, wherein the sum of the areas of all the third regions is greater than the sum of the areas of all the first regions;

[0018] forming a first dielectric layer and a P-type doped layer in sequence on the first region;

[0019] forming a second dielectric layer and an N-type doping layer in sequence on the third region;

[0020] forming a first passivation film layer on the first surface and forming a second passivation film layer on the second surface;

[0021] A first electrode and a second electrode are prepared on the first passivation film layer and the second passivation film layer respectively. The first electrode penetrates the first passivation film layer and contacts the P-type doped layer. The second electrode penetrates the second passivation film layer and contacts the N-type doped layer.

[0022] The present application also provides a battery assembly, which includes any of the solar cell sheets described above.

[0023] The present application also provides a photovoltaic system, which includes the above-mentioned battery assembly.

[0024] In the solar cell, preparation method, solar cell assembly, and photovoltaic system of the embodiments of the present application, a P-type silicon substrate is used as the base layer of the solar cell. The P-type doped layer only covers the first region of the first surface and does not cover the second region. The N-type doped layer only covers the third region of the second surface and does not cover the fourth region. The sum of the areas of all third regions is greater than the sum of the areas of all first regions. Thus, using the P-type silicon substrate as the base layer, the first surface of the P-type silicon substrate is not completely covered by the P-type doped layer, and the second surface of the P-type silicon substrate is not completely covered by the N-type doped layer. That is, the P-type doped layer is only provided on the first region for local passivation, while the second region is directly passivated using the first passivation film layer. The passivation performance is good and can improve the passivation effect of the first surface. In this way, the parasitic absorption of light by the P-type doped layer and the N-type doped layer can be effectively reduced while improving the passivation effect, thereby improving the conversion efficiency. Moreover, on a P-type silicon substrate, setting the P-type doped layer on the light-facing surface and setting it locally can reduce parasitic absorption while improving the passivation effect, while setting the N-type doped layer locally on the backlight surface and setting the sum of the areas of all third regions to be larger than the sum of the areas of all first regions can reduce the parasitic absorption on the back side while avoiding the area of ​​the PN junction being too small to cause a decrease in efficiency.

[0025] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic diagram of a module of a photovoltaic system provided in an embodiment of the present application;

[0027] FIG2 is a schematic diagram of a module of a battery assembly provided in an embodiment of the present application;

[0028] FIG3 is a schematic diagram of the cross-sectional structure of a solar cell provided in an embodiment of the present application;

[0029] FIG4 is a schematic diagram of a partial structure of a solar cell provided in an embodiment of the present application;

[0030] FIG5 is another partial structural diagram of a solar cell provided in an embodiment of the present application;

[0031] FIG6 is another schematic cross-sectional view of a solar cell according to an embodiment of the present application;

[0032] FIG7 is another schematic cross-sectional view of a solar cell according to an embodiment of the present application;

[0033] FIG8 is a schematic flow chart of a method for preparing a solar cell according to an embodiment of the present application;

[0034] FIG9 is another schematic flow chart of the method for preparing a solar cell provided in an embodiment of the present application;

[0035] FIG10 is another schematic flow chart of the method for preparing a solar cell provided in an embodiment of the present application.

[0036] Description of main component symbols:

[0037] Photovoltaic system 1000, battery assembly 200, solar cell 100, P-type silicon substrate 10, first surface 11, first region 111, second region 112, second surface 12, third region 121, fourth region 122, P-type doped layer 20, first dielectric layer 30, N-type doped layer 40, second dielectric layer 50, first electrode 60, second electrode 70, first passivation film layer 80, second passivation film layer 90, first inner expansion layer 110, second inner expansion layer 120. Modes for Carrying Out the Invention

[0038] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are merely used to explain the present application and are not intended to limit the present application.

[0039] In the description of this application, it should be understood that the terms "upper", "lower", "length", "width", "back", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0040] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0041] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art will appreciate the application of other processes and / or the use scenarios of other materials.

[0042] Example 1

[0043] Please refer to Figures 1 and 2. The photovoltaic system 1000 in the embodiment of the present application may include the battery assembly 200 in the embodiment of the present application. The battery assembly 200 in the embodiment of the present application may include multiple solar cells 100 in the embodiment of the present application. The multiple solar cells 100 in the battery assembly 200 can be connected in series in sequence to form a battery string. The battery strings can be connected in series, in parallel, or in a combination of series and parallel to achieve current bus output. For example, the connection between the battery cells can be achieved by welding welding strips, and the connection between the battery strings can be achieved by bus bars.

[0044] 3 , the solar cell 100 in the embodiment of the present application may include a P-type silicon substrate 10 , a P-type doped layer 20 , a first dielectric layer 30 , an N-type doped layer 40 , a second dielectric layer 50 , a first electrode 60 , and a second electrode 70 .

[0045] As shown in Figure 3, a P-type silicon substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11. The first surface 11 is the light-facing surface, and the second surface 12 is the backlight surface. The light-facing surface can be understood as the side facing the sunlight when the solar cell 100 is installed, and the backlight surface can be understood as the side facing away from the sunlight when the solar cell 100 is installed. The first surface 11 has a plurality of first regions 111 and second regions 112 arranged alternately in sequence, and the second surface 12 has a plurality of third regions 121 and fourth regions 122 arranged alternately in sequence.

[0046] The P-type doped layer 20 is disposed on the first region 111 and does not cover the second region 112. That is, on the first surface 11, a plurality of P-type doped layers 20 are spaced apart by the second region 112, and two adjacent P-type doped layers 20 are separated by one second region 112. The first dielectric layer 30 is disposed between the P-type doped layer 20 and the first surface 11.

[0047] Specifically, the first dielectric layer 30 may be a tunneling oxide layer, such as a silicon dioxide film layer. The first dielectric layer 30 may cover the entire first region 111 or the first dielectric layer 30 may cover the entire first region 111 and at least a portion of the second region 112 , which is not specifically limited here.

[0048] The N-type doped layer 40 is disposed on the third region 121 and does not cover the fourth region 122. The second dielectric layer 50 is disposed between the N-type doped layer 40 and the second surface 12. The N-type doped layer 40 has opposite polarity to the P-type doped layer 20. That is, on the second surface 12, several N-type doped layers 40 are spaced apart by the fourth region 122, and one fourth region 122 separates two adjacent N-type doped layers 40. The sum of the areas of all third regions 121 is greater than the sum of the areas of all first regions 112. It can be understood that in a P-type silicon substrate 10, the overall areas of the first surface 11 and the second surface 12 are equal. The fact that the sum of the areas of all third regions 121 is greater than the sum of the areas of all first regions 112 means that, in the solar cell 100, the sum of the areas of all N-type doped layers 40 is greater than the sum of the areas of all P-type doped layers 20.

[0049] Specifically, the second dielectric layer 50 can also be a tunneling oxide layer, such as a silicon dioxide film layer. The second dielectric layer 50 can cover the entire third region 121 to achieve carrier tunneling, or the second dielectric layer 50 covers the entire third region 121 and at least part of the fourth region 122. There is no specific limitation here.

[0050] The first electrode 60 contacts the P-type doping layer 20 , and the second electrode 70 contacts the N-type doping layer 40 .

[0051] In the solar cell 100, the battery assembly 200, and the photovoltaic system 1000 of the embodiment of the present application, a P-type silicon substrate 10 is used as the base layer of the solar cell 100, the P-type doped layer 20 only covers the first area 111 of the first surface 11 and does not cover the second area 112, and the N-type doped layer 40 only covers the third area 121 of the second surface 12 and does not cover the fourth area 122, and the sum of the areas of all the third areas 121 is greater than the sum of the areas of all the first areas 112.

[0052] In this manner, a P-type silicon substrate 10 is used as the base layer. The first surface 11 of the P-type silicon substrate 10 is not completely covered by the P-type doped layer 20, and the second surface 12 of the P-type silicon substrate is not completely covered by the N-type doped layer 40. That is, a P-type doped layer is provided only on the first region 111 for localized passivation, while the second region 112 is directly passivated using the first passivation film layer 80. This provides excellent passivation performance and can enhance the passivation effect of the first surface 11. This effectively reduces parasitic absorption of light by the P-type doped layer 20 and the N-type doped layer 40 while enhancing the passivation effect, thereby improving conversion efficiency. Furthermore, on the P-type silicon substrate 10, disposing the P-type doped layer 20 locally on the light-facing surface can reduce parasitic absorption and enhance the passivation effect. Disposing the N-type doped layer 40 locally on the backlight surface and arranging the sum of the areas of all third regions 121 to be greater than the sum of the areas of all first regions 112 can reduce parasitic absorption on the back surface while avoiding the reduced efficiency caused by an excessively small PN junction area.

[0053] It is understandable that because the P-type doped layer 20 has a poor passivation effect on the P-type silicon substrate 10 and parasitic absorption exists, it is necessary to minimize the area of ​​the P-type doped layer 20 to reduce parasitic absorption and improve the passivation effect. At the same time, for the solar cell 100, the parasitic absorption on the light-facing side has a greater impact on efficiency than the parasitic absorption on the back side. Therefore, positioning the P-type doped layer 20 on the light-facing side and localizing it can reduce parasitic absorption while improving the passivation effect. At the same time, the area of ​​the PN junction will also affect the performance of the solar cell 100. If the N-type doped layer 40 is positioned on the light-facing side and the P-type doped layer 20 is positioned on the backlight side, in order to minimize the parasitic absorption on the light-facing side, the area of ​​the N-type doped layer 40 needs to be smaller. At the same time, in order to improve the passivation effect, the area of ​​the P-type doped layer 20 also needs to be smaller. In this case, the area of ​​the PN junction of the solar cell 100 is smaller, affecting efficiency, thus forming a contradiction.

[0054] Therefore, in the embodiment of the present application, a P-type silicon substrate 10 is used, the P-type doped layer 20 is locally arranged on the light-facing surface, the N-type doped layer 40 is arranged on the backlight surface, and the sum of the areas of all third regions 121 is set to be larger than the sum of the areas of all first regions 112. This can improve the passivation effect while reducing the parasitic absorption of the light-facing layer and the backlight side. At the same time, it can also avoid the area of ​​the N-type doped layer 40 being too small, which will lead to the area of ​​the PN junction being too small and affecting the efficiency.

[0055] That is, in the embodiments of the present application, by designing the structure of the silicon substrate, P-type doped layer 20, and N-type doped layer 40 of the solar cell 100, and by setting the sum of the areas of the third region 121 to be larger than the sum of the areas of the first region 111, it is possible to simultaneously reduce parasitic absorption on both the light-facing side and the backlight side, while improving the passivation effect and ensuring the area of ​​the PN junction as much as possible, thereby improving the efficiency of the solar cell 100. From another perspective, although the P-type doped layer 20 and the N-type doped layer 40 are in local contact with the P-type silicon substrate 10, due to the reduction in parasitic absorption and the improvement in passivation effect, and by reasonably setting the areas of the third region 121 and the first region 111, it is also possible to improve the efficiency of the solar cell 100.

[0056] Specifically, in an embodiment of the present application, the solar cell 100 is a solar cell having a double-sided passivation contact structure, wherein the first dielectric layer 30 and the P-type doped layer 20 form a tunneling passivation structure of the first surface 11 , and the second dielectric layer 50 and the N-type doped layer 40 form a tunneling passivation structure of the second surface 12 .

[0057] It can be understood that, as shown in Figure 3, the first surface 11 of the solar cell 100 of the present application is also provided with a first passivation film layer 80, and the first passivation film layer 80 covers the entire first surface 11, that is, the first passivation film layer 80 covers the P-type doped layer 20 and the second region 112.

[0058] A second passivation film layer 90 is provided on the second surface 12, and the second passivation film layer 90 covers the entire second surface 12, that is, the second passivation film layer 90 covers the N-type doped layer 40 and the fourth region 122, the first electrode 60 contacts the P-type doped layer 20 through the first passivation film layer 80, and the second electrode 70 contacts the N-type doped layer 40 through the second passivation film layer 90.

[0059] The first passivation film layer 80 may include at least one of an aluminum oxide film layer, a silicon oxide film layer, a silicon nitride film layer, a silicon carbide film layer, and a silicon oxynitride film layer, or a combination of multiple thereof. For example, in some embodiments, the first passivation film layer 80 may include an aluminum oxide film layer and a silicon nitride film layer stacked in sequence, without limitation herein. The second passivation film layer 90 may also include at least one of an aluminum oxide film layer, a silicon oxide film layer, a silicon nitride film layer, a silicon carbide film layer, and a silicon oxynitride film layer, or a combination of multiple thereof.

[0060] It is understood that in the embodiments of the present application, the battery assembly 200 may further include a metal frame, a backsheet, photovoltaic glass, and an adhesive film (not shown). The adhesive film may be filled between the front surface of the solar cell 100 and the photovoltaic glass, between the back surface and the backsheet, and between adjacent solar cells. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the adhesive film may be EVA film or POE film. The specific selection can be based on actual conditions and is not limited here.

[0061] Photovoltaic glass can cover the adhesive film on the front surface of the solar cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and excellent physical, mechanical, and optical properties. For example, ultra-clear glass can have a light transmittance of over 92%, which can protect the solar cell 100 while minimizing the impact on the efficiency of the solar cell 100. The adhesive film can also bond the photovoltaic glass and solar cell 100 together, providing sealing, insulation, and waterproofing of the solar cell 100.

[0062] The backsheet can be attached to the film on the back of the solar cell 100. The backsheet provides protection and support for the solar cell 100, and has reliable insulation, water resistance, and aging resistance. A variety of backsheet options are available, typically including tempered glass, organic glass, aluminum alloy TPT composite film, etc. The specific configuration can be tailored to the specific situation and is not limited here. The entire assembly consisting of the backsheet, solar cell 100, film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the primary external support structure for the entire battery assembly 200 and provides stable support and installation for the battery assembly 200. For example, the metal frame can be used to install the battery assembly 200 in the desired location.

[0063] Furthermore, in this embodiment, the photovoltaic system 1000 can be applied in photovoltaic power stations, such as ground-based power stations, rooftop power stations, and water-based power stations. It can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it is understood that the application scenarios of the photovoltaic system 1000 are not limited to these. In other words, the photovoltaic system 1000 can be applied in all fields that require solar power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system 1000 may include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array may be an array combination of multiple battery assemblies 200. For example, multiple battery assemblies 200 may form multiple photovoltaic arrays. The photovoltaic arrays are connected to a combiner box, which can combine the current generated by the photovoltaic arrays. The combined current flows through the inverter to convert it into the AC power required by the mains power grid and then connects to the mains power grid to achieve solar power supply.

[0064] In some embodiments, the area of ​​at least a portion of the third region 121 is larger than the sum of the areas of at least a portion of the first region 111. Thus, by making the area of ​​at least a portion of the third region 121 larger, the sum of the areas of all the third regions 121 can be larger than the sum of the areas of all the first regions 111, thereby reducing parasitic absorption while ensuring the area of ​​the PN junction and thus ensuring efficiency.

[0065] In some embodiments, it is preferred that the area of ​​each third region 121 is larger than the area of ​​each first region 111 so that the sum of the areas of all third regions 121 is larger than the sum of the areas of all first regions 111 .

[0066] Furthermore, in some embodiments, the number of the first regions 111 is less than or equal to the number of the third regions 121 .

[0067] Furthermore, in some embodiments, the number of first electrodes 60 is smaller than the number of second electrodes 70. Thus, when each first electrode 60 corresponds to a P-type doped layer 20 and each second electrode 70 corresponds to an N-type doped layer 40, the number of N-type doped layers 40 is relatively large, so that the sum of the areas of all N-type doped layers 40 is larger than the sum of the areas of all P-type doped layers 20, thereby reducing parasitic absorption while ensuring the area of ​​the PN junction to ensure efficiency.

[0068] In some embodiments, the sum of the areas of all second regions 112 is greater than the sum of the areas of all fourth regions 122. Thus, by properly configuring the areas of the second and fourth regions 112, 122, the sum of the areas of all third regions 121 can be made greater than the sum of the areas of all first regions 111. That is, by increasing the area of ​​the second regions 112, the contact area between the P-type doped layer 20 and the P-star silicon substrate can be minimized, thereby reducing parasitic absorption while improving the passivation effect. This also prevents the area of ​​the N-type doped layer 40 from being too small, which would reduce the area of ​​the PN junction and affect efficiency.

[0069] Furthermore, in some embodiments, the area of ​​a single second region 112 may be preferably larger than the area of ​​a single fourth region 122 , such that the sum of the areas of all second regions 112 is larger than the sum of the areas of all fourth regions 122 .

[0070] In some embodiments, the thickness of the N-type doping layer 40 is smaller than the thickness of the P-type doping layer 20 .

[0071] Thus, in the P-type silicon substrate 10, setting the thickness of the P-type doped layer 20 to be thicker can improve the passivation effect of the first surface 11, thereby improving the electrical performance of the cell. In other words, the passivation effect can be improved by increasing the thickness of the P-type doped layer 20.

[0072] In some embodiments, both the P-type doped layer 20 and the N-type doped layer 40 may include a doped semi-insulating polysilicon layer. Thus, the materials of both the P-type doped layer 20 and the N-type doped layer 40 are semi-insulating polysilicon, which has less parasitic absorption than traditional polysilicon. In other words, using such a material can reduce parasitic absorption and improve conversion efficiency.

[0073] Example 2

[0074] In some embodiments, the ratio of the area of ​​the first region 111 to the area of ​​the first surface 11 (ie, the area proportion of the first region 111 ) is less than 8%.

[0075] Thus, setting the area ratio of the first region 111 to the first surface 11 within a range of less than 8% can significantly reduce the area proportion of the P-type doped layer 20, thereby reducing parasitic absorption of the P-type doped layer 20 and improving efficiency. At the same time, setting the area of ​​the first region 111 to be smaller can increase the area of ​​the second region 112, thereby improving the passivation effect of the first surface 11. In other words, the passivation effect of the first surface 11 can be improved while reducing parasitic absorption, thereby improving efficiency.

[0076] Furthermore, in such an embodiment, the ratio of the area of ​​the first region 111 to the area of ​​the first surface 11 is preferably less than 6%, and most preferably less than 5%. In this way, the area of ​​the first region 111 can be set as small as possible to reduce parasitic absorption while improving the passivation effect.

[0077] Example 3

[0078] In some embodiments, the ratio of the area of ​​the third region 121 to the area of ​​the second surface 12 is greater than or equal to 30% and less than 100%.

[0079] In this way, by setting the area of ​​the third region 121 of the second surface 12 to be larger, the area ratio of the N-type doped layer 40 can be guaranteed while reducing parasitic absorption, balancing the passivation contact area (the area of ​​the PN junction) of the N-type doped layer 40 and the parasitic absorption, thereby improving the conversion efficiency.

[0080] Furthermore, in such an embodiment, the ratio of the area of ​​the third region 121 to the area of ​​the second surface 12 is preferably greater than or equal to 40% and less than 100%. Furthermore, in such an embodiment, the ratio of the area of ​​the third region 121 to the area of ​​the second surface 12 is more preferably greater than or equal to 50% and less than 100%, and most preferably greater than or equal to 60% and less than 100%. In this way, the parasitic absorption and the area of ​​the PN junction can be balanced, thereby reducing the parasitic absorption while ensuring the PN junction area as much as possible to ensure efficiency.

[0081] Example 4

[0082] In some embodiments, the oxygen content in the P-type silicon substrate 10 is less than or equal to 12.5 ppma.

[0083] In this way, the oxygen content of the P-type silicon substrate 10 is set to be lower than 12.5 ppma, which can avoid the oxygen content in the P-type silicon substrate 10 being too high, resulting in the formation of oxygen precipitation in the P-type silicon substrate 10 when the P-type doping layer 20 and the N-type doping layer 40 are subsequently formed, thereby reducing the minority carrier lifetime in the P-type silicon substrate 10 and improving the conversion efficiency.

[0084] Specifically, it is not difficult to understand that during the manufacturing process of the battery cell, high temperature is usually used for processing to realize the preparation of the front emitter and the back field (that is, the P-type doping layer 20 and the N-type doping layer 40). During the high temperature process, if the oxygen content in the P-type silicon substrate 10 is too high, it will cause the P-type silicon substrate 10 to produce radially distributed annular or spiral oxygen precipitation during the high temperature process, which will cause the lifetime of the minority carriers in the P-type silicon substrate to decrease, resulting in higher photoinduced decay and lower conversion efficiency.

[0085] In the present application, the inventors of the present application have found through research and verification that by controlling the oxygen content in the P-type silicon substrate 10 to be within 12.5 ppma, the formation of oxygen precipitation can be effectively suppressed, thereby improving the conversion efficiency.

[0086] Furthermore, in such an embodiment, the oxygen content in the P-type silicon substrate 10 may preferably be less than or equal to 12 ppma. Furthermore, in such an embodiment, the oxygen content in the P-type silicon substrate 10 is preferably less than or equal to 11 ppma, and most preferably less than 10 ppma. Specifically, the inventors of the present application have discovered through research and verification that reducing the oxygen content to 12 ppma, 11 ppma, or even below 10 ppma can further suppress the formation of oxygen precipitates and improve the minority carrier lifetime.

[0087] Example 5

[0088] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the first region 111 may have a flat structure, that is, the surface area corresponding to the first region 111 may be a planarized surface.

[0089] Of course, in some embodiments, the surface of the P-type silicon substrate 10 corresponding to the first region 111 has a tower base or micro-texture structure, that is, the surface area corresponding to the first region 111 is a tower base plane or a micro-texture surface.

[0090] It is understandable that, in some implementations, the surface of the P-type silicon substrate 10 corresponding to the first region 111 may also have a flat structure and a tower base or micro-texture structure, which is not specifically limited here.

[0091] Example 6

[0092] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the second region 112 has a pyramid velvet structure, an inverted pyramid velvet structure, or a chain pyramid velvet structure.

[0093] Example 7

[0094] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the third region 121 has a planarized structure, that is, the surface area corresponding to the third region 121 can be a planarized surface.

[0095] Of course, in some embodiments, the surface of the P-type silicon substrate 10 corresponding to the third region 121 has a tower base or micro-texture structure, that is, the surface area corresponding to the third region 121 is a tower base surface or a micro-texture surface.

[0096] It is understandable that, in some implementations, the surface of the P-type silicon substrate 10 corresponding to the third region 121 may also have a flat structure and a tower base or micro-texture structure, which is not specifically limited here.

[0097] Example 8

[0098] In some embodiments, the surface of the P-type silicon substrate 10 corresponding to the fourth region 122 has a pyramid velvet structure, an inverted pyramid velvet structure, or a chain pyramid velvet structure.

[0099] Embodiment 9

[0100] Referring to FIG. 3 , in some embodiments, the width H2 of the third region 121 is greater than the width H1 of the first region 111 .

[0101] In this way, the width of the N-type doped layer 40 in the third region 121 on the backlight side is greater than the width of the P-type doped layer 20 in the first region 111 on the light-facing side. This can reduce parasitic absorption of the N-type doped layer 40 while preventing the passivation contact area (i.e., the area of ​​the PN junction) of the N-type doped layer 40 with the P-type silicon substrate 10 from being too small, which would significantly affect efficiency. It will be understood that in such an embodiment, the length of the first region 11 is consistent with the length of the third region 121.

[0102] Example 10

[0103] In some embodiments, the thickness of the first dielectric layer 30 is greater than the thickness of the second dielectric layer 50 .

[0104] Thus, setting the thickness of the first dielectric layer 30 to be thicker can ensure the passivation effect of the first surface 11 .

[0105] Specifically, in such an embodiment, in the P-type silicon substrate 10 , since the passivation effect of the P-type doped layer 20 is poor, in order to ensure the passivation effect on the light-facing surface, the thickness of the first dielectric layer 30 may be set thicker to improve efficiency.

[0106] Example 11

[0107] In some embodiments, both the first dielectric layer 30 and the second dielectric layer 50 may be porous dielectric layers, and the size of the pores in the first dielectric layer 30 is larger than the size of the pores in the second dielectric layer 50 .

[0108] In this way, by configuring both the first dielectric layer 30 and the second dielectric layer 50 as porous dielectric layers and the pore size of the first dielectric layer 30 being relatively large, the longitudinal resistance of the first dielectric layer 30 can be controlled at a reasonable level.

[0109] Furthermore, in some embodiments, both the first dielectric layer 30 and the second dielectric layer 50 are porous dielectric layers, and the number of holes per unit area in the first dielectric layer 30 is greater than the number of holes per unit area in the second dielectric layer 50 .

[0110] In this way, the greater the number of holes per unit area in the first dielectric layer 30 , the more the longitudinal resistance of the first dielectric layer 30 can be controlled at a reasonable level.

[0111] Example 12

[0112] In some embodiments, the second region 112 and the fourth region 122 are both trench regions, that is, the P-type silicon substrate 10 is sunken to form a groove in the second region 112 and the fourth region 122 .

[0113] In this way, by forming a groove area, the P-type doped layer 20 and the first dielectric layer 30 covering the second area 112 and the N-type doped layer 40 and the second dielectric layer 50 covering the fourth area 122 can be removed, thereby forming an exposed second area 112 and the fourth area 122, so that the first passivation film layer 80 and the second passivation film layer 90 can directly cover the second area 112 and the fourth area 122 directly on the P-type silicon substrate 10, thereby improving the passivation performance.

[0114] Specifically, in such an embodiment, a first dielectric layer 30 and a P-type doped layer 20 may be formed on the first surface 11, and then a portion of the first dielectric layer 30 and the N-type doped layer 40 may be etched away by etching to form the second region 112 (i.e., the trench region). Similarly, for the fourth region 122, a second dielectric layer 50 and an N-type doped layer 40 may be formed on the second surface 12, and then a portion of the second dielectric layer 50 and the fourth doped layer may be etched away by etching to form the fourth region 122 (i.e., the trench region).

[0115] Example 13

[0116] Furthermore, referring to FIG. 4 , in some embodiments, the trench corresponding to the second region 112 extends to below the P-type doped layer 20 , and the P-type doped layer 20 includes a suspended portion 31 suspended above the trench.

[0117] In this way, when the second area 112 of the trench area is formed, the trench extends and etches away part of the P-type silicon substrate 10 below the P-type doped layer 20 so that the P-type doped layer 20 has a suspended portion 31, which can further reduce the passivation contact area of ​​the P-type doped layer 20 with the P-type silicon substrate 10 and improve the passivation effect.

[0118] Example 14

[0119] Referring to FIG. 5 , in some embodiments, the width of the surface of the N-type doped layer 40 in contact with the second dielectric layer 50 is greater than the width of the surface of the N-type doped layer 40 where the second electrode 70 is disposed.

[0120] In this way, it is possible to avoid the passivation contact area of ​​the N-type doped layer 40 to the P-type silicon substrate 10 being too small, thereby significantly affecting the cell efficiency.

[0121] Specifically, as shown in FIG. 5 , in such an embodiment, the N-type doping layer 40 may be in an inverted trapezoidal shape, and the width of the N-type doping layer 40 gradually decreases from the first surface 11 toward the second surface 12 .

[0122] Example 15

[0123] 6 , in some embodiments, a first inner expansion layer 110 is formed between the first dielectric layer 30 and the P-type silicon substrate 10 , and a first preset distance L1 is formed between the first inner expansion layer 110 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10 .

[0124] In this way, when the P-type doped layer 20 is formed, a first inner expansion layer 110 is formed on the P-type silicon substrate 10. The first inner expansion layer 110 at the edge is set to have a certain distance from the side surface of the P-type silicon substrate 10, which can prevent the first inner expansion layer 110 from extending to the edge of the P-type silicon substrate 10 and contacting the N-type doped layer 40 on the second surface 12 to cause leakage.

[0125] Specifically, the "first inner expansion layer 110 located at the edge of the P-type silicon substrate 10" refers to the first inner expansion layer 110 located at the edge on both sides of the arrangement direction of the first region 111 and the second region 112 on the first surface 11 of the P-type silicon substrate 10. As shown in Figure 6, the first inner expansion layer 110 located at the edge of the P-type silicon substrate 10 is the leftmost first inner expansion layer 110 and the rightmost first inner expansion layer 110 in Figure 6, and the side surfaces of the P-type silicon substrate 10 refer to the left and right side surfaces in Figure 6.

[0126] In such an embodiment, the first preset distance may be 0.3um-50um. For example, the first preset distance may be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 15um, 20um, 25um, 30um, 40um, 45um, 50um, or any value between 0.3um and 50um, without limitation. In the embodiment of the present application, the first preset distance may preferably be 1um-20um.

[0127] Example 16

[0128] 7 , in some embodiments, a second inner expansion layer 120 is formed between the second dielectric layer 50 and the P-type silicon substrate 10 , and a second preset distance L2 is formed between the second inner expansion layer 120 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10 .

[0129] In this way, when the N-type doped layer 40 is formed, a second inner expansion layer 120 is formed on the P-type silicon substrate 10. The second inner expansion layer 120 at the edge is set to have a certain distance from the side surface of the P-type silicon substrate 10, which can prevent the second inner expansion layer 120 from extending to the edge of the P-type silicon substrate 10 and contacting the first inner expansion layer 110 to cause leakage.

[0130] Specifically, the "second inner expansion layer 120 located at the edge of the P-type silicon substrate 10" refers to the second inner expansion layer 120 located at the edge on both sides of the arrangement direction of the third region 121 and the fourth region 122 on the second surface 12 of the P-type silicon substrate 10. As shown in Figure 7, the second inner expansion layer 120 located at the edge of the P-type silicon substrate 10 is the leftmost second inner expansion layer 120 and the rightmost second inner expansion layer 120 in Figure 7. The side surfaces of the P-type silicon substrate 10 refer to the left and right side surfaces in Figure 7.

[0131] In such an embodiment, the second preset distance may be 0.3um-50um. For example, the second preset distance may be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1um, 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 15um, 20um, 25um, 30um, 40um, 45um, 50um, or any value between 0.3um and 50um, without limitation. In the embodiment of the present application, the second preset distance may preferably be 1um-20um.

[0132] In some embodiments, the thickness of the second inner expansion layer 120 may be greater than the thickness of the first inner expansion layer 110. Thus, the greater thickness of the second inner expansion layer 120 can further increase the area of ​​the PN junction to improve the efficiency of the solar cell 100.

[0133] Furthermore, in some embodiments, the width of the second inner expansion layer 120 may be greater than the width of the first inner expansion layer 110. This can further increase the area of ​​the PN junction and improve the efficiency of the solar cell 100.

[0134] Furthermore, in some embodiments, the doping concentration of the second inner extension layer 120 may be greater than the doping concentration of the first inner extension layer 110. Thus, by setting the doping concentration of the second inner extension layer 120 to be greater, the passivation effect of the PN junction contact region can be improved.

[0135] 7 , in some embodiments, the second predetermined distance L2 may be preferably greater than the first predetermined distance L1 , so as to prevent the second inner extension layer 120 with a deeper diffusion depth from contacting the first inner extension layer 110 at the edge of the P-type silicon substrate 10 .

[0136] Furthermore, in some embodiments, the distance between the N-type doped layer 40 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10 is greater than the distance between the P-type doped layer 20 located at the edge of the P-type silicon substrate 10 and the side surface of the P-type silicon substrate 10. This further prevents the second inner expansion layer 120 formed by the N-type doped layer 40 from contacting the first inner expansion layer 110 formed by the P-type doped layer 20 at the edge of the P-type silicon substrate 10.

[0137] Example 17

[0138] Referring to FIG. 8 , this embodiment provides a method for preparing a solar cell 100 , which includes the following steps:

[0139] S10: providing a P-type silicon substrate 10;

[0140] The P-type silicon substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11. The first surface 11 is a light-facing surface, and the second surface 12 is a backlight surface. The first surface 11 has a plurality of first regions 111 and second regions 112 alternately arranged in sequence. The second surface 12 has a plurality of third regions 121 and fourth regions 122 alternately arranged in sequence. The sum of the areas of all the third regions 121 is greater than the sum of the areas of all the first regions 112.

[0141] S20: forming a first dielectric layer 30 and a P-type doped layer 20 in sequence on the first region 111;

[0142] S30: forming a second dielectric layer 50 and an N-type doped layer 40 in sequence on the third region 121;

[0143] S40: forming a first passivation film layer 80 on the first surface 11 and forming a second passivation film layer 90 on the second surface 12;

[0144] S50: A first electrode 60 and a second electrode 70 are respectively prepared on the first passivation film layer 80 and the second passivation film layer 90 . The first electrode 60 penetrates the first passivation film layer 80 and contacts the P-type doped layer 20 , and the second electrode 70 penetrates the second passivation film layer 90 and contacts the N-type doped layer 40 .

[0145] In this manner, a P-type silicon substrate 10 is used as the base layer. The first surface 11 of the P-type silicon substrate 10 is not completely covered by the P-type doped layer 20, and the second surface 12 of the P-type silicon substrate is not completely covered by the N-type doped layer 40. That is, a P-type doped layer is provided only on the first region 111 for localized passivation, while the second region 112 is directly passivated using the first passivation film layer 80. This provides excellent passivation performance and can enhance the passivation effect of the first surface 11. This effectively reduces parasitic absorption of light by the P-type doped layer 20 and the N-type doped layer 40 while enhancing the passivation effect, thereby improving conversion efficiency. Furthermore, on the P-type silicon substrate 10, disposing the P-type doped layer 20 locally on the light-facing surface can reduce parasitic absorption and enhance the passivation effect. Disposing the N-type doped layer 40 locally on the backlight surface and arranging the sum of the areas of all third regions 121 to be greater than the sum of the areas of all first regions 112 can reduce parasitic absorption on the back surface while avoiding the reduced efficiency caused by an excessively small PN junction area.

[0146] Embodiment 18

[0147] Referring to FIG. 9 , in some embodiments, step S20 may be implemented by the following steps:

[0148] S21: preparing a first dielectric layer 30 on the entire first surface 11;

[0149] S22: preparing a P-type doped layer 20 on the first dielectric layer 30;

[0150] S23: removing the wrapping layer formed during the preparation of the P-type doped layer 20;

[0151] S24: The P-type doped layer 20 and the first dielectric layer 30 are patterned to form a plurality of spaced grooves on the P-type doped layer 20 and the first dielectric layer 30 to expose a portion of the P-type silicon substrate 10 at the grooves. The portion of the first surface 11 exposed from the grooves is the second region 112, and the unexposed portion is the first region 111.

[0152] Specifically, in step S21 and step S22, the first dielectric layer 30 can be realized by thermal oxidation, chemical liquid oxidation, chemical vapor deposition, or plasma treatment, and the preparation of the P-type doped layer 20 can be formed by physical vapor deposition or chemical vapor deposition.

[0153] In step S23, the wrap-around coating formed during the deposition process can be removed by laser or wet etching. In step S24, the P-type doped layer 20 and the first dielectric layer 30 can be patterned by acid etching, alkaline etching, laser etching, or a combination of at least two of them. For example, in one example, laser patterning can be performed first, and then alkaline etching can be used to remove a portion of the P-type doped layer 20 and the first dielectric layer 30, thereby forming a plurality of grooves, thereby forming a first region 111 having the P-type doped layer 20 and an exposed second region 112 on the P-type silicon substrate 10.

[0154] Example 19

[0155] Referring to FIG. 10 , in some embodiments, step S30 may be implemented by the following steps:

[0156] S31: preparing a second dielectric layer 50 on the entire second surface 12;

[0157] S32: preparing an N-type doped layer 40 on the second dielectric layer 50;

[0158] S33: removing the winding plating layer formed during the preparation of the N-type doping layer 40;

[0159] S34: The N-type doped layer 40 and the second dielectric layer 50 are patterned to form a plurality of spaced grooves on the N-type doped layer 40 and the second dielectric layer 50, thereby exposing a portion of the P-type silicon substrate 10 at the grooves. The portion of the second surface 12 exposed from the grooves is the fourth region 122, and the unexposed portion is the third region 121.

[0160] Specifically, in step S31 and step S32, the second dielectric layer 50 can be realized by thermal oxidation, chemical liquid oxidation, chemical vapor deposition, or plasma treatment, and the preparation of the N-type doped layer 40 can be formed by physical vapor deposition or chemical vapor deposition, which is not limited here.

[0161] In step S33, the wrap-around coating formed during the deposition process can also be removed by laser or wet etching. In step S34, the N-type doped layer 50 and the second dielectric layer 50 are patterned by acid etching, alkaline etching, laser etching, or a combination of at least two. For example, in one example, laser patterning can be performed first, and then alkaline etching can be used to remove a portion of the N-type doped layer 40 and the second dielectric layer 50, thereby forming a plurality of grooves, thereby forming a third region 121 having the N-type doped layer 40 and an exposed fourth region 122 on the P-type silicon substrate 10.

[0162] Throughout this specification, reference to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, the illustrative use of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0163] In addition, the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A solar cell, characterized in that: include: A P-type silicon substrate, the P-type silicon substrate having a first surface and a second surface opposite to the first surface, the first surface being a light-facing surface, the second surface being a light-backed surface, the first surface having a plurality of first regions and second regions alternately arranged in sequence, and the second surface having a plurality of third regions and fourth regions alternately arranged in sequence; A P-type doped layer disposed on the first region and not covering the second region; a first dielectric layer disposed between the P-type doped layer and the first surface; An N-type doped layer disposed on the third region and not covering the fourth region, wherein the sum of areas of all the third regions is greater than the sum of areas of all the first regions; a second dielectric layer disposed between the N-type doped layer and the second surface; and A first electrode and a second electrode, wherein the first electrode contacts the P-type doping layer, and the second electrode contacts the N-type doping layer.

2. The solar cell according to claim 1, characterized in that: An area of ​​at least a portion of the third region is larger than an area of ​​at least a portion of the first region.

3. The solar cell according to claim 1, characterized in that: The area of ​​each of the third regions is greater than the area of ​​each of the first regions.

4. The solar cell according to claim 1, characterized in that: The number of the first regions is less than or equal to the number of the third regions.

5. The solar cell according to claim 4, characterized in that: The number of the first electrodes is less than or equal to the number of the second electrodes.

6. The solar cell according to claim 1, characterized in that: A ratio of an area of ​​the first region to an area of ​​the first surface is less than 8%.

7. The solar cell according to claim 6, characterized in that: A ratio of an area of ​​the first region to an area of ​​the first surface is less than 6%.

8. The solar cell according to claim 7, characterized in that: A ratio of an area of ​​the first region to an area of ​​the first surface is less than 5%.

9. The solar cell according to claim 1, characterized in that: A ratio of an area of ​​the third region to an area of ​​the second surface is greater than or equal to 30% and less than 100%.

10. The solar cell according to claim 9, characterized in that: A ratio of an area of ​​the third region to an area of ​​the second surface is greater than or equal to 40% and less than 100%.

11. The solar cell according to claim 10, characterized in that: A ratio of an area of ​​the third region to an area of ​​the second surface is greater than or equal to 50% and less than 100%.

12. The solar cell according to claim 11, characterized in that: A ratio of an area of ​​the third region to an area of ​​the second surface is greater than or equal to 60% and less than 100%.

13. The solar cell according to claim 1, characterized in that: The oxygen content in the P-type silicon substrate is less than or equal to 12.5 ppma.

14. The solar cell according to claim 13, characterized in that: The oxygen content in the P-type silicon substrate is less than or equal to 12 ppma.

15. The solar cell according to claim 14, characterized in that: The oxygen content in the P-type silicon substrate is less than or equal to 11 ppma.

16. The solar cell according to claim 15, characterized in that: The oxygen content in the P-type silicon substrate is less than or equal to 10 ppma.

17. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the first region has a flat structure; and / or The surface of the P-type silicon substrate corresponding to the first region has a tower base or a micro-texture structure.

18. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the second region has a pyramid velvet structure, an inverted pyramid velvet structure, or a chain pyramid velvet structure.

19. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the third region has a planarized structure; or The surface of the P-type silicon substrate corresponding to the third region has a tower base or a micro-texture structure.

20. The solar cell according to claim 1, characterized in that: The surface of the P-type silicon substrate corresponding to the fourth region has a flat structure; or The surface of the P-type silicon substrate corresponding to the fourth region has a tower base or a micro-texture structure; or The surface of the P-type silicon substrate corresponding to the fourth region has a pyramid structure, an inverted pyramid structure, or a chain pyramid velvet structure.

21. The solar cell according to claim 1, characterized in that: The thickness of the N-type doping layer is smaller than the thickness of the P-type doping layer.

22. The solar cell according to claim 1, characterized in that: The P-type doping layer and the N-type doping layer both include doped semi-insulating polysilicon layers.

23. The solar cell according to claim 1, characterized in that: The width of the third region is greater than the width of the first region.

24. The solar cell according to claim 1, characterized in that: The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

25. The solar cell according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are both porous dielectric layers, and the size of the holes in the first dielectric layer is larger than the size of the holes in the second dielectric layer.

26. The solar cell according to claim 1, characterized in that: The first dielectric layer and the second dielectric layer are both porous dielectric layers, and the number of holes per unit area in the first dielectric layer is greater than the number of holes per unit area in the second dielectric layer.

27. The solar cell according to claim 1, characterized in that: The second region and the fourth region are both groove regions.

28. The solar cell according to claim 1, characterized in that: The trench corresponding to the second region extends to below the P-type doping layer, and the P-type doping layer includes a suspended portion suspended above the trench.

29. The solar cell according to claim 1, characterized in that: A width of a surface of the N-type doping layer in contact with the second dielectric layer is greater than a width of a surface of the N-type doping layer provided with the second electrode.

30. The solar cell according to claim 1, characterized in that: A first inner expansion layer is formed between the first dielectric layer and the P-type silicon substrate, and a first preset distance exists between the first inner expansion layer located at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

31. The solar cell according to claim 30, characterized in that: A second inner expansion layer is formed between the second dielectric layer and the P-type silicon substrate, and a second preset distance exists between the second inner expansion layer located at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

32. The solar cell according to claim 31, characterized in that: The thickness of the second inner expansion layer is greater than the thickness of the first inner expansion layer; and / or The doping concentration of the second inner extension layer is greater than the doping concentration of the first inner extension layer; and / or The width of the second inner expansion layer is greater than the width of the first inner expansion layer.

33. The solar cell according to claim 31, characterized in that: The second preset distance is greater than the first preset distance.

34. The solar cell according to claim 1, characterized in that: The distance between the N-type doped layer at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate is greater than the distance between the P-type doped layer at the edge of the P-type silicon substrate and the side surface of the P-type silicon substrate.

35. A method for preparing a solar cell, characterized in that: include: A P-type silicon substrate is provided, wherein the P-type silicon substrate has a first surface and a second surface opposite to the first surface, wherein the first surface is a light-facing surface, and the second surface is a light-backed surface, wherein the first surface has a plurality of first regions and second regions that are alternately arranged in sequence, and the second surface has a plurality of third regions and fourth regions that are alternately arranged in sequence; and the sum of the areas of all the third regions is greater than the sum of the areas of all the first regions; forming a first dielectric layer and a P-type doped layer in sequence on the first region; forming a second dielectric layer and an N-type doping layer in sequence on the third region; Prepare a first passivation film layer on the first surface and prepare a second passivation film layer on the second surface; A first electrode and a second electrode are prepared on the first passivation film layer and the second passivation film layer, respectively. The first electrode penetrates the first passivation film layer and contacts the P-type doped layer, and the second electrode penetrates the second passivation film layer and contacts the N-type doped layer.

36. The method for preparing a solar cell according to claim 35, characterized in that: Sequentially forming a first dielectric layer and a P-type doped layer on the first region, comprising: forming a first dielectric layer on the entire first surface; Preparing a P-type doped layer on the first dielectric layer; Removing the plating layer formed in the process of preparing the P-type doping layer; The P-type doped layer and the first dielectric layer are patterned to form a plurality of spaced grooves on the P-type doped layer and the first dielectric layer to expose a portion of the P-type silicon substrate at the grooves, the portion of the first surface exposed from the grooves being the second region, and the portion not exposed being the first region.

37. The method for preparing a solar cell according to claim 35, characterized in that: Sequentially forming a second dielectric layer and an N-type doping layer on the third region; comprising: forming a second dielectric layer on the entire second surface; Preparing an N-type doped layer on the second dielectric layer; Removing the wrap-around layer formed during the preparation of the N-type doped layer; The N-type doped layer and the second dielectric layer are patterned to form a plurality of spaced grooves on the N-type doped layer and the second dielectric layer, thereby partially exposing the P-type silicon substrate at the grooves, the portion of the second surface exposed from the grooves being the fourth region, and the unexposed portion being the third region.

38. A battery assembly, characterized in that: A solar cell comprising the solar cell described in any one of claims 1 to 34.

39. A photovoltaic system, characterized in that: Comprising the battery assembly of claim 38.

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