Control circuit of variable-frequency switching converter, and variable-frequency switching converter

Abstract

The present disclosure provides a control circuit of a variable-frequency switching converter, and a variable-frequency switching converter. The control circuit comprises a duty cycle modulation signal generation module, a COT trigger signal generation module, and a control module. The duty cycle modulation signal generation module outputs a duty cycle modulation signal to a first end of the control module. The COT trigger signal generation module outputs a constant on-time trigger signal to a second end of the control module when ripple voltage is smaller than ripple reference voltage. The control module generates a fixed on-frequency pulse width signal on the basis of the duty cycle modulation signal and a clock signal and outputs a control signal on the basis of the fixed on-frequency pulse width signal when not receiving the constant on-time trigger signal, and generates a constant on-time pulse width signal on the basis of the control signal and the constant on-time trigger signal and outputs a target pulse width signal on the basis of the fixed on-frequency pulse width signal and the constant on-time pulse width signal when receiving the constant on-time trigger signal. The switching converter has a faster transient response speed.

Description

Control circuit of variable frequency switching converter and variable frequency switching converter

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on August 8, 2023, with application number 202310996004.9, entitled “Control Circuit of Variable Frequency Switching Converter and Variable Frequency Switching Converter,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuits, and in particular to a control circuit of a variable frequency switching converter and a variable frequency switching converter. Background Art

[0004] Today, the pace of upgrades in consumer, communications, IoT, and automotive electronics is accelerating, with increasingly stringent performance requirements and increasingly complex functionality, placing ever-higher demands on the dynamic performance of switching converters. With the world entering the era of big data, the implementation of national East-West Computing projects, and the rapid advancement of AI technology, the demand for servers and data centers is becoming increasingly urgent. Many servers require rapid current changes in loads such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and other high-power central processing units (CPUs). Furthermore, to ensure data security and the safety and reliability of server systems, server power systems often have even more stringent transient response requirements.

[0005] Fixed-frequency circuits, with their constant cycle, narrower noise spectrum, simpler filtering circuits, and smaller output voltage ripple, are advantageous for multi-phase parallel connection and stable phase control. Variable-frequency circuits, on the other hand, offer faster transient response, resulting in smaller output voltage variations under the same varying load. Therefore, there is an urgent need for a power supply circuit that operates at a constant frequency under stable load conditions and, when the load changes, switches to a variable-frequency circuit to quickly respond to load changes.

[0006] Summary of the Invention

[0007] The embodiments described in the present disclosure provide a control circuit for a variable-frequency switching converter and a variable-frequency switching converter.

[0008] According to a first aspect of the present disclosure, there is provided a control circuit for a variable frequency switching converter, comprising: a duty cycle modulation signal generation module, a COT trigger signal generation module, and a control module;

[0009] Wherein, the duty cycle modulation signal generating module is configured to output the duty cycle modulation signal to the first terminal of the control module;

[0010] The COT trigger signal generating module is configured to output a constant on-time trigger signal to the second terminal of the control module when the ripple voltage is less than the ripple reference voltage;

[0011] The control module is configured to, when not receiving the constant on-time trigger signal, generate a fixed on-frequency pulse width signal based on the duty cycle modulation signal and the clock signal, and generate a control signal based on the fixed on-frequency pulse width signal; when receiving the constant on-time trigger signal, generate a constant on-time pulse width signal based on the control signal and the constant on-time trigger signal, and generate a target pulse width signal based on the fixed on-frequency pulse width signal and the constant on-time pulse width signal;

[0012] Among them, the ripple voltage is generated based on a ripple voltage generating circuit, the ripple voltage generating circuit is used to generate a first ripple voltage, and superimpose the feedback voltage on the output voltage feedback node and the first ripple voltage to generate a ripple voltage, and the first ripple voltage is related to the target pulse width signal output by the control module.

[0013] In some embodiments of the present disclosure, the control module includes a first control unit, a second control unit, a time expansion unit, and a logic OR gate unit;

[0014] The first control unit is configured to generate a fixed conduction frequency pulse width signal based on the duty cycle modulation signal and the clock signal, and output the fixed conduction frequency pulse width signal to the time expansion unit and the logic OR gate unit respectively;

[0015] The time expansion unit is configured to output a first control signal to the second control unit based on the received fixed conduction frequency pulse width signal when the fixed conduction frequency pulse width signal is in a first preset time period, and output a second control signal to the second control unit when the fixed conduction frequency pulse width signal is in a second preset time period, wherein the first preset time period includes a time period when the fixed conduction frequency pulse width signal is a high-level signal plus a minimum off-time of at least one constant on-time pulse width signal; and the second preset time period includes a time period when the fixed conduction frequency pulse width signal is a low-level signal minus the minimum off-time of at least one constant on-time pulse width signal;

[0016] The second control unit is configured to output a constant on-time pulse width signal to the logic OR gate unit based on the constant on-time trigger signal when receiving the second control signal and the constant on-time trigger signal;

[0017] The logic OR gate unit is configured to generate a target pulse signal based on the fixed conduction frequency pulse width signal and the constant conduction time pulse width signal.

[0018] In some embodiments of the present disclosure, when the second control unit receives the first control signal output by the time expansion unit and does not receive the constant on-time trigger signal output by the COT trigger signal generation module, the second control unit does not output the constant on-time pulse width signal to the logic OR gate unit, and the first control unit generates a fixed on-frequency pulse width signal based on the duty cycle modulation signal and the clock signal, and sends the generated fixed on-frequency pulse width signal to the logic OR gate unit, and the logic OR gate unit outputs a target pulse width signal based on the fixed on-frequency pulse width signal;

[0019] When the second control unit receives the second control signal output by the time expansion unit and the constant on-time trigger signal output by the COT trigger signal generation module, the second control unit outputs the constant on-time pulse width signal to the logic OR gate unit. The logic OR gate unit outputs the fixed on-frequency pulse width signal when the fixed on-frequency pulse width signal is at a high level. The logic OR gate unit outputs the constant on-time pulse width signal when the fixed on-frequency pulse width signal is at a low level.

[0020] In some embodiments of the present disclosure, the first end of the first control unit is electrically connected to the oscillator module, the second end of the first control unit is electrically connected to the duty cycle modulation signal generation module, the third end of the first control unit is electrically connected to the first end of the time expansion unit and the first end of the logic OR gate unit, respectively, the second end of the time expansion unit is electrically connected to the first end of the second control unit, the second end of the second control unit is electrically connected to the COT trigger signal generation module, and the third end of the second control unit is electrically connected to the second end of the logic OR gate.

[0021] In some embodiments of the present disclosure, the first control unit includes at least a first latch and a minimum on / off time control unit, wherein a first input terminal of the first latch is electrically connected to the oscillator module, a second input terminal of the first latch is electrically connected to the duty cycle modulation signal generation module, an output terminal of the first latch is electrically connected to a first terminal of the minimum on / off time control unit, and a second terminal of the minimum on / off time control unit is electrically connected to a first terminal of the time expansion unit and a first terminal of the logic OR gate unit, respectively;

[0022] The second control unit at least includes an AND gate, a second latch, a timer and a minimum off-time control unit, wherein the first input end of the AND gate is electrically connected to the second end of the time expansion unit, the second input end of the AND gate is electrically connected to the COT trigger signal generation module, the output end of the AND gate is electrically connected to the first input end of the second latch, the output end of the second latch is electrically connected to the input end of the timer, the output end of the timer is electrically connected to the first end of the minimum off-time control unit, the second end of the minimum off-time control unit is electrically connected to the second end of the logic OR gate unit, and the third end of the minimum off-time control unit is electrically connected to the third input end of the AND gate.

[0023] In some embodiments of the present disclosure, the duty cycle modulation signal generation module includes at least an error amplifier and a first comparator, and the COT trigger signal generation module includes at least a ripple voltage generation circuit, a ripple reference voltage generation circuit, and a second comparator;

[0024] The error amplifier receives a DC output feedback voltage of the main power module, and outputs a first error voltage to the first comparator according to the DC output feedback voltage and a reference voltage;

[0025] The first comparator outputs a duty cycle modulation signal according to the first error voltage and the reference voltage, wherein the duty cycle modulation signal generation module, the COT trigger signal generation module, the control module and the main power module form a loop, and the reference voltage is generated by real-time acquisition of information of the loop;

[0026] The second comparator receives the ripple voltage output by the ripple voltage generating circuit and the ripple reference voltage output by the ripple reference voltage generating circuit, and outputs a constant on-time trigger signal according to the ripple voltage and the ripple reference voltage.

[0027] In some embodiments of the present disclosure, the COT trigger signal generating module and the duty cycle modulation signal generating module reuse the same comparator;

[0028] The first input terminal of the comparator is electrically connected to the output terminal of the error amplifier, the second input terminal of the comparator is electrically connected to the reference voltage node, the third input terminal of the comparator is electrically connected to the ripple voltage generating circuit, the fourth input terminal of the comparator is electrically connected to the ripple reference voltage generating circuit, the first output terminal of the comparator is electrically connected to the first terminal of the control module, and the second output terminal of the comparator is electrically connected to the second terminal of the control module;

[0029] The comparator outputs a duty cycle modulation signal according to the first error voltage and the reference voltage, and outputs a constant on-time trigger signal according to the ripple voltage and the ripple reference voltage.

[0030] In some embodiments of the present disclosure, the ripple voltage generating circuit includes: a first resistor, a first capacitor, a DC offset extraction circuit, a first adder, an amplifier, a first buffer, and a second adder;

[0031] A first end of the first resistor is electrically connected to a switch node, a second end of the first resistor is electrically connected to a first end of a first summer, a first end of the DC offset extraction circuit, and a first end of a first capacitor, respectively, a second end of the DC offset extraction circuit is electrically connected to a second end of the first summer, a third end of the first summer is electrically connected to a first end of an amplifier, a second end of the amplifier is electrically connected to a first end of the second summer, a first end of the first buffer is electrically connected to an output voltage feedback node, a second end of the first buffer is electrically connected to a second end of the second summer, an output end of the second summer is electrically connected to a ripple voltage generation node, and a second end of the first capacitor is electrically connected to a ground node.

[0032] In some embodiments of the present disclosure, the first resistor and the first capacitor filter the sampled voltage corresponding to the switch node and output the filtered voltage to the DC offset extraction circuit. The DC offset extraction circuit extracts the DC signal from the filtered sampled voltage of the switch node. The first adder removes the DC signal from the filtered sampled voltage of the switch node and outputs the AC signal from the filtered sampled voltage of the switch node to the amplifier. The amplifier amplifies the AC signal from the filtered sampled voltage of the switch node and adds the amplified voltage to the DC output voltage of the output voltage feedback node through the second adder to obtain a ripple voltage.

[0033] In some embodiments of the present disclosure, the ripple voltage generating circuit includes: a second buffer, a second resistor, a second capacitor, a first transconductance amplifier, a second transconductance amplifier, a switch, a third capacitor, and a third transconductance amplifier;

[0034] A first end of the second buffer is electrically connected to an output voltage feedback node, a second end of the second buffer is electrically connected to a first end of the second resistor, a second end of the second resistor is electrically connected to a first end of the first transconductance amplifier and a first end of the second capacitor, respectively, a second end of the second capacitor is electrically connected to a ground node, a second end of the first transconductance amplifier is electrically connected to a first reference voltage node, a third end of the first transconductance amplifier and a fourth end of the third transconductance amplifier are electrically connected to a ripple voltage generation node, a fourth end of the first transconductance amplifier is electrically connected to a power supply voltage node, a first end of the second transconductance amplifier is electrically connected to a second reference voltage node, a second end of the second transconductance amplifier is electrically connected to a ground node, a third end of the second transconductance amplifier is electrically connected to a first end of the third capacitor, a first end of the switch, and a first end of the third transconductance amplifier, respectively, a fourth end of the second transconductance amplifier is electrically connected to the power supply voltage node, a second end of the third transconductance amplifier and a third end of the third transconductance amplifier are connected to a ground node, a second end and a third end of the switch are electrically connected to the ground node, a control end of the switch is electrically connected to a pulse width signal output node, and a second end of the third capacitor is electrically connected to the ground node.

[0035] In some embodiments of the present disclosure, the second resistor and the second capacitor filter the sampling voltage corresponding to the output voltage feedback node and output it to the first transconductance amplifier, and the first transconductance amplifier generates a ripple DC voltage; when the switch is in an off state based on the pulse width signal output by the pulse width signal output node, the current output by the third end of the second transconductance amplifier charges the third capacitor, and when the switch is in an on state based on the pulse width signal output by the pulse width signal output node, the third capacitor discharges, and a triangular wave is formed based on the charging and discharging of the third capacitor and input to the third transconductance amplifier, a ripple current is generated based on the third transconductance amplifier, and a ripple voltage is generated based on the voltage generated by the ripple current and the ripple DC voltage.

[0036] In some embodiments of the present disclosure, the ripple reference voltage generating circuit includes: a fourth transconductance amplifier and a fifth transconductance amplifier;

[0037] A first end of the fourth transconductance amplifier is electrically connected to a reference voltage node for outputting a feedback voltage, a second end of the fourth transconductance amplifier is electrically connected to a first reference voltage node, a third end of the fourth transconductance amplifier and a third end of the fifth transconductance amplifier are electrically connected to a ripple reference voltage node, a first end of the fifth transconductance amplifier is electrically connected to a loop voltage node, a second end of the fifth transconductance amplifier is electrically connected to a ground node, and a fourth end of the fourth transconductance amplifier and a fourth end of the fifth transconductance amplifier are electrically connected to a power supply voltage node, respectively.

[0038] According to a second aspect of the present disclosure, a variable frequency switching converter is provided, comprising the control circuit of the variable frequency switching converter according to any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure, rather than limitations of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] FIG1 is a schematic structural diagram of a control circuit of a switching converter provided by an embodiment of the present disclosure;

[0041] FIG2 is a schematic diagram of a circuit structure of a control module provided in an embodiment of the present disclosure;

[0042] FIG3 is a schematic structural diagram of a control circuit of another switching converter provided by an embodiment of the present disclosure;

[0043] FIG4 is a schematic structural diagram of a ripple voltage generating circuit provided by an embodiment of the present disclosure;

[0044] FIG5 is a schematic structural diagram of another ripple voltage generating circuit provided by an embodiment of the present disclosure;

[0045] FIG6 is a schematic structural diagram of a ripple reference voltage generating circuit provided by an embodiment of the present disclosure;

[0046] FIG7 is a working timing diagram provided by an embodiment of the present disclosure;

[0047] FIG8 is an operation timing diagram of a control circuit of a switching converter provided by an embodiment of the present disclosure;

[0048] FIG9 is a schematic diagram of simulation results of the output voltage of a switching converter with an additional variable frequency transient enhancement circuit and the output voltage of a switching converter without an additional variable frequency transient enhancement circuit according to an embodiment of the present disclosure.

[0049] In the drawings, reference numerals having the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0052] Based on the problems existing in the prior art, an embodiment of the present disclosure provides a control circuit of a variable frequency switching converter. As shown in FIG1 , the control circuit of the switching converter includes a duty cycle modulation signal generation module 10, a COT trigger signal generation module 20 and a control module 30; wherein the duty cycle modulation signal generation module 10 is configured to output a duty cycle modulation signal to a first end of the control module 30; the COT trigger signal generation module 20 is configured to output a constant on-time trigger signal to a second end of the control module 30 when the ripple voltage is less than the ripple reference voltage; the control module 30 is configured to output a constant on-time trigger signal based on the duty cycle modulation when the constant on-time trigger signal is not received. A fixed on-frequency pulse width signal is generated based on a control signal and a clock signal, and a control signal is generated based on the fixed on-frequency pulse width signal. When a constant on-time trigger signal is received, a constant on-time pulse width signal is generated based on the control signal and the constant on-time trigger signal, and a target pulse width signal is generated based on the fixed on-frequency pulse width signal and the constant on-time pulse width signal. The ripple voltage is generated based on a ripple voltage generating circuit, the ripple voltage generating circuit is used to generate a first ripple voltage, and the feedback voltage on the output voltage feedback node and the first ripple voltage are superimposed to generate a ripple voltage, and the first ripple voltage is related to the target pulse width signal output by the control module.

[0053] In a specific embodiment, a load R of the power system is electrically connected to a DC output voltage node OUT of the main power module 40. When the power system operates normally, the ripple voltage generation circuit in the COT trigger signal generation module 20 collects the operating status of the main power module 40 (including the upper power tube and the lower power tube), and generates a ripple voltage Vripple based on the collected operating status of the main power module 40 (including the upper power tube and the lower power tube). When the ripple voltage Vripple is higher than the ripple reference voltage Vref_ripple, the COT trigger signal generation module 20 does not generate the constant on-time trigger signal COT_TRIGGLE, that is, the control module 30 does not receive the constant on-time trigger signal COT_TRIGGLE. At this time, the control module 30 generates a fixed on-frequency pulse width signal based on the received duty cycle modulation signal MAIN_TRIP and the clock signal CLK, and generates a control signal corresponding to the fixed on-frequency pulse width signal. At this time, the main power module 40 operates in a fixed on-frequency mode. When the load R corresponding to the power supply system increases, causing the output voltage of the main power module 40 to drop (i.e., the output voltage of the output voltage feedback node FB to drop), at this time, the ripple voltage Vripple generated by the ripple voltage generating circuit 21 based on the collected operating status of the main power module is lower than the ripple reference voltage Vref_ripple. At this time, the COT trigger signal generating module 20 generates a constant on-time trigger signal COT_TRIGGER, that is, the control module 30 receives the constant on-time trigger signal COT_TRIGGER, and the control module 30 first generates a fixed on-frequency pulse width signal based on the received duty cycle modulation signal MAIN_TRIP and the clock signal CLK, generates a control signal based on the fixed frequency pulse signal, and then generates a constant on-time pulse width signal based on the control signal and the constant on-time trigger signal COT_TRIGGER. At this time, the main power module 40 operates alternately in a fixed on-frequency mode and a constant on-time mode.

[0054] As a specific embodiment, as shown in Figure 2, the control module 30 includes a first control unit 31, a second control unit 32, a time expansion unit 33 and a logic OR gate unit 34; the first end of the first control unit 31 is electrically connected to the oscillator module (not shown in the figure), the second end of the first control unit 31 is electrically connected to the duty cycle modulation signal generation module 10, the third end of the first control unit 31 is electrically connected to the first end of the time expansion unit 33 and the first end of the logic OR gate unit 34 respectively, the second end of the time expansion unit 33 is electrically connected to the first end of the second control unit 32, the second end of the second control unit 32 is electrically connected to the COT trigger signal generation module 20, and the third end of the second control unit 32 is electrically connected to the second end of the logic OR gate unit 34.

[0055] The first control unit 31 includes at least a first latch 310 and a minimum on / off time control unit 311. The first input terminal S of the first latch 310 is electrically connected to the oscillator module, the second input terminal R of the first latch 310 is electrically connected to the duty cycle modulation signal generation module 10, the output terminal of the first latch 310 is electrically connected to the first terminal of the minimum on / off time control unit 311, and the second terminal of the minimum on / off time control unit 311 is electrically connected to the first terminal of the time expansion unit 33 and the first terminal of the logic OR gate unit 34 respectively.

[0056] The second control unit 32 at least includes an AND gate 320, a second latch 321, a timer 322 and a minimum off-time control unit 323. The first input terminal of the AND gate 320 is electrically connected to the second terminal of the time expansion unit 33, the second input terminal of the AND gate 320 is electrically connected to the COT trigger signal generation module 20, the output terminal of the AND gate 320 is electrically connected to the first input terminal S of the second latch 321, the output terminal of the second latch 321 is electrically connected to the input terminal of the timer 322, the output terminal of the timer 322 is electrically connected to the first terminal of the minimum off-time control unit 323, the second terminal of the minimum off-time control unit 323 is electrically connected to the second terminal of the logic OR gate unit 34, and the third terminal of the minimum off-time control unit 323 is electrically connected to the third input terminal of the AND gate 320.

[0057] The first control unit 31 is configured to generate a fixed-frequency pulse width signal fixed-frequency PWM based on the duty cycle modulation signal MAIN_TRIP and the clock signal CLK, and output the fixed-frequency pulse width signal fixed-frequency PWM to the time expansion unit 33 and the logic OR gate unit 34 respectively;

[0058] The time expansion unit 33 is configured to, based on the received fixed-frequency pulse width signal fixed-frequency PWM, output a first control signal to the second control unit 32 when the fixed-frequency pulse width signal fixed-frequency PWM is in a first preset time period, and output a second control signal to the second control unit 32 when the fixed-frequency pulse width signal fixed-frequency PWM is in a second preset time period, wherein the first preset time period includes a time period when the fixed-frequency pulse width signal fixed-frequency PWM is a high-level signal plus a minimum off-time of at least one constant on-time pulse width signal COT PWM, and the second preset time period includes a time period when the fixed-frequency pulse width signal fixed-frequency PWM is a low-level signal minus the minimum off-time of at least one constant on-time pulse width signal COT PWM;

[0059] The second control unit 32 is configured to output a constant on-time pulse width signal COT PWM to the logic OR gate unit 34 based on the constant on-time trigger signal COT_TRIGGER when receiving the second control signal and the constant on-time trigger signal COT_TRIGGER;

[0060] The logic OR gate unit 34 is configured to generate a target pulse signal PWM based on the fixed-frequency pulse width signal fixed-frequency PWM and the constant on-time pulse width signal COT PWM.

[0061] As shown in FIG2 , the operating principle of the control module is as follows: when the second control unit 32 receives the first control signal output by the time expansion unit 33 and does not receive the constant on-time trigger signal COT_TRIGGER output by the COT trigger signal generation module 20, the second control unit 32 does not output the constant on-time pulse width signal COT PWM to the logic OR gate unit 34. At this time, the first control unit 31 generates a fixed-frequency pulse width signal fixed-frequency PWM based on the duty cycle modulation signal MAIN_TRIP and the clock signal CLK, and sends the generated fixed-frequency pulse width signal fixed-frequency PWM to the logic OR gate unit 34. Therefore, the logic OR gate unit 34 outputs a target pulse width signal based on the fixed-frequency pulse width signal fixed-frequency PWM, and controls the on and off of the upper power transistor MH and the lower power transistor ML in the main power module 40 based on the target pulse width signal. The main power module 40 operates in a fixed on-frequency mode. When the second control unit 32 receives the second control signal output by the time expansion unit 33 and the constant on-time trigger signal COT_TRIGGER output by the COT trigger signal generation module, the second control unit 32 outputs the constant on-time pulse width signal COT PWM to the logic OR gate unit 34. At this time, the logic OR gate unit 34 outputs the fixed-frequency pulse width signal fixed-frequency PWM when the fixed on-frequency pulse width signal is at a high level, and outputs the constant on-time pulse width signal COT PWM when the fixed on-frequency pulse width signal is at a low level. That is, the target pulse width signal at this time includes the fixed-frequency pulse width signal fixed-frequency PWM and the constant on-time pulse width signal COT PWM, the main power module 40 operates alternately in a fixed conduction frequency mode and a constant conduction time mode, wherein the second control unit 32 receives a constant conduction time trigger signal COT_TRIGGER indicating that the output voltage of the DC output voltage node of the power supply system drops due to a load change, causing the ripple voltage of the COT trigger signal generating module to be lower than the ripple reference voltage. At this time, the working mode of the main power module is adjusted from the fixed frequency mode to the variable frequency mode (that is, the main power module 40 operates alternately in a fixed conduction frequency mode and a constant conduction time mode).

[0062] In the above embodiment, the time expansion unit 33 receives a fixed-frequency pulse width signal (PWM) and outputs a first control signal to the second control unit 32 when the fixed-frequency pulse width signal is within a first preset time period. Furthermore, the time expansion unit 33 outputs a second control signal to the second control unit 32 when the fixed-frequency pulse width signal is within a second preset time period. Specifically, the first control signal is output during the time window in which the fixed-frequency pulse width signal is effective (i.e., the time period in which the fixed-frequency pulse width signal is a high-level signal plus the minimum off-time of at least one constant on-time pulse width signal), and the second control signal is output outside the time window in which the fixed-frequency pulse width signal is effective (i.e., the time period in which the fixed-frequency pulse width signal is a low-level signal minus the minimum off-time of at least one constant on-time pulse width signal). This allows the transient enhancement circuit to intervene in the control when the load increases, adjusting the operating mode of the main power module from the fixed-frequency mode to the variable-frequency mode (i.e., the main power module 40 operates alternately in the fixed-frequency mode and the constant on-time mode).

[0063] It should be noted that, in the above embodiment, when the fixed frequency mode is switched to the variable frequency mode, in order to avoid directly outputting a high-level signal after the switching, a time extension unit is provided. The time extension unit extends the time period in which the fixed on-frequency pulse width signal is a high-level signal by at least one minimum off-time of the constant on-time pulse width signal COT PWM. That is, after the high-level signal of the fixed on-frequency pulse width signal ends, the minimum off-time of the constant on-time pulse width signal COT PWM is added before switching to the variable frequency mode.

[0064] In addition, the above embodiment exemplarily indicates that the first preset time period includes the time period when the fixed-frequency pulse width signal fixed-frequency PWM is a high-level signal plus the minimum off-time of the constant on-time pulse width signal COT PWM, and the second preset time period includes the time period when the fixed-frequency pulse width signal fixed-frequency PWM is a low-level signal minus the minimum off-time of the constant on-time pulse width signal COT PWM. In a specific embodiment, when the variable frequency mode is switched to the fixed frequency mode, in order to avoid switching to the fixed frequency mode when the variable frequency mode is a high-level signal, it is also necessary to extend the time window in which the fixed frequency mode is effective by using a time extension unit to extend the minimum off-time of the constant on-time pulse width signal COT PWM, that is, before the high-level signal of the fixed on-frequency pulse width signal begins, the minimum off-time of the constant on-time pulse width signal COT PWM is added.

[0065] In the above embodiment, the first control unit 31 includes a first latch 310 and a minimum on / off time control unit 311. The set terminal S (i.e., the first input terminal) of the first latch 310 receives the clock signal CLK output by the oscillator module, and the reset terminal R (i.e., the second input terminal) of the first latch 310 receives the duty cycle modulation signal MAIN_TRIP output by the duty cycle modulation signal generation module 10. The output terminal Q of the first latch 310 outputs the first output signal to the minimum on / off time control unit 311. The minimum on / off time control unit processes the first output signal and generates a fixed on-frequency pulse width signal (i.e., a pulse width signal for the first on / off time). The first output signal is processed to ensure that the time when the pulse width signal is at a high level and the time when it is at a low level meet the set time), and the fixed conduction frequency pulse width signal is output respectively and input to the logic OR gate unit 34 and the time expansion unit 33 respectively. When the logic OR gate unit 34 does not receive the constant conduction time pulse width signal output by the second control unit 32, the logic OR gate unit 34 outputs the target pulse width signal PWM to the drive circuit (not shown) based on the fixed conduction frequency pulse width signal. The drive circuit generates a control signal based on the target pulse width signal to the control end of the upper power tube ML and the lower power tube MH to control the conduction and shutdown of the upper power tube MH and the lower power tube ML.

[0066] The second control unit 32 at least includes an AND gate 320, a second latch 321, a timer 322 and a minimum off-time control unit 323. The first end of the AND gate 320 receives the first control signal (low-level signal) or the second control signal (high-level signal) output by the time expansion unit 33, and the second end of the AND gate 320 receives the constant on-time trigger signal COT_TRIGGER (high-level signal) output by the COT trigger signal generation module 20. When the second control signal (high-level signal) is received at the first end of the AND gate 320, the second end of the AND gate 320 receives the constant on-time trigger signal COT_TRIGGER (high-level signal) output by the COT trigger signal generation module 20. When the AND gate 320 receives the constant on-time trigger signal COT_TRIGGER (a high-level signal), the AND gate 320 outputs a high-level signal to the set terminal S (first input terminal) of the second latch 321. The output terminal Q of the second latch 321 outputs a high-level signal, and the timer 322 starts timing so that the time during which the pulse width signal output by the timer is at a high level satisfies the set constant on-time. Then, the minimum off-time control unit ensures that the time during which the pulse width signal output is at a low level satisfies the minimum off-time. Thus, a constant on-time pulse width signal COT PWM is generated and sent to the logic OR gate unit 34. At this time, the logic OR gate unit 34 outputs a target pulse width signal PWM to the drive circuit (not shown) based on the fixed-frequency pulse width signal fixed-frequency PWM and the constant on-time pulse width signal COT PWM. The drive circuit generates a control signal based on the target pulse width signal to the control terminals of the upper power transistor MH and the lower power transistor ML to control the on and off of the upper power transistor MH and the lower power transistor ML.

[0067] In addition, after the timer 322 starts timing, ONE SHOT receives the high level output by the output terminal Q of the second latch 321, outputs a reset pulse to the reset terminal R of the second latch, and resets the state of the second latch 321, so that the output terminal Q of the second latch 321 outputs a low level signal to the timer 322. The timer continues to timing without being affected by the output flip of the output terminal Q of the second latch 321 until the next time the second latch 321 outputs a high level signal, triggering the timer 322 to start timing again, that is, when the inputs of the AND gate 320 are high at the same time again, the set terminal S of the second latch once again receives the high level output by the AND gate 320, and the output terminal Q of the second latch 321 outputs a high level signal to the timer 322.

[0068] It should be noted that in the above embodiment, in the initial state, the third terminal of the AND gate 320 continuously receives the high-level signal output by the minimum off-time control unit 323. At this time, because the first terminal of the AND gate 320 does not receive the second control signal (high-level signal) or the second terminal of the AND gate 320 does not receive the constant on-time trigger signal COT_TRIGGER (high-level signal), the AND gate 320 does not output a high-level signal to the set terminal S of the second latch 321. When the first terminal of the AND gate 320 receives the second control signal (high-level signal) and the second terminal of the AND gate 320 receives the constant on-time trigger signal COT_TRIGGER (high-level signal), the AND gate 320 outputs a high-level signal to the set terminal S of the second latch 321, and the output terminal Q of the second latch 321 outputs a high-level signal. The timer 322 starts timing so that the time during which the pulse width signal output by the timer is at a high level meets the set constant on-time. Then, the minimum off-time control unit ensures that the time during which the pulse width signal output is at a low level meets the minimum off-time. In addition, by setting the third end of the minimum off-time control unit to be electrically connected to the third input end of the AND gate, that is, when the time when the output pulse width signal is at a low level does not meet the minimum off-time, a low-level signal is output to the AND gate, and when the time when the output pulse width signal is at a low level meets the minimum off-time, a high-level signal is output to the AND gate, thereby ensuring that the time when the output constant on-time pulse width signal is at a low level meets the minimum on-time.

[0069] The control circuit of the switching converter provided by the embodiments of the present disclosure combines the characteristics of fixed-frequency and variable-frequency systems. When the ripple voltage generated by the ripple voltage generation circuit based on the collected operating status of the main power module is higher than the ripple reference voltage, the control module generates a fixed on-frequency pulse width signal based on the received duty cycle modulation signal and the clock signal, and outputs a control signal corresponding to the fixed on-frequency pulse width signal, causing the main power module to operate in a fixed on-frequency mode. When the ripple voltage generated by the ripple voltage generation circuit based on the collected operating status of the main power module is lower than the ripple reference voltage, the control module generates a control signal based on the fixed-frequency pulse signal, and then generates a constant on-time pulse width signal based on the control signal and the constant on-time trigger signal. In this case, the main power module operates alternately in a fixed on-frequency mode and a constant on-time mode, thereby improving the transient response speed of the switching converter and minimizing the output voltage variation, thereby ensuring system stability. In addition, the control circuit of the switching converter provided by the embodiments of the present disclosure accelerates the transient response of the power supply system when the load increases, i.e., there is no need to wait for the error amplifier output to change or the next clock cycle to wait. At the same time, it remains a true fixed-frequency system during steady-state operation.

[0070] In addition, as can be seen from FIG1 and FIG2, by adding a variable-frequency transient enhancement circuit to the fixed-frequency system, where the fixed-frequency system can be a voltage-mode, current-mode, V2 control, V2C control, or other fixed-frequency control system, the switching converter remains a true fixed-frequency system during steady-state operation, and the original loop characteristics are not destroyed, and only participate in regulation during the loading process.

[0071] In the above embodiment, as shown in Figure 1, the duty cycle modulation signal generation module 10 includes at least an error amplifier 11 and a first comparator 12, and the COT trigger signal generation module 20 includes at least a ripple voltage generation circuit 21, a ripple reference voltage generation circuit 22 and a second comparator 23; the error amplifier 11 receives the DC output feedback voltage VFB of the main power module 40, and outputs a first error voltage Veaout to the first comparator 12 based on the DC output feedback voltage VFB and the reference voltage Vref_FB; the first comparator 12 outputs the duty cycle modulation signal MAIN_TRIP based on the first error voltage Veaout and the reference voltage Vref; the second comparator 23 receives the ripple voltage Vripple output by the ripple voltage generation circuit 21 and the ripple reference voltage Vref_ripple output by the ripple reference voltage generation circuit 22, and outputs a constant on-time trigger signal based on the ripple voltage Vripple and the ripple reference voltage Vref_ripple.

[0072] As an implementation method, when the power supply system operates normally, the COT trigger signal generation module 20 does not output a constant on-time trigger signal to the control module. The control module 30 generates a fixed on-frequency pulse width signal based on the duty cycle modulation signal MAIN_TRIP and the clock signal CLK, and controls the on and off of the upper power transistor MH and the lower power transistor ML of the main power module 40 based on the generated fixed on-frequency pulse width signal. When the fixed on-frequency pulse width signal is a high-level signal, the control module 30 outputs a control signal to control the upper transistor MH to be turned on and the lower transistor ML to be turned off. When the fixed on-frequency pulse width signal is a low-level signal, the control module 30 outputs a drive control signal to control the upper transistor MH to be turned off and the lower transistor ML to be turned on.

[0073] When the load corresponding to the power supply system increases, the COT trigger signal generating module 20 outputs a constant on-time trigger signal to the control module 30. At this time, the control module 30 controls the on and off of the upper power tube MH and the lower power tube ML of the main power module 40 based on the fixed on-frequency pulse width signal during the time window in which the fixed on-frequency pulse width signal is effective. Outside the time window in which the fixed on-frequency pulse width signal is effective, the control module 30 controls the on and off of the upper power tube MH and the lower power tube ML of the main power module 40 based on the constant on-time pulse width signal. Specifically, in the time window in which the fixed on-frequency pulse width signal is effective, that is, when the fixed on-frequency pulse width signal is a high-level signal, the control module 30 outputs a drive control signal to control the upper transistor MH to be turned on and the lower transistor ML to be turned off. Outside the time window in which the fixed on-frequency pulse width signal is effective, that is, when the fixed on-frequency pulse width signal is a low-level signal, the control module 30 controls the on and off of the upper power transistor MH and the lower power transistor ML of the main power module 40 based on the constant on-time pulse width signal. When the constant on-time pulse width signal is a high-level signal, the control module 30 outputs a drive control signal to control the upper transistor MH to be turned on and the lower transistor ML to be turned off. When the constant on-time pulse width signal is a low-level signal, the control module 30 outputs a drive control signal to control the upper transistor MH to be turned on and the lower transistor ML to be turned on.

[0074] It should be noted that, in this embodiment, when the load corresponding to the power supply system increases, during the process of the COT trigger signal generation module 20 outputting the constant on-time trigger signal to the control module 30, the constant on-time pulse width signal is allowed to be triggered only after the previous fixed on-frequency pulse width signal ends the min-off of at least one constant on-time pulse width signal, that is, outside the time window when the fixed on-frequency pulse width signal is effective, so as to avoid directly outputting a high-level signal when switching from the fixed on-frequency mode to the constant on-time mode, and to ensure that the fixed on-frequency pulse width signal in each cycle will not be interfered with by the constant on-time pulse width signal.

[0075] In addition, the ratio of on time to minimum off time in the constant on-time pulse width signal generated by the second control unit determines, to a certain extent, the maximum duty cycle (i.e., minimum off time) during the system's response to a load change, and thus the speed at which the system can respond to load changes. The on time can be freely selected within a time period less than the clock cycle. When the on time is set to a short value, the frequency conversion action will be more drastic when the system load changes. When the on time is set to a long value, the frequency change is smaller when the system load changes, but there is a possibility of overshoot during the recovery process. The disclosed embodiments do not specifically limit the ratio of on time to minimum off time.

[0076] As a specific implementable manner, the COT trigger signal generating module 20 and the duty cycle modulation signal generating module 30 reuse the same comparator, as shown in Figure 3 (Figure 3 exemplarily shows the multiplexing of the first comparator 12), the first input terminal of the comparator 12 is electrically connected to the output terminal of the error amplifier 11, the second input terminal of the comparator 12 is electrically connected to the reference voltage node Vref, the third input terminal of the comparator 12 is electrically connected to the ripple voltage generating circuit 21, the fourth input terminal of the comparator 12 is electrically connected to the ripple reference voltage generating circuit 22, the first output terminal of the comparator 12 is electrically connected to the first terminal of the control module 30, and the second output terminal of the comparator 12 is electrically connected to the second terminal of the control module 30.

[0077] That is, the comparator outputs the duty cycle modulation signal MAIN_TRIP according to the first error voltage Veaout and the reference voltage Vref, and outputs the constant on-time trigger signal according to the ripple voltage Vripple and the ripple reference voltage Vref_ripple.

[0078] Based on the above embodiment, FIG4 is a schematic structural diagram of a ripple voltage generating circuit provided by an embodiment of the present disclosure. As shown in FIG4, the ripple voltage generating circuit 31 includes: a first resistor R1, a first capacitor C1, a DC offset extraction circuit 311, a first adder 312, an amplifier 313, a first buffer 314 and a second adder 315; a first end of the first resistor R1 is electrically connected to the switch node SW, and a second end of the first resistor R1 is electrically connected to the first end of the first adder 312, the first end of the DC offset extraction circuit 311 and the first end of the first capacitor C1 respectively. The first and second ends of the first summer 315 are electrically connected to each other, a second end of the first buffer 314 is electrically connected to the output voltage feedback node FB, a second end of the first buffer 314 is electrically connected to the second end of the second summer 315, an output end of the second summer 315 is electrically connected to the ripple voltage generation node ripple, and a second end of the first capacitor C1 is electrically connected to the ground node.

[0079] 4 , the first resistor R1 and the first capacitor C1 form a filtering circuit that filters the sampled voltage corresponding to the switch node SW (collecting the voltage corresponding to the main power module) and outputs it to the DC offset extraction circuit 311. The DC offset extraction circuit 311 extracts the DC signal from the signal of the switch node SW. The first adder removes the DC signal from the signal from the switch node SW and outputs the filtered AC signal from the signal of the switch node SW to the amplifier 313. The amplifier amplifies the AC signal from the filtered signal of the switch node SW and adds it to the DC output voltage of the output voltage feedback node FB through the second adder 315 to obtain a ripple voltage.

[0080] In this embodiment, the first ripple voltage generated by the ripple circuit generating circuit 21 is an AC signal in the signal corresponding to the switching node SW output by the first adder 312. The AC signal is related to the target pulse width signal output by the control module. In this implementation, the first ripple voltage can be an AC signal. The specific manner in which the first ripple voltage is related to the target pulse width signal output by the control module 30 includes: the frequency of the first ripple voltage is the same as the frequency of the target pulse width signal, and the duty cycle of the first ripple voltage is the same as the duty cycle of the target pulse width signal.

[0081] On the basis of the above embodiment, FIG5 is a structural diagram of another ripple voltage generating circuit provided by an embodiment of the present disclosure. As shown in FIG5, the ripple voltage generating circuit includes: a second buffer buffer2, a second resistor R2, a second capacitor C2, a first transconductance amplifier gm1, a second transconductance amplifier gm2, a switch P, a third capacitor C3 and a third transconductance amplifier gm3; a first end of the second buffer buffer2 is electrically connected to the output voltage feedback node FB, a second end of the second buffer buffer2 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is electrically connected to the first end of the first transconductance amplifier gm1, the second end of the second resistor R2, and the first end of the second transconductance amplifier gm1 and the second end of the second resistor R2 are respectively connected. A first end of the capacitor C2 is electrically connected, a second end of the second capacitor C2 is electrically connected to the ground node, a second end of the first transconductance amplifier gm1 is electrically connected to the first reference voltage node Ref_1, a third end of the first transconductance amplifier gm1 and a fourth end of the third transconductance amplifier gm3 are electrically connected to the ripple voltage generating node ripple, a fourth end of the first transconductance amplifier gm1 is electrically connected to the power supply voltage node VCC, a first end of the second transconductance amplifier gm2 is electrically connected to the second reference voltage node Ref_2, a second end of the second transconductance amplifier gm2 is electrically connected to the ground node, and a third end of the second transconductance amplifier gm2 is electrically connected to the first end and the fourth end of the third capacitor C3, respectively. A first end of the switch P is electrically connected to a first end of the third transconductance amplifier gm3, a fourth end of the second transconductance amplifier gm2 is electrically connected to a power supply voltage node VCC, a second end of the third transconductance amplifier gm3 and a third end of the third transconductance amplifier gm3 are electrically connected to a ground node, a second end and a third end of the switch P are electrically connected to the ground node, a control end of the switch P is electrically connected to a pulse width signal output node PWM, and a second end of the third capacitor C3 is electrically connected to the ground node.

[0082] In conjunction with Figure 5 , the second resistor R2 and the second capacitor C2 form a filter circuit. The filter circuit filters the sampled voltage corresponding to the output voltage feedback node FB and outputs it to the first transconductance amplifier gm1. The first transconductance amplifier gm1 generates a ripple DC voltage. The control terminal of the switch P is electrically connected to the pulse width signal output node PWM. When the switch P is in the off state based on the pulse width signal output by the pulse width signal output node, the third terminal of the second transconductance amplifier gm2 outputs a current to charge the third capacitor C3. When the switch P is in the on state based on the pulse width signal output by the pulse width signal output node, the third capacitor C3 discharges. The charge and discharge of the third capacitor C3 generates a triangular wave that is input to the third transconductance amplifier gm3. The third transconductance amplifier gm3 generates a ripple current. The ripple voltage Vripple is output based on the voltage generated by the ripple current, the resistor, and the ripple DC voltage.

[0083] In the above embodiment, FIG4 shows a structure in which a ripple signal is superimposed on the output voltage feedback node FB to generate a ripple voltage, and the ripple signal is obtained through the switch node SW. FIG5 shows a structure in which a ripple voltage is generated in the form of a charge pump, wherein the second reference node Ref_2, the second transconductance amplifier gm2, and the third transconductance amplifier gm3 can be used to change the ripple current, thereby controlling the speed of the transient response.

[0084] It should be noted that the applicant has discovered through research that, compared with generating a ripple voltage through the ESR of the output capacitor, the ripple voltage generated by the ripple voltage generating circuit provided in the embodiment of the present application drops faster during the loading process. That is, since a portion of the charge will be extracted from the output capacitor during the load loading process, the response speed of the ripple voltage generating circuit in the present application is slower and the output voltage drops more. Therefore, the ripple voltage generating circuit also includes a differentiator. By setting the differentiator, the differentiator differentiates the DC output feedback voltage VFB and adds it to the ripple voltage to ensure the speed of generating the ripple voltage.

[0085] In addition, in this embodiment, the first ripple voltage generated by the ripple circuit generating circuit 21 is a triangular wave output by the third end of gm2, and the specific manner in which the first ripple voltage generated by the ripple voltage generating circuit 21 is related to the target pulse width signal output by the control module 30 includes: the frequency of the first ripple voltage is the same as the frequency of the target pulse width signal, and the duty cycle of the first ripple voltage is 1-the duty cycle of the target pulse width signal.

[0086] Based on the above embodiments, Figure 6 is a structural schematic diagram of a ripple reference voltage generating circuit provided by an embodiment of the present disclosure. As shown in Figure 6, the ripple reference voltage generating circuit includes: a fourth transconductance amplifier gm4 and a fifth transconductance amplifier gm5; the first end of the fourth transconductance amplifier gm4 is electrically connected to the reference voltage node Ref_FB of the DC feedback voltage, the second end of the fourth transconductance amplifier gm4 is electrically connected to the first reference voltage node Ref_1, the third end of the fourth transconductance amplifier gm4 and the third end of the fifth transconductance amplifier gm5 are electrically connected to the ripple reference voltage node ref_ripple, the first end of the fifth transconductance amplifier gm5 is electrically connected to the loop voltage node, the second end of the fifth transconductance amplifier gm5 is electrically connected to the ground node, and the fourth end of the fourth transconductance amplifier gm4 and the fourth end of the fifth transconductance amplifier gm5 are respectively electrically connected to the power supply voltage node VCC.

[0087] By electrically connecting the first terminal of the fourth transconductance amplifier gm4 to the reference voltage node Ref_FB for the output feedback voltage (the output reference voltage outputted from the reference voltage node Ref_FB), the fourth transconductance amplifier generates a ripple reference voltage based on the output reference voltage outputted from the reference voltage node for the output feedback voltage. Furthermore, by providing the fifth transconductance amplifier gm5, the transient enhancement characteristics can better cover both high and low duty cycle applications.

[0088] In the above embodiment, the loop voltage node is the output node of the voltage processing module. The voltage processing module receives the DC input voltage and the DC output voltage, and outputs a voltage signal associated with the DC input voltage and the DC output voltage after processing the DC input voltage and the DC output voltage.

[0089] In a specific embodiment, with reference to FIG7 , PWM represents a pulse width signal input to the control terminal of the switch P, Vripple represents a ripple voltage generated by the ripple voltage generating circuit shown in FIG5 , and Vref_ripple represents a ripple reference voltage generated by the ripple voltage generating circuit shown in FIG6 . The amplitude H of the ripple voltage can be expressed as: H = k × (1-D) T

[0090] Where k is the ripple voltage slope, D is the duty cycle, and T is the period.

[0091] From Figure 5, it can be deduced that the ripple voltage slope satisfies:

[0092] Therefore, the amplitude H of the ripple voltage can be expressed as:

[0093] From Figure 6, it can be deduced that the ripple reference voltage and ripple voltage satisfy the relationship:

[0094] Right now,

[0095] Among them, C1 and C2 are constants.

[0096] That is, the voltage signal output by the loop voltage node satisfies That is, it is related to the DC input voltage and DC output voltage.

[0097] It should be noted that the circuit in the dotted box in Figure 6 is an optional circuit, that is, the ripple reference voltage generating circuit may include the circuit diagram in the dotted box, or may not include it. In a specific implementation, the ripple reference voltage can be generated by the output reference voltage, that is, it can be generated by the circuit excluding the dotted part shown in Figure 6, or it can be generated by the circuit including the dotted part shown in Figure 6. The embodiment of the present disclosure does not specifically limit this. When the ripple reference voltage is generated based on the ripple reference voltage generating circuit shown in Figure 6, the ripple reference voltage is associated with the DC input voltage and the DC output voltage, and the transient enhancement characteristics can better cover application scenarios with high and low duty cycles.

[0098] The following is an illustration using a specific embodiment. Under the conditions of an input voltage Vin = 12V, an output voltage Vout = 1V, a load step of 1A to 16A in 15μs, an output capacitor C = 100uF, and an inductor L = 220nH, an operating timing diagram of the control circuit of the switching converter is shown in FIG8 . A schematic diagram of the simulation results of the output voltage of the switching converter with and without the variable frequency transient enhancement circuit is shown in FIG9 .

[0099] In FIG9 , waveform 01 is a schematic diagram of the simulation results of the output voltage of the switching converter with the variable frequency transient enhancement circuit added, and waveform 02 is a schematic diagram of the simulation results of the output voltage of the switching converter without the variable frequency transient enhancement circuit added. Combining FIG8 and FIG9 , before time t1, the ripple voltage Vripple is greater than the ripple reference voltage Vref_ripple, and the switching converter operates in a fixed conduction frequency mode. After time t1, the ripple voltage Vripple is less than the ripple reference voltage Vref_ripple, and the COT trigger signal generation module outputs a constant The on-time trigger signal is sent to the control module. At this time, the switching converter operates in a constant on-time mode within the off-time of the fixed on-frequency pulse width signal (that is, outside the time window when the fixed on-frequency pulse width signal is effective, the high-level interval in Figure 8, that is, within the t time period). As can be seen from Figures 8 and 9, under the same conditions, the switching converter with the variable frequency transient enhancement circuit is added. The system performs frequency conversion during the loading process, and the total on-time of the power tube within a fixed frequency cycle is significantly extended. Vout is reduced by 30mV, and the drop is reduced by 58.5%, which greatly reduces the Vout drop value.

[0100] In the control circuit of the switching converter provided by the embodiment of the present disclosure, when the power supply system is operating normally, the ripple voltage Vripple is always higher than the ripple reference voltage Vref_ripple, the COT trigger signal generation module does not trigger the generation of the constant on-time trigger signal, and the control circuit of the switching converter operates in the original fixed on-frequency mode.

[0101] When the load on the power system increases, the output voltage of the main power module drops. If the ripple voltage Vripple is lower than the ripple reference voltage Vref_ripple outside the time window in which the fixed-frequency PWM is effective, the COT trigger signal generation module triggers the generation of a constant on-time trigger signal. The control circuit of the switching converter switches from the original fixed on-frequency mode to alternating operation of the fixed on-frequency mode and the constant on-time mode. That is, the transient enhancement circuit intervenes in the control, and the power system increases the frequency in response to the load change until the ripple voltage Vripple is higher than the ripple reference voltage Vref_ripple. The control circuit of the switching converter switches to the fixed on-frequency mode.

[0102] Based on the above embodiments, the embodiments of the present disclosure further provide a variable frequency switching converter, including the control circuit of the variable frequency switching converter described in any of the above embodiments, and having the beneficial effects described in any of the above embodiments. The embodiments of the present disclosure do not provide examples one by one for this.

[0103] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0104] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0105] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A control circuit for a variable frequency switching converter, characterized in that: include: Duty cycle modulation signal generating module, COT trigger signal generating module and control module; Wherein, the duty cycle modulation signal generating module is configured to output the duty cycle modulation signal to the first end of the control module; The COT trigger signal generating module is configured to output a constant on-time trigger signal to the second terminal of the control module when the ripple voltage is less than the ripple reference voltage; The control module is configured to generate a fixed on-frequency pulse width signal based on the duty cycle modulation signal and the clock signal when the constant on-time trigger signal is not received, and to generate a control signal based on the fixed on-frequency pulse width signal; when the constant on-time trigger signal is received, to generate a constant on-time pulse width signal based on the control signal and the constant on-time trigger signal; and to generate a target pulse width signal based on the fixed on-frequency pulse width signal and the constant on-time pulse width signal; Among them, the ripple voltage is generated based on a ripple voltage generating circuit, the ripple voltage generating circuit is used to generate a first ripple voltage, and the feedback voltage on the output voltage feedback node and the first ripple voltage are superimposed to generate a ripple voltage, and the first ripple voltage is related to the target pulse width signal output by the control module.

2. The control circuit according to claim 1, characterized in that: The control module includes a first control unit, a second control unit, a time expansion unit and a logic OR gate unit; The first control unit is configured to generate a fixed conduction frequency pulse width signal based on the duty cycle modulation signal and the clock signal, and output the fixed conduction frequency pulse width signal to the time expansion unit and the logic OR gate unit respectively; The time expansion unit is configured to output a first control signal to the second control unit based on the received fixed conduction frequency pulse width signal when the fixed conduction frequency pulse width signal is in a first preset time period, and output a second control signal to the second control unit when the fixed conduction frequency pulse width signal is in a second preset time period, wherein the first preset time period includes a time period when the fixed conduction frequency pulse width signal is a high level signal plus a minimum threshold value of at least one constant conduction time pulse width signal. off time; the second preset time period includes a time period in which the fixed conduction frequency pulse width signal is a low level signal minus a minimum off time of at least one constant conduction time pulse width signal; The second control unit is configured to output a constant on-time pulse width signal to the logic OR gate unit based on the constant on-time trigger signal when receiving the second control signal and the constant on-time trigger signal; The logic OR gate unit is configured to generate a target pulse signal based on the fixed conduction frequency pulse width signal and the constant conduction time pulse width signal.

3. The control circuit according to claim 2, characterized in that: When the second control unit receives the first control signal output by the time expansion unit and does not receive the constant on-time trigger signal output by the COT trigger signal generation module, the second control unit does not output the constant on-time pulse width signal to the logic OR gate unit, the first control unit generates a fixed on-frequency pulse width signal based on the duty cycle modulation signal and the clock signal, and sends the generated fixed on-frequency pulse width signal to the logic OR gate unit, and the logic OR gate unit outputs a target pulse width signal based on the fixed on-frequency pulse width signal; When the second control unit receives the second control signal output by the time expansion unit and the constant on-time trigger signal output by the COT trigger signal generating module, the second control unit outputs a constant on-time pulse width signal to the logic OR gate unit. The logic OR gate unit outputs a fixed on-frequency pulse width signal when the fixed on-frequency pulse width signal is at a high level. The logic OR gate unit outputs a constant on-time pulse width signal when the fixed on-frequency pulse width signal is at a low level.

4. The control circuit according to claim 2, characterized in that: A first end of the first control unit is electrically connected to the oscillator module, a second end of the first control unit is electrically connected to the duty cycle modulation signal generating module, a third end of the first control unit is electrically connected to the first end of the time expansion unit and the first end of the logic OR gate unit respectively, a second end of the time expansion unit is electrically connected to the first end of the second control unit, a second end of the second control unit is electrically connected to the COT trigger signal generating module, and a third end of the second control unit is electrically connected to the second end of the logic OR gate.

5. The control circuit according to claim 4, characterized in that: The first control unit at least includes a first latch and a minimum on / off time control unit, a first input end of the first latch is electrically connected to the oscillator module, a second input end of the first latch is electrically connected to the duty cycle modulation signal generation module, an output end of the first latch is electrically connected to a first end of the minimum on / off time control unit, and a second end of the minimum on / off time control unit is electrically connected to a first end of the time expansion unit and a first end of the logic OR gate unit, respectively; The second control unit at least includes an AND gate, a second latch, a timer and a minimum off-time control unit, wherein the first input end of the AND gate is electrically connected to the second end of the time expansion unit, the second input end of the AND gate is electrically connected to the COT trigger signal generating module, the output end of the AND gate is electrically connected to the first input end of the second latch, the output end of the second latch is electrically connected to the input end of the timer, the output end of the timer is electrically connected to the first end of the minimum off-time control unit, the second end of the minimum off-time control unit is electrically connected to the second end of the logic OR gate unit, and the third end of the minimum off-time control unit is electrically connected to the third input end of the AND gate.

6. The control circuit according to claim 1, characterized in that: The duty cycle modulation signal generating module at least includes an error amplifier and a first comparator, and the COT trigger signal generating module at least includes a ripple voltage generating circuit, a ripple reference voltage generating circuit and a second comparator; The error amplifier receives a DC output feedback voltage of the main power module, and outputs a first error voltage to the first comparator according to the DC output feedback voltage and a reference voltage; The first comparator outputs a duty cycle modulation signal according to the first error voltage and the reference voltage, wherein the duty cycle modulation signal generation module, the COT trigger signal generation module, the control module and the main power module form a loop, and the reference voltage is generated by real-time acquisition of loop information; The second comparator receives the ripple voltage output by the ripple voltage generating circuit and the ripple reference voltage output by the ripple reference voltage generating circuit, and outputs a constant on-time trigger signal according to the ripple voltage and the ripple reference voltage.

7. The control circuit according to claim 6, characterized in that: The COT trigger signal generating module and the duty cycle modulation signal generating module reuse the same comparator; The first input terminal of the comparator is electrically connected to the output terminal of the error amplifier, the second input terminal of the comparator is electrically connected to the reference voltage node, the third input terminal of the comparator is electrically connected to the ripple voltage generating circuit, the fourth input terminal of the comparator is electrically connected to the ripple reference voltage generating circuit, the first output terminal of the comparator is electrically connected to the first terminal of the control module, and the second output terminal of the comparator is electrically connected to the second terminal of the control module; The comparator outputs a duty cycle modulation signal according to the first error voltage and the reference voltage. And outputting a constant on-time trigger signal according to the ripple voltage and the ripple reference voltage.

8. The control circuit according to claim 6 or 7, characterized in that: The ripple voltage generating circuit comprises: a first resistor, a first capacitor, a DC offset extraction circuit, a first adder, an amplifier, a first buffer and a second adder; A first end of the first resistor is electrically connected to a switch node, a second end of the first resistor is electrically connected to a first end of a first adder, a first end of the DC offset extraction circuit, and a first end of a first capacitor, respectively, a second end of the DC offset extraction circuit is electrically connected to a second end of the first adder, a third end of the first adder is electrically connected to a first end of an amplifier, a second end of the amplifier is electrically connected to a first end of the second adder, a first end of the first buffer is electrically connected to an output voltage feedback node, a second end of the first buffer is electrically connected to a second end of the second adder, an output end of the second adder is electrically connected to a ripple voltage generation node, and a second end of the first capacitor is electrically connected to a ground node.

9. The control circuit according to claim 8, characterized in that: The first resistor and the first capacitor filter the sampled voltage corresponding to the switch node and output the filtered voltage to the DC offset extraction circuit. The DC offset extraction circuit extracts the DC signal from the filtered sampled voltage of the switch node. The first adder removes the DC signal from the filtered sampled voltage of the switch node and outputs the AC signal from the filtered sampled voltage of the switch node to the amplifier. The amplifier amplifies the AC signal from the filtered sampled voltage of the switch node and then adds the amplified AC signal to the DC output voltage of the output voltage feedback node through the second adder to obtain a ripple voltage.

10. The control circuit according to claim 6 or 7, characterized in that: The ripple voltage generating circuit comprises: a second buffer, a second resistor, a second capacitor, a first transconductance amplifier, a second transconductance amplifier, a switch, a third capacitor and a third transconductance amplifier; The first end of the second buffer is electrically connected to the output voltage feedback node, the second end of the second buffer is electrically connected to the first end of the second resistor, the second end of the second resistor is electrically connected to the first end of the first transconductance amplifier and the first end of the second capacitor respectively, the second end of the second capacitor is electrically connected to the ground node, the second end of the first transconductance amplifier is electrically connected to the first reference voltage node, the third end of the first transconductance amplifier and the fourth end of the third transconductance amplifier are electrically connected to the ripple voltage generation node, the fourth end of the first transconductance amplifier is electrically connected to the power supply voltage node, and the The first end of the second transconductance amplifier is electrically connected to the second reference voltage node, the second end of the second transconductance amplifier is electrically connected to the ground node, the third end of the second transconductance amplifier is electrically connected to the first end of the third capacitor, the first end of the switch and the first end of the third transconductance amplifier respectively, the fourth end of the second transconductance amplifier is electrically connected to the power supply voltage node, the second end of the third transconductance amplifier and the third end of the third transconductance amplifier are connected to the ground node, the second end and the third end of the switch are electrically connected to the ground node, the control end of the switch is electrically connected to the pulse width signal output node, and the second end of the third capacitor is electrically connected to the ground node.

11. The control circuit according to claim 10, characterized in that: The second resistor and the second capacitor filter the sampling voltage corresponding to the output voltage feedback node and output it to the first transconductance amplifier, and the first transconductance amplifier generates a ripple DC voltage; when the switch is in an off state based on the pulse width signal output by the pulse width signal output node, the current output by the third end of the second transconductance amplifier charges the third capacitor, and when the switch is in an on state based on the pulse width signal output by the pulse width signal output node, the third capacitor discharges, and a triangular wave is formed based on the charging and discharging of the third capacitor and input to the third transconductance amplifier, a ripple current is generated based on the third transconductance amplifier, and a ripple voltage is generated based on the voltage generated by the ripple current and the ripple DC voltage.

12. The control circuit according to claim 6 or 7, characterized in that: The ripple reference voltage generating circuit comprises: a fourth transconductance amplifier and a fifth transconductance amplifier; The first end of the fourth transconductance amplifier is electrically connected to a reference voltage node of the output feedback voltage, the second end of the fourth transconductance amplifier is electrically connected to a first reference voltage node, the third end of the fourth transconductance amplifier and the third end of the fifth transconductance amplifier are electrically connected to a ripple reference voltage node, the first end of the fifth transconductance amplifier is electrically connected to a loop voltage node, the second end of the fifth transconductance amplifier is electrically connected to a ground node, and the fourth end of the fourth transconductance amplifier and the fourth end of the fifth transconductance amplifier are electrically connected to a power supply voltage node, respectively.

13. A variable frequency switching converter, characterized in that: A control circuit for a switching converter comprising any one of claims 1-12.

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