Non-volatile memory, control method therefor, and electronic device

Abstract

A non-volatile memory, a control method therefor, and an electronic device. The non-volatile memory comprises a main memory array, which is used for writing data therein and storing data and comprises a plurality of different word lines and a plurality of different bit lines, the word lines intersecting the bit lines, each word line corresponding to one memory address, each single memory address comprising a plurality of memory bit cells, and each word line and each bit line jointly determining one memory bit cell; a counting array, which is configured to count write operations with respect to the memory address corresponding to each single word line, wherein the counting array performs counting once every time data is written once into one or more memory bit cells in the memory address corresponding to the single word line; a gear selection array, which is configured to store gear information of reference currents, each word line corresponding to gear information of one reference current; and a gear lookup table, which is configured to, on the basis of the gear information of the gear selection array, store the information of corresponding reference currents.

Description

Non-volatile memory, control method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on August 4, 2023, with application number 202310981918.8 and application name “A non-volatile memory, its control method, and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a non-volatile memory, a control method thereof, and an electronic device. Background Art

[0003] Memory is a device used to store program and data information. This information is typically digitized and then stored using electrical, magnetic, or optical media. Common memory storage uses binary units within the chip, meaning it is stored as logic 0 or logic 1. In physical devices, this is typically achieved through high or low voltage, high or low resistance, or high or low charge.

[0004] Memories are categorized as volatile and non-volatile, depending on whether the information stored in the memory persists after the chip's external power supply is removed. Volatile memory requires a continuous external power supply to store information. When the external power supply is removed, the stored information disappears. Non-volatile memory, on the other hand, maintains its stored information even after the external power supply is removed.

[0005] Due to the different interface state properties of the memory storage material, the drain-source current corresponding to the two states 0 and 1 in the non-volatile memory changes as the number of write operations increases. It is possible that the drain-source current corresponding to both states increases simultaneously, or that the drain-source current corresponding to both states decreases simultaneously, or that the drain-source current corresponding to one state increases while the drain-source current corresponding to the other state decreases. However, as the number of write operations increases, when the drain-source current corresponding to the two states 0 and 1 stored in the non-volatile memory increases (or decreases) simultaneously, if the reference current remains unchanged, the upper limit of the number of memory write operations is relatively low. In contrast, when the drain-source current corresponding to one state stored in the non-volatile memory increases while the drain-source current corresponding to the other state decreases, the upper limit of the number of memory write operations is relatively high.

[0006] Therefore, when the drain-source currents corresponding to the two states 0 and 1 stored in the non-volatile memory increase (or decrease) simultaneously, how to increase the upper limit of the number of memory write operations is a hot issue studied by those skilled in the art.

[0007] Summary of the Invention

[0008] Embodiments of the present application provide a novel non-volatile memory and a control method thereof, as well as an electronic device, which can effectively increase the upper limit of the number of write operations of the non-volatile memory.

[0009] To achieve the above objectives, this application adopts the following technical solutions:

[0010] According to a first aspect of an embodiment of the present application, a non-volatile memory is provided, which includes a main storage array for being written to and storing data, including multiple different word lines and multiple different bit lines, where the word lines and bit lines intersect; each word line corresponds to a memory address, and a single memory address includes multiple storage bit units, and each word line and each bit line jointly determine a storage bit unit; a counting array is configured to count the number of write operations for the memory address corresponding to a single word line, and the counting array counts once each time data is written to one or more storage bit units in the memory address corresponding to the single word line; a gear selection array is configured to store gear information of a reference current; each word line corresponds to gear information of a reference current; and a gear lookup table is configured to store corresponding reference current information according to the gear information of the gear selection array.

[0011] In a possible implementation, some word lines of a memory are used to store information of the gear lookup table unit.

[0012] In a possible implementation, the reference current information corresponding to each gear is written into the gear lookup table unit when the chip is tested at the factory.

[0013] In a possible implementation, the gear lookup table further stores reference current redundancy information.

[0014] In a possible implementation, the same word line in the main memory array corresponds to the same reference current.

[0015] In a possible implementation, the memory further includes a sense amplifier, which is used to compare a reference current value with data read out from the main storage array.

[0016] In a possible implementation, one end of the sense amplifier is coupled to a reference current value, and the other end is coupled to current value data read out from the main memory array.

[0017] In a possible implementation, a memory includes a plurality of sense amplifiers and a plurality of bit lines, and each of the plurality of sense amplifiers is coupled to a corresponding one of the plurality of bit lines.

[0018] In a second aspect of an embodiment of the present application, a method for controlling a nonvolatile memory is provided. The method includes the following steps: writing desired data to a main memory array, using a counting array to count the number of times data is written to a memory address of a single word line; reading data from a selected word line, selecting a reference current level in a level selection array based on the word line, and finding a reference current corresponding to the level in a level lookup table.

[0019] In a third aspect of an embodiment of the present application, an electronic device is provided. The electronic device includes: a circuit board and a non-volatile memory, wherein the circuit board and the non-volatile memory are coupled. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0021] FIG2a is a schematic diagram showing the relationship between leakage current and the number of times data is written into a memory according to an embodiment of the present application;

[0022] FIG2 b is a schematic diagram showing the relationship between leakage current and the number of times data is written into the memory according to an embodiment of the present application;

[0023] FIG3 is a schematic diagram showing the relationship between leakage current and the number of times data is written into a memory according to an embodiment of the present application;

[0024] FIG4 is a schematic diagram of a circuit structure of a non-volatile memory provided in an embodiment of the present application;

[0025] FIG5 is a schematic diagram of a main storage array and a counter array gear selection circuit provided in an embodiment of the present application;

[0026] FIG6 is a schematic diagram of a data writing process of a counting array according to an embodiment of the present application;

[0027] FIG7 is a schematic diagram of the circuit structure of another non-volatile memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0029] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0030] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0031] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0032] In the embodiments of this application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship. Below, some terms in the embodiments of this application are explained.

[0033] Volatile memory and non-volatile memory (NVM): Memory can be categorized as either volatile or non-volatile based on whether the stored information persists after the chip's external power supply is removed. Volatile memory, exemplified by static random access memory (SRAM) and dynamic random access memory (DRAM), requires a continuous external power supply to store information. Without external power, the stored information is lost. Non-volatile memory includes traditional read-only memory (ROM) and flash memory, ferroelectric random-access memory (FeRAM, ferroelectric field effect transistor (FeFET), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and phase-change random access memory (PCRAM). These non-volatile memories each utilize unique physical principles to maintain information retention after power is removed.

[0034] The main difference between FeRAM, MRAM, RRAM, and PCRAM lies in the different dielectric films connected to the drain of their respective transistors. The drains of FeRAM, MRAM, RRAM, and PCRAM transistors are connected to ferroelectric materials, ferromagnetic materials, resistive switching materials, and phase-change materials, respectively. Therefore, when the transistor gate is turned on, the resistance between the transistor source and drain is different, resulting in different currents flowing through the source and drain. The different drain-source currents then determine the state of the stored information. For example, eflash and FeFET transistors have different dielectrics connected to the gate of the transistor: thin-film floating gate material and ferroelectric material, respectively. Therefore, the threshold voltage Vt of the two transistors is different. At a given gate voltage, the different threshold voltages Vt lead to different resistances between the source and drain, resulting in different currents flowing through the source and drain, which in turn determines the state of the stored information.

[0035] An embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (for example, soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronic products include communication equipment such as servers, storage devices, radars, and base stations.

[0036] As shown in FIG1 , an electronic device 1 includes components such as a memory 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will appreciate that the architecture of the electronic device 1 shown in FIG1 does not limit the electronic device 1 , and the electronic device 1 may include more or fewer components than those shown in FIG1 , or may combine some of the components shown in FIG1 , or may have a different arrangement of components than shown in FIG1 .

[0037] The memory 11 is used to store software programs and modules. The memory 11 primarily includes a program storage area and a data storage area. The program storage area can store and back up the operating system and at least one application required for a function (such as sound playback or image playback). The data storage area can store data generated by the use of the electronic device 1 (such as audio data, image data, and a phone book).

[0038] The processor 12 is the control center of the electronic device 1. It uses various interfaces and lines to connect the various parts of the entire electronic device 1. By running or executing software programs and / or modules stored in the memory 11 and calling data stored in the memory 11, it performs various functions of the electronic device 1 and processes data, thereby monitoring the electronic device 1 as a whole. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Among them, different processing units can be independent devices or integrated into one or more processors. For example, the processor 12 can integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 12. The above-mentioned application processor may be, for example, a central processing unit (CPU).

[0039] The input device 13 is used to receive input digital or character information and generate key signal input related to user settings and function control of the electronic device. For example, the input device 13 may include a touch screen and other input devices. A touch screen, also known as a touch panel, can collect user touch operations on or near the touch screen (such as operations performed by a user using a finger, stylus, or any other suitable object or accessory on or near the touch screen) and drive corresponding connected devices according to a pre-set program.

[0040] The output device 14 is used to output signals corresponding to the input of the input device 13 and the data stored in the memory 11. For example, the output device 14 outputs a sound signal or a video signal.

[0041] As a new type of memory, ferroelectric memory has become one of the mainstream memories due to its characteristics such as non-volatility of stored data.

[0042] 1 , the memory 11 includes a controller and a memory array or a memory circuit. The controller is used to control the reading and writing of the memory array and the memory circuit.

[0043] The memory array includes a plurality of memory cells arranged in an array, and the storage density of the memory cells 200 directly affects the storage density of the memory array.

[0044] The information stored in the memory 11 is typically in binary units, that is, stored in the memory in the form of "logic 0" or "logic 1." This digital logic information is mapped to physical devices, and the corresponding physical states are high or low voltage, high or low resistance, and high or low charge.

[0045] Depending on whether the stored signal in the memory 11 still exists after the external power supply of the chip is removed, the memory 11 can be divided into a volatile memory and a non-volatile memory.

[0046] Due to its unique physical properties, non-volatile memory can retain the state of previously written information when the power is turned off, ensuring that the information is not lost after the power is turned off. In addition, when the power supply of the chip is turned on again, the information stored in the non-volatile memory can be read out.

[0047] Because the state of information retention is closely tied to the physical characteristics of memory 11, a common characteristic of various non-volatile memories is that, after a certain number of write cycles, the physical and electrical states corresponding to the two digital information states represented by logic 0 and logic 1 become too close to be reliably distinguished due to factors such as memory device aging. This upper limit on the number of write cycles is called the non-volatile memory's "upper limit on write cycles," also known as "write endurance."

[0048] As shown in Figure 2a, the horizontal axis represents the number of write operations, cycle, and the vertical axis represents the drain-source current Ids. When the measured value of the drain-source current Ids is greater than the reference current, the first physical state, State 0, is read; when the measured value of the drain-source current Ids is less than the reference current, the second physical state, State 1, is read (Note: The definitions of 0 and 1 can be reversed and are arbitrary). For example, the two physical states can be interchanged: when the measured value of the drain-source current Ids is less than the reference current, the first physical state, State 0, is read; when the measured value of the drain-source current Ids is greater than the reference current, the first physical state, State 1, is read. When the number of memory write operations is approximately 10 to (10^16), the curves of the drain-source current Ids of the two different physical states lie on either side of the reference current line (shown by the dashed line in Figure 2a). When the number of memory write operations is within this range, the drain-source current corresponding to the first physical state, State 0, is consistently greater than the reference current, while the drain-source current corresponding to the second physical state, State 1, is consistently less than the reference current. The two different physical states can be clearly distinguished by the reference current value. However, as the number of write operations to the memory increases, due to aging of the memory device, the drain-source current corresponding to the first physical state, State 0, and the drain-source current corresponding to the second physical state, State 1, become increasingly close. At this point, the number of write operations to the non-volatile memory gradually reaches the upper limit, and the difference in the drain-source currents Ids corresponding to the two physical states is too small to be reliably distinguished.

[0049] As shown in Figure 2b, the horizontal axis is the number of write operations, cycle, and the vertical axis is the drain-source current Ids. When the measured value of the drain-source current Ids is greater than the reference current value, the first physical state, state 0, is read out; when the measured value of the drain-source current Ids is less than the reference current value, the second physical state, state 1, is read out. When the number of memory write operations is less than a specific value C0, the drain-source current value corresponding to the first physical state, state 0, is greater than the reference current value, and the drain-source current value corresponding to the second physical state, state 1, is less than the reference current value. The two different physical states can be clearly distinguished by the reference current value. However, as the number of memory write operations increases, the drain-source current value corresponding to the first physical state, state 0, and the drain-source current value corresponding to the second physical state, state 1, are both greater than the reference current value. Therefore, the two states, the first physical state, state 0, and the second physical state, state 1, cannot be distinguished by the reference current value.

[0050] To summarize, in both of the above scenarios, to distinguish between two different states of information stored in a memory device, a reference current value must first be selected. The drain-source current of the memory device is then measured and the measured current value is compared with the reference current value. When the measured drain-source current of the memory device is greater than the reference current value, one of the information states is inferred; otherwise, the other state is inferred. Alternatively, a reference voltage value or any other measurable physical quantity in the electrical field, such as a reference resistance value, can be selected as the reference physical value.

[0051] By comparison, it can be seen that the characteristic curve of the drain-source current Ids varying with the number of memory write operations in FIG2 a is better than the characteristic curve of the drain-source current Ids varying with the number of memory write operations in FIG2 b .

[0052] Therefore, in some embodiments, when manufacturing a non-volatile memory, a memory medium material that complies with the characteristic curve of FIG. 2 a is preferably selected.

[0053] However, when selecting non-volatile memory dielectric materials or adjusting their properties, multiple dimensions should be considered. In addition to the relationship between the drain-source current Ids and the number of memory write operations, factors such as the memory's read / write speed, read / write power consumption, data retention time, and process difficulty must also be considered. The desired characteristics of various applications often cannot be met simultaneously, and sometimes even conflict. Therefore, it is necessary to prioritize the most important characteristics, sacrificing other characteristics to meet the primary application scenario.

[0054] Therefore, in certain specific scenarios, it is preferred to use memory dielectric materials that meet the characteristics of Figure 2b. However, as shown in Figure 2b, only when the number of memory write operations is less than a specific value C0, the drain-source current value corresponding to the first physical state state 0 is greater than the reference current value, and the drain-source current value corresponding to the second physical state state 1 is less than the reference current value, and the two different physical states can be distinguished by the reference current value. When the number of memory write operations is greater than the specific value C0, the two different physical states cannot be distinguished by the reference current value. How to increase the size of this specific value C0, how to increase the upper limit of the number of memory write operations, and extend the service life of memory devices have become hot issues studied by those skilled in the art.

[0055] Based on this, the present application proposes a non-volatile memory capable of dynamically adjusting a reference current value, which effectively increases the upper limit of the number of write operations of the non-volatile memory and enhances the reliability of the non-volatile memory device.

[0056] As shown in Figure 3, as the number of write operations of the non-volatile memory increases, the drain-source current value corresponding to the first physical state state 0 and the drain-source current value corresponding to the second physical state state 1 will increase accordingly. When the drain-source current value corresponding to the second physical state state 1 is close to the reference current value of gear 1, through the dynamic adjustment of the solution proposed in this application, the reference current value jumps to a higher gear (the reference current value of gear 2 as shown in Figure 3). At this time, corresponding to the same number of write operations of the memory, the drain-source current value corresponding to the second physical state state 1 is less than the reference current value of gear 2, and the drain-source current value corresponding to the first physical state state 0 is greater than the reference current value of gear 2. The drain-source current value corresponding to the second physical state state 1 and the drain-source current value corresponding to the first physical state state 0 can still be distinguished by the reference current value of gear 2.

[0057] By analogy, as shown in Figure 3, when the number of write operations of the memory increases infinitely, the difference between the drain-source current corresponding to the two different physical states can be ignored and cannot be stably distinguished by the reference current value of any gear, reaching the upper limit of the number of write operations of the device.

[0058] Based on the on-chip dynamic reference current adjustment solution provided in the embodiment of the present application, when the number of memory write operations continues to increase, the reference current value level can be continuously changed and improved, thereby effectively increasing the upper limit of the number of memory write operations and greatly extending the service life of the memory.

[0059] As shown in Figure 4, a circuit structure of a memory proposed in an embodiment of the present application includes a plurality of different word lines and a plurality of different bit lines. The product of the number of word lines and the number of bit lines represents the capacity of the memory. The horizontal axis represents the word line WL, for example, WL0, WL1, WL2, WL3...WLn are all word lines. Each word line WL corresponds to a memory address. The number of word lines represents the depth of the memory, that is, how many memory addresses the memory can accommodate. The vertical axis represents the bit line, and the types of bit lines include: bit lines of the main storage array, bit lines of the counting array, and bit lines of the gear selection array. Each bit line intersects with the word line, and each word line and each bit line together determine a storage bit cell bitcell. There are multiple storage bit cells bitcells in the same memory address.

[0060] The main storage array receives information data written from the outside and stores the information data written from the outside.

[0061] The bit lines BL of the main memory array include BL0, BL1, ..., BLn. Typically, the number of bit lines allocated to the main memory array is an integer power of 2. For example, the main memory array may have 16, 32, ..., 128 bit lines.

[0062] When writing data to the memory, the data is written sequentially according to the memory addresses represented by the word lines WL. Data can be written to all bitcells within the same memory address in the main memory array, or to a portion of the bitcells within the same memory address in the main memory array.

[0063] The counting array is configured to count the number of write operations to the memory address corresponding to a single word line. Each time data is written to one or more memory bit cells within the memory address corresponding to the single word line, the counting array counts once. The bit lines CL of the counting array include CL0, CL1, ..., CLn. Assuming that the counting array is assigned 4 to 6 bit lines, the counting limits of the counting array are 16, 32, and 64 times, respectively. Whenever the counting limit is reached, the information in the counting array is cleared and counting restarts. The reference current level must also be re-determined and adjusted.

[0064] When the drain-source current Ids corresponding to the two physical states increases with the accumulation of the number of write operations, if the physical state with the smaller drain-source current Ids is set to 0, the counting array is first cleared, and then the reference current value and the smaller drain-source current Ids value are compared to determine whether the reference current gear needs to be readjusted. Once it is found that the smaller drain-source current Ids value is also greater than the reference current value, the reference current gear is readjusted; if the physical state with the smaller drain-source current Ids is set to 1, the reference current value and the smaller drain-source current Ids value are first compared to determine whether the reference current gear needs to be readjusted, and then the counting array is cleared.

[0065] When the drain-source currents Ids corresponding to both physical states decrease with the accumulation of write operations, if the physical state with the smaller drain-source current Ids is set to 0, the reference current value and the smaller drain-source current Ids value are first compared to determine whether the reference current range needs to be readjusted, and then the count array is cleared. If the physical state with the smaller drain-source current Ids is set to 1, the count array is first cleared, and then the reference current value and the smaller drain-source current Ids value are compared to determine whether the reference current range needs to be readjusted.

[0066] The gear selection array is configured to store the gear information of the reference current. Each word line corresponds to a gear information of a reference current. The bit lines SL of the gear selection array include SL0, SL1, ... SLn. Assuming that three bit lines are assigned to the gear selection array, the gear selection array can store eight different gears. Each gear corresponds to a reference current value. The correspondence between the gear information of the gear selection array and the reference current value is stored in the gear lookup table. Some word lines of the memory are used to store the information of the gear lookup table.

[0067] As shown in Figure 6, the logic flow chart of the cooperation between the counting array and the gear selection array, where Iref is the reference current and σ is the current redundancy. At the beginning of the process, the counting array information is cleared and the main storage array writes data information. Every time data information is written to the main storage array, the counting array counts once until the count of the counting array reaches the upper limit. When the count of the counting array reaches the upper limit, the current information of the lowest bit line CL0 of the counting array is read to determine whether it is greater than the reference current Iref-σ. If the current information of the lowest bit line CL0 of the counting array is greater than the reference current Iref-σ, the information in the gear selection array is increased by 1, that is, it jumps to a higher reference current gear, and the information of the counting array is cleared. If the current information of the lowest bit line CL0 of the counting array is still less than Iref-σ, the information in the gear selection array remains unchanged, and the counting array information is cleared.

[0068] The number of allocated bit lines of different memory arrays can be flexibly allocated according to specific usage scenarios, and the embodiments of the present application do not limit this.

[0069] As shown in Figure 4, it can also be seen that the same word line WL intersects the bit lines BL of the main storage array, the bit lines CL of the counter array, and the bit lines SL of the gear select array. In other words, the same memory address corresponds to the same gear select array information and the same count array information.

[0070] Because the information in the gear select array can be used to index the corresponding reference current value in the gear lookup table, and the information in the count array represents the number of write operations for the memory address corresponding to the word line WL, all bitcells in the main memory array are compared with the same reference current value for the same memory address, and all bitcells at the same memory address have the same number of write operations.

[0071] Similarly, different word lines WL correspond to different memory addresses, and bit cells at different addresses have different write operation times, and the difference is large. The reference current values ​​corresponding to bit cells at different memory addresses are also different.

[0072] Before the chip is tested at the factory, the reference current information and current redundancy information corresponding to each gear are written into the gear lookup table according to the test results for subsequent search.

[0073] The memory further includes a sense amplifier SA, which is used to compare a reference current value with the current read out from the main memory array to determine the stored information data.

[0074] First, the memory address of the main memory array to be read is selected, that is, the word line WL is selected first, the information data in the main memory array is read, and then the bit line SL of the gear selection array that intersects with the word line is found. The gear information stored in the gear selection array is determined by the bit line SL. Based on the gear information, the corresponding reference current value is found in the gear lookup table. The reference current is drawn and compared with the information data read from the main memory array. It should be noted that when the word line WL to be read is selected, the channel of the word line WL will be opened, and the channels of the remaining word lines WL will remain closed. The information data of all the bit cells of the main memory array that intersect with the word line WL will be read.

[0075] As shown in Figure 4, one end of the sense amplifier SA receives a reference current value (which can also be voltage information, which is then converted into current information through a resistor), and the other end receives information data read from the main storage array. For ease of description, the embodiment of the present application uses eight different levels of reference current values ​​as an example. Of course, in other embodiments, the reference current value level is not limited to eight, and can be any other integer level.

[0076] As shown in FIG4 , each of the plurality of sense amplifiers SA is coupled to a corresponding bit line of the plurality of bit lines, including the bit lines BL of the main storage array, the bit lines CL of the counter array, and the bit lines SL of the gear selection array.

[0077] As shown in Figure 5, the input terminals of the sense amplifiers SA corresponding to different arrays are different. The sense amplifier SA corresponding to the gear selection array has its first input terminal coupled to the gear selection array's bit line SL, and its second input terminal is coupled to the reference ground voltage terminal. Therefore, the information output by the sense amplifier SA is the information of the gear selection array's bit lines SL. For example, when there are three bit lines SL assigned to the gear selection array, three sense amplifiers SA are assigned to couple to the gear selection array's bit lines SL. The first input terminals of the three sense amplifiers SA are coupled to the gear selection array's bit lines SL0, SL1, and SL2, respectively. The output terminals of the multiple sense amplifiers SA coupled to the gear selection array's bit lines SL are all coupled to the bit select terminals of a data selector MUX8, which provides gear information to the data selector. The data input terminal of the data selector MUX8 is coupled to a gear lookup table to receive information entered in the gear lookup table. Therefore, the data selector MUX8 retrieves the reference current value corresponding to the gear information from the gear lookup table according to the gear information received by the bit selection terminal, and uses the reference current value as the output terminal of the data selector MUX8.

[0078] The first input terminal of the sense amplifier SA corresponding to the main storage array is coupled to the bit line BL of the main storage array to receive the information data read out of the main storage array; the second input terminal of the sense amplifier SA is coupled to the output terminal of the data selector MUX8 to receive the reference current value retrieved by the data selector MUX8 from the gear lookup table, and finally compares the retrieved reference current value with the information data read out of the main storage array.

[0079] In the above embodiment, both the bit lines CL of the counter array and the bit lines BL of the main memory array are coupled to sense amplifiers SA, which compare a reference current with the information read from the array. The two input terminals of the sense amplifier SA compare the magnitudes of analog signals.

[0080] In other embodiments, as shown in FIG7 , one of the bit lines CL0 of the counting array is coupled to a comparison readout circuit. The comparison readout circuit includes an analog-to-digital converter ADC and a comparator. The analog current value drawn from the counting array bit line CL0 is first converted into a digital signal through the analog-to-digital converter ADC. The output end of the analog-to-digital converter ADC is then coupled to the first input end of the comparator, and the second input end of the comparator receives information on the reference current value, and the two are compared. Compared with the above embodiment, the embodiment of the present application replaces the sensitive comparator SA corresponding to the counting array with a combination of the analog-to-digital converter ADC and the comparator. Since the sum of the circuit area of ​​the analog-to-digital converter ADC and the comparator is still smaller than the circuit area of ​​the sensitive comparator SA, the design scheme of the embodiment of the present application saves circuit area costs.

[0081] In other embodiments, the information data derived from all bit lines CL of the counting array can be read, and then the average value of the information data derived from all bit lines CL of the counting array can be calculated. For example, if the counting array is assigned 6 bit lines, the average value of the information data is (CL0+CL1+CL2+CL3+CL4+CL5) / 6. The average value of all bit lines CL of the counting array is then compared with a reference current value to determine whether the reference current level needs to be adjusted.

[0082] In some embodiments, the main memory array, counter array, gear selection array, and gear lookup table unit can be combined into a single memory array during chip manufacturing. In some special application scenarios, these four memory components can also be independent arrays during chip manufacturing to facilitate a more regular chip layout and metal wiring.

[0083] The design proposed in the embodiments of this application not only avoids the shortcomings of parameter drift caused by aging and other factors in core materials, but also effectively increases the upper limit of the number of memory write operations. This improves the consistency of the entire memory bit cell, increases the yield, and reduces the bit error rate.

[0084] Dynamic reference current adjustment is implemented within the memory, eliminating the need for external software. This eliminates the need for external non-volatile memory and other on-chip non-volatile memory, saving area costs. Furthermore, there's no need to store the number of memory write operations, reducing the capacity of the counter array and gear selection array.

[0085] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0086] Those skilled in the art will appreciate that the devices and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0087] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the electronic device and display device described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0088] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0089] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0090] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A non-volatile memory, characterized in that: include: A main storage array, for being written with data and storing data, the main storage array comprising a plurality of different word lines and a plurality of different bit lines, the word lines and the bit lines intersecting; Each word line of the plurality of word lines corresponds to a memory address, the single memory address includes a plurality of memory bit units, and each word line of the plurality of word lines and each bit line of the plurality of bit lines jointly determine one memory bit unit; a counting array configured to count the number of write operations of the memory address corresponding to the single word line, wherein the counting array counts once each time data is written to one or more storage bit cells in the memory address corresponding to the single word line; A gear selection array is configured to store gear information of a reference current; each of the word lines corresponds to a gear information of the reference current; The gear lookup table is configured to store corresponding reference current information according to the gear information of the gear selection array.

2. The nonvolatile memory according to claim 1, wherein: Some word lines of the memory are used to store information of the gear lookup table.

3. The non-volatile memory according to any one of claims 1 to 2, characterized in that: The reference current information corresponding to each gear is written into the gear lookup table unit when the chip is tested at the factory.

4. The non-volatile memory according to any one of claims 1 to 3, characterized in that: The gear lookup table also stores the reference current redundant information.

5. The non-volatile memory according to any one of claims 1 to 4, characterized in that: The same word line in the main storage array corresponds to the same reference current.

6. The non-volatile memory according to any one of claims 1 to 5, characterized in that: The memory further includes a sense amplifier, which is used to compare the reference current value with the data read out from the main storage array.

7. The non-volatile memory according to any one of claims 1 to 6, characterized in that: One end of the sense amplifier is coupled to the reference current value, and the other end is coupled to the current value data read out from the main storage array.

8. The non-volatile memory according to any one of claims 1 to 7, characterized in that: The memory includes a plurality of the sense amplifiers and a plurality of bit lines, and each of the plurality of sense amplifiers is coupled to each of the plurality of bit lines.

9. A method for controlling a non-volatile memory, characterized in that: Writing the data to be stored into the main storage array, the counting array is used to count the number of times the memory address of a single word line is written with data; The data of the selected word line is read, a gear of the reference current is selected in the gear selection array according to the word line, and a corresponding reference current is found according to the gear in the gear lookup table.

10. An electronic device, characterized in that: include: A circuit board and a non-volatile memory are coupled to each other.

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