Tile distribution control method, chip and apparatus, tile distribution controller, electronic device, storage medium, and computer program product

Abstract

The embodiments of the present disclosure relate to the technical field of computers. Disclosed are a tile distribution control method, chip and apparatus, a tile distribution controller, an electronic device, a storage medium, and a computer program product, which at least solve the problems of an initialization time being long, hardware resource consumption being high, a GPU utilization rate being low, etc. The specific implementation solution includes: on the basis of at least one identification bit in layer-effective identification information, determining at least one target layer to be rendered from among at least one layer to be rendered, wherein each identification bit indicates whether a corresponding layer to be rendered is effective; and for each target layer to be rendered, on the basis of tile indication information of at least one rendering core, determining a target rendering core corresponding to at least one target tile in the target layer to be rendered, such that each target rendering core renders a corresponding target tile in parallel, wherein each piece of tile indication information is used for indicating the number of tiles to be rendered that a corresponding rendering core may receive.

Description

Control method, chip and device for tile distribution, controller, electronic device, storage medium and computer program product

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The embodiments of the present disclosure are based on and claim the priority of Chinese patent application with application number 202310993195.3, application date August 8, 2023, and application name “Control method, chip and device, controller, equipment and medium for tile distribution”. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to, but is not limited to, the field of computer technology, and in particular to a control method, chip and device, controller, electronic device, storage medium, and computer program product for tile distribution. Background Art

[0004] In the DirectX (DX) standard, a render target (RT) is allowed to bind two-dimensional array (2DArray) resources (e.g., scenes, textures, etc.) to achieve multi-layer rendering, that is, rendering multiple rendering scenes or multiple texture resources to different layers.

[0005] In the related art, in a tile-based rendering (TBR) architecture, rendering is usually performed layer by layer. On the one hand, since each layer requires designated hardware (e.g., Fireware) to perform register initialization and other tasks, this not only prolongs the initialization time but also increases hardware resource consumption. On the other hand, since the rendering of the subsequent layer must wait for the rendering of the previous layer to be completed, the two layers are discontinuous in the hardware, resulting in a large amount of idle time (also known as pipeline interruption) of the GPU (Graphics Processing Unit), reducing GPU utilization.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a control method, chip and device, controller, electronic device, storage medium, and computer program product for tile distribution.

[0008] The present disclosure provides a method for controlling tile distribution, including:

[0009] Determining at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information;

[0010] For each target layer to be rendered, based on the tile indication information of at least one rendering core, a target rendering core corresponding to at least one target tile in the target layer to be rendered is determined, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0011] An embodiment of the present disclosure provides a controller for distributing tiles, the controller including a processing part and a generating part, wherein:

[0012] The processing part is used to determine at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information;

[0013] Therefore, the generating part is used to determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on the tile indication information of at least one rendering core, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0014] The present disclosure provides a control chip for tile distribution, which is applied to a graphics processor. The graphics processor performs a tile distribution process based on a tile rendering (TBR) architecture, wherein:

[0015] The front-end module of the TBR architecture is used to determine layer validity identification information based on a picture to be rendered; wherein the picture to be rendered includes at least one layer to be rendered, and the layer validity identification information includes at least one identification bit;

[0016] The controller is configured to obtain the layer valid identification information determined by the front-end module; determine at least one target layer to be rendered from at least one layer to be rendered based on at least one identification bit in the layer valid identification information; and determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on tile indication information of at least one rendering core; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0017] The back-end module of the TBR architecture is used to utilize each target rendering core to render the corresponding target tile in parallel to complete the rendering of the to-be-rendered picture.

[0018] An embodiment of the present disclosure provides a device for controlling tile distribution, the device comprising:

[0019] A first determining module is configured to determine at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information;

[0020] The second determination module is configured to determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on tile indication information of at least one rendering core, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0021] An embodiment of the present disclosure provides an electronic device, including a processor and a memory, wherein the memory stores a computer program that can be run on the processor, and the processor implements the above method when executing the computer program.

[0022] An embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the above method is implemented.

[0023] An embodiment of the present disclosure provides a computer program product, including a non-transitory computer-readable storage medium storing a computer program, wherein the computer program implements the above method when read and executed by a computer.

[0024] In an embodiment of the present disclosure, at least one target layer to be rendered is determined from at least one layer to be rendered based on at least one identification bit in layer validity identification information; for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered is determined based on tile indication information of at least one rendering core, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive. In this way, multiple valid target layers to be rendered are determined based on the layer validity identification information, thereby achieving the merging of multiple layers to be rendered. On the one hand, compared to performing initialization work for each layer once, the initialization of multiple layers to be rendered is completed through a single initialization work, which not only shortens the initialization time but also reduces hardware resource consumption. On the other hand, compared to rendering a subsequent layer, which must wait for the previous layer to be rendered, processing multiple target layers to be rendered simultaneously makes the multiple target layers to be rendered continuous in the hardware, thereby reducing GPU idle time, thereby improving GPU utilization and reducing the possibility of hardware performance degradation caused by pipeline interruption. At the same time, the target rendering core of the target tile is determined by the tile indication information of each rendering core, reducing the possibility of idleness caused by the idleness of some rendering cores and the waste of hardware resources. This balances the load of each rendering core while improving the rendering efficiency, thereby improving the overall rendering performance of the graphics processor.

[0025] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments of the present disclosure will be described below.

[0027] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0028] FIG1A is a first schematic diagram of multi-layer rendering in a related technology provided by an embodiment of the present disclosure;

[0029] FIG1B is a schematic diagram of a typical TBR pipeline process provided by an embodiment of the present disclosure;

[0030] FIG1C is a second schematic diagram of multi-layer rendering in a related technology provided by an embodiment of the present disclosure;

[0031] FIG1D is a schematic diagram of a first implementation flow of a method for controlling tile distribution according to an embodiment of the present disclosure;

[0032] FIG1E is a schematic diagram of layer valid identification information provided by an embodiment of the present disclosure;

[0033] FIG1F is a schematic diagram of a division result of a target layer to be rendered provided by an embodiment of the present disclosure;

[0034] FIG1G is a schematic diagram of a target layer to be rendered and a rendering core provided by an embodiment of the present disclosure;

[0035] FIG1H is a schematic diagram of storage locations of multiple layers to be rendered in a GPU memory according to an embodiment of the present disclosure;

[0036] FIG2A is a second schematic diagram of an implementation flow of a method for controlling tile distribution provided by an embodiment of the present disclosure;

[0037] FIG2B is a schematic diagram of a resource table provided in an embodiment of the present disclosure;

[0038] FIG3 is a third schematic diagram of an implementation flow of a method for controlling tile distribution provided by an embodiment of the present disclosure;

[0039] FIG4A is a first structural diagram of a controller for tile distribution according to an embodiment of the present disclosure;

[0040] FIG4B is a schematic diagram of target tile distribution provided by an embodiment of the present disclosure;

[0041] FIG4C is a second structural diagram of a controller for tile distribution provided by an embodiment of the present disclosure;

[0042] FIG5A is a schematic diagram of the structure of a control chip for block distribution provided by an embodiment of the present disclosure;

[0043] FIG5B is a schematic diagram of a backend module processing multi-layer rendering according to an embodiment of the present disclosure;

[0044] FIG5C is a schematic diagram of a multi-layer rendering provided by an embodiment of the present disclosure;

[0045] FIG6 is a schematic diagram of the structure of a control device for distributing image tiles according to an embodiment of the present disclosure;

[0046] FIG7 is a schematic diagram of a hardware entity of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0048] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0049] In the following description, the terms "first\second\third" are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0051] In DX, RT is allowed to bind multiple scenes or multiple textures of 2DArray, and an index value (RenderTargetArrayIndex, rta_idx) is output for each primitive in multiple scenes or multiple textures through the Geometry Shader (GS). The Output Merger Stage renders each primitive to a different layer according to the rta_idx carried by the primitive to achieve multi-layer rendering. Figure 1A is a schematic diagram of multi-layer rendering in a related technology provided by an embodiment of the present disclosure. As shown in Figure 1A, the GPU receives multiple primitives 101 processed by the GS, and parses each primitive 101 to obtain the rta_idx of each primitive 101, and renders each primitive 101 to a different layer 102 of the rendering target according to the rta_idx of each primitive 101.

[0052] TBR is a process that subdivides a computer graphics image into a regular grid in optical space and renders each portion of the grid or tile separately. The advantage of this design is that it reduces memory and bandwidth consumption compared to Immediate Mode Rendering (IMR), which draws the entire frame immediately. This makes TBR commonly used on low-power hardware devices.

[0053] FIG1B is a schematic diagram of a typical TBR pipeline process provided by an embodiment of the present disclosure. As shown in FIG1B , the TBR pipeline process is divided into a front-end module 110 (also known as a geometry stage) and a back-end module 120 (also known as a 3D stage), wherein:

[0054] The front-end module 110 includes a vertex processing module, a graphics processing module, and a tiling module. The vertex processing module is used to perform vertex and primitive transformations on the graphics data 150; the graphics processing module is used to perform culling, cropping, and other processing on primitives; and the tiling module is used to segment the screen, record the graphics data covering the tiles, and write generated information such as the primitive list and vertex data into the system memory 130. The primitive list is a fixed-length array of the same length as the tile. Each element in the array is a linked list that stores pointers to all triangles that intersect the current tile, with the pointers pointing to the vertex data. The vertex data stores vertex and vertex attribute data.

[0055] The backend module 120 includes a rasterization module, a hidden surface removal (HSR) module, a pixel shading module, and an output merging module. The rasterization module converts primitives into a two-dimensional image, where each point contains color, depth, and texture data. This point and related information are called a fragment. The HSR module removes occluded triangles. The pixel texture shading module shades pixels. The output merging module merges multiple tiles and outputs them to the RT.

[0056] Since each tile has a small amount of data, the required depth data, texture data, and color data can be loaded into the GPU's on-chip static random-access memory (SRAM), i.e., the on-chip memory 140. For example, the hidden surface removal module can store depth data in a depth buffer in the on-chip memory 140, the pixel shading module can store texture data in a texture buffer in the on-chip memory 140, and the output merging module can store color data in a color buffer in the on-chip memory 140.

[0057] During the rendering process, the rendering object (image) is divided into multiple tiles, so that all the data for this tile can be accommodated using the on-chip memory 140. After at least one drawing instruction arrives at the GPU, the front-end module 110 processes each drawing instruction in turn and stores the corresponding tile information and vertex information in the system memory 130 until the data stored in the system memory 130 reaches a preset threshold or at least one drawing instruction has been processed. The back-end module 120 will read the corresponding vertex information from the system memory 130 in units of tiles and perform subsequent processing. In this way, since the back-end module 120's access to the system memory 130 is changed to the back-end module 120's access to the on-chip memory 140, the rendering efficiency can be improved.

[0058] In the related art, in a TBR architecture, the front-end module usually outputs the data of each layer to the system memory, and the designated hardware Fireware starts the back-end module to render the data of each layer separately. FIG1C is a second schematic diagram of multi-layer rendering in a related art provided by an embodiment of the present disclosure, as shown in FIG1C , wherein:

[0059] Outputting the metadata of each layer to the GPU memory 152 through the front-end module 110;

[0060] After receiving the signal 154 indicating that all layers have been processed, the designated hardware 153 first kicks the first layer (layer0) to the backend module 120 for rendering. After the first layer is rendered, the second layer (layer1) is kicked to the backend module 120 for rendering, and so on until the tenth layer (layer9) is kicked to the backend module 120 for rendering.

[0061] The backend module 120 receives rendering instructions, obtains data of a layer from the memory 152 of the GPU, and writes the data of the layer to the position corresponding to the RT to complete the rendering of the layer.

[0062] First, since the rendering is done layer by layer, each layer requires the hardware to perform preparatory work such as register initialization. This not only prolongs the initialization time, but also increases the resource consumption of the hardware. Secondly, since the rendering of the next layer must wait for the rendering of the previous layer to be completed, the two layers are discontinuous in the hardware, which causes the GPU to have more idle time and reduces the utilization of the GPU. Finally, in a GPU that includes multiple rendering cores, if the number of tiles in each layer is small, then the tiles of each layer will only be processed by the same rendering core, while other rendering cores are idle, resulting in a waste of hardware resources.

[0063] The disclosed embodiment provides a control method for tile distribution, which determines multiple valid target layers to be rendered through the layer's valid identification information, thereby realizing the merging of multiple layers to be rendered. On the one hand, compared with performing initialization work on each layer once, the initialization of multiple layers to be rendered is completed through a single initialization work, which not only shortens the initialization time but also reduces hardware resource consumption. On the other hand, compared with the fact that the rendering of the next layer must wait for the rendering of the previous layer to be completed, multiple target layers to be rendered are processed simultaneously, so that the multiple target layers to be rendered are continuous in the hardware, thereby reducing the idle time of the GPU, thereby improving the utilization of the GPU while reducing the possibility of hardware performance degradation caused by pipeline interruption. At the same time, the target rendering core of the target tile is determined through the tile indication information of each rendering core, reducing the possibility of wasting hardware resources due to the idleness of some rendering cores, thereby balancing the load of each rendering core while also improving the rendering efficiency, thereby improving the rendering performance of the graphics processor as a whole. The method provided in the embodiments of the present disclosure can be performed by an electronic device, which can be various types of terminals such as laptop computers, tablet computers, desktop computers, set-top boxes, mobile devices (e.g., mobile phones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices), etc., and can also be implemented as a server. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0064] Below, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings in the embodiments of the present disclosure.

[0065] FIG1D is a schematic diagram of a first implementation flow of a method for controlling tile distribution according to an embodiment of the present disclosure. As shown in FIG1D , the method includes steps S11 to S12, wherein:

[0066] Step S11: Determine at least one target layer to be rendered from at least one layer to be rendered based on at least one identification bit in the layer valid identification information.

[0067] Here, the GPU includes a preset number of rendering cores (Cores), for example, the preset number may be 4, 8, etc.

[0068] The controller can be any suitable module that can realize the control function. The controller communicates with the front-end module and the back-end module of the TBR architecture respectively to realize parallel processing of multiple layers. In some embodiments, the front-end module determines the layer valid identification information and stores the layer valid identification information in the memory of the GPU, and then the controller can obtain the layer valid identification information from the memory of the GPU. During implementation, the front-end module can refer to the specific embodiment of the front-end module 110 in Figure 1B, and the back-end module can refer to the specific embodiment of the back-end module 120 in Figure 1B.

[0069] The number of identification bits is at least one. For example, the number of identification bits can be 1024 bits, 2048 bits, etc. Each identification bit represents a layer to be rendered, and the value of the identification bit is used to determine whether the corresponding layer to be rendered is valid. Among them, whether the layer to be rendered is valid represents whether there is valid primitive information on the layer to be rendered. For example, the front-end module specifies through the GS that there are 20 triangles on the first layer, no triangles on the second layer, and 10 triangles on the third layer, then there is valid primitive information on the first layer, no valid primitive information on the second layer, and valid primitive information on the third layer.

[0070] FIG1E is a schematic diagram of layer validity identification information provided by an embodiment of the present disclosure. As shown in FIG1E , the layer validity identification information includes 2048 identification bits 161, each of which indicates whether the corresponding layer to be rendered is valid. For example, if the second identification bit, bit1, is 1, it indicates that valid primitive information exists on the second layer to be rendered, layer1.

[0071] In some embodiments, the identification bit of a layer to be rendered can be compared with a first preset condition to determine whether the layer to be rendered is valid. The first preset condition can be any suitable condition. For example, the first preset condition can be any suitable preset value; for example, the first preset condition can be a preset value of 1. During implementation, if the identification bit of a layer to be rendered meets the first preset condition, it indicates that the layer to be rendered is valid; conversely, if the identification bit of a layer to be rendered does not meet the first preset condition, it indicates that the layer to be rendered is invalid. For example, if the preset condition is a preset value of 1, then if the identification bit of layer A to be rendered is 1, it indicates that layer A to be rendered is a valid layer; conversely, if the identification bit of layer A to be rendered is not 1, for example, if the identification bit of layer A to be rendered is 0, it indicates that layer A to be rendered is an invalid layer.

[0072] The number of target layers to be rendered is at least one. In some embodiments, at least one target layer to be rendered can be determined from each layer to be rendered based on the number of valid layers to be rendered. In implementation, if the number of valid layers to be rendered is small, each valid layer to be rendered can be used as a target layer to be rendered. If the number of valid layers to be rendered is large, a preset selection method can be used to select some of the valid layers to be rendered from all the valid layers to be rendered as a target layer to be rendered. The selection method may include, but is not limited to, random, sequential, custom, or default.

[0073] For example, if six valid layers to be rendered are obtained by parsing the valid layer identification information, then these six valid layers to be rendered can be used as a target layer to be rendered; conversely, if there are 30 valid layers to be rendered, then according to the layer identification, the valid layers to be rendered with earlier identifications can be used as a target layer to be rendered.

[0074] In some embodiments, a first preset condition can be used to determine a valid layer to be rendered from multiple layers to be rendered, and at least one target layer to be rendered can be determined from each valid layer to be rendered based on at least one resource table entry in a preset resource table. The resource table is used to record information about the layer being rendered by the pipeline. The number of resource table entries can be any suitable number; for example, the number of resource table entries can be 16, 32, or 48. During implementation, a resource table entry is applied for each valid layer to be rendered. If the application is successful, the valid layer to be rendered can be used as a target layer to be rendered; if the application is unsuccessful, the application is continued.

[0075] For example, if there are many valid layers to be rendered (for example, 2048), but the backend module cannot draw many valid layers to be rendered at the same time, then each valid layer to be rendered needs to apply for a resource table entry from the resource table before it can be rendered. If all resource table entries are occupied, no new valid layers to be rendered are allowed to be executed until an occupied resource table entry in the resource table is released.

[0076] During implementation, the resource table may be stored in the controller or located in other modules, such as a front-end module or a back-end module.

[0077] Step S12: For each target layer to be rendered, based on the tile indication information of at least one rendering core, determine a target rendering core corresponding to at least one target tile in the target layer to be rendered, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0078] Here, the tile indication information is used to indicate the number of tiles that the corresponding rendering core can receive for rendering. For example, for rendering core Core1, if the number of tiles to be rendered in rendering core Core1 is 2 and rendering core Core1 can process a maximum of 4 tiles, then the tile indication information for rendering core Core1 is 2.

[0079] In some embodiments, a rendering core can process any suitable preset number of tiles; for example, the preset number can be 4, 6, or 8. In practice, different rendering cores can process the same or different numbers of tiles. For example, for rendering cores Core0 through Core2, each of these three rendering cores can process 4 tiles, or rendering cores Core0 and Core1 can process 8 tiles, and rendering core Core2 can process 4 tiles.

[0080] The number of target tiles is at least one. During implementation, a preset partitioning strategy can be used to partition a target layer to be rendered into multiple target tiles. The partitioning strategy may include, but is not limited to, a partitioning method, a partitioning length, and a partitioning number. The partitioning method may include, but is not limited to, uniform partitioning, random partitioning, and uneven partitioning. For example, the target layer to be rendered may be evenly divided into 8 target tiles. For another example, the target layer to be rendered may be divided according to any suitable preset size, such as 16*16, to obtain multiple target tiles.

[0081] In some embodiments, each rendering core divides the target layer to be rendered using the division strategy, and the obtained multiple tiles are distributed to each rendering core in a round-robin manner.

[0082] FIG1F is a schematic diagram of a division result of a target layer to be rendered provided by an embodiment of the present disclosure. As shown in FIG1F , three target layers to be rendered, layer0 to layer2, are included. Each target layer to be rendered is evenly divided into six target tiles. Therefore, target layer to be rendered, layer0, includes tiles 0 to 5, target layer to be rendered, layer1, includes tiles 0 to 5, and target layer to be rendered, layer2, includes tiles 0 to 5.

[0083] In some implementations, since each target layer to be rendered has the same size, through the same partitioning strategy, each target layer to be rendered includes the same number of target tiles.

[0084] In some embodiments, each rendering core can be sorted based on its tile indication information to obtain order information for each rendering core, and the target rendering core corresponding to the target tile can be determined based on the order information for each rendering core. Methods for determining the order information include, but are not limited to, sorting the tiles from most to least, or from least to most, based on the tile indication information, or using a tile threshold. The tile threshold represents the maximum number of tiles that a rendering core can process.

[0085] For example, a GPU includes rendering cores Core0 to Core2, each of which can process four tiles. If the tile indication information of rendering core Core0 is 0, the tile indication information of rendering core Core1 is 2, and the tile indication information of rendering core Core2 is 4, according to the tile indication information of each rendering core:

[0086] Sort each rendering core in order from least to most: Core2, Core1, Core0, so the order information of Core0 to Core2 is: 3, 2, 1 respectively;

[0087] According to the tile threshold, each rendering core is sorted as: Core1, Core2, Core0, and the order information of Core0 to Core2 is: 3, 1, 2 respectively. During implementation, the rendering cores that meet the conditions (for example, fully loaded, busy, etc.) are moved to the end, and the order information can be obtained without comparing each rendering core with the condition. For example, if the tile indication information of rendering core Core0 and rendering core Core2 is 0, and the tile indication information of rendering core Core1 is 2, then according to the tile threshold, each rendering core is sorted as: Core1, Core2, Core0, that is, since Core0 meets the condition, Core0 is moved to the end; since Core1 does not meet the condition, there is no need to determine whether Core2 meets the condition.

[0088] In some embodiments, the order information of different rendering cores may be the same or different. For example, when the tile indication information of rendering core Core1 is the same as the tile indication information of rendering core Core2, the order information of rendering core Core1 may be the same as the order information of rendering core Core2. For another example, when the tile indication information of rendering core Core1 is the same as the tile indication information of rendering core Core2, the order information of rendering core Core1 and the order information of rendering core Core2 are further distinguished based on naming, status information, etc. The status information may include but is not limited to busy status, idle status, etc.

[0089] Methods for determining the target rendering core include, but are not limited to, random, custom, first, and sequential. For example, the rendering core with the first order information is used as the target rendering core. In another example, a rendering core is randomly selected from multiple rendering cores with the same order information as the target rendering core.

[0090] In some embodiments, each rendering core may be sorted according to the tile indication information of each rendering core and the naming information of each rendering core to obtain the order information of each rendering core.

[0091] For example, if the tile indication information of rendering core Core1 is the same as the tile indication information of rendering core Core2, then the order information of rendering core Core1 can be determined to be 1 and the order information of rendering core Core2 can be determined to be 2 based on the naming information of rendering core Core1 and rendering core Core2.

[0092] In some embodiments, each rendering core may be sorted according to the tile indication information of each rendering core and the state information of each rendering core to obtain the order information of each rendering core.

[0093] For example, the GPU includes rendering cores Core0 to Core2. Each rendering core is sorted according to the tile indication information of each rendering core, so that the first order information of the rendering cores Core0 to Core2 is: 3, 1, 2, respectively; because the rendering core Core1 is in a busy state, the first order information is updated according to the state information of each rendering core, and the order information of the rendering cores Core0 to Core2 is: 3, 2, 1, respectively.

[0094] In some embodiments, if the target layer to be rendered includes multiple target tiles, all rendering cores may be target rendering cores, and the target layer to be rendered may be allocated to all rendering cores. For example, if a GPU includes four rendering cores, Core0 to Core3, and each rendering core can process four tiles, then when the target layer to be rendered includes eight target tiles, these eight target tiles may be allocated to at least two rendering cores, e.g., Core0 and Core1 are each allocated four target tiles, or, for another example, Core0 is allocated one target tile, Core1 is allocated four target tiles, and Core2 is allocated three target tiles. When the target layer to be rendered includes at least ten target tiles, these at least ten target tiles may be allocated to each rendering core, i.e., Core0 is allocated one target tile, Cores 1 to Core 2 are allocated four target tiles, and Core 3 is allocated one target tile.

[0095] FIG1G is a schematic diagram of a target layer to be rendered and a rendering core provided by an embodiment of the present disclosure. As shown in FIG1G , the GPU includes eight rendering cores Core0 to Core7, each of which can process four tiles. The target layers to be rendered include layer0 to layer2047, where:

[0096] When layer0 includes at least 26 target tiles, each target tile of layer0 is allocated to Core0 to Core7, that is, one target tile is allocated to Core0, four target tiles are allocated to Core1 to Core6, and one target tile is allocated to Core7, and the cycle is repeated to complete the allocation of 2048 target tiles of the target layer to be rendered.

[0097] During the rendering process, the back-end module determines the first address of the target layer to be rendered in the GPU memory to which the target tile belongs, based on the base address of the RTA (Render Target Array), the size of each target layer to be rendered, and the layer identifier of the target layer to which the target tile belongs. Then, based on the information carried by the target tile, the target address of the rendering data (including color, depth, texture, etc.) of the target tile in the GPU memory is determined, and finally the target tile is rendered to the position corresponding to the RT.

[0098] During implementation, the first address LayerRtBaseAddress of the target layer to be rendered to which the target tile belongs in the GPU memory can be calculated according to the following formula (1-1), namely:

[0099] LayerRtBaseAddress=RtBaseAddress+LayerRtSize*rta_idx(1-1);

[0100] Among them, RtBaseAddress is the base address of RTA, LayerRtSize is the size of the target layer to be rendered, and rta_idx is the layer identifier of the target layer to be rendered to which the target tile belongs.

[0101] FIG1H is a schematic diagram of the storage locations of multiple layers to be rendered in the memory of a GPU provided by an embodiment of the present disclosure. As shown in FIG1H , each layer to be rendered has the same size, and each layer to be rendered is stored in sequence according to its layer identifier. That is, the first address of the storage location 171 of the first layer to be rendered, layer0, is the base address of the RTA; the first address of the storage location 172 of the second layer to be rendered, layer1, is "base address + layer size * 1"; and the first address of the storage location 173 of the third layer to be rendered, layer2, is "base address + layer size * 2."

[0102] The information carried in the target tile may include, but is not limited to, the layer identifier of the target layer to be rendered to which the target tile belongs, the location information of the target tile in the target layer to be rendered, and the resource index identifier of the target layer to be rendered. In implementation, the information carried by the target tile may be implemented in the form of a structure, a key-value pair, a table, etc. For example, the information carried by the target tile is defined by the following structure Tile_Info:

[0103] typedef struct Tile_Info

[0104] {

[0105] uint16_t tile_x;

[0106] uint16_t tile_y;

[0107] uint16_t rta_idx;

[0108] uint8_t layer_id;

[0109] }

[0110] Among them, tile_x and tile_y are used to represent the position information of the target tile in the target to-be-rendered layer, rta_idx is used to represent the layer identifier of the target to-be-rendered layer to which the target tile belongs, and layer_id is used to represent the resource index identifier of the target to-be-rendered layer to which the target tile belongs.

[0111] In the embodiment of the present disclosure, multiple valid target layers to be rendered are determined through the valid identification information of the layer, thereby realizing the merging of multiple layers to be rendered. On the one hand, compared with performing initialization work once for each layer, the initialization of multiple layers to be rendered is completed through a single initialization work, which not only shortens the initialization time, but also reduces the resource consumption of the hardware. On the other hand, compared with the rendering of the next layer having to wait for the rendering of the previous layer to be completed, multiple target layers to be rendered are processed at the same time, so that the multiple target layers to be rendered are continuous in the hardware, thereby reducing the idle time of the GPU, thereby improving the utilization of the GPU while reducing the possibility of hardware performance degradation caused by pipeline interruption. At the same time, the target rendering core of the target tile is determined through the tile indication information of each rendering core, reducing the possibility of wasting hardware resources due to the idleness of some rendering cores, thereby balancing the load of each rendering core while also improving the rendering efficiency, thereby improving the rendering performance of the graphics processor as a whole.

[0112] FIG2A is a second schematic diagram of an implementation flow of a method for controlling tile distribution provided by an embodiment of the present disclosure. As shown in FIG2A , the method includes steps S21 to S23, wherein:

[0113] Step S21 : determining at least one valid layer to be rendered from at least one layer to be rendered based on at least one identification bit in the layer validity identification information; wherein each identification bit indicates whether the corresponding layer to be rendered is valid.

[0114] Here, each flag bit represents a layer to be rendered, and whether the corresponding layer to be rendered is valid is determined by the value of the flag bit.

[0115] The number of valid layers to be rendered may be at least one. A valid layer to be rendered is a valid layer to be rendered. During implementation, the flag bit may be compared with a first preset condition to determine whether the layer to be rendered is a valid layer to be rendered. The first preset condition may be any suitable condition, for example, a preset value.

[0116] In some embodiments, step S21 includes step S211, wherein:

[0117] Step S211: for each identification bit in the layer valid identification information, if the identification bit meets a first preset condition, take the to-be-rendered layer corresponding to the identification bit as a valid to-be-rendered layer.

[0118] Here, each identification bit represents a layer to be rendered. Then, the valid identification information of the layer can be traversed from LSB (Least Significant Bit) to MSB (Most Significant Bit). If a certain identification bit meets the first preset condition, the layer to be rendered corresponding to the identification bit is regarded as a valid layer to be rendered; on the contrary, if the identification bit does not meet the first preset condition, it indicates that the layer to be rendered corresponding to the identification bit is invalid, and no subsequent processing is required for the layer to be rendered. For example, for the 10th layer to be rendered, if the value of the identification bit bit9 is 1 (corresponding to the aforementioned first preset condition), the 10th layer to be rendered is regarded as a valid layer to be rendered.

[0119] Step S22: For each valid layer to be rendered, determine a resource entry result of the valid layer to be rendered based on at least one resource entry in a preset resource table, and if the resource entry result of the valid layer to be rendered is a first result, use the valid layer to be rendered as the target layer to be rendered.

[0120] Here, the resource table is used to record information about the layers being rendered by the pipeline. The number of resource table entries can be any suitable number; for example, the number of resource table entries can be 16, 32, or 48. In practice, the number of resource table entries represents the number of layers that the GPU can render simultaneously.

[0121] Figure 2B is a schematic diagram of a resource table provided in an embodiment of the present disclosure. As shown in Figure 2B, the resource table includes 32 resource table entries, among which 16 of the 32 resource table entries are occupied (occupancy flag = 1), and 16 are unoccupied (occupancy flag = 0).

[0122] The resource entry result may include but is not limited to a first result, a second result, etc. The first result indicates that the resource entry allocation of the valid layer to be rendered is successful, and the second result indicates that the resource entry allocation of the valid layer to be rendered is unsuccessful.

[0123] In some embodiments, the step S22 of “determining the resource entry result of the valid layer to be rendered based on at least one resource entry in a preset resource table” includes steps S221 to S222, wherein:

[0124] Step S221: traverse each resource entry in the resource table in sequence, determine the resource index identifier of the valid layer to be rendered based on the occupation flag of the currently traversed resource entry, and stop traversing if the resource index identifier is not a preset index identifier.

[0125] Here, the resource table entry may include but is not limited to an occupation flag, an index flag, etc. Among them, the occupation flag is used to indicate whether the resource table entry is occupied. The index flag is used to indicate the position of the resource table entry in the resource table.

[0126] Different values ​​of the occupancy flag are used to indicate whether the resource entry is occupied. For example, a first value of the occupancy flag indicates that the resource entry is occupied; a second value of the occupancy flag indicates that the resource entry is not occupied. In implementation, the occupancy flag value can be represented in any suitable manner. For example, the first value can be 1, the second value can be 0, or the first value can be "True" and the second value can be "False."

[0127] The resource index identifier represents the resource identification information of the valid layer to be rendered. Through the resource index identifier, it can be determined whether the resource table entry of the valid layer to be rendered is successfully allocated. The resource index identifier may include, but is not limited to, a preset index identifier, an index identifier of a resource table entry, etc. The preset index identifier can be any suitable value; for example, the preset index identifier can be 0xff, or -1, etc. During implementation, the preset index identifier is different from the index identifier of each resource table entry in the resource table. In this way, based on the resource index identifier, the resource table entry result of the valid layer to be rendered can be accurately obtained.

[0128] For example, when the occupancy flag of the currently traversed resource table item indicates that the resource table item is not occupied, the index identifier of the resource table item can be used as the resource index identifier; conversely, when the occupancy flag of the currently traversed resource table item indicates that the resource table item is occupied, the preset index identifier can be used as the resource index identifier.

[0129] During implementation, multiple resource table items in the resource table items are traversed in sequence according to a preset traversal method. If the occupation flag of the currently traversed resource table item indicates that the resource table item is not occupied, the index identifier of the resource table item can be used as the resource index identifier, and the traversal is stopped. Conversely, if the occupation flag of the currently traversed resource table item indicates that the resource table item is occupied, the preset index identifier can be used as the resource index identifier, and the traversal is continued. The traversal method can be any appropriate traversal method, for example, from front to back, from back to front, etc.

[0130] If the occupation flag of each resource table entry in the resource table indicates that the corresponding resource table entry is occupied, it is necessary to wait until the occupation flag of at least one resource table entry in the resource table indicates that the corresponding resource table entry is not occupied.

[0131] In some embodiments, step S221 includes step S2211 and / or step S2212, wherein:

[0132] Step S2211: When the occupation flag of the currently traversed resource entry is a preset occupation flag, the index identifier of the resource entry is used as the resource index identifier of the valid layer to be rendered.

[0133] Here, the preset occupancy flag is used to indicate that the resource table entry is not occupied. In implementation, the preset occupancy flag can be any suitable occupancy flag; for example, the preset occupancy flag can be "False" or "0". If the occupancy flag of the resource table entry is the same as the preset occupancy flag, it indicates that the resource table entry is not occupied. For example, when the preset occupancy flag is 0, if the occupancy flag of resource table entry T6 is also 0, indicating that the resource table entry is not occupied, then the index identifier 6 of resource table entry T6 can be used as the resource index identifier of the valid layer to be rendered.

[0134] Step S2212: When the occupation flag of the currently traversed resource entry is not the preset occupation flag, use the preset index flag as the resource index flag of the valid layer to be rendered.

[0135] Here, if the occupied flag of the resource entry is different from the preset occupied flag, it indicates that the resource entry is occupied. For example, if the preset occupied flag is 0, if the occupied flag of resource entry T6 is 1, indicating that the resource entry is occupied, then the preset index identifier 0xff can be used as the resource index identifier of the valid layer to be rendered.

[0136] Step S222: Determine the resource entry result of the valid layer to be rendered based on the resource index identifier.

[0137] Here, the resource index identifier can be compared with the preset index identifier to obtain the resource table item result for the valid layer to be rendered. For example, if the resource index identifier is the same as the preset index identifier, it indicates that all resource table items in the resource table are occupied, that is, the allocation of the resource table item for the valid layer to be rendered is unsuccessful, and the second result can be used as the resource table item result for the valid layer to be rendered. Conversely, if the resource index identifier is different from the preset index identifier, it indicates that a resource table item in the resource table is not occupied and is allocated to the valid layer to be rendered, that is, the allocation of the resource table item for the valid layer to be rendered is successful, and the first result can be used as the resource table item result for the valid layer to be rendered.

[0138] In some embodiments, step S222 includes step S2221 and / or step S2222, wherein:

[0139] Step S2221: When the resource index identifier is not a preset index identifier, use the first result as the resource entry result of the valid layer to be rendered.

[0140] Here, if the resource index identifier is different from the preset index identifier, it indicates that a resource table entry in the resource table is not occupied, and the resource table entry is allocated to the valid layer to be rendered. Therefore, the first result can be used as the resource table entry result of the valid layer to be rendered.

[0141] Step S2222: When the resource index identifier is the preset index identifier, use the second result as the resource entry result of the valid layer to be rendered.

[0142] Here, if the resource index identifier is the same as the preset index identifier, it indicates that all resource entries in the resource table are occupied, that is, allocation of resource entries for the valid layer to be rendered is unsuccessful, and the second result can be used as the resource entry result for the valid layer to be rendered.

[0143] Step S23: For each target layer to be rendered, based on the tile indication information of at least one rendering core, determine a target rendering core corresponding to at least one target tile in the target layer to be rendered, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0144] Here, the above step S23 corresponds to the above step S12. When implementing, the specific implementation of the above step S12 can be referred to.

[0145] In the embodiments of the present disclosure, on the one hand, multiple layers to be rendered are filtered using the identification bit corresponding to each layer to be rendered, thereby improving the accuracy of valid layers to be rendered. On the other hand, the resource entry result of each valid layer to be rendered is used to determine whether to use it as the target layer to be rendered. This comprehensively considers the performance of the GPU. Compared with directly using each valid layer to be rendered as the target layer to be rendered, this not only improves the accuracy of the target layer to be rendered, but also improves rendering efficiency.

[0146] In some embodiments, the method further comprises step S24, wherein:

[0147] Step S24: For each target layer to be rendered, determine a first target resource table entry from at least one resource table entry in the resource table based on the resource index identifier of the target layer to be rendered, and update the first target resource table entry based on the layer identifier of the target layer to be rendered.

[0148] Here, since each resource table entry has an index identifier, during implementation, an index identifier identical to the resource index identifier of the target layer to be rendered can be searched among multiple index identifiers, and the resource table entry corresponding to the found index identifier is used as the first target resource table entry. For example, if the resource table includes 32 resource table entries, and the index identifiers of these 32 resource table entries are 0 to 31, respectively, and the resource index identifier of the target layer to be rendered is 6, then the 7th resource table entry corresponding to the index identifier 6 is used as the first target resource table entry.

[0149] The resource table entry may include but is not limited to an occupation flag, a layer identifier, a last layer flag, etc. During implementation, a resource table entry may be represented in a structure, a table, or the like.

[0150] For example, a resource entry is defined using the following structure LayerEntry:

[0151] Wherein, LID_TABLE_SIZE is the number of resource table entries contained in the resource table.

[0152] Then, you can use the AllocateLayerID() function to apply for the resource table entry of the valid layer to be rendered, that is:

[0153] Among them, uRtaIdx represents the identifier of the valid layer to be rendered, and each resource table entry in the resource table is traversed through a for loop:

[0154] If the occupied flag of the i-th resource table item is 0, it indicates that the i-th resource table item is not occupied. At this time, the occupied flag of the i-th resource table item is updated to 1, the identifier of the valid layer to be rendered is used as the layer of the i-th resource table item, the passed-in bLastLayer is used as the last layer identifier of the i-th resource table item, and the index identifier of the i-th resource table item is used as the return value uLayerId (corresponding to the resource index identifier of the aforementioned valid layer to be rendered) to complete the resource table item application and stop traversal.

[0155] If the occupation flags of all resource table entries are 1, it indicates that all resource table entries are occupied. At this time, 0xff is used as the return value uLayerId, and the resource table entry release event lid_tlb_free_event is waited for to execute the AllocateLayerID() function again.

[0156] In the disclosed embodiment, for each target layer to be rendered, a first target resource entry is determined from at least one resource entry in the resource table based on the resource index identifier of the target layer to be rendered, and the first target resource entry is updated based on the layer identifier of the target layer to be rendered. Thus, updating the first target resource entry based on the layer identifier of the target layer to be rendered reduces the likelihood of multiple layers to be rendered being assigned to the same resource entry, thereby improving rendering efficiency.

[0157] In some embodiments, the method further comprises step S25, wherein:

[0158] Step S25: For each target layer to be rendered, in response to detecting that the rendering status of the target layer to be rendered is a completed state, determining a second target resource table entry from at least one resource table entry in the resource table based on the resource index identifier of the target layer to be rendered, and resetting the second target resource table entry.

[0159] Here, the rendering state may include but is not limited to a completed state, an unfinished state, etc. In implementation, different rendering states may be represented by any appropriate means, for example, "1" represents a completed state and "0" represents an unfinished state.

[0160] Since each resource table entry has an index identifier, during implementation, an index identifier identical to the resource index identifier of the target layer to be rendered can be searched among multiple index identifiers, and the resource table entry corresponding to the found index identifier is used as the second target resource table entry. For example, if the resource table includes 32 resource table entries, and the index identifiers of these 32 resource table entries are 0 to 31, and the resource index identifier of the target layer to be rendered is 8, then the 9th resource table entry corresponding to the index identifier 8 is used as the second target resource table entry.

[0161] The resource table entry may include but is not limited to an occupied flag, a layer identifier, a last layer flag, etc. Resetting the second target resource table entry requires initializing all information of the second target resource table entry.

[0162] For example, a resource table entry is reset using the following function ReleaseLayerID():

[0163] The occupation flag, layer identifier, and last layer flag of a resource table entry are reset, and a notification of a resource table entry release event lid_tlb_free_event is sent.

[0164] In an embodiment of the present disclosure, for each target layer to be rendered, in response to detecting that the rendering state of the target layer to be rendered is complete, a second target resource entry is determined from at least one resource entry in the resource table based on the resource index identifier of the target layer to be rendered, and the second target resource entry is reset. Thus, by resetting the second target resource entry based on the layer identifier of the target layer to be rendered, the resource entry can be released in a timely manner to facilitate the application of resource entries by other layers to be rendered, thereby improving rendering efficiency.

[0165] FIG3 is a third schematic diagram of an implementation flow of a method for controlling tile distribution provided by an embodiment of the present disclosure. As shown in FIG3 , the method includes steps S31 to S33, wherein:

[0166] Step S31: Determine at least one target layer to be rendered from at least one layer to be rendered based on at least one identification bit in the layer valid identification information.

[0167] Here, the above step S31 corresponds to the above step S11. When implementing, reference may be made to the specific implementation of the above step S11.

[0168] Step S32 : For each target layer to be rendered, divide the target layer to be rendered according to a preset division strategy to obtain at least one target block.

[0169] Here, the division strategy may include, but is not limited to, a division method, a division length, and a number of divisions. The division method may include, but is not limited to, uniform division, random division, and non-uniform division. For example, the target layer to be rendered may be evenly divided into six target tiles. For another example, the target layer to be rendered may be divided according to any suitable preset size, such as 16*16, to obtain multiple target tiles.

[0170] Step S33: For each target tile, based on the tile indication information of at least one rendering core, determine the order information of each rendering core, and based on the order information of each rendering core, determine the target rendering core corresponding to the target tile, so that the target tiles are rendered in parallel using the target rendering core; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0171] Here, each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive. For example, the tile indication information of the rendering core Core0 of the GPU is 4, indicating that the rendering core Core0 can receive 4 tiles to be rendered.

[0172] The order information represents the order in which the rendering cores are arranged. For example, a GPU includes four rendering cores, Core0 to Core3, and the default order of Core0 to Core3 is Core0, Core1, Core2, Core3. Therefore, the order information for Core0 is 1, the order information for Core1 is 2, the order information for Core2 is 3, and the order information for Core3 is 4.

[0173] Methods for determining the order information may include, but are not limited to, determining the order of tiles from most to least, or from least to most, as indicated by the tile indication information, or using a tile threshold. For example, a GPU includes rendering cores Core0 through Core3, each capable of processing four tiles. If the tile indication information for rendering cores Core0 through Core3 is 0, 2, 4, and 4, respectively, then, based on the tile indication information of each rendering core and the tile threshold, each rendering core is sorted as: Core1, Core2, Core3, and Core0. Therefore, the order information for Core0 through Core3 is 4, 1, 2, and 3, respectively.

[0174] In some embodiments, the order information of different rendering cores may be the same or different. During implementation, when the order information of different rendering cores is the same, the order information of different rendering cores may be further determined by at least one of the naming, status information, etc. For example, the order information of each rendering core is determined based on the tile indication information of each rendering core and the naming information of each rendering core. For another example, the order information of each rendering core is determined based on the tile indication information of each rendering core and the status information of each rendering core. For another example, the order information of each rendering core is determined based on the tile indication information of each rendering core, the status information of each rendering core, and the naming information of each rendering core.

[0175] In some embodiments, the step S33 of “determining the order information of each rendering core based on the tile indication information of at least one rendering core” includes step S331, wherein:

[0176] Step S331 : For each rendering core, if the tile indication information of the rendering core meets a second preset condition, determine the order information of each rendering core based on the previous order information of each rendering core.

[0177] Here, the second preset condition can be any suitable condition that can represent a tile threshold. For example, the second preset condition is a preset value, such as 0. For another example, the second preset condition is full load, where full load indicates that the rendering core includes the tile threshold number of tiles to be rendered. During implementation, if the tile indication information of the rendering core does not meet the second preset condition, the previous order information of each rendering core is used as the order information of each rendering core.

[0178] The previous order information can be the default order information or the order information at the previous moment. During implementation, the default order information can be determined based on naming, status information, etc. For example, the GPU includes rendering cores Core0 to Core3. Based on the naming, the default order information of rendering cores Core0 to Core3 is determined to be 1, 2, 3, and 4, respectively. In some embodiments, when the order information of the rendering cores is determined for the first time, the previous order information can be the default order information; when the order information of the rendering cores is not determined for the first time, the previous order information is the order information at the previous moment.

[0179] During implementation, each rendering core is traversed, and during the traversal process, the previous order information is updated in real time to obtain the current order information (corresponding to the aforementioned order information).

[0180] For example, the GPU includes rendering cores Core0 to Core3. The tile indication information of rendering cores Core0 to Core3 is 0, 0, 2, and 4, respectively. The tile threshold is 4. According to the naming, the default order information of rendering cores Core0 to Core3 is 1, 2, 3, and 4, respectively. Then, the rendering cores Core0 to Core3 are traversed:

[0181] For the first rendering core Core0, since the tile indication information of rendering core Core0 is 0, it indicates that there are tile threshold tiles to be rendered in Core0, which meets the second preset condition. Therefore, the previous order information (default order information) of rendering cores Core0 to Core3 is 1, 2, 3, and 4, respectively. Then the current order information of rendering cores Core0 to Core3 is: 4, 1, 2, 3, respectively.

[0182] The second time, for rendering core Core 1, since the tile indication information of rendering core Core 1 is 0, it means that Core 1 has the tile threshold number of tiles to be rendered, which meets the second preset condition. Therefore, the previous order information of rendering cores Core 0 to Core 3 is 4, 1, 2, and 3, respectively. Therefore, the current order information of rendering cores Core 0 to Core 3 is: 3, 4, 1, and 2, respectively.

[0183] The third time, for Core2, since the tile indication information of rendering core Core2 is 2, which is less than the tile threshold and does not meet the second preset condition, the previous order information of rendering cores Core0 to Core3 is used as the current order information, that is, the current order information of rendering cores Core0 to Core3 is 3, 4, 1, and 2 respectively;

[0184] The fourth time is for rendering core Core3. Since the tile indication information of rendering core Core3 is 4, which is less than the tile threshold and does not meet the second preset condition, the previous order information of rendering cores Core0 to Core3 is used as the current order information, that is, the current order information of rendering cores Core0 to Core3 is 3, 4, 1, and 2 respectively.

[0185] The target rendering core may be determined in a manner including, but not limited to, random, custom, first, sequential, etc. For example, the rendering core with the first order information is used as the target rendering core.

[0186] In some embodiments, the step S33 of “determining the target rendering core corresponding to the target tile based on the order information of each rendering core” includes step S341, wherein:

[0187] Step S341 : traverse each rendering core according to the order information of each rendering core, and use the first rendering core that does not meet the second preset condition as the target rendering core corresponding to the target tile.

[0188] Here, the same meaning can be represented by different order information, so the traversal method can include but is not limited to from small to large, from large to small, etc. For example, the GPU includes rendering cores Core0 to Core2, and the tile indication information of rendering cores Core0 to Core2 is 0, 2, and 4 respectively. Then the order information of rendering cores Core0 to Core2 can be 3, 1, 2, or 1, 3, 2. For rendering core Core0, the order information of rendering core Core0 can be 3 or 1. Then, when the order information of rendering core Core0 is 3, traversal can be performed in a small to large traversal method; when the order information of rendering core Core0 is 1, traversal can be performed in a large to small traversal method.

[0189] In practice, the first rendering core traversed generally does not meet the second preset condition. Therefore, the first rendering core traversed can be used as the target rendering core. If the first rendering core traversed meets the second preset condition, it indicates that all rendering cores are currently fully loaded. At this time, the tile indication information of each rendering core can be reset, and the order information of each rendering core can be re-determined based on the tile indication information, naming, status information, etc., to facilitate the next round of tile distribution.

[0190] In the embodiments of the present disclosure, on the one hand, the order information of each rendering core is determined by the tile indication information of each rendering core, which not only improves the accuracy of the order information to facilitate the subsequent determination of the target rendering core, but also ensures that the probability of each rendering core being used is basically the same, thereby improving the load balancing capability of the GPU; on the other hand, the target rendering core is determined by the order information of each rendering core, which improves the accuracy of the target rendering core compared to randomly and arbitrarily assigning rendering cores, thereby improving rendering efficiency.

[0191] In some embodiments, the method further comprises step S34, wherein:

[0192] Step S34 : For each target tile, in response to allocating the target tile to the corresponding target rendering core, updating the tile indication information of the target rendering core corresponding to the target tile.

[0193] Here, after the target tile is assigned to the target rendering core, the tile indication information needs to be updated in a timely manner. For example, if the tile indication information of rendering core Core1 is 2, if the target tile is assigned to rendering core Core1, the tile indication information of rendering core Core1 should be 1. In this way, by updating the tile indication information of the target rendering core in a timely manner, the possibility of rendering failure due to incorrect target tile allocation (for example, exceeding the threshold) can be reduced, thereby improving rendering efficiency.

[0194] In some embodiments, the method further comprises step S35, wherein:

[0195] Step S35 : In response to the tile indication information of each rendering core satisfying the second preset condition, resetting the tile indication information of each rendering core.

[0196] Here, if each tile indication satisfies the second pre-set condition, indicating that all rendering cores are fully loaded, then each tile indication can be reset, i.e., set to a default value. This default value can be any suitable value; for example, it can be 0 or -1. This allows for timely resetting of all tile indications to facilitate the next round of tile distribution.

[0197] Based on the above embodiments, an embodiment of the present disclosure provides a controller for tile distribution. FIG4A is a first schematic diagram of the structure of a controller for tile distribution provided by an embodiment of the present disclosure. As shown in FIG4A , the controller 40 for tile distribution includes a processing portion 41 and a generating portion 42, wherein:

[0198] The processing part 41 is used to determine at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information;

[0199] Therefore, the generating portion 42 is configured to determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on the tile indication information of at least one rendering core, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is respectively used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0200] Here, the GPU includes a preset number of rendering cores. For example, the preset number can be 4, 8, etc. The processing portion 41 can be any suitable software module and / or hardware module capable of implementing the function, and the generation portion 42 can be any suitable software module and / or hardware module capable of implementing the function. During implementation, the functions implemented by the processing portion 41 can refer to the specific implementation of step S11 described above. The functions implemented by the generation portion 42 can refer to the specific implementation of step S12 described above.

[0201] In some embodiments, the controller 40 also includes a port part; the processing part is also used to respond to receiving a rendering instruction, use the port part to obtain the layer valid identification information from the memory, and store the layer valid identification information in the cache part of the controller.

[0202] Here, the port portion may be any suitable portion capable of implementing a communication function, and can be used to communicate with other portions.

[0203] The rendering instruction can be a flush instruction, which is used to instruct the GPU to process the multiple draw call instructions it has received. In practice, when a rendering operation is required, the CPU (Central Processing Unit) will call the graphics programming interface built into the operating system to sequentially issue multiple draw call instructions to the GPU to instruct the GPU to perform the rendering operation.

[0204] The memory may be a memory of a GPU. During implementation, since the front-end module of the TBR architecture generates layer valid identification information and stores the layer valid identification information in the memory, the layer valid identification information can be obtained by reading the memory.

[0205] The cache portion may be any suitable portion capable of implementing a storage function, such as an on-chip memory, a certain storage space in the on-chip memory, and the like.

[0206] In some embodiments, the controller 40 further includes a cache portion; the cache portion is used to store the layer valid identification information; and the processing portion is further used to obtain the layer valid identification information from the cache portion.

[0207] Here, since the layer valid identification information is stored in the cache part in advance, the layer valid identification information can be obtained by reading the cache part.

[0208] In some embodiments, the controller further includes a preset resource table, wherein the resource table includes at least one resource table item; the processing portion is further configured to determine, for each target layer to be rendered, based on a resource index identifier of the target layer to be rendered, a first target resource table item from at least one resource table item in the resource table, and update the first target resource table item based on a layer identifier of the target layer to be rendered.

[0209] Here, the resource table is used to record the information of the layer being rendered by the pipeline. The number of resource table entries can be any appropriate number; for example, the number of resource table entries can be 16, 32, or 48. Since each resource table entry has an index identifier, and the target layer to be rendered is the layer to be rendered to which the resource table entry is successfully assigned, the index identifier of the resource table entry can be used as the resource index identifier of the target layer to be rendered. During implementation, the resource index identifier of the target layer to be rendered is used as the target index identifier, and the resource table entry corresponding to the target index identifier can be quickly obtained from the resource table, and the resource table entry is used as the first target resource table entry.

[0210] A resource entry may include, but is not limited to, an occupied flag, a layer identifier, and a last layer identifier. In some embodiments, a resource entry may be represented by a structure, an array, or the like. During implementation, the first target resource entry is updated based on the layer identifier of the target layer to be rendered. By promptly updating the first target resource entry, the likelihood of multiple layers to be rendered being assigned to the same resource entry can be reduced, thereby improving rendering efficiency.

[0211] In some embodiments, the controller 40 further includes a layer rendering state table, wherein the layer rendering state table includes a rendering state of each target layer to be rendered. The processing portion 41 is further configured to: in response to receiving a layer end signal, determine a first target layer to be rendered from at least one target layer to be rendered in the layer rendering state table, and update the rendering state of the first target layer to be rendered to a completed state; determine a second target resource table entry from at least one resource table entry in the resource table based on a resource index identifier of the first target layer to be rendered, and reset the second target resource table entry.

[0212] Here, the number of rendering states in the layer rendering state table is the same as the number of target layers to be rendered. The layer end signal indicates that the rendering of a certain layer is completed. In implementation, the layer end signal pbe_eol can be a signal sent by the back-end module of the GPU. The layer end signal carries a layer identifier. After receiving the layer end signal, the layer end signal is parsed to obtain the layer identifier. Based on the layer identifier, the layer rendering state table is traversed to obtain the first target layer to be rendered that matches the layer identifier. The resource table entry reset process can be seen in the specific implementation of the aforementioned step S26.

[0213] In some embodiments, when the rendering status of a target layer to be rendered is in the completed state, the target layer to be rendered can be deleted from the layer rendering state table, or the target layer to be rendered can be marked as completed. Next time after receiving a layer end signal, the target layer to be rendered will no longer be traversed when the layer rendering state table is traversed.

[0214] In some embodiments, the processing portion 41 is further configured to: in response to receiving the end signal, determine at least one second target to-rendering layer from the at least one target to-rendering layer in the layer rendering state table, and update the rendering state of each second target to-rendering layer to a completed state; and for each second target to-rendering layer, determine a third target resource table entry from at least one resource table entry in the resource table based on a resource index identifier of the second target to-rendering layer, and reset the third target resource table entry.

[0215] Here, the end signal indicates that all target layers to be rendered have been rendered. In practice, the end signal eor can be sent by the GPU's backend module. This layer end signal may or may not carry a layer identifier. Upon receiving this end signal, the layer rendering state table is traversed, and all target layers to be rendered that are in an unfinished state are treated as second target layers to be rendered. The resource table entry resetting process can be found in the detailed implementation of step S26 above.

[0216] FIG4B is a schematic diagram of target tile distribution provided by an embodiment of the present disclosure. As shown in FIG4B , the GPU includes four rendering cores Core0 to Core3, which divide the three target layers to be rendered, layer0 to layer2. Layer0 to layer2 each include six target tiles tile0 to tile5. If four target tiles are sent to Core0 to Core3 in each round, the target tiles in layer0 to layer2 are distributed as follows:

[0217] For the first round, the target rendering core of the four target tiles tile0-tile3 in layer0 is Core0, and the target rendering core of the two target tiles tile4-tile5 is Core1. At this time, a first end signal 411 can be sent to Core0-Core3, and the first end signal 411 indicates that the distribution of layer0 has ended; the target rendering core of the two target tiles tile0-tile1 in layer1 is Core1, and the target rendering core of the four target tiles tile2-tile5 is Core2. At this time, a first end signal 412 can be sent to Core0-Core3, and the first end signal 412 indicates that the distribution of layer1 has ended; the target rendering core of the four target tiles tile0-tile3 in layer2 is Core3;

[0218] For the second round, the target rendering core of the two target tiles tile0~tile1 in layer2 is Core0. At this time, a first end signal 413 can be sent to Core0~Core3. The first end signal 413 indicates that the distribution of layer2 is completed. During implementation, if all target layers to be rendered are distributed, a second end signal 414 can be sent to Core0~Core3. The second end signal 414 indicates that the distribution of all target layers to be rendered is completed.

[0219] FIG4C is a second schematic diagram of the structure of a controller for tile distribution provided by an embodiment of the present disclosure. As shown in FIG4C , the controller 40 includes a processing part 41, a generation part 42, a port part 43, a cache part 44, a resource table 45, and a layer rendering state table 46, wherein:

[0220] When receiving the rendering instruction, the processing part 41 obtains the layer valid identification information from the memory of the GPU through the port part 43 and stores the layer valid identification information in the cache part 44;

[0221] The processing portion 41 obtains the layer valid identification information from the cache portion 44, and for each identification bit in the layer valid identification information, determines whether the identification bit satisfies a first preset condition. If the first preset condition is satisfied, the processing portion 41 determines a resource table entry result for the to-be-rendered layer corresponding to the identification bit based on at least one resource table entry in the resource table 45. If the resource table entry result indicates that the resource table entry allocation is successful, the to-be-rendered layer is used as the target to-be-rendered layer, the first target resource table entry in the resource table 45 is updated, and the target to-be-rendered layer is sent to the generating portion 42.

[0222] The generating section 42 receives the target layer to be rendered sent by the processing section 41, divides the target layer to be rendered according to a preset division strategy to obtain a plurality of target tiles, and determines a corresponding target rendering core for each target tile according to the tile indication information of each rendering core;

[0223] Upon receiving the layer end signal 47, the processing portion 41 determines the first target layer to be rendered from the layer rendering state table 46, updates the rendering state of the first target layer to be rendered to a completed state, and resets the second target resource table entry in the resource table 45 based on the resource index identifier of the first target layer to be rendered.

[0224] In the disclosed embodiment, the processing portion determines multiple valid target layers to be rendered through the layer's valid identification information, thereby merging multiple layers to be rendered. On the one hand, compared to performing initialization work on each layer once, the initialization of multiple layers to be rendered is completed through a single initialization work, which not only shortens the initialization time but also reduces hardware resource consumption. On the other hand, compared to the situation where the rendering of the next layer must wait for the rendering of the previous layer to be completed, the simultaneous processing of multiple target layers to be rendered makes the multiple target layers to be rendered continuous in the hardware, thereby reducing the idle time of the GPU, thereby improving the utilization of the GPU and reducing the possibility of hardware performance degradation caused by pipeline interruption. At the same time, the generation portion determines the target rendering core of the target tile through the tile indication information of each rendering core, reducing the possibility of idleness caused by the idleness of some rendering cores and the waste of hardware resources, thereby balancing the load of each rendering core while also improving rendering efficiency, thereby improving the rendering performance of the graphics processor as a whole.

[0225] In some embodiments, the processing part 41 is further used to: determine at least one valid to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer validity identification information; wherein each identification bit respectively indicates whether the corresponding to-be-rendered layer is valid; for each valid to-be-rendered layer, determine the resource table item result of the valid to-be-rendered layer based on at least one resource table item in a preset resource table, and if the resource table item result of the valid to-be-rendered layer is a first result, use the valid to-be-rendered layer as the target to-be-rendered layer; wherein the first result indicates that the resource table item allocation of the valid to-be-rendered layer is successful

[0226] In some embodiments, the processing part 41 is further used to: traverse at least one resource table item in the resource table in sequence, determine the resource index identifier of the valid layer to be rendered based on the occupancy flag of the currently traversed resource table item, and stop traversal if the resource index identifier is not a preset index identifier; determine the resource table item result of the valid layer to be rendered based on the resource index identifier.

[0227] In some embodiments, the processing part 41 is further used to: when the occupancy flag of the currently traversed resource table entry is a preset occupancy flag, use the index identifier of the resource table entry as the resource index identifier of the valid layer to be rendered; and / or, when the occupancy flag of the currently traversed resource table entry is not the preset occupancy flag, use the preset index identifier as the resource index identifier of the valid layer to be rendered.

[0228] In some embodiments, the processing part 41 is further configured to: when the resource index identifier is not a preset index identifier, use the first result as the resource entry result of the valid layer to be rendered; and / or, when the resource index identifier is the preset index identifier, use the second result as the resource entry result of the valid layer to be rendered; wherein the second result indicates that the resource entry of the valid layer to be rendered was not successfully allocated.

[0229] In some embodiments, the processing part 41 is further configured to: for each identification bit in the layer valid identification information, if the identification bit satisfies a first preset condition, treat the to-be-rendered layer corresponding to the identification bit as a valid to-be-rendered layer.

[0230] In some embodiments, the processing part 41 is further used to: for each target tile, in response to allocating the target tile to the corresponding target rendering core, update the tile indication information of the target rendering core corresponding to the target tile; and / or, in response to the tile indication information of each rendering core satisfying the second preset condition, reset the tile indication information of each rendering core.

[0231] In some embodiments, the generating part 42 is further used to: divide the target layer to be rendered according to a preset division strategy to obtain the at least one target tile; for each target tile, determine the order information of each rendering core based on the tile indication information of each rendering core, and determine the target rendering core corresponding to the target tile based on the order information of each rendering core.

[0232] In some embodiments, the generating part 42 is further configured to: for each rendering core, determine the order information of each rendering core based on the previous order information of each rendering core when the tile indication information of the rendering core satisfies a second preset condition.

[0233] In some embodiments, the generating part 42 is further configured to: traverse each of the rendering cores according to the order information of each of the rendering cores, and use the first rendering core that does not meet the second preset condition as the target rendering core corresponding to the target tile.

[0234] The description of the controller embodiment above is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the controller embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0235] Based on the above embodiments, the present disclosure provides a control chip for tile distribution, which is applied to a graphics processor. The graphics processor performs a tile distribution process based on a tile rendering (TBR) architecture. FIG5A is a schematic diagram of the structure of a control chip for tile distribution provided by the present disclosure. As shown in FIG5A , the control chip 50 for tile distribution includes a front-end module 51 of the TBR architecture, a controller 52, and a back-end module 53 of the TBR architecture, wherein:

[0236] The front-end module 51 of the TBR architecture is used to determine layer validity identification information based on the picture to be rendered; wherein the picture to be rendered includes at least one layer to be rendered, and the layer validity identification information includes at least one identification bit;

[0237] The controller 52 is configured to obtain the layer valid identification information determined by the front-end module; determine at least one target layer to be rendered from at least one layer to be rendered based on at least one identification bit in the layer valid identification information; and determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on tile indication information of at least one rendering core; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0238] The backend module 53 of the TBR architecture is used to utilize each target rendering core to render the corresponding target tile in parallel to complete the rendering of the to-be-rendered image.

[0239] Here, the front-end module 51 is similar to the front-end module 110 in FIG. 1B , and reference may be made to the front-end module 110 in FIG. During implementation, the front-end module 51 is further configured to specify at least one valid layer to be rendered through the GS, generate valid identification information for the layer based on the at least one valid layer to be rendered specified by the GS, and store the valid identification information for the layer in the memory of the GPU.

[0240] The controller 52 is any of the aforementioned controllers, and for details, reference may be made to the implementation methods of the aforementioned controllers.

[0241] Backend module 53 is similar to backend module 120 in FIG. 1B , and reference may be made to backend module 120 in FIG. During implementation, because multiple target tiles of multiple layers to be rendered are processed in parallel within the pipeline, it is necessary to enhance the hardware's address calculation capabilities. When data for a target tile needs to be read from the GPU's memory, its address in the GPU's memory must be calculated based on the target layer to be rendered.

[0242] FIG5B is a schematic diagram of a backend module processing multi-layer rendering according to an embodiment of the present disclosure, as shown in FIG5B , wherein:

[0243] First, the backend module 53 parses the received target image block to obtain the information carried in the target image block;

[0244] Secondly, the back-end module 53 determines the first address of the first target layer to be rendered in the GPU memory according to the above formula (1-1), and then determines the target address of the rendering data (including color, depth, texture, etc.) of the target tile in the GPU memory according to the first address of the first target layer to be rendered and the position information of the target tile in the first target layer to be rendered;

[0245] Finally, the target tiles are rendered into corresponding layers in RT, that is, the target tile 531 is rendered into the fourth layer 544 , the target tile 532 is rendered into the first layer 541 , and the target tile 533 is rendered into the third layer 543 .

[0246] FIG5C is a schematic diagram of a multi-layer rendering provided by an embodiment of the present disclosure, as shown in FIG5C , wherein:

[0247] Outputting the metadata of each layer to the memory 522 of the GPU through the front-end module 51;

[0248] After receiving the signal 524 indicating that all layers have been processed, the designated hardware 523 sends all layers to be rendered (layer0 to layer9) to the controller 52 at once.

[0249] Obtaining layer valid identification information from the GPU memory 522 through the controller 52, determining at least one target layer to be rendered from all layers to be rendered based on the layer valid identification information, and determining, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on the tile indication information of each rendering core, and sending each target tile to the backend module 53 for rendering;

[0250] The backend module 53 receives rendering instructions, retrieves data for at least one target tile in each target layer from the GPU memory 522, and writes the data for at least one target tile in each target layer to the corresponding location in the RT to complete the rendering of all target layers. In this way, the controller 52 can load all the layers to be rendered at once, completing the processing of all the layers to be rendered with a single load.

[0251] The description of the chip embodiment above is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the system embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0252] Based on the above embodiments, an embodiment of the present disclosure provides a control device for tile distribution. FIG6 is a schematic diagram of the structure of a control device for tile distribution provided in an embodiment of the present disclosure. As shown in FIG6 , the control device 60 for tile distribution includes a first determination module 61 and a second determination module 62, wherein:

[0253] The first determining module 61 is configured to determine at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information;

[0254] The second determination module 62 is configured to determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on tile indication information of at least one rendering core, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

[0255] In some embodiments, the first determining module 61 is further configured to: determine at least one valid to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer validity identification information, wherein each identification bit indicates whether the corresponding to-be-rendered layer is valid; for each valid to-be-rendered layer, determine a resource table entry result for the valid to-be-rendered layer based on at least one resource table entry in a preset resource table; and if the resource table entry result for the valid to-be-rendered layer is a first result, use the valid to-be-rendered layer as the target to-be-rendered layer; wherein the first result indicates that the resource table entry for the valid to-be-rendered layer is successfully allocated.

[0256] In some embodiments, the first determination module 61 is further configured to: sequentially traverse at least one resource table entry in the resource table, determine the resource index identifier of the valid layer to be rendered based on the occupancy flag of the currently traversed resource table entry, and stop traversal if the resource index identifier is not a preset index identifier; and determine the resource table entry result of the valid layer to be rendered based on the resource index identifier.

[0257] In some embodiments, the first determining module 61 is further configured to do at least one of the following: when the occupation flag of the currently traversed resource table entry is a preset occupation flag, use the index identifier of the resource table entry as the resource index identifier of the valid layer to be rendered; when the occupation flag of the currently traversed resource table entry is not the preset occupation flag, use the preset index identifier as the resource index identifier of the valid layer to be rendered.

[0258] In some embodiments, the first determining module 61 is further configured to do at least one of the following: when the resource index identifier is not a preset index identifier, use the first result as the resource entry result of the valid layer to be rendered; when the resource index identifier is the preset index identifier, use the second result as the resource entry result of the valid layer to be rendered; wherein the second result indicates that the resource entry of the valid layer to be rendered was not successfully allocated.

[0259] In some embodiments, the first determining module 61 is further configured to: for each identification bit in the layer valid identification information, if the identification bit meets a first preset condition, treat the to-be-rendered layer corresponding to the identification bit as a valid to-be-rendered layer.

[0260] In some embodiments, the apparatus further includes an update module configured to: for each target layer to be rendered, determine a first target resource table entry from at least one resource table entry in the resource table based on a resource index identifier of the target layer to be rendered, and update the first target resource table entry based on a layer identifier of the target layer to be rendered.

[0261] In some embodiments, the apparatus further includes a reset module, configured to: for each target layer to be rendered, in response to detecting that the rendering status of the target layer to be rendered is a completed state, determine a second target resource table entry from at least one resource table entry in the resource table based on a resource index identifier of the target layer to be rendered, and reset the second target resource table entry.

[0262] In some embodiments, the second determination module 62 is further configured to: divide the target layer to be rendered according to a preset division strategy to obtain the at least one target tile; for each target tile, determine the order information of each rendering core based on the tile indication information of each rendering core, and determine the target rendering core corresponding to the target tile based on the order information of each rendering core.

[0263] In some embodiments, the second determination module 62 is further configured to: for each rendering core, when the tile indication information of the rendering core meets the second preset condition, determine the order information of each rendering core based on the previous order information of each rendering core.

[0264] In some embodiments, the second determining module 62 is further configured to: traverse each of the rendering cores according to the order information of each of the rendering cores, and use the first rendering core that does not meet the second preset condition as the target rendering core corresponding to the target tile.

[0265] In some embodiments, the update module is further configured to: for each target tile, in response to allocating the target tile to the corresponding target rendering core, update the tile indication information of the target rendering core corresponding to the target tile.

[0266] In some embodiments, the resetting module is further configured to: in response to the tile indication information of each rendering core satisfying the second preset condition, reset the tile indication information of each rendering core.

[0267] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0268] It should be noted that, in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

[0269] An embodiment of the present disclosure provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor implements the above method when executing the computer program.

[0270] The present disclosure provides a computer-readable storage medium having a computer program stored thereon, which implements the above method when executed by a processor. The computer-readable storage medium may be transient or non-transient.

[0271] The present disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, implements some or all of the steps in the above method. The computer program product can be implemented specifically by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0272] It should be noted that FIG7 is a schematic diagram of a hardware entity of an electronic device in an embodiment of the present disclosure. As shown in FIG7 , the hardware entity of the electronic device 700 includes: a processor 701, a communication interface 702, and a memory 703, wherein:

[0273] The processor 701 generally controls the overall operations of the electronic device 700 .

[0274] The communication interface 702 enables the electronic device to communicate with other terminals or servers through a network.

[0275] The memory 703 is configured to store instructions and applications executable by the processor 701, and can also cache data to be processed or processed by the processor 701 and various modules in the electronic device 700 (for example, image data, audio data, voice communication data, and video communication data). This can be implemented using flash memory (FLASH) or random access memory (RAM). Data can be transmitted between the processor 701, the communication interface 702, and the memory 703 via the bus 704.

[0276] It should be noted that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0277] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0278] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0279] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0280] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0281] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0282] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0283] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks or optical disks.

[0284] The above description is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure. Industrial Applicability

[0285] The embodiments of the present disclosure provide a control method, chip and device, controller, electronic device, storage medium and computer program product for tile distribution, wherein the control method for tile distribution determines at least one target layer to be rendered from at least one layer to be rendered based on at least one identification bit in the layer valid identification information; for each target layer to be rendered, based on the tile indication information of at least one rendering core, determines the target rendering core corresponding to at least one target tile in the target layer to be rendered, so that each target rendering core renders the corresponding target tile in parallel; wherein each tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive. In this way, multiple valid target layers to be rendered are determined through the layer valid identification information, thereby realizing the merging of multiple layers to be rendered.

Claims

1. A method for controlling tile distribution, wherein: Determine at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information; For each target layer to be rendered, based on the tile indication information of at least one rendering core, determine the target rendering core corresponding to at least one target tile in the target layer to be rendered, so that each of the target rendering cores renders the corresponding target tiles in parallel; wherein each of the tile indication information is respectively used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

2. The control method for tile distribution according to claim 1, wherein: The determining at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information includes: Based on at least one identification bit in the layer validity identification information, determining at least one valid layer to be rendered from at least one layer to be rendered; wherein each of the identification bits indicates whether the corresponding layer to be rendered is valid; For each valid layer to be rendered, a resource table item result of the valid layer to be rendered is determined based on at least one resource table item in a preset resource table, and when the resource table item result of the valid layer to be rendered is a first result, the valid layer to be rendered is used as the target layer to be rendered; wherein the first result indicates that the resource table item of the valid layer to be rendered is allocated successfully.

3. The control method for tile distribution according to claim 2, wherein: The determining of the resource table item result of the valid layer to be rendered based on at least one resource table item in a preset resource table includes: Traversing at least one resource table entry in the resource table in sequence, determining the resource index identifier of the valid layer to be rendered based on the occupation flag of the currently traversed resource table entry, and stopping the traversal if the resource index identifier is not a preset index identifier; Based on the resource index identifier, a resource entry result of the valid layer to be rendered is determined.

4. The control method for tile distribution according to claim 3, wherein: The determining of the resource index identifier of the valid layer to be rendered based on the occupation flag of the currently traversed resource table entry includes at least one of the following: When the occupation flag of the currently traversed resource table entry is a preset occupation flag, the index identifier of the currently traversed resource table entry is used as the resource index identifier of the valid layer to be rendered; When the occupation flag of the currently traversed resource table entry is not the preset occupation flag, the preset index flag is used as the resource index flag of the valid layer to be rendered.

5. The control method for tile distribution according to claim 3, wherein: The determining of the resource entry result of the valid layer to be rendered based on the resource index identifier includes at least one of the following: When the resource index identifier is not a preset index identifier, taking the first result as the resource entry result of the valid layer to be rendered; In a case where the resource index identifier is the preset index identifier, the second result is used as the resource entry result of the valid layer to be rendered; wherein the second result indicates that the resource entry of the valid layer to be rendered is not allocated successfully.

6. The control method for tile distribution according to claim 2, wherein: The determining at least one valid to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer valid identification information includes: For each identification bit in the layer valid identification information, when the identification bit meets a first preset condition, the to-be-rendered layer corresponding to the identification bit is taken as a valid to-be-rendered layer.

7. The control method for tile distribution according to claim 2, wherein: The control method for distributing tiles further includes: For each target layer to be rendered, a first target resource table entry is determined from at least one resource table entry in the resource table based on the resource index identifier of the target layer to be rendered, and the first target resource table entry is updated based on the layer identifier of the target layer to be rendered.

8. The method according to claim 2, wherein: The control method for distributing tiles further includes: For each target layer to be rendered, in response to detecting that the rendering state of the target layer to be rendered is a completed state, determining a first resource from at least one resource table item in the resource table based on a resource index identifier of the target layer to be rendered. The second target resource table entry is reset.

9. The control method for distributing tiles according to any one of claims 1 to 8, wherein: The determining, based on the tile indication information of at least one rendering core, a target rendering core corresponding to at least one target tile in the target to-be-rendered layer comprises: Dividing the target layer to be rendered according to a preset division strategy to obtain the at least one target block; For each target tile, the order information of each rendering core is determined based on the tile indication information of each rendering core, and the target rendering core corresponding to the target tile is determined based on the order information of each rendering core.

10. The control method for tile distribution according to claim 9, wherein: The determining the order information of each rendering core based on the tile indication information of each rendering core comprises: for each rendering core, when the tile indication information of the rendering core satisfies a second preset condition, determining the order information of each rendering core based on the previous order information of each rendering core; The determining the target rendering core corresponding to the target tile based on the order information of each rendering core includes: traversing each rendering core according to the order information of each rendering core, and taking the first rendering core that does not meet the second preset condition as the target rendering core corresponding to the target tile.

11. The control method for tile distribution according to claim 10, wherein: The control method for distributing tiles further includes at least one of the following: For each target tile, in response to allocating the target tile to a corresponding target rendering core, updating tile indication information of the target rendering core corresponding to the target tile; In response to the situation that the tile indication information of each rendering core satisfies the second preset condition, the tile indication information of each rendering core is reset.

12. A controller for distributing tiles, the controller comprising a processing part and a generating part, wherein: The processing part is used to determine at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer effective identification information; Therefore, the generating part is used to determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on the tile indication information of at least one rendering core, so that each of the target rendering cores renders the corresponding target tiles in parallel; wherein each of the tile indication information is used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

13. The controller according to claim 12, wherein: The controller also includes a cache part, wherein: The cache part is used to store the layer effective identification information; The processing part is also used to obtain the layer validity identification information from the cache part.

14. The controller according to claim 12, wherein: The controller also includes a preset resource table, and the resource table includes at least one resource table item; The processing part is further used to determine, for each target layer to be rendered, a first target resource table entry from at least one resource table entry in the resource table based on the resource index identifier of the target layer to be rendered, and update the first target resource table entry based on the layer identifier of the target layer to be rendered.

15. The controller according to claim 12, wherein: The controller further includes a layer rendering status table, wherein the layer rendering status table includes the rendering status of each target layer to be rendered; the processing part is further used for at least one of the following: In response to receiving a layer end signal, determining a first target to-be-rendered layer from at least one target to-be-rendered layer in the layer rendering state table, and updating the rendering state of the first target to-be-rendered layer to a completed state; determining a second target resource table item from at least one resource table item in the resource table based on a resource index identifier of the first target to-be-rendered layer, and resetting the second target resource table item; In response to receiving the end signal, determining at least one second target to-rendering layer from at least one target to-rendering layer in the layer rendering state table, and updating the rendering state of each of the second target to-rendering layers to a completed state; For each second target layer to be rendered, based on the resource index identifier of the second target layer to be rendered, a third target resource table entry is determined from at least one resource table entry in the resource table, and the third target resource table entry is reset.

16. A controller according to any one of claims 12 to 15, wherein: The controller also includes a port part, wherein: The processing part is also used to obtain the layer validity identification information from the memory using the port part in response to receiving the rendering instruction, and store the layer validity identification information in the cache part of the controller.

17. A control chip for tile distribution, applied to a graphics processor, wherein the graphics processor performs a tile distribution process based on a tile rendering TBR architecture, wherein: The front-end module of the TBR architecture is used to determine the layer valid identification information based on the picture to be rendered; wherein the picture to be rendered includes at least one layer to be rendered, and the layer valid identification information includes at least one identification bit; A controller, configured to obtain the layer valid identification information determined by the front-end module; determine at least one target layer to be rendered from at least one layer to be rendered based on at least one identification bit in the layer valid identification information; for each target layer to be rendered, determine a target rendering core corresponding to at least one target tile in the target layer to be rendered based on tile indication information of at least one rendering core; wherein each tile indication information is respectively used to indicate the number of tiles to be rendered that can be received by the corresponding rendering core; The back-end module of the TBR architecture is used to utilize each target rendering core to render the corresponding target tile in parallel to complete the rendering of the to-be-rendered picture.

18. A control device for distributing tiles, wherein: The control device for distributing tiles comprises: A first determination module is configured to determine at least one target to-be-rendered layer from at least one to-be-rendered layer based on at least one identification bit in the layer effective identification information; The second determination module is configured to determine, for each target layer to be rendered, a target rendering core corresponding to at least one target tile in the target layer to be rendered based on tile indication information of at least one rendering core, so that each of the target rendering cores renders the corresponding target tiles in parallel; wherein each of the tile indication information is respectively used to indicate the number of tiles to be rendered that the corresponding rendering core can receive.

19. An electronic device comprising a processor and a memory, wherein the memory stores a computer program executable on the processor, and the processor implements the method according to any one of claims 1 to 11 when executing the computer program.

20. A computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the method according to any one of claims 1 to 11 when executed by a processor.

21. A computer program product, comprising a non-transitory computer-readable storage medium storing a computer program, wherein the computer program implements the method according to any one of claims 1 to 11 when read and executed by a computer.

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