Photodetector and electronic appliance

Abstract

A photodetector according to one embodiment of the present disclosure comprises: a semiconductor layer; a plurality of pixels including a first pixel which has a photoelectric conversion element provided in the semiconductor layer; and trenches provided, in the semiconductor layer, between adjacent pixels among the plurality of pixels. The first pixel includes: a transistor provided on a first-surface side of the semiconductor layer; a first semiconductor region of a first conduction type, which is provided on the first-surface side of the semiconductor layer; and a first contact, which is electrically connected to the first semiconductor region. The first semiconductor region is provided so as to adjoin the transistor. The transistor has a gate electrode provided on the first-surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to photodetection devices and electronic equipment.

[0002] An image sensor has been proposed that has a plurality of unit pixels, each of which includes a photoelectric conversion element, a transfer transistor, a reset transistor, a selection transistor, and a drive transistor (Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-113750

[0004] It is desirable for a light detecting device to be able to accommodate miniaturization.

[0005] It is desirable to provide a photodetector that is advantageous for miniaturization.

[0006] A photodetector according to an embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels. The first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the transistor. The transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer. The photodetector according to an embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels. The first pixel includes a first transistor and a second transistor provided on the first surface side of the semiconductor layer, a first semiconductor region of the first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the first transistor and the second transistor. The first transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer. An electronic device according to an embodiment of the present disclosure includes an optical system and a photodetector that receives light transmitted through the optical system. The photodetector includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels. The first pixel includes a transistor provided on the first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the transistor. The transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer. An electronic device according to an embodiment of the present disclosure includes an optical system and a photodetector that receives light transmitted through the optical system. The photodetector device has a semiconductor layer, a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer, and trenches provided in the semiconductor layer between adjacent pixels.The first pixel includes a first transistor and a second transistor provided on the first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the first transistor and the second transistor. The first transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a part of the semiconductor layer therebetween.

[0007] FIG. 1 is a block diagram showing an example of a schematic configuration of an imaging device that is an example of a photodetector according to a first embodiment of the present disclosure. FIG. 2 is a diagram showing an example of an arrangement of pixels in the imaging device according to the first embodiment of the present disclosure. FIG. 3 is a diagram for explaining an example of a circuit configuration of a pixel in the imaging device according to the first embodiment of the present disclosure. FIG. 4A is a diagram for explaining another example of a circuit configuration of a pixel in the imaging device according to the first embodiment of the present disclosure. FIG. 4B is a diagram for explaining another example of a circuit configuration of a pixel in the imaging device according to the first embodiment of the present disclosure. FIG. 5 is a diagram showing an example of a planar configuration of a pixel in the imaging device according to the first embodiment of the present disclosure. FIG. 6 is a diagram for explaining an example of a cross-sectional configuration of a pixel in the imaging device according to the first embodiment of the present disclosure. FIG. 7 is a diagram showing an example of an arrangement of pixel transistors in the imaging device according to the first embodiment of the present disclosure. FIG. 8 is a diagram showing an example of an arrangement of pixel transistors in the imaging device according to the first embodiment of the present disclosure. FIG. 9 is a diagram showing an example of a cross-sectional configuration of the imaging device according to the first embodiment of the present disclosure. FIG. 10A is a diagram showing an example of a planar configuration of a pixel in the imaging device according to Modification 1 of the present disclosure. FIG. 10B is a diagram showing an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 1 of the present disclosure. FIG. 11A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 2 of the present disclosure. FIG. 11B is a diagram showing an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 2 of the present disclosure. FIG. 12A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 3 of the present disclosure. FIG. 12B is a diagram showing an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 3 of the present disclosure. FIG. 13A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 4 of the present disclosure. FIG. 13B is a diagram showing an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 4 of the present disclosure. FIG. 14 is a diagram showing another example of the planar configuration of a pixel of an imaging device according to Modification 4 of the present disclosure. FIG. 15A is a diagram showing an example of a planar configuration of a pixel of an imaging device according to Modification 5 of the present disclosure. FIG. 15B is a diagram showing an example of a cross-sectional configuration of a pixel of an imaging device according to Modification 5 of the present disclosure. FIG. 16A is a diagram for explaining another example of the configuration of a pixel of an imaging device according to Modification 5 of the present disclosure. FIG. 16B is a diagram for explaining another example configuration of a pixel of an imaging device according to the fifth modification of the present disclosure.FIG. 17 is a diagram illustrating an example configuration of a pixel of an imaging device according to Modification 6 of the present disclosure. FIG. 18 is a diagram illustrating an example configuration of a pixel of an imaging device according to Modification 7 of the present disclosure. FIG. 19A is a diagram illustrating an example planar configuration of a pixel of an imaging device according to Modification 8 of the present disclosure. FIG. 19B is a diagram illustrating an example cross-sectional configuration of a pixel of an imaging device according to Modification 8 of the present disclosure. FIG. 20A is a diagram illustrating an example planar configuration of a pixel of an imaging device according to Modification 9 of the present disclosure. FIG. 20B is a diagram illustrating an example cross-sectional configuration of a pixel of an imaging device according to Modification 9 of the present disclosure. FIG. 21 is a diagram illustrating an example arrangement of pixels of an imaging device according to a second embodiment of the present disclosure. FIG. 22 is a diagram illustrating an example planar configuration of a pixel of an imaging device according to the second embodiment of the present disclosure. FIG. 23 is a diagram illustrating an example configuration of a pixel of an imaging device according to Modification 10 of the present disclosure. FIG. 24 is a diagram illustrating an example configuration of a pixel of an imaging device according to Modification 11 of the present disclosure. FIG. 25 is a diagram illustrating another example configuration of a pixel of an imaging device according to Modification 11 of the present disclosure. FIG. 26 is a diagram for describing an example configuration of a pixel of an imaging device according to Modification 12 of the present disclosure. FIG. 27 is a diagram for describing another example configuration of a pixel of an imaging device according to Modification 12 of the present disclosure. FIG. 28 is a diagram for describing an example configuration of a pixel of an imaging device according to Modification 13 of the present disclosure. FIG. 29 is a diagram for describing an example configuration of a pixel of an imaging device according to Modification 14 of the present disclosure. FIG. 30 is a diagram for describing an example configuration of a pixel of an imaging device according to Modification 15 of the present disclosure. FIG. 31 is a diagram for describing another example configuration of a pixel of an imaging device according to Modification 15 of the present disclosure. FIG. 32 is a diagram for describing an example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 33A is a diagram for describing another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 33B is a diagram for describing another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 33C is a diagram for describing another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 33D is a diagram for describing another example configuration of an imaging device according to the third embodiment of the present disclosure. Fig. 33E is a diagram for explaining another configuration example of an imaging device according to the third embodiment of the present disclosure. Fig. 34 is a diagram for explaining a configuration example of an imaging device according to the third embodiment of the present disclosure.FIG. 35A is a diagram for explaining another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 35B is a diagram for explaining another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 35C is a diagram for explaining another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 35D is a diagram for explaining another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 35E is a diagram for explaining another example configuration of an imaging device according to the third embodiment of the present disclosure. FIG. 36 is a block diagram showing an example configuration of an electronic device having an imaging device. FIG. 37 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 38 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit. FIG. 39 is a diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 40 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Application example 5. Application example

[0009] 1. First Embodiment Fig. 1 is a block diagram showing an example of a schematic configuration of an imaging device that is an example of a photodetection device according to a first embodiment of the present disclosure. The photodetection device is a device that can detect incident light. The imaging device 1 that is a photodetection device has a plurality of pixels P each having a photoelectric conversion unit (photoelectric conversion element) and is configured to photoelectrically convert incident light to generate a signal. The imaging device 1 can receive light that has passed through an optical system (not shown) that includes an optical lens and generate a signal.

[0010] The imaging device 1 is configured, for example, using a semiconductor substrate (e.g., a silicon substrate) on which a plurality of pixels P are provided. The photoelectric conversion unit of each pixel P of the imaging device 1 is, for example, a photodiode (PD) and is configured to be able to photoelectrically convert light. The imaging device 1 has, as an imaging area, a region (pixel unit 100) in which a plurality of pixels P are two-dimensionally arranged in a matrix. The pixel unit 100 of the imaging device 1 can also be referred to as a pixel array in which a plurality of pixels P are arranged. The photoelectric conversion unit of each pixel P can also be referred to as a photoelectric conversion region.

[0011] The imaging device 1 captures incident light (image light) from a subject to be measured via an optical system including an optical lens. The imaging device 1 captures an image of the subject formed by the optical lens. The imaging device 1 can generate pixel signals by photoelectrically converting the received light (e.g., visible light, infrared light, etc.). The imaging device 1, which is a photodetector, is a device that can receive incident light and generate a signal, and can also be called a light-receiving device.

[0012] The imaging device 1 (photodetector) may be configured as an image sensor, for example, a complementary metal oxide semiconductor (CMOS) image sensor, and may be used in various electronic devices such as digital still cameras, video cameras, and mobile phones.

[0013] 1 , the imaging device 1 includes a pixel unit 100, a pixel driving unit 111, a signal processing unit 112, a control unit 113, and a processing unit 114. The imaging device 1 is also provided with, for example, a plurality of control lines L1 and a plurality of signal lines L2.

[0014] The control lines L1 are signal lines capable of transmitting signals for controlling the pixels P, and are connected to the pixel driving unit 111 and the pixels P of the pixel unit 100. In the example shown in FIG. 1 , in the pixel unit 100, a plurality of control lines L1 are wired for each pixel row made up of a plurality of pixels P arranged in the horizontal direction (row direction). The control lines L1 are configured to transmit control signals for reading out signals from the pixels P.

[0015] The plurality of control lines L1 for each pixel row of the imaging device 1 include, for example, wiring for transmitting signals that control transfer transistors, wiring for transmitting signals that control selection transistors, wiring for transmitting signals that control reset transistors, etc. The control lines L1 can also be referred to as drive lines (pixel drive lines) that transmit signals that drive the pixels P.

[0016] The signal line L2 is a signal line capable of transmitting a signal from the pixel P, and is connected to the pixel P of the pixel unit 100 and the signal processing unit 112. In the pixel unit 100, for example, a signal line L2 is wired for each pixel column made up of a plurality of pixels P aligned in the vertical direction (column direction). The signal line L2 is a vertical signal line and is configured to transmit a signal output from the pixel P.

[0017] The pixel driving unit 111 is configured to be able to drive each pixel P of the pixel unit 100. The pixel driving unit 111 is a driving circuit and is configured by a plurality of circuits including, for example, a buffer, a shift register, an address decoder, etc. The pixel driving unit 111 generates a signal for driving the pixel P and outputs the signal to each pixel P of the pixel unit 100 via a control line L1. The pixel driving unit 111 is controlled by the control unit 113 and controls the pixels P of the pixel unit 100.

[0018] The pixel driving unit 111 generates signals for controlling the pixels P, such as signals for controlling the transfer transistors, selection transistors, and reset transistors of the pixels P, and supplies these signals to each pixel P via a control line L1. The pixel driving unit 111 can control the reading of pixel signals from each pixel P. The pixel driving unit 111 can also be referred to as a pixel control unit configured to be able to control each pixel P. The pixel driving unit 111 and the control unit 113 can also be referred to collectively as a pixel control unit.

[0019] The signal processing unit 112 is configured to be able to perform signal processing of input pixel signals. The signal processing unit 112 is a signal processing circuit and includes, for example, a load circuit, an AD (Analog-Digital) conversion circuit, a horizontal selection switch, etc. The load circuit is, for example, configured by a current source capable of supplying current to the amplification transistor of the pixel P. The load circuit, together with the amplification transistor of the pixel P, forms, for example, a source follower circuit.

[0020] The signal processing unit 112 may have an amplifier circuit configured to amplify signals read from the pixels P via the signal lines L2. A load circuit, an amplifier circuit, an AD conversion circuit, etc. may be provided for each of the multiple signal lines L2. A load circuit, an amplifier circuit, an AD conversion circuit, etc. may be provided for each pixel column of the pixel unit 100.

[0021] The signals output from each pixel P selected and scanned by the pixel driving unit 111 are input to the signal processing unit 112 via the signal line L2. The signal processing unit 112 can perform signal processing such as AD conversion of the signal from the pixel P and CDS (Correlated Double Sampling). The signals from each pixel P transmitted through each signal line L2 are subjected to signal processing by the signal processing unit 112 and output to the processing unit 114.

[0022] The processing unit 114 is configured to be able to perform signal processing on the input signal. The processing unit 114 is a signal processing circuit and is configured, for example, by a circuit that performs various types of signal processing on pixel signals. The processing unit 114 may include a processor and a memory. The processing unit 114 performs signal processing on pixel signals input from the signal processing unit 112 and outputs the processed pixel signals. The processing unit 114 can perform various types of signal processing, for example, noise reduction processing, gradation correction processing, etc.

[0023] The control unit 113 is configured to be able to control each unit of the imaging device 1. The control unit 113 receives an externally provided clock, data instructing an operation mode, etc., and can also output data such as internal information of the imaging device 1. The control unit 113 is a control circuit, and has, for example, a timing generator configured to be able to generate various timing signals.

[0024] The control unit 113 controls the driving of the pixel driving unit 111, the signal processing unit 112, etc. based on various timing signals (pulse signals, clock signals, etc.) generated by the timing generator. The control unit 113 and the processing unit 114 may be configured integrally.

[0025] The pixel driving unit 111, the signal processing unit 112, the control unit 113, the processing unit 114, etc. may be provided on a single semiconductor substrate, or may be provided separately on multiple semiconductor substrates. The imaging device 1 may have a structure (a stacked structure) formed by stacking multiple substrates. Some or all of the signal processing unit 112, the control unit 113, and the processing unit 114 may be integrally configured.

[0026] 2 is a diagram showing an example of the arrangement of pixels in the imaging device according to the first embodiment. A pixel P of the imaging device 1 includes a photoelectric conversion unit 12, a lens 21, and a filter 22. As shown in FIG. 2 , the incident direction of light from the subject is defined as the Z-axis direction, the left-right direction on the paper perpendicular to the Z-axis direction is defined as the X-axis direction, and the up-down direction on the paper perpendicular to the Z-axis and X-axis directions is defined as the Y-axis direction. In the following figures, directions may be indicated based on the directions of the arrows in FIG. 2 .

[0027] In the imaging device 1, for example, a lens 21 and a filter 22 may be provided on the side where light from an optical system such as an imaging lens is incident (see also FIG. 9 described later). The lens 21 (lens unit) is a lens that condenses light and is an optical member also called an on-chip lens. The lens 21 is provided above the photoelectric conversion unit 12, for example, for each pixel P or for each set of pixels P.

[0028] Light from a subject to be measured is incident on the lens 21 via an optical system such as an imaging lens. The lens 21 guides the incident light to the photoelectric conversion unit 12 of the pixel P. The photoelectric conversion unit 12 of the pixel P photoelectrically converts the light incident via the lens 21 and the filter 22.

[0029] The filter 22 is configured to selectively transmit light in a specific wavelength range from among the incident light. The filter 22 is, for example, an RGB color filter, a filter that transmits infrared light, etc. The filter 22 is provided above the photoelectric conversion unit 12, for example, for each pixel P or for each set of multiple pixels P.

[0030] The plurality of pixels P provided in the pixel section 100 of the imaging device 1 include, for example, pixels (R pixels) provided with filters 22 that transmit red (R) light, pixels (G pixels) provided with filters 22 that transmit green (G) light, and pixels (B pixels) provided with filters 22 that transmit blue (B) light. In the pixel section 100, a plurality of R pixels, a plurality of G pixels, and a plurality of B pixels are repeatedly arranged.

[0031] The R, G, and B pixels are arranged, for example, according to a Bayer array. The R, G, and B pixels can generate R component pixel signals, G component pixel signals, and B component pixel signals, respectively. The imaging device 1 can obtain RGB pixel signals. Note that the pixel arrangement is not limited to the above example and can be set arbitrarily.

[0032] As an example, the R pixels, G pixels, and B pixels may each be arranged in a 2×2 pixel unit. For example, four adjacent R pixels, four adjacent G pixels, and four adjacent B pixels are repeatedly arranged in the pixel unit 100. It can also be said that the R pixels, G pixels, and B pixels are each periodically arranged in 2 rows and 2 columns.

[0033] The filter 22 provided in the pixel P of the pixel unit 100 is not limited to a primary color (RGB) color filter, but may be a complementary color filter such as Cy (cyan), Mg (magenta), or Ye (yellow). A filter corresponding to W (white), i.e., a filter that transmits light of the entire wavelength range of incident light, may also be provided. The filter 22 may also be a filter that transmits infrared light.

[0034] It should be noted that the filter 22 may be omitted as needed in the imaging device 1. The filter 22 may not be provided in some or all of the pixels P of the imaging device 1. For example, the filter 22 may not be provided in the pixels P that receive white (W) light and perform photoelectric conversion.

[0035] 3 is a diagram illustrating an example of a circuit configuration of a pixel of the imaging device according to the first embodiment. The pixel P of the imaging device 1 includes a photoelectric conversion unit 12 (photoelectric conversion element), a transfer transistor TR, a floating diffusion FD, and a readout circuit 20. The photoelectric conversion unit 12 is configured to receive light and generate a signal. The photoelectric conversion unit 12 is a light-receiving unit (light-receiving element) configured to generate electric charges through photoelectric conversion.

[0036] The readout circuit 20 is configured to be able to output a signal based on the charges photoelectrically converted. The readout circuit 20 can read out a pixel signal based on the charges photoelectrically converted by the photoelectric conversion unit 12. In the imaging device 1, the readout circuit 20 is provided for multiple pixels P. The imaging device 1 has a configuration in which multiple pixels P share one readout circuit 20. This makes it possible to reduce the number of elements (e.g., the number of transistors) per pixel P (or per photoelectric conversion unit 12). The imaging device 1 can have a structure that is advantageous for miniaturizing pixels.

[0037] 3, a readout circuit 20 is arranged for every four pixels P (referred to as pixel Pa to pixel Pd). Pixels Pa, Pb, Pc, and Pd share one readout circuit 20. For example, 2×2 pixels formed by adjacent pixels Pa to Pd share one readout circuit 20.

[0038] The imaging device 1 can read out pixel signals of each of the 2×2 pixels by operating the readout circuit 20 in a time-division manner. The imaging device 1 can also read out pixel signals obtained by adding up the signals of each of the 2×2 pixels. For example, the imaging device 1 can read out pixel signals corresponding to the sum of charges photoelectrically converted by each of the 2×2 pixels.

[0039] 3, the photoelectric conversion unit 12 is a photodiode (PD) that converts incident light into electric charges. The photoelectric conversion unit 12 (in FIG. 3, the photodiode PD of pixel Pa to the photodiode PD of pixel Pd) can perform photoelectric conversion to generate electric charges according to the amount of received light.

[0040] The transfer transistor TR (in FIG. 3, the transfer transistor TR of pixel Pa to the transfer transistor TR of pixel Pd) is configured to be able to transfer charges photoelectrically converted in the photoelectric conversion unit 12 to the floating diffusion FD. The transfer transistor TR is controlled by a signal STR to electrically connect or disconnect the photoelectric conversion unit 12 and the floating diffusion FD. The transfer transistor TR can transfer charges photoelectrically converted and accumulated in the photoelectric conversion unit 12 to the floating diffusion FD.

[0041] 3, the transfer transistors TR of pixels Pa to Pd are controlled to be turned on and off by different signals. The transfer transistor TR of pixel Pa is controlled by a signal STR1, and the transfer transistor TR of pixel Pb is controlled by a signal STR2. The transfer transistor TR of pixel Pc is controlled by a signal STR3, and the transfer transistor TR of pixel Pd is controlled by a signal STR4.

[0042] The floating diffusion FD is an accumulation unit configured to be able to accumulate transferred charges. The floating diffusion FD can accumulate charges photoelectrically converted by the photoelectric conversion unit 12. The floating diffusion FD can also be considered a holding unit capable of holding the transferred charges. The floating diffusion FD accumulates the transferred charges and converts them into a voltage according to the capacitance of the floating diffusion FD.

[0043] 3, the readout circuit 20 includes, for example, an amplifier transistor AMP, a select transistor SEL, and a reset transistor RST. The amplifier transistor AMP is configured to generate and output a signal based on the charge accumulated in the floating diffusion FD. The amplifier transistor AMP can generate and output a signal based on the charge converted by the photoelectric conversion unit 12.

[0044] 3, the gate of the amplification transistor AMP is electrically connected to the floating diffusion FD of each pixel P, and receives the voltage converted by the floating diffusion FD. The drain of the amplification transistor AMP is connected to a power supply line to which a power supply voltage VDD is supplied.

[0045] The source of the amplifier transistor AMP is connected to a signal line L2 via a selection transistor SEL. The amplifier transistor AMP is configured to generate a signal based on the charge accumulated in the floating diffusion FD, i.e., a signal based on the voltage of the floating diffusion FD, and output the signal to the signal line L2.

[0046] The selection transistor SEL is configured to be able to control the output of a pixel signal. The selection transistor SEL is electrically connected in series to the amplification transistor AMP, for example, as in the example shown in FIG. 3. The selection transistor SEL is controlled by a signal SSEL and is configured to be able to output a signal from the amplification transistor AMP to a signal line L2. The selection transistor SEL can control the output timing of the pixel signal.

[0047] The selection transistor SEL is configured to be able to output a signal based on the charge converted by the photoelectric conversion unit 12. The selection transistor SEL can output a pixel signal of the pixel P to a signal line L2. The selection transistor SEL may be electrically connected between a power supply line to which a power supply voltage VDD is applied and the amplification transistor AMP. Furthermore, the selection transistor SEL may be omitted as necessary.

[0048] The reset transistor RST is configured to be able to reset the voltage of the floating diffusion FD. In the example shown in FIG. 3, the reset transistor RST is electrically connected to a power supply line to which a power supply voltage VDD is applied, and is configured to reset the charge of the pixel P.

[0049] The reset transistor RST is controlled by a signal SRST to reset the charge accumulated in the floating diffusion FD and reset the voltage of the floating diffusion FD. In the example shown in Figure 3, the reset transistor RST electrically connects the power supply line and the floating diffusion FD and can discharge the charge accumulated in the floating diffusion FD. The reset transistor RST can also discharge the charge accumulated in the photoelectric conversion unit 12 via the transfer transistor TR.

[0050] 4A is a diagram illustrating another example of the circuit configuration of a pixel of the imaging device according to the first embodiment. The readout circuit 20 may include a transistor FDG, as shown in the example of FIG. The transistor FDG is configured, for example, to be capable of electrically connecting the floating diffusion FD and the reset transistor RST. For example, the transistor FDG is controlled by a signal SFDG to electrically connect or disconnect the floating diffusion FD and the reset transistor RST.

[0051] When the transistor FDG is turned on, the capacitance added to the floating diffusion FD of the pixel P increases, and the conversion efficiency (gain) when converting electric charge to voltage is switched. The transistor FDG is a switching transistor used to set the conversion efficiency. The transistor FDG can change the conversion efficiency by switching the capacitance connected to the gate of the amplification transistor AMP.

[0052] The transistor FDG may be electrically connected in series to the reset transistor RST or electrically connected in parallel to the reset transistor RST. As shown in the example of FIG. 4B , the transistor FDG may be configured to be able to electrically connect the floating diffusion FD and the capacitance element C1. For example, the transistor FDG is controlled by a signal SFDG to electrically connect or disconnect the floating diffusion FD and the capacitance element C1. Switching the connection state of the capacitance element C1 makes it possible to change the conversion efficiency.

[0053] The transfer transistor TR, the amplification transistor AMP, the selection transistor SEL, the transistor FDG (switching transistor), and the reset transistor RST are each a MOS transistor (MOSFET) having a gate, a source, and a drain terminal.

[0054] 3, 4A, and 4B, the transfer transistor TR, the amplification transistor AMP, the selection transistor SEL, the transistor FDG, and the reset transistor RST are each configured as an NMOS transistor. Note that the transistor of the pixel P may be configured as a PMOS transistor. As will be described later, the transistor of the pixel P may be configured as a 3D transistor, for example, a FinFET (FinFET).

[0055] The imaging device 1 may have a configuration in which five or more pixels P, for example, eight pixels P, share one readout circuit 20. For example, in the imaging device 1, a readout circuit 20 is arranged for every eight pixels P, and 2 × 4 pixels share one readout circuit 20.

[0056] The pixel driving unit 111 (see FIG. 1) of the imaging device 1 supplies control signals to the gates of the transfer transistor TR, the selection transistor SEL, the transistor FDG, the reset transistor RST, etc. of each pixel P via the control line L1 described above, thereby turning the transistors on (conducting state) or off (non-conducting state).

[0057] The multiple control lines L1 for each pixel row of the imaging device 1 include, for example, a wiring for transmitting a signal STR that controls the transfer transistor TR, a wiring for transmitting a signal SSEL that controls the selection transistor SEL, a wiring for transmitting a signal SFDG that controls the transistor FDG, and a wiring for transmitting a signal SRST that controls the reset transistor RST.

[0058] The transfer transistor TR, the selection transistor SEL, the transistor FDG, the reset transistor RST, etc. are controlled to be turned on and off by a pixel driving unit 111. The pixel driving unit 111 controls the readout circuit 20 of each pixel P to output a pixel signal from each pixel P to a signal line L2. The pixel driving unit 111 can control the reading out of the pixel signal of each pixel P to the signal line L2.

[0059] Fig. 5 is a diagram showing an example of the planar configuration of a pixel of the imaging device according to the first embodiment. Fig. 6 is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 6 shows an example of the configuration of a pixel in the direction of line A-A' shown in Fig. 5.

[0060] 5 and 6. The pixel P includes a photoelectric conversion unit 12, a transfer transistor TR, a floating diffusion FD, a pixel transistor 30, and a semiconductor region 35. The pixel transistor 30 is, for example, the transistor of the readout circuit 20 described above.

[0061] The pixel transistor 30 is used as an amplification transistor AMP, a selection transistor SEL, a transistor FDG, a reset transistor RST, or the like. Note that the pixel transistor 30 of some of the pixels P may be a dummy transistor. The readout circuit 20 may include a dummy transistor as the pixel transistor 30.

[0062] Each transistor of the readout circuit 20, such as the amplification transistor AMP, the selection transistor SEL, the transistor FDG, and the reset transistor RST, is provided, for example, as a separate pixel transistor 30 for a plurality of pixels P and is shared by the plurality of pixels P. By configuring the imaging device 1 in this manner, it is possible to reduce the number of transistors in one pixel P.

[0063] The imaging device 1 is configured using a substrate 101 including a semiconductor layer 110. The substrate 101 is configured of a semiconductor substrate such as a Si (silicon) substrate. For example, the above-described photoelectric conversion unit 12 and readout circuit 20 are formed on the substrate 101 including the semiconductor layer 110.

[0064] The substrate 101 may be configured using an SOI (Silicon On Insulator) substrate, a SiGe (Silicon Germanium) substrate, other compound semiconductor materials, etc. In the examples shown in Figures 5 and 6, the substrate 101 is configured to include a semiconductor layer 110 and a wiring layer 120.

[0065] As shown in FIG. 6 , the semiconductor layer 110 has opposing surfaces 11S1 and 11S2. The surface 11S2 is the surface opposite to the surface 11S1. The surface 11S1 of the semiconductor layer 110 is an element formation surface on which elements such as transistors are formed. A gate electrode, a gate insulating film (e.g., a gate oxide film), etc. are provided on the surface 11S1 of the semiconductor layer 110. The surface 11S2 of the semiconductor layer 110 is, for example, a light-receiving surface (light incident surface).

[0066] In the semiconductor layer 110, a plurality of photoelectric conversion units 12 (photoelectric conversion elements) are provided along a surface 11S1 and a surface 11S2 of the semiconductor layer 110. For example, the plurality of photoelectric conversion units 12 are embedded in the semiconductor layer 110. The photoelectric conversion units 12 can also be referred to as a photoelectric conversion layer. The photoelectric conversion units 12 are provided between the surface 11S1 and the surface 11S2 of the semiconductor layer 110.

[0067] As shown in Fig. 6, the semiconductor layer 110 has a well 25. The well 25 is, for example, a p-type semiconductor region, or a p-type well (p-well). In the example shown in Fig. 6, the well 25, which is a p-type well region, is provided in the semiconductor layer 110. The photoelectric conversion unit 12 is configured to include a semiconductor region 15 provided in the well 25. The semiconductor region 15 is, for example, an n-type semiconductor region.

[0068] The transfer transistor TR, the floating diffusion FD, the pixel transistor 30, the semiconductor region 35, etc. are provided on the surface 11S1 side of the semiconductor layer 110. The floating diffusion FD includes, for example, an n-type semiconductor region.

[0069] 5 and 6 , trenches 91 and 92 are provided in the imaging device 1. The trenches 91 and 92 are each provided between adjacent pixels P in the semiconductor layer 110. The trenches 91 and 92 are provided between the photoelectric conversion units 12 of adjacent pixels P, and separate the pixels P (or the photoelectric conversion units 12). It can also be said that the pixels P have a structure partitioned by the trenches 91 and 92.

[0070] The trenches 91 and 92 are each an isolation portion (groove portion) and are made of, for example, an insulating material. At least a portion of each of the trenches 91 and 92 is provided at the boundary between adjacent pixels P (or photoelectric conversion portions 12). The trench 91 has an STI (Shallow Trench Isolation) structure and is provided on the surface 11S1 side of the semiconductor layer 110. The trench 92 has an FTI (Full Trench Isolation) structure and is provided so as to penetrate the semiconductor layer 110.

[0071] 5 and 6 , the trench 91 is provided in the semiconductor layer 110 so as to surround the transfer transistor TR, the floating diffusion FD, the pixel transistor 30, the semiconductor region 35, etc. Furthermore, the trench 92 is provided in the semiconductor layer 110 so as to surround the photoelectric conversion unit 12. In plan view, the trenches 91 and 92 are provided in a lattice pattern so as to surround each photoelectric conversion unit 12 of each pixel P. The trenches 91 and 92 can also be referred to as inter-pixel isolation units or inter-pixel isolation walls.

[0072] For example, an insulating film (insulator) such as an oxide film (e.g., a silicon oxide film) or a nitride film (e.g., a silicon nitride film) is provided inside the trench 91 and the trench 92. Polysilicon, a metal material, another insulating material, or the like may be embedded in the trench 91 and the trench 92. A void (cavity) may also be provided inside the trench 91 and the trench 92. The trench 92 may be formed inside the trench 91. For example, the trench 92 may be provided from the trench 91 provided on the surface 11S1 side of the semiconductor layer 110 to the surface 11S2 of the semiconductor layer 110.

[0073] The imaging device 1 is also provided with trenches 93. The trenches 93 are isolation portions (grooves) having an STI structure. An insulating film such as an oxide film (e.g., a silicon oxide film) or a nitride film (e.g., a silicon nitride film) is provided within the trenches 93. The trenches 93 are provided on the surface 11S1 side of the semiconductor layer 110 and separate the elements. The trenches 93 are formed between the pixel transistor 30 and the floating diffusion FD, between the pixel transistor 30 and the transfer transistor TR, between the transfer transistor TR and the semiconductor region 35, etc.

[0074] The imaging device 1 is provided with a plurality of regions (active regions) partitioned by isolation portions (trench). The imaging device 1 has, for example, an active region 81 and an active region 82 provided in the semiconductor layer 110 of the substrate 101. As an example, as shown in FIG. 5 , each pixel P of the imaging device 1 has the active region 81 and the active region 82 surrounded by a trench 93 (or trench 91).

[0075] The active region 81 and the active region 82 are, for example, regions of the semiconductor layer 110 (or the well 25 of the semiconductor layer 110) electrically isolated by the trenches 93 and 91, and are island-shaped regions. As shown in the example of FIG. 5 , the pixel transistor 30 and the semiconductor region 35 are provided in the active region 81. The transfer transistor TR and the floating diffusion FD are provided in the active region 82.

[0076] The transfer transistor TR has a gate insulating film 45 and a gate electrode 46. The transfer transistor TR has, for example, a planar gate structure. The transfer transistor TR is configured as, for example, a planar transistor. The transfer transistor TR is disposed in the active region 82. The transfer transistor TR may have a vertical gate structure. For example, the gate electrode 46 and the gate insulating film 45 of the transfer transistor TR may be formed in the semiconductor layer 110 so as to reach the photoelectric conversion unit 12.

[0077] The semiconductor region 35 is a semiconductor region of the same conductivity type as the well 25, and is provided on the surface 11S1 side of the semiconductor layer 110. The semiconductor region 35 is provided in the active region 81 relative to the well 25, and is electrically connected to the well 25. The semiconductor region 35 is, for example, a p-type semiconductor region, and is a region formed using p-type impurities.

[0078] The semiconductor region 35 has, for example, a higher impurity concentration than the impurity concentration of the well 25, and is a p+ type semiconductor region. The semiconductor region 35, which is a p+ region, is a p+ type diffusion region and can also be said to be a p+ type conductive region. The semiconductor region 35 is also electrically connected to a contact 55. The contact 55 is provided in the wiring layer 120 of the substrate 101.

[0079] 5 , the semiconductor region 35 is connected to a contact 55 provided on the semiconductor region 35, and is electrically connected to a wiring (not shown) of the wiring layer 120 via the contact 55. The contact 55 is electrically connected to the well 25 by the semiconductor region 35.

[0080] The contact 55 is, for example, in ohmic contact with the semiconductor region 35, and is electrically connected to the well 25 via the semiconductor region 35. A predetermined potential (voltage) is supplied to the region of the well 25 electrically connected to the semiconductor region 35 by the wiring of the wiring layer 120, the contact 55, etc.

[0081] The contact 55 is a well contact, and the semiconductor region 35 is a well contact region. The contact 55 and the semiconductor region 35 are arranged, for example, for each pixel P. The semiconductor region 35 and the contact 55 can be collectively referred to as a well contact region.

[0082] The semiconductor region 35 is electrically connected to a reference potential line in the wiring layer 120 via, for example, a contact 55, and a reference potential is applied to the semiconductor region 35 and the well 25. As an example, a GND potential (ground potential) is applied to the semiconductor region 35 and the well 25 via the contact 55.

[0083] The pixel transistor 30 has a semiconductor region 31, a semiconductor region 32, a semiconductor region 33, a gate insulating film 41, and a gate electrode 42. The semiconductor regions 31 to 33 are each provided for a well 25 in the active region 81. It can also be said that the semiconductor regions 32, 33, etc. are arranged to replace part of the well 25. The semiconductor region 31 and the semiconductor region 32 (or the semiconductor region 33) have mutually different conductivity types.

[0084] The semiconductor region 31 is a region where a channel is formed (channel region). As shown in the example of FIG. 6, a portion P1 of a gate electrode 42 and a gate insulating film 41 are provided around the semiconductor region 31. The semiconductor region 31 is, for example, a p-type semiconductor region, and is a region formed using p-type impurities. The semiconductor region 31 is a p-type diffusion region, and can also be said to be a p-type conductive region.

[0085] The semiconductor region 32 and the semiconductor region 33 are the source region and the drain region of the pixel transistor 30. One of the semiconductor regions 32 and 33 is the source region of the pixel transistor 30, and the other of the semiconductor regions 32 and 33 is the drain region of the pixel transistor 30.

[0086] The semiconductor region 32 and the semiconductor region 33 are, for example, n-type semiconductor regions formed using n-type impurities. The semiconductor region 32 and the semiconductor region 33 are formed, for example, by doping (adding) n-type impurities into regions of the semiconductor layer 110. The semiconductor region 32 and the semiconductor region 33 are, for example, n-type diffusion regions and can also be called n-type conductive regions.

[0087] The semiconductor region 32 is connected to a contact 52 provided on the semiconductor region 32, and is electrically connected to a wiring (not shown) of the wiring layer 120 via the contact 52. The semiconductor region 33 is connected to a contact 53 provided on the semiconductor region 33, and is electrically connected to a wiring of the wiring layer 120 via the contact 53.

[0088] A semiconductor region 32 and a semiconductor region 33 are arranged around the gate electrode 42 of the pixel transistor 30. The pixel transistor 30 having the semiconductor regions 32 and 33 is formed in a region around the transfer transistor TR. Note that the shape of the pixel transistor 30 is not limited to the example shown in FIG. 5 and can be changed as appropriate.

[0089] The gate electrode 42 of the pixel transistor 30 is provided, for example, on the surface 11S1 side of the semiconductor layer 110 so as to sandwich a part of the semiconductor layer 110. For example, the part of the gate electrode 42 is provided in the semiconductor layer 110 so as to sandwich a part of the semiconductor layer 110 that becomes a channel region of the pixel transistor 30, via a gate insulating film 41. The pixel transistor 30 can be configured as a Fin type transistor.

[0090] In the imaging device 1, at least a portion of the gate electrode 42 of the pixel transistor 30 is provided, for example, in the semiconductor layer 110. As an example, at least a portion of each of the gate electrode 42 and the gate insulating film 41 is provided by digging into the semiconductor layer 110. For example, each of the gate electrode 42 and the gate insulating film 41 of the pixel transistor 30 can be disposed so as to be embedded in the semiconductor layer 110.

[0091] 6, the gate electrode 42 of the pixel transistor 30 has a plurality of portions P1. The plurality of portions P1 of the gate electrode 42 are provided in the semiconductor layer 110 so as to sandwich the semiconductor region 31, which becomes the channel region of the pixel transistor 30. The plurality of portions P1 are arranged, for example, so as to be aligned with each other in the Y-axis direction (or X-axis direction) with the semiconductor region 31 sandwiched between them. Note that the number, shape, etc. of the portions P1 are not limited to the example shown in the figure and can be changed as appropriate.

[0092] The gate electrode 42 of the pixel transistor 30 may have a plurality of portions P1 provided in the semiconductor layer 110. As an example, the plurality of portions P1 of the gate electrode 42 are arranged in a plurality of grooves (trenches) provided in the semiconductor layer 110. The pixel transistor 30 may have the gate electrode 42 that is a trench-type gate electrode.

[0093] The plurality of portions P1 of the gate electrode 42 have a fin shape and can also be called fin portions. The semiconductor region 31 of the semiconductor layer 110 also has a fin shape and can also be called fin portions. The portions P1 or the semiconductor region 31 are protruding structural portions and can also be called protruding portions.

[0094] In the imaging device 1, the portion P1 of the gate electrode 42 protrudes, for example, from the surface 11S1 of the semiconductor layer 110 toward the inside of the semiconductor layer 110. The portion P1 or the semiconductor region 31 can also be referred to as a convex portion (or a protruding portion). For example, the portion P1 can also be referred to as a convex portion extending from the surface 11S1 of the semiconductor layer 110 toward the inside of the semiconductor layer 110.

[0095] The gate electrode 42 of the pixel transistor 30 may be configured to include a plurality of structural portions provided so as to extend in the thickness direction of the semiconductor layer 110 (or the substrate 101). For example, the gate electrode 42 has a plurality of portions P1 formed so as to extend in the thickness direction perpendicular to the surface 11S1 of the semiconductor layer 110.

[0096] 6, portion P1 of the gate electrode 42 is provided between trench 93 and trench 91. As shown in Fig. 6, a bottom B1 (lower end) of the gate electrode 42 is located higher than a bottom B2 of the trench 93. The portion P1 (fin portion) of the gate electrode 42 is formed in a region whose depth from the surface 11S1 of the semiconductor layer 110 is shallower than the bottom B2 (lower end) of the trench 93, for example.

[0097] The gate insulating film 41 of the pixel transistor 30 is provided on the channel region (semiconductor region 31) of the pixel transistor 30. The gate insulating film 41 (e.g., a gate oxide film) is provided between the semiconductor region 31, which is the channel region, and the gate electrode 42. The gate electrode 42 is provided on the gate insulating film 41.

[0098] 6 , the gate electrode 42 is disposed so as to cover the semiconductor region 31 of the semiconductor layer 110 via a gate insulating film 41. As an example, the gate insulating film 41 is formed along a plurality of portions P1 of the gate electrode 42 within the semiconductor layer 110.

[0099] The portion P1 of the gate electrode 42 and the gate insulating film 41 are provided by digging into the semiconductor layer 110, for example, as shown in the example in FIG. 6 . The pixel transistor 30 may have a dug-out gate structure. A portion of each of the gate electrode 42 and the gate insulating film 41 is disposed so as to be buried in the semiconductor layer 110, for example. The pixel transistor 30 has a dug-out fin structure and can also be called a dug-out fin transistor.

[0100] The gate insulating film 41 of the pixel transistor 30 and the gate insulating film 45 of the transfer transistor TR are each formed of a single layer film made of one of silicon oxide (SiO), silicon oxynitride (SiON), hafnium oxide (HfO), etc., or a laminated film made of two or more of these materials. The gate insulating films 41 and 45 may be formed using a high-dielectric-constant material having a higher dielectric constant than that of silicon oxide, such as a hafnium-based insulating film.

[0101] The gate electrode 42 of the pixel transistor 30 and the gate electrode 46 of the transfer transistor TR are made of, for example, polysilicon (Poly-Si). The gate electrodes 42 and 46 may be made of a metal material or a metal compound. The gate electrodes 42 and 46 may be made of, for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or the like. Sidewalls may be provided on the side surfaces of the gate electrode 42 and the gate electrode 46, respectively.

[0102] The contacts 52, 53, and 55 are each made of a conductive material. For example, the contacts 52, 53, and 55 are each formed by embedding (filling) a conductive material such as tungsten (W) into a contact hole. Note that the contacts 52, 53, and 55 may each be made of a metal material such as aluminum (Al) or copper (Cu), or may be made of other materials.

[0103] In the imaging device 1, the semiconductor region 35 is provided adjacent to the pixel transistor 30. For example, in the pixel P, the semiconductor region 35 is provided adjacent to the source region or the drain region of the pixel transistor 30. The semiconductor region 35 and the source region or the drain region of the pixel transistor 30 are provided in an active region 81 as shown in FIG.

[0104] 5 and 6 , the semiconductor region 35 is disposed adjacent to the semiconductor region 33 of the pixel transistor 30 on the surface 11S1 side of the semiconductor layer 110. In this disclosure, "adjacent" includes cases where there is no contact. "Adjacent" includes cases where there is direct contact and cases where there is adjacent via a native oxide film or the like. In this disclosure, "in contact" includes cases where there is direct contact and cases where there is contact via a native oxide film or the like.

[0105] The semiconductor region 35 is provided, for example, adjacent to an end (side) of the semiconductor region 33, which is the source region or drain region of the pixel transistor 30. The semiconductor region 35 may be provided adjacent to the semiconductor region 32. The semiconductor region 35 may also be provided adjacent to the gate of the pixel transistor 30.

[0106] As described above, in the present embodiment, the semiconductor region 35 is provided adjacent to the pixel transistor 30. This allows the imaging device 1 to have a structure that is advantageous for miniaturization. Compared to when the semiconductor region 35 and the pixel transistor 30 are provided in different active regions, the area of ​​the region in which transistors and the like are arranged in the pixel P can be increased. It is possible to increase the size (e.g., gate width, gate length, etc.) of the transistor arranged in the pixel P.

[0107] Furthermore, in the imaging device 1, as described above, the pixel transistor 30 has the gate electrode 42 that is provided so as to sandwich a part of the semiconductor layer 110. The pixel transistor 30 can be configured as a Fin-type transistor. This allows the area of ​​the gate electrode 42 of the pixel transistor 30 to be increased. This makes it possible to increase the effective gate width, etc. of the pixel transistor 30. This allows the area of ​​the gate of the transistor in the readout circuit 20, for example, the amplification transistor AMP, to be increased, making it possible to suppress noise that gets mixed into pixel signals.

[0108] In particular, it is possible to improve the area efficiency in fine pixels and increase the size of the pixel transistor 30. The pixel transistor 30 can be configured to have multiple fin portions (portions P1), and the gate area of ​​the pixel transistor 30 can be secured. This makes it possible to improve the characteristics of the transistors (amplification transistor AMP, selection transistor SEL, transistor FDG, reset transistor RST, etc.) of the readout circuit 20. This makes it possible to suppress degradation in the quality of pixel signals and suppress degradation in image quality.

[0109] Furthermore, in this embodiment, the gate electrode 42 of the pixel transistor 30 is provided so that the bottom B1 of the gate electrode 42 is located higher than the bottom B2 of the trench 93. This allows the pixel transistor 30 to be isolated from other elements, thereby suppressing crosstalk between elements. This makes it possible to suppress noise from being mixed into pixel signals.

[0110] In the imaging device 1, the portion P1 (fin portion) of the gate electrode 42 is formed in a region whose depth from the surface 11S1 of the semiconductor layer 110 is shallower than the bottom B2 of the trench 93. This makes it possible to suppress manufacturing variations in the portion P1 (variations in the length, width (thickness) of the portion P1, etc.), and to suppress deterioration of the characteristics of the pixel transistor 30.

[0111] 7 is a diagram showing an example of the arrangement of pixel transistors in the image pickup device according to the first embodiment. In FIG. 7, four pixels P that share the readout circuit 20 are designated as pixels Pa to Pd, and a 2×2 pixel arrangement is shown. The other pixels P in the image pickup device 1 may also have a configuration similar to that shown in FIG.

[0112] 7, pixel Pa is provided with an amplification transistor AMP as the pixel transistor 30. Pixel Pb is provided with a selection transistor SEL as the pixel transistor 30. Pixel Pc is provided with a reset transistor RST as the pixel transistor 30. Pixel Pd is provided with a transistor FDG as the pixel transistor 30.

[0113] 7, the imaging device 1 is provided with a wiring L3. The floating diffusion FD of each of the multiple pixels P that share the readout circuit 20 is electrically connected to the transistor of the readout circuit 20 via the wiring L3. The floating diffusion FD of each of the pixels Pa to Pd is electrically connected to the gate electrode of the amplification transistor AMP, which is the pixel transistor 30 of the pixel Pa, for example, via the wiring L3.

[0114] The wiring L3 is a wiring shared by four pixels Pa to Pd. The wiring L3 is formed using a metal material such as aluminum (Al) or tungsten (W). The wiring L3 may also be made of polysilicon (Poly-Si) or other conductive materials.

[0115] The imaging device 1 may have a configuration in which a floating diffusion FD is shared by multiple pixels P, as in the example shown in Fig. 8. In the example shown in Fig. 8, the floating diffusion FD is provided for four pixels Pa to Pd and is shared by the pixels Pa to Pd.

[0116] Fig. 9 is a diagram showing an example of a cross-sectional configuration of the imaging device according to the first embodiment. As shown in Fig. 9, the imaging device 1 includes, for example, a light guide section 90, a semiconductor layer 110, and a wiring layer 120. The imaging device 1 has a configuration in which the light guide section 90, the semiconductor layer 110, and the wiring layer 120 are stacked in the Z-axis direction.

[0117] 9 , a wiring layer 120 is provided on a surface 11S1 side of the semiconductor layer 110. A light guiding section 90 is provided on a surface 11S2 side of the semiconductor layer 110. The light guiding section 90 is provided on the side where light from the optical system is incident, and the wiring layer 120 is provided on the side opposite to the side where the light is incident. The imaging device 1 is a so-called backside illuminated imaging device.

[0118] The wiring layer 120 includes, for example, a conductor film and an insulating film, and has a plurality of wirings and vias (VIAs). The wiring layer 120 includes, for example, two or more layers of wirings, or three or more layers of wirings. The wiring layer 120 may include five or more layers of wirings. The wiring layer 120 has a configuration in which a plurality of wirings are stacked with an insulating film interposed therebetween as an interlayer insulating film (interlayer insulating layer). The insulating film of the wiring layer 120 can also be called an interlayer insulating film (interlayer insulating layer).

[0119] The wiring of the wiring layer 120 is formed using a metal material such as aluminum (Al), tungsten (W), or copper (Cu). The wiring of the wiring layer 120 may be formed using polysilicon (Poly-Si) or other conductive materials. The interlayer insulating film is formed using, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or the like.

[0120] As described above, for example, the photoelectric conversion unit 12, the readout circuit 20, etc. are provided in the semiconductor layer 110 and the wiring layer 120. Furthermore, the pixel driving unit 111, the signal processing unit 112, the control unit 113, the processing unit 114, etc. may be provided on a substrate separate from the semiconductor layer 110, or on the semiconductor layer 110 and the wiring layer 120.

[0121] 9 is stacked on the semiconductor layer 110 in a thickness direction perpendicular to the surface 11S2 of the semiconductor layer 110. The light guide 90 has a lens 21 and a filter 22, and guides incident light to the semiconductor layer 110 side.

[0122] The lens 21 is provided on the filter 22, for example, for each pixel P or for each set of pixels P. Light from a subject is incident on the lens 21 via an optical system such as an imaging lens. The photoelectric conversion unit 12 photoelectrically converts the light incident via the lens 21 and the filter 22.

[0123] 9 , the imaging device 1 is provided with a light-shielding portion 23. The light-shielding portion 23 (light-shielding film) is made of a material that blocks light, and is provided at the boundary between adjacent pixels P. For example, at least a part of the light-shielding portion 23 (light-shielding member) may be provided between adjacent filters 22 and positioned at the boundary between the adjacent filters 22.

[0124] The light-shielding portion 23 is made of, for example, a metal material that blocks light (aluminum (Al), tungsten (W), copper (Cu), etc.). The light-shielding portion 23 may also be made of a material that absorbs light. In the imaging device 1, the provision of the light-shielding portion 23 prevents light from leaking to surrounding pixels P. This prevents unnecessary light from leaking to the surroundings, and prevents color mixing.

[0125] The imaging device 1 may have at least one of a fixed charge film and an anti-reflection film. The fixed charge film and the anti-reflection film are provided, for example, on the surface 11S2 side of the semiconductor layer 110. The fixed charge film is a film having a fixed charge and may be formed using a high dielectric material. For example, the fixed charge film is made of a metal oxide such as hafnium oxide or aluminum oxide.

[0126] The fixed charge film is, for example, a film having a negative fixed charge. As an example, the fixed charge film is provided between the semiconductor layer 110 and the filter 22. By providing the fixed charge film, the generation of dark current at the interface of the semiconductor layer 110 is suppressed. Note that the fixed charge film may be formed of another metal oxide film, or may be formed using a metal nitride film or a metal oxynitride film. A film having a positive fixed charge may be provided as the fixed charge film.

[0127] The anti-reflection film is made of, for example, an insulating material such as silicon nitride (SiN) or silicon oxide (SiO). The anti-reflection film is provided, for example, so as to be stacked with the fixed charge film. The anti-reflection film is provided, for example, between the semiconductor layer 110 and the filter 22, and reduces (suppresses) reflection. The anti-reflection film may be made of a metal compound (metal oxide, metal nitride, etc.) such as aluminum oxide, hafnium oxide, or tantalum oxide, or may be made of other materials.

[0128] [Actions and Effects] The photodetector according to this embodiment includes a semiconductor layer (semiconductor layer 110), a plurality of pixels including a first pixel (e.g., pixel Pa) having a photoelectric conversion element (photoelectric conversion unit 12) provided in the semiconductor layer, and trenches (trench 91, trench 92) provided in the semiconductor layer between adjacent pixels. The first pixel includes a transistor (pixel transistor 30) provided on the first surface side of the semiconductor layer, a first semiconductor region (semiconductor region 35) of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact (contact 55) electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the transistor. The transistor has a gate electrode (gate electrode 42) provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer.

[0129] In the photodetector (image capture device 1) according to this embodiment, the semiconductor region 35 is provided adjacent to the pixel transistor 30. The semiconductor region 35 is provided adjacent to the semiconductor region 33, which is the source region or drain region of the pixel transistor 30. The pixel transistor 30 also has a gate electrode 42 provided to sandwich a part of the semiconductor layer 110. This allows the image capture device 1 to have a structure that is advantageous for miniaturization of pixels. The gate area of ​​the pixel transistor can be increased, making it possible to improve the characteristics of the pixel transistor. It is possible to realize a photodetector that is advantageous for miniaturization.

[0130] Next, a modified example of the present disclosure will be described. In the following, the same components as those in the above embodiment will be denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0131] (1-1. Modification 1) Fig. 10A is a diagram showing an example of the planar configuration of a pixel of an imaging device according to Modification 1 of the present disclosure. Fig. 10B is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 10B schematically shows an example of the configuration of a pixel in the direction of line AA' shown in Fig. 10A.

[0132] In the imaging device 1 according to this modification, the transfer transistor TR has a vertical gate structure. That is, the transfer transistor TR has a vertical gate (VG) structure. The transfer transistor TR can also be called a vertical transistor. At least a portion of each of the gate insulating film 45 and the gate electrode 46 of the transfer transistor TR is provided within the semiconductor layer 110. At least a portion of each of the gate insulating film 45 and the gate electrode 46 is provided by digging into the semiconductor layer 110, as in the example shown in FIG. 10B .

[0133] 10B , a portion of each of the gate electrode 46 and the gate insulating film 45 of the transfer transistor TR is disposed so as to be embedded in, for example, the semiconductor layer 110. The gate electrode 46 is provided so as to reach, for example, the photoelectric conversion unit 12. The gate electrode 46 can be provided in the semiconductor layer 110 from between the floating diffusion FD and the trench 93 to the region of the photoelectric conversion unit 12. The gate insulating film 45 is formed along the gate electrode 46 in the semiconductor layer 110.

[0134] 10B , in the imaging device 1, the bottom B3 (lower end) of the gate electrode 46 of the transfer transistor TR is located, for example, below the bottom B2 of the trench 93. The bottom B3 of the gate electrode 46 is formed, for example, up to a region whose depth from the surface 11S1 of the semiconductor layer 110 is deeper than the bottom B2 of the trench 93.

[0135] In the imaging device 1 according to this modification, the transfer transistor TR has a VG structure. The gate electrode 46 of the transfer transistor TR can be provided so as to reach the photoelectric conversion unit 12. This makes it possible to improve the efficiency of charge transfer from the photoelectric conversion unit 12 to the floating diffusion FD.

[0136] Furthermore, in the imaging device 1, the gate electrode 42 of the pixel transistor 30 is provided so that the bottom B1 of the gate electrode 42 is located higher than the bottom B3 of the gate electrode 46 of the transfer transistor TR and the bottom B2 of the trench 93. This allows the pixel transistor 30 to be appropriately isolated from other elements, suppressing crosstalk between elements and making it possible to suppress noise from being mixed into pixel signals.

[0137] (1-2. Modification 2) Fig. 11A is a diagram showing an example of the planar configuration of a pixel of an imaging device according to Modification 2. Fig. 11B is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 11B schematically shows an example of the configuration of a pixel in the direction of line AA' shown in Fig. 11A.

[0138] The gate electrode 46 of the transfer transistor TR may be provided adjacent to the trench 93. The gate insulating film 45 and the gate electrode 46 of the transfer transistor TR are provided so as to contact the trench 93, for example, as in the examples shown in Figures 11A and 11B. This makes it possible to reduce the parasitic capacitance added to the transfer transistor TR.

[0139] In the imaging device 1 according to this modification, the parasitic capacitance added to the transfer transistor TR can be reduced, thereby improving the characteristics of the transfer transistor TR. The gm (mutual conductance) of the transfer transistor TR can be improved. Furthermore, power consumption can be reduced.

[0140] (1-3. Modification 3) Fig. 12A is a diagram showing an example of the planar configuration of a pixel of an imaging device according to Modification 3. Fig. 12B is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 12B schematically shows an example of the configuration of a pixel in the direction of line A-A' shown in Fig. 12A.

[0141] 12B , the pixel transistor 30 has a sidewall 43. The sidewall 43 is provided on a side surface of the gate electrode 42 of the pixel transistor 30. The transfer transistor TR also has a sidewall 47. The sidewall 47 is provided on a side surface of the gate electrode 46 of the transfer transistor TR.

[0142] The sidewalls 43 and 47 are made of an insulating film such as silicon oxide (SiO) or silicon nitride (SiN), and are provided around the gate electrodes 42 and 46. The sidewalls 43 and 47 may be made of silicon oxynitride (SiON) or other materials.

[0143] 12A and 12B, the imaging device 1 is provided with an insulating film 49. The insulating film 49 is provided in the semiconductor layer 110 between the floating diffusion FD and the gate electrode 46 of the transfer transistor TR. For example, as shown in FIG. 12B, the insulating film 49 is provided in a recessed portion 96 in the gate electrode 46. It can also be said that the insulating film 49 is disposed so as to replace a part of the gate electrode 46. The recessed portion 96 can also be said to be a groove (recess).

[0144] The insulating film 49 is composed of an insulating film such as an oxide film, a nitride film, or an oxynitride film. The insulating film 49 is formed using silicon oxide (SiO), silicon nitride (SiN), aluminum oxide (AlO), or other insulating materials. The insulating film 49 can be provided, for example, on a region of the side surface of the gate electrode 46 that faces the floating diffusion FD (in FIG. 12B , a recessed portion 96 of the gate electrode 46).

[0145] In the imaging device 1 according to this modification, the provision of the insulating film 49 makes it possible to reduce the parasitic capacitance added to the transfer transistor TR. This makes it possible to improve the characteristics of the transfer transistor TR. The insulating film 49 may be configured integrally with the sidewall 47. At least a portion of the sidewall 47 may be provided in the semiconductor layer 110 and arranged as the insulating film 49.

[0146] (1-4. Modification 4) Fig. 13A is a diagram showing an example of the planar configuration of a pixel of an imaging device according to Modification 4. Fig. 13B is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 13B schematically shows an example of the configuration of a pixel in the direction of line A-A' shown in Fig. 13A.

[0147] 13A and 13B , the imaging device 1 may be provided with an insulating film 48. The insulating film 48 is provided, for example, in a recessed portion 95 at an end of the gate electrode 42 of the pixel transistor 30 in the semiconductor layer 110. In the example shown in FIG. 13B , the insulating film 48 can also be said to be disposed so as to replace part of the portion P1 of the gate electrode 42. In the imaging device 1 according to this modification, the insulating film 48 is provided in the recessed portion 96 of the gate electrode 42, thereby making it possible to suppress deterioration in the characteristics of the pixel transistor 30 due to variations in gate position.

[0148] It should be noted that the shape and arrangement of the insulating film 48 of the imaging device 1 are not limited to the example shown in the drawing. For example, as shown in FIG. 14 , the insulating film 48 may be provided on both ends of the gate electrode 42 of the pixel transistor 30. The insulating film 48 may be configured integrally with the sidewall 43. At least a portion of the sidewall 43 may be provided in the semiconductor layer 110 and arranged as the insulating film 48.

[0149] (1-5. Modification 5) Fig. 15A is a diagram showing an example of the planar configuration of a pixel of an imaging device according to Modification 5. Fig. 15B is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 15B schematically shows an example of the configuration of a pixel in the direction of line A-A' shown in Fig. 15A.

[0150] The transfer transistor TR may have multiple vertical gates (VG). In the example shown in Figures 15A and 15B, the transfer transistor TR has a gate electrode 46a and a gate electrode 46b. The transfer transistor TR can transfer charges from the photoelectric conversion unit 12 using the gate electrodes 46a and 46b, which serve as vertical gates. This makes it possible to improve the charge transfer efficiency.

[0151] 16A and 16B are diagrams illustrating another example of the configuration of a pixel of an imaging device according to Modification 5. As shown in the example of Fig. 16A and 16B, an insulating film 49 may be provided in the recessed portion of at least one of the gate electrodes 46a and 46b. For example, the parasitic capacitance added to the transfer transistor TR can be reduced, thereby improving the characteristics of the transfer transistor TR.

[0152] 17 is a diagram illustrating an example of the configuration of a pixel of an imaging device according to Modification 6. The source region and drain region of the pixel transistor 30 may have different sizes. For example, in the imaging device 1, of the semiconductor region 32 and the semiconductor region 33 of the pixel transistor 30, the size of the semiconductor region 33 that is closer to the semiconductor region 35, which is a well contact region, is smaller than the size of the semiconductor region 32.

[0153] Furthermore, in the imaging device 1, the size of the region of the active region 81 in which the pixel transistors 30 are arranged, which is closer to the semiconductor region 33 and closer to the semiconductor region 35, may be smaller than the size of the region of the active region 81 on the semiconductor region 32 side. The pixel transistors 30 may have, for example, a trapezoidal shape. By configuring the imaging device 1 in this manner, it is possible to alleviate the electric field (potential gradient) between the well contact region and the pixel transistors 30. This makes it possible to suppress noise from being mixed into pixel signals and to suppress degradation in image quality.

[0154] (1-7. Modification 7) FIG. 18 is a diagram illustrating an example of the configuration of a pixel of an imaging device according to Modification 7. In the pixel P, the semiconductor region 35 may be provided adjacent to at least one of the gate electrode 42 and the gate insulating film 41 of the pixel transistor 30. In the example shown in FIG. 18, the semiconductor region 35 is arranged in the active region 81 on the surface 11S1 side of the semiconductor layer 110 so as to be adjacent to the gate insulating film 41 and the gate electrode 42 of the pixel transistor 30. The semiconductor region 35 is provided in contact with the active region 81 in which the gate electrode 42 and the like are arranged. Note that the shape of the pixel transistor 30 is not limited to the example shown in FIG. 18 and can be modified as appropriate.

[0155] In the photodetector device according to this modification, the transistor (pixel transistor 30) has a gate electrode and a gate insulating film (gate electrode 42 and gate insulating film 41) provided on a first region (active region 81) of the semiconductor layer (semiconductor layer 110). The first semiconductor region is provided in contact with the first region (active region 81) so as to be adjacent to at least one of the gate electrode and the gate insulating film of the transistor.

[0156] In this modified example, the imaging device 1 can also have a structure that is advantageous for miniaturization. Compared to when the semiconductor region 35 and the pixel transistor 30 are disposed apart, the area of ​​the region in which transistors and the like are disposed in the pixel P can be increased. The size of the pixel transistor 30 disposed in the pixel P can be increased, and the characteristics of the transistors (amplification transistor AMP, selection transistor SEL, etc.) of the readout circuit 20 can be improved.

[0157] (1-8. Modification 8) Fig. 19A is a diagram showing an example of the planar configuration of a pixel of an imaging device according to Modification 8. Fig. 19B is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 19B schematically shows an example of the configuration of a pixel in the direction of line A-A' shown in Fig. 19A.

[0158] 19A and 19B , the imaging device 1 according to this modification has a conductor region 36. The conductor region 36 is provided around the semiconductor region 35. At least a portion of the conductor region 36 is provided in contact with the semiconductor region 35. The conductor region 36 is formed adjacent to the semiconductor region 35, for example, on the surface 11S1 side of the semiconductor layer 110. In the example shown in FIG. 19B , the conductor region 36 is located above and inside the trenches 91 and 92.

[0159] The conductor region 36 is made of, for example, polysilicon doped with impurities. Note that the conductor region 36 (conductive portion) may be made of other conductive materials (for example, metal materials). The conductor region 36 has, for example, a higher impurity concentration than the impurity concentration of the well 25.

[0160] The contact 55 is provided on the conductor region 36. The contact 55 is electrically connected to the semiconductor region 35 and the well 25 via the conductor region 36. In the imaging device 1 according to this modification, the semiconductor region 35 provided in the well 25 is electrically connected to the contact 55 via the conductor region 36. By providing the well contact and the well contact region with a side contact structure, it is possible to improve the area efficiency of the pixel P.

[0161] Furthermore, it is possible to reduce the impurity concentration of the semiconductor region 35 required for electrical connection with the contact 55. By reducing the impurity concentration of the semiconductor region 35, it is possible to reduce the electric field between the semiconductor region 35 and the semiconductor region 33 (source region or drain region) of the pixel transistor 30. This makes it possible to suppress defects from occurring in the pixel transistor 30. It is also possible to prevent an increase in noise mixed into pixel signals.

[0162] (1-9. Modification 9) Fig. 20A is a diagram showing an example of the planar configuration of a pixel of an imaging device according to Modification 9. Fig. 20B is a diagram for explaining an example of the cross-sectional configuration of a pixel of the imaging device. Fig. 20B schematically shows an example of the configuration of a pixel in the direction of line AA' shown in Fig. 20A.

[0163] As shown in FIGS. 20A and 20B , the imaging device 1 may have a semiconductor region 37. The semiconductor region 37 is provided in the semiconductor layer 110 around the floating diffusion FD. The semiconductor region 37 is made of, for example, polysilicon doped with impurities. Note that the semiconductor region 37 may also be made of other conductive materials. At least a portion of the semiconductor region 37 is provided in contact with the floating diffusion FD.

[0164] The floating diffusions FD of the plurality of pixels P (for example, pixels Pa to Pd in ​​FIG. 7 and the like) that share the readout circuit 20 can be electrically connected to each other via the semiconductor region 37. The floating diffusions FD of the pixels Pa to Pd are electrically connected to the amplification transistor AMP, reset transistor RST, etc. of the readout circuit 20 via the semiconductor region 37.

[0165] In this way, in the imaging device 1 according to this modification, the floating diffusion FD and the semiconductor region 37 have a side contact structure, which makes it possible to improve the area efficiency of the pixel P. It becomes possible to secure the area of ​​the region in the pixel P where the transistors and the like are arranged.

[0166] 2. Second Embodiment Next, a second embodiment of the present disclosure will be described. In the following, components similar to those in the above-described embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0167] 21 is a diagram showing an example of pixel arrangement in an imaging device according to a second embodiment of the present disclosure. A pixel P of the imaging device 1 has a plurality of photoelectric conversion units 12 (photoelectric conversion unit 12a and photoelectric conversion unit 12b in the example shown in FIG. 21). The photoelectric conversion unit 12b is provided adjacent to the photoelectric conversion unit 12a. It can also be said that a pixel having the photoelectric conversion unit 12a and a pixel having the photoelectric conversion unit 12b are provided.

[0168] In this embodiment, one lens 21 (lens unit) is provided for a plurality of photoelectric conversion units 12, for example, two photoelectric conversion units 12 (photoelectric conversion unit 12 a, photoelectric conversion unit 12 b). The photoelectric conversion units 12 a and 12 b receive light that has passed through different regions of an optical system such as an imaging lens, and perform pupil division.

[0169] Phase difference data (phase difference information) can be obtained by using a first pixel signal based on the charges photoelectrically converted by the photoelectric conversion unit 12 a and a second pixel signal based on the charges photoelectrically converted by the photoelectric conversion unit 12 b. Phase difference data can be used to perform phase difference AF (Auto Focus).

[0170] The readout circuit 20 is configured to be able to output a first pixel signal and a second pixel signal of each pixel P that shares the readout circuit 20. The readout circuit 20 can also read out a pixel signal corresponding to the charge obtained by adding together the charge converted by the photoelectric conversion unit 12 a and the charge converted by the photoelectric conversion unit 12 b.

[0171] 22 is a diagram showing an example of the planar configuration of a pixel of the imaging device according to Embodiment 2. The pixel P of the imaging device 1 includes transfer transistors TRa and TRb, floating diffusions FDa and FDb, pixel transistors 30a and 30b, and a semiconductor region 35.

[0172] The transfer transistor TRa is configured to be able to transfer charges photoelectrically converted by the photoelectric conversion unit 12a to the floating diffusion FDa. The transfer transistor TRb is configured to be able to transfer charges photoelectrically converted by the photoelectric conversion unit 12b to the floating diffusion FDb. The floating diffusion FDa can store the charges photoelectrically converted by the photoelectric conversion unit 12a. The floating diffusion FDb can store the charges photoelectrically converted by the photoelectric conversion unit 12b.

[0173] The readout circuit 20 is configured to be able to output, for example, a pixel signal based on the charge accumulated in the floating diffusion FDa, a pixel signal based on the charge accumulated in the floating diffusion FDb, etc. Furthermore, for example, the readout circuit 20 is configured to be able to output a pixel signal corresponding to the charge obtained by adding the charge accumulated in the floating diffusion FDa and the charge accumulated in the floating diffusion FDb.

[0174] The pixel transistor 30 a and the pixel transistor 30 b are, for example, transistors of the readout circuit 20. The semiconductor region 32 a and the semiconductor region 33 a are the source region and the drain region of the pixel transistor 30 a. One of the semiconductor regions 32 a and 33 a is the source region of the pixel transistor 30 a, and the other of the semiconductor regions 32 a and 33 a is the drain region of the pixel transistor 30 a.

[0175] The semiconductor region 32b and the semiconductor region 33b are the source region and the drain region of the pixel transistor 30b. One of the semiconductor regions 32b and 33b is the source region of the pixel transistor 30b, and the other of the semiconductor regions 32b and 33b is the drain region of the pixel transistor 30b.

[0176] The pixel transistors 30a and 30b are used as an amplification transistor AMP, a selection transistor SEL, a transistor FDG, a reset transistor RST, or the like. The pixel transistor 30a or the pixel transistor 30b of some pixels P may be a dummy transistor. The readout circuit 20 may include a dummy transistor as the pixel transistor 30a or the pixel transistor 30b. One pixel transistor 30 may be provided for each of the photoelectric conversion units 12a and 12b.

[0177] The pixel transistors 30 a and 30 b can each be configured as a Fin-type transistor. The pixel transistor 30 a has a gate electrode 42 a including a plurality of portions P1 a (fin portions). The plurality of portions P1 a of the gate electrode 42 a are provided in the semiconductor layer 110 so as to sandwich a portion of the semiconductor layer 110 that becomes a channel region of the pixel transistor 30 a.

[0178] Furthermore, the pixel transistor 30b has a gate electrode 42b including a plurality of portions P1b (fin portions). The plurality of portions P1b of the gate electrode 42b are provided in the semiconductor layer 110 so as to sandwich a portion of the semiconductor layer 110 that becomes a channel region of the pixel transistor 30b. The pixel transistors 30a and 30b each have, for example, a recessed fin structure and can also be called recessed fin transistors.

[0179] The imaging device 1 may also include an isolation portion 95 a and an isolation portion 95 b. The isolation portion 95 a and the isolation portion 95 b may each include a trench, for example. The isolation portion 95 a and the isolation portion 95 b may each be provided between the photoelectric conversion portion 12 a and the photoelectric conversion portion 12 b in the semiconductor layer 110.

[0180] The isolation portions 95 a and 95 b may be made of an insulating material or may be made of a semiconductor region formed by ion implantation. For example, the isolation portions 95 a and 95 b may be made of a p-type semiconductor region or an n-type semiconductor region.

[0181] The separation portion 95a is provided, for example, between adjacent floating diffusions FD on the surface 11S1 side of the semiconductor layer 110. In the example shown in Fig. 22, the separation portion 95a is formed between the floating diffusion FDa and the floating diffusion FDb.

[0182] The separation portion 95b is provided between adjacent pixel transistors 30 on the surface 11S1 side of the semiconductor layer 110. In the example shown in Fig. 22 , the separation portion 95b is formed between the pixel transistor 30a and the pixel transistor 30b. The semiconductor region 35 is provided between the separation portion 95a and the separation portion 95b in a plan view, for example, as shown in Fig. 22 .

[0183] In the imaging device 1 according to the present embodiment, the semiconductor region 35 is provided adjacent to the pixel transistor 30 a and the pixel transistor 30 b. For example, in the pixel P, the semiconductor region 35 is disposed adjacent to the source region or drain region of the pixel transistor 30 a and the source region or drain region of the pixel transistor 30 b.

[0184] 22 , the semiconductor region 35, the source region or drain region of the pixel transistor 30a, and the source region or drain region of the pixel transistor 30b are provided in the active region 81. The semiconductor region 35 is provided adjacent to the semiconductor region 33a of the pixel transistor 30a and the semiconductor region 33b of the pixel transistor 30b. The semiconductor region 35 may be provided adjacent to the semiconductor regions 32a and 32b. The semiconductor region 35 may also be provided adjacent to the gates of the pixel transistors 30a and 30b.

[0185] As described above, in this embodiment, the semiconductor region 35 is provided adjacent to the pixel transistor 30a and the pixel transistor 30b. Therefore, the imaging device 1 can have a structure that is advantageous for miniaturization. Compared to when the semiconductor region 35 and the pixel transistors 30a and 30b are provided apart, the area of ​​the region in which transistors and the like are arranged in the pixel P can be increased. It is possible to increase the size of the transistors arranged in the pixel P.

[0186] Furthermore, in the imaging device 1, the pixel transistors 30a, 30b can each be configured as a Fin-type transistor. This allows the areas of the gate electrodes 42a, 42b of the pixel transistors 30a, 30b to be increased. This also allows the effective gate widths of the gate electrodes 42a, 42b to be increased. This allows the gate area of ​​the transistors (e.g., the amplification transistor AMP) of the readout circuit 20 to be increased, making it possible to suppress noise from being mixed into pixel signals.

[0187] [Actions and Effects] The photodetector according to this embodiment includes a semiconductor layer (semiconductor layer 110), a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element (photoelectric conversion unit 12a and photoelectric conversion unit 12b; i.e., a first photoelectric conversion region and a second photoelectric conversion region) provided in the semiconductor layer, and trenches (trench 91, trench 92) provided in the semiconductor layer between adjacent pixels. The first pixel includes a first transistor and a second transistor (pixel transistor 30a, pixel transistor 30b) provided on the first surface side of the semiconductor layer, a first semiconductor region (semiconductor region 35) of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact (contact 55) electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the first transistor and the second transistor. The first transistor has a gate electrode (e.g., gate electrode 42a) provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer therebetween.

[0188] In the photodetector (image capture device 1) according to this embodiment, the semiconductor region 35 is provided adjacent to the pixel transistor 30a and the pixel transistor 30b. The semiconductor region 35 is provided adjacent to the semiconductor region 33a, which is the source region or drain region of the pixel transistor 30a, and the semiconductor region 33b, which is the source region or drain region of the pixel transistor 30b. The pixel transistor 30a also has a gate electrode 42a provided to sandwich a portion of the semiconductor layer 110. This allows the image capture device 1 to have a structure advantageous for miniaturization of pixels. The gate area of ​​the pixel transistor can be increased, making it possible to improve the characteristics of the pixel transistor. This makes it possible to realize a photodetector advantageous for miniaturization.

[0189] Next, a modified example of the present disclosure will be described. In the following, the same components as those in the above embodiment will be denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0190] (2-1. Modification 10) FIG. 23 is a diagram illustrating an example of the configuration of a pixel of an imaging device according to Modification 10. The transfer transistor TR may have a vertical gate (VG) structure. In the example shown in FIG. 23, the transfer transistors TRa and TRb each have a vertical gate (VG). In this modification, it is possible to improve the efficiency of charge transfer from the photoelectric conversion units 12a and 12b to the floating diffusions FDa and FDb.

[0191] (2-2. Modification 11) FIG. 24 is a diagram illustrating an example of the configuration of a pixel of an imaging device according to Modification 11. As shown in the example of FIG. 24, the gate electrode 46a of the transfer transistor TRa and the gate electrode 46b of the transfer transistor TRb may be provided adjacent to the trench 91 (or trench 93). In this case, the parasitic capacitance added to the transfer transistors TRa and TRb can be reduced. The characteristics of the transfer transistors TRa and TRb can be improved.

[0192] 25 is a diagram illustrating another example configuration of a pixel of an imaging device according to Modification 11. As shown in FIG. 25 , the imaging device 1 may have an insulating film 49a and an insulating film 49b. The insulating film 49a is provided in the semiconductor layer 110 between the floating diffusion FDa and the gate electrode 46a of the transfer transistor TRa. The insulating film 49a may be formed in a recessed portion of the gate electrode 46a, for example.

[0193] Furthermore, the insulating film 49b is provided in the semiconductor layer 110 between the floating diffusion FDb and the gate electrode 46b of the transfer transistor TRb. The insulating film 49b may be formed, for example, in a recessed portion of the gate electrode 46b. In the imaging device 1, the provision of the insulating films 49a and 49b makes it possible to reduce the parasitic capacitance added to the transfer transistors TRa and TRb, thereby improving the characteristics of the transfer transistors TRa and TRb.

[0194] In the imaging device 1, the insulating film 48 may be provided in a recessed portion at an end of the gate electrode 42a of the pixel transistor 30a. Also, for example, the insulating film 48 may be provided in a recessed portion at an end of the gate electrode 42b of the pixel transistor 30b.

[0195] (2-3. Modification 12) FIG. 26 is a diagram illustrating an example of the configuration of a pixel of an imaging device according to Modification 12. Each of the transfer transistors TRa and TRb may have a plurality of vertical gates (VG). In the example shown in FIG. 26, the transfer transistor TRa has gate electrodes 46a1 and 46a2. Furthermore, the transfer transistor TRb has gate electrodes 46b1 and 46b2. By configuring the imaging device 1 in this way, it is possible to improve the charge transfer efficiency.

[0196] 27 is a diagram illustrating another example configuration of a pixel of an imaging device according to Modification 12. In the example shown in Fig. 27, the gate electrodes 46a1 and 46a2 of the transfer transistor TRa are provided between the pixel transistor 30a and the floating diffusion FDa. The pixel transistor 30a, the gate electrode 46a1 (or the gate electrode 46a2), and the floating diffusion FDa are arranged to be aligned in the Y-axis direction in a plan view.

[0197] 27, the gate electrodes 46b1 and 46b2 of the transfer transistor TRb are provided between the pixel transistor 30b and the floating diffusion FDb. The pixel transistor 30b, the gate electrode 46b1 (or the gate electrode 46b2), and the floating diffusion FDb are arranged side by side in the Y-axis direction in a plan view. By configuring the imaging device 1 in this manner, it is expected that the charge transfer efficiency will be further improved.

[0198] In the pixel P of the imaging device 1, the pixel transistor 30a, the gate electrode 46a1 (or the gate electrode 46a2), and the floating diffusion FDa may be arranged side by side in the X-axis direction in a plan view. Also, the pixel transistor 30b, the gate electrode 46b1 (or the gate electrode 46b2), and the floating diffusion FDb may be arranged side by side in the X-axis direction in a plan view.

[0199] (2-4. Modification 13) Fig. 28 is a diagram for explaining a configuration example of a pixel of an imaging device according to Modification 13. The source region and the drain region of the pixel transistor 30a (or the pixel transistor 30b) may have different sizes, as in the example shown in Fig. 28 .

[0200] As an example, in the imaging device 1, of the semiconductor region 32a and the semiconductor region 33a of the pixel transistor 30a, the size of the semiconductor region 33a closer to the semiconductor region 35, which is a well contact region, is smaller than the size of the semiconductor region 32a. Also, in the imaging device 1, of the active region 81 in which the pixel transistor 30a is arranged, the size of the region on the semiconductor region 33a side closer to the semiconductor region 35 may be smaller than the size of the region on the semiconductor region 32a side.

[0201] Furthermore, for example, in the imaging device 1, of the semiconductor region 32b and the semiconductor region 33b of the pixel transistor 30b, the size of the semiconductor region 33b closer to the semiconductor region 35, which is a well contact region, is smaller than the size of the semiconductor region 32b. Of the active region 81 in which the pixel transistor 30b is arranged, the size of the region on the semiconductor region 33b side closer to the semiconductor region 35 may be smaller than the size of the region on the semiconductor region 32b side.

[0202] The pixel transistor 30 a and the pixel transistor 30 b may each have, for example, a trapezoidal shape. In the imaging device 1 according to this modification, it is possible to alleviate the electric field between the well contact region and the pixel transistor 30 a (or the pixel transistor 30 b). This makes it possible to prevent noise from being mixed into the pixel signal and to prevent degradation of image quality.

[0203] (2-5. Modification 14) Fig. 29 is a diagram illustrating an example of the configuration of a pixel of an imaging device according to Modification 14. As in the example shown in Fig. 29, the imaging device 1 may have a semiconductor region 37 that electrically connects a plurality of floating diffusions FD. Furthermore, the imaging device 1 may have the above-mentioned conductor region 36 that electrically connects the contact 55 and the semiconductor region 35.

[0204] (2-6. Modification 15) Fig. 30 is a diagram illustrating an example of the configuration of a pixel of an imaging device according to Modification 15. As shown in Fig. 30, the semiconductor region 35 may be provided between the semiconductor region 33a, which is the source region or drain region of the pixel transistor 30a, and the semiconductor region 33b, which is the source region or drain region of the pixel transistor 30b. In this case, it is possible to ensure the distance between the contact 55 and the channel regions of the pixel transistors 30a and 30b.

[0205] The imaging device 1 may have a separation portion 95a and a separation portion 95b, as in the example shown in Fig. 30 . The imaging device 1 may also be configured to have only one of the separation portion 95a and the separation portion 95b. For example, as in the example shown in Fig. 31 , in a pixel P of the imaging device 1, only the separation portion 95a may be provided, and the separation portion 95b may not be provided. The semiconductor region 35 may be provided between the semiconductor region 32a, which is the source region or drain region of the pixel transistor 30a, and the semiconductor region 32b, which is the source region or drain region of the pixel transistor 30b.

[0206] 30 or 31 , the semiconductor region 35 (or the active region 81) may have a first portion 61 and a second portion 62. The first portion 61 is provided adjacent to the pixel transistors 30 a and 30 b in the horizontal direction (X-axis direction) in a plan view. The first portion 61 is disposed, for example, adjacent to the gates of the pixel transistors 30 a and 30 b.

[0207] Furthermore, the second portion 62 is in contact with the first portion 61 in the vertical direction (Y-axis direction). The contact 55 is provided in the second portion 62. The contact 55 is provided on the second portion 62. The first portion 61 has, for example, an impurity concentration lower than the impurity concentration of the second portion 62.

[0208] As shown in FIG. 30 , the semiconductor region 35 is located between the isolation portions 95 a and 95 b, and the contact 55 is spaced apart from the channel regions of the pixel transistors 30 a and 30 b. This prevents noise from being mixed into the pixel signal. It is also possible to prevent a decrease in the accuracy of phase difference detection. It is also expected that a decrease in image quality can be suppressed. Furthermore, by separating (moving away) the contact 55 from the channel region, it is also possible to lower the impurity concentration near the portion where the channel region and the semiconductor region 35 are adjacent to each other. This enables a design that alleviates the generation of a strong electric field.

[0209] Furthermore, the first portion 61 has, for example, a lower impurity concentration than the impurity concentration of the second portion 62 connected to the contact 55. By lowering the impurity concentration of the first portion 61, it is possible to suppress the generation of a strong electric field between the first portion 61 and the channel region, which is expected to reduce noise mixed into pixel signals.

[0210] 3. Third Embodiment Next, a third embodiment of the present disclosure will be described. In the following, components similar to those in the above-described embodiment will be denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0211] 32 is a diagram illustrating a configuration example of an imaging device according to a third embodiment of the present disclosure. In the above-described embodiment, an example in which the semiconductor region 35 and the pixel transistor 30 are arranged in the same active region has been described, but the semiconductor region 35 and the pixel transistor 30 may be arranged in different active regions.

[0212] 32, the pixel transistor 30 is provided in an active region 81a, and the semiconductor region 35 is provided in an active region 81b. The transfer transistor TR and the floating diffusion FD are provided in an active region 82. The configuration of the pixel P of the imaging device 1 is not limited to the example shown in FIG. 32 and can be changed as appropriate.

[0213] 33A to 33E are diagrams illustrating another example configuration of the imaging device according to the third embodiment. For example, the transfer transistor TR may have a vertical gate (VG) structure as shown in FIG. 33A. Furthermore, the gate electrode 46 of the transfer transistor TR may be provided adjacent to the trench 91 (or trench 93) as shown in FIG. 33B. The imaging device 1 may also have an insulating film 49 as shown in FIG. 33C.

[0214] The transfer transistor TR may have a plurality of vertical gates (gate electrodes 46a and 46b in FIG. 33D) as shown in Fig. 33D. In addition, in the imaging device 1, an insulating film 49 may be provided in the recessed portions of the gate electrodes 46a and 46b as shown in the example of Fig. 33E.

[0215] 34 is a diagram illustrating a configuration example of an imaging device according to a third embodiment of the present disclosure. A pixel P of the imaging device 1 may have a plurality of photoelectric conversion units 12 (photoelectric conversion units 12a and 12b in the example shown in FIG. 34). It can also be said that a pixel having a photoelectric conversion unit 12a and a pixel having a photoelectric conversion unit 12b are provided. The semiconductor region 35 and the pixel transistor 30a (and also the pixel transistor 30b) may be arranged in different active regions.

[0216] One lens 21 (lens unit) is provided for a plurality of photoelectric conversion units 12, for example, two photoelectric conversion units 12 (photoelectric conversion unit 12a, photoelectric conversion unit 12b). Phase difference data can be obtained by using a first pixel signal based on the charge photoelectrically converted by the photoelectric conversion unit 12a and a second pixel signal based on the charge photoelectrically converted by the photoelectric conversion unit 12b. Phase difference AF can be performed by using the phase difference data.

[0217] 35A to 35E are diagrams illustrating another example configuration of the imaging device according to the third embodiment. For example, the transfer transistors TRa and TRb may each have a vertical gate (VG) structure, as shown in FIG. 35A. Furthermore, as shown in FIG. 35B, the gate electrode 46a of the transfer transistor TRa and the gate electrode 46b of the transfer transistor TRb may be provided adjacent to the trench 91 (or trench 93). Furthermore, the imaging device 1 may have an insulating film 49a and an insulating film 49b, as shown in FIG. 35C.

[0218] In the imaging device 1, the transfer transistors TRa and TRb may each have multiple vertical gates (VG). For example, as shown in FIG. 35D , the transfer transistor TRa may have gate electrodes 46a1 and 46a2. The transfer transistor TRb may have gate electrodes 46b1 and 46b2.

[0219] 35E, the imaging device 1 may have a semiconductor region 37 that electrically connects a plurality of floating diffusions FD. The imaging device 1 may also have the above-described conductor region 36 that electrically connects the contact 55 and the semiconductor region 35.

[0220] In the photodetector (image capture device 1) according to this embodiment, the pixel transistor 30 has a gate electrode 42 that is provided so as to sandwich a part of the semiconductor layer 110. The pixel transistor 30 can be configured as a Fin-type transistor. This allows the image capture device 1 to have a structure that is advantageous for miniaturization of pixels. The gate area of ​​the pixel transistor can be increased, making it possible to improve the characteristics of the pixel transistor. It is possible to realize a photodetector that is advantageous for miniaturization.

[0221] 4. Application Examples The imaging device 1 and the like can be applied to any type of electronic device equipped with an imaging function, for example, a camera system such as a digital still camera or video camera, a mobile phone with an imaging function, etc. Fig. 36 shows a schematic configuration of an electronic device 1000.

[0222] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, which are interconnected via a bus line 1008.

[0223] The lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1002.

[0224] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily stores the image data processed by the DSP circuit 1002 on a frame-by-frame basis.

[0225] The display unit 1004 is composed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records image data of moving images or still images captured by the imaging device 1 on a recording medium such as a semiconductor memory or a hard disk.

[0226] The operation unit 1006, in response to a user's operation, outputs operation signals for various functions of the electronic device 1000. The power supply unit 1007 supplies various types of power to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006 as needed.

[0227] 5. Application Examples (Application Examples to Mobile Bodies) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0228] FIG. 37 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0229] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 37, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0230] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0231] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0232] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0233] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0234] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0235] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0236] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0237] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0238] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 37, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0239] FIG. 38 is a diagram showing an example of the installation position of the imaging unit 12031.

[0240] In FIG. 38 , a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0241] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0242] 38 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0243] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0244] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0245] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0246] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0247] An example of a mobile object control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, for example, the image capturing device 1 or the like can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it becomes possible to obtain high-resolution captured images. It becomes possible to perform high-precision control using captured images in the mobile object control system.

[0248] (Application Example to Endoscopic Surgery System) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0249] FIG. 39 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0250] Figure 39 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0251] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0252] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0253] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0254] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0255] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0256] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies the endoscope 11100 with irradiation light when photographing the surgical site, etc.

[0257] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0258] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0259] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0260] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0261] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light in a narrower band than the light irradiated during normal observation (i.e., white light) to capture high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, in what is known as narrow band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or may involve locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissues with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0262] FIG. 40 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0263] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0264] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0265] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (so-called single-chip type) or multiple (so-called multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0266] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0267] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0268] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0269] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0270] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0271] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0272] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0273] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0274] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0275] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0276] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0277] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0278] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0279] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the above-described configurations, the technology according to the present disclosure can be suitably applied to, for example, the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to provide a high-definition endoscope 11100.

[0280] Although the present disclosure has been described above by way of embodiments, modifications, application examples, and applied examples, the present technology is not limited to the above-described embodiments, etc., and various modifications are possible. For example, although the modifications described above have been described as modifications of the above-described embodiments, the configurations of the modifications can be combined as appropriate.

[0281] In the above embodiments, an imaging device has been described as an example. However, the photodetector of the present disclosure may be, for example, a device that receives incident light and converts the light into an electric charge. The output signal may be a signal of image information or a signal of ranging information. The photodetector (imaging device) may be applied to an image sensor, a ranging sensor, etc. Note that the present disclosure is not limited to a back-illuminated image sensor, but may also be applied to a front-illuminated image sensor.

[0282] The photodetector according to the present disclosure may also be applied as a distance measuring sensor capable of measuring distances using a time-of-flight (TOF) method. The photodetector (image capture device) may also be applied as a sensor capable of detecting events, such as an event-driven sensor (also known as an event vision sensor (EVS), an event-driven sensor (EDS), or a dynamic vision sensor (DVS)).

[0283] A photodetector according to one embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels. The first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the transistor. The transistor has a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer. This allows the photodetector to have a structure advantageous for miniaturization of pixels. This makes it possible to realize a photodetector advantageous for miniaturization.

[0284] A photodetector according to an embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer, and a trench provided in the semiconductor layer between adjacent pixels. The first pixel includes a transistor having a gate electrode provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region. The first semiconductor region is provided adjacent to the transistor. At least a portion of the gate electrode of the transistor is provided within the semiconductor layer. This allows the photodetector to have a structure advantageous for miniaturization of pixels. The gate area of ​​the transistor can be increased, thereby improving the characteristics of the transistor. This makes it possible to realize a photodetector advantageous for miniaturization.

[0285] Note that the effects described in this specification are merely examples and are not limited to those described above, and other effects may be present. The present disclosure may also have the following configurations. (1) A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent pixels, wherein the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, the first semiconductor region being provided adjacent to the transistor, and the transistor having a gate electrode provided on the first surface side of the semiconductor layer so as to sandwich a portion of the semiconductor layer therebetween. (2) The photodetector according to (1), wherein a portion of the gate electrode of the transistor is provided within the semiconductor layer so as to sandwich a portion of the semiconductor layer that is a channel region of the transistor. (3) The photodetector according to (1) or (2), wherein the transistor is a Fin-type transistor. (4) The photodetector according to any one of (1) to (3), wherein the gate electrode of the transistor has a plurality of first portions provided in the semiconductor layer so as to sandwich a part of the semiconductor layer. (5) The photodetector according to (4), further comprising an isolation portion provided in the semiconductor layer around the plurality of first portions, wherein bottoms of the first portions are located higher than bottoms of the isolation portions. (6) The photodetector according to any one of (1) to (5), wherein the transistor has a second semiconductor region of a second conductivity type provided in the semiconductor layer, wherein the second semiconductor region is a source region or a drain region, and the first semiconductor region is provided adjacent to the second semiconductor region.(7) The photodetector according to (6), wherein the transistor has a third semiconductor region of the second conductivity type provided in the semiconductor layer, the second semiconductor region being one of the source region and the drain region, the third semiconductor region being the other of the source region and the drain region, and the size of the second semiconductor region being smaller than the size of the third semiconductor region. (8) The photodetector according to (7), wherein the first semiconductor region is a p-type semiconductor region, and the second semiconductor region and the third semiconductor region are each an n-type semiconductor region. (9) The photodetector according to any one of (1) to (8), wherein the transistor has a gate electrode and a gate insulating film provided on a first region of the semiconductor layer, and the first semiconductor region is provided in contact with the first region so as to be adjacent to at least one of the gate electrode and the gate insulating film of the transistor. (10) The photodetector according to any one of (1) to (9), further comprising a first well of the first conductivity type provided in the semiconductor layer, the first semiconductor region being provided in the first well, and the first contact being electrically connected to the first well via the first semiconductor region. (11) The photodetector according to any one of (1) to (10), wherein the first pixel comprises: a floating diffusion; and a transfer transistor provided on a first surface side of the semiconductor layer and capable of transferring charges converted by the photoelectric conversion element to the floating diffusion. (12) The photodetector according to (11), wherein the transfer transistor has a gate electrode provided in the semiconductor layer to reach the photoelectric conversion element. (13) The photodetector according to (12), wherein the gate electrode of the transistor has a plurality of first portions provided in the semiconductor layer to sandwich a portion of the semiconductor layer, and bottoms of the first portions are located higher than a bottom of the gate electrode of the transfer transistor.(14) The photodetector according to (13), further comprising an isolation portion provided in the semiconductor layer between the first portion and the gate electrode of the transfer transistor, wherein the gate electrode of the transfer transistor is adjacent to the isolation portion. (15) The photodetector according to any one of (12) to (14), further comprising a first insulating film provided in a recessed portion of the gate electrode of the transfer transistor between the floating diffusion and the gate electrode of the transfer transistor. (16) The photodetector according to any one of (12) to (15), further comprising a second insulating film provided in a recessed portion at an end of the gate electrode of the transistor. (17) The photodetector according to any one of (1) to (16), further comprising a conductor region in contact with a portion of the first semiconductor region and provided inside the trench, wherein the first contact is provided on the conductor region and electrically connected to the first semiconductor region via the conductor region. (18) The photodetector according to (17), wherein the conductor region is provided within the semiconductor layer. (19) The photodetector according to any one of (1) to (18), wherein the plurality of pixels includes a second pixel adjacent to the first pixel, and the first pixel and the second pixel each have the photoelectric conversion element, a floating diffusion, the transistor, and the first semiconductor region. (20) The photodetector according to (19), further comprising: a conductor region electrically connecting the first semiconductor region of the first pixel to the first semiconductor region of the second pixel. (21) The photodetector according to (19) or (20), further comprising: a fourth semiconductor region electrically connecting the floating diffusion of the first pixel to the floating diffusion of the second pixel; and a second contact electrically connected to the fourth semiconductor region.(22) The photodetector according to any one of (1) to (21), further comprising a readout circuit including the transistor and capable of outputting a signal based on charges photoelectrically converted by the photoelectric conversion element, wherein the transistor is an amplification transistor, a selection transistor, a reset transistor, a switching transistor, or a dummy transistor. (23) The photodetector according to any one of (1) to (22), further comprising a lens provided on a second surface side opposite to the first surface of the semiconductor layer, wherein the photoelectric conversion element photoelectrically converts light transmitted through the lens. (24) A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent pixels, wherein the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, the first semiconductor region is provided adjacent to the first transistor and the second transistor, and the first transistor has a gate electrode provided on the first surface side of the semiconductor layer to sandwich a portion of the semiconductor layer. (25) The photodetector according to (24), wherein the gate electrode has a plurality of first portions provided in the semiconductor layer to sandwich the portion of the semiconductor layer. (26) The photodetector according to (25), further comprising an isolation portion provided around the plurality of first portions in the semiconductor layer, wherein bottoms of the first portions are located higher than bottoms of the isolation portions. (27) The photodetector according to any one of (24) to (26), wherein the first pixel has: a first isolation portion provided between the first transistor and the second transistor, a first floating diffusion and a second floating diffusion, and a second isolation portion provided between the first floating diffusion and the second floating diffusion.(28) The photodetector according to (27), wherein the first semiconductor region is provided between the first isolation portion and the second isolation portion. (29) An electronic device comprising: an optical system; and a photodetector that receives light that has passed through the optical system, wherein the photodetector has: a semiconductor layer; a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent ones of the pixels, wherein the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, wherein the first semiconductor region is provided adjacent to the transistor, and the transistor has a gate electrode provided on the first surface side of the semiconductor layer to sandwich a part of the semiconductor layer therebetween. (30) An electronic device comprising: an optical system; and a photodetector that receives light transmitted through the optical system, wherein the photodetector has: a semiconductor layer; a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between the plurality of adjacent pixels, wherein the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, wherein the first semiconductor region is provided adjacent to the first transistor and the second transistor, and the first transistor has a gate electrode provided on the first surface side of the semiconductor layer to sandwich a part of the semiconductor layer.(31) A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent ones of the plurality of pixels, wherein the first pixel includes a transistor having a gate electrode provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, the first semiconductor region is provided adjacent to the transistor, and at least a portion of the gate electrode of the transistor is provided within the semiconductor layer. (32) The photodetector according to (31), wherein the gate electrode of the transistor is a trench gate electrode. (33) A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between the plurality of adjacent pixels, wherein the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, the first semiconductor region being provided adjacent to the transistor, and the transistor having a trench gate electrode. (34) A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent pixels, wherein the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, the first semiconductor region is provided adjacent to the transistor, and the transistor has a gate electrode including a plurality of first portions provided in the semiconductor layer. (35) The photodetector according to (34), wherein the first portion of the transistor is provided around a portion of the semiconductor layer that is a channel region of the transistor.(36) The photodetector according to (34) or (35), further comprising a separation section provided around the plurality of first portions in the semiconductor layer, wherein a bottom of the first portion is located above a bottom of the separation section.

[0286] This application claims priority based on Japanese Patent Application No. 2023-127886, filed on August 4, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0287] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent ones of the pixels, wherein the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, the first semiconductor region is provided adjacent to the transistor, and the transistor has a gate electrode provided on the first surface side of the semiconductor layer to sandwich a portion of the semiconductor layer.

2. The photodetector according to claim 1, wherein a portion of the gate electrode of the transistor is provided within the semiconductor layer so as to sandwich a portion of the semiconductor layer that is a channel region of the transistor.

3. The photodetector according to claim 1, wherein the transistor is a Fin-type transistor.

4. The photodetector according to claim 1, wherein the gate electrode of the transistor has a plurality of first portions provided in the semiconductor layer so as to sandwich a part of the semiconductor layer.

5. The photodetector according to claim 4, further comprising a separation portion provided around the plurality of first portions in the semiconductor layer, wherein a bottom of the first portion is located above a bottom of the separation portion.

6. The photodetector according to claim 1, wherein the transistor has a second semiconductor region of a second conductivity type provided in the semiconductor layer, the second semiconductor region being a source region or a drain region, and the first semiconductor region being provided adjacent to the second semiconductor region.

7. The photodetector device according to claim 6, wherein the transistor has a third semiconductor region of the second conductivity type provided in the semiconductor layer, the second semiconductor region being one of the source region and the drain region, the third semiconductor region being the other of the source region and the drain region, and the size of the second semiconductor region being smaller than the size of the third semiconductor region.

8. The photodetector according to claim 7, wherein the first semiconductor region is a p-type semiconductor region, and the second semiconductor region and the third semiconductor region are each an n-type semiconductor region.

9. The photodetector according to claim 1, wherein the transistor has a gate electrode and a gate insulating film provided on a first region of the semiconductor layer, and the first semiconductor region is provided in contact with the first region so as to be adjacent to at least one of the gate electrode and the gate insulating film of the transistor.

10. The photodetection device of claim 1, further comprising a first well of the first conductivity type provided in the semiconductor layer, the first semiconductor region being provided in the first well, and the first contact being electrically connected to the first well via the first semiconductor region.

11. The photodetection device according to claim 1, wherein the first pixel has: a floating diffusion; and a transfer transistor provided on the first surface side of the semiconductor layer and capable of transferring electric charges converted by the photoelectric conversion element to the floating diffusion.

12. The photodetector according to claim 11, wherein the transfer transistor has a gate electrode provided in the semiconductor layer so as to reach the photoelectric conversion element.

13. The photodetector device according to claim 12, wherein the gate electrode of the transistor has a plurality of first portions provided in the semiconductor layer so as to sandwich a part of the semiconductor layer, and the bottoms of the first portions are positioned higher than the bottom of the gate electrode of the transfer transistor.

14. The photodetector according to claim 13, further comprising an isolation portion provided in the semiconductor layer between the first portion and the gate electrode of the transfer transistor, the gate electrode of the transfer transistor being adjacent to the isolation portion.

15. The photodetector according to claim 12, further comprising a first insulating film provided in a recessed portion of the gate electrode of the transfer transistor between the floating diffusion and the gate electrode of the transfer transistor.

16. The photodetector according to claim 12, further comprising a second insulating film provided in a recessed portion at an end of the gate electrode of the transistor.

17. The photodetector device of claim 1, further comprising a conductor region in contact with a portion of the first semiconductor region and provided within the trench, the first contact being provided on the conductor region and electrically connected to the first semiconductor region via the conductor region.

18. The photodetector device according to claim 17, wherein the conductive region is provided within the semiconductor layer.

19. The photodetection device according to claim 1, wherein the plurality of pixels includes a second pixel adjacent to the first pixel, and the first pixel and the second pixel each have the photoelectric conversion element, a floating diffusion, the transistor, and the first semiconductor region.

20. The photodetector according to claim 19, further comprising a conductor region that electrically connects the first semiconductor region of the first pixel and the first semiconductor region of the second pixel.

21. The photodetection device of claim 19, further comprising: a fourth semiconductor region electrically connecting the floating diffusion of the first pixel and the floating diffusion of the second pixel; and a second contact electrically connected to the fourth semiconductor region.

22. The photodetection device according to claim 1, further comprising a readout circuit including the transistor and capable of outputting a signal based on the charge photoelectrically converted by the photoelectric conversion element, the transistor being an amplification transistor, a selection transistor, a reset transistor, a switching transistor, or a dummy transistor.

23. The photodetector according to claim 1, further comprising a lens provided on a second surface side opposite to the first surface of the semiconductor layer, wherein the photoelectric conversion element photoelectrically converts light transmitted through the lens.

24. A photodetector comprising: a semiconductor layer; a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent pixels, wherein the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, the first semiconductor region is provided adjacent to the first transistor and the second transistor, and the first transistor has a gate electrode provided on the first surface side of the semiconductor layer to sandwich a portion of the semiconductor layer.

25. The photodetector according to claim 24, wherein the gate electrode has a plurality of first portions provided in the semiconductor layer so as to sandwich a part of the semiconductor layer therebetween.

26. The photodetector according to claim 25, further comprising a separator provided in the semiconductor layer around the plurality of first portions, wherein a bottom of the first portion is located above a bottom of the separator.

27. The photodetection device of claim 24, wherein the first pixel has: a first isolation portion provided between the first transistor and the second transistor; a first floating diffusion and a second floating diffusion; and a second isolation portion provided between the first floating diffusion and the second floating diffusion.

28. The photodetector according to claim 27, wherein the first semiconductor region is provided between the first isolation portion and the second isolation portion.

29. An electronic device comprising: an optical system; and a photodetector that receives light that has passed through the optical system, wherein the photodetector has: a semiconductor layer; a plurality of pixels including a first pixel having a photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between adjacent ones of the pixels, wherein the first pixel includes a transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, wherein the first semiconductor region is provided adjacent to the transistor, and the transistor has a gate electrode provided on the first surface side of the semiconductor layer to sandwich a portion of the semiconductor layer.

30. An electronic device comprising: an optical system; and a photodetector that receives light transmitted through the optical system, wherein the photodetector has: a semiconductor layer; a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element provided in the semiconductor layer; and a trench provided in the semiconductor layer between the plurality of adjacent pixels, wherein the first pixel includes a first transistor and a second transistor provided on a first surface side of the semiconductor layer, a first semiconductor region of a first conductivity type provided on the first surface side of the semiconductor layer, and a first contact electrically connected to the first semiconductor region, wherein the first semiconductor region is provided adjacent to the first transistor and the second transistor, and the first transistor has a gate electrode provided on the first surface side of the semiconductor layer to sandwich a portion of the semiconductor layer.

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