Stream processor, operation method, chip, and electronic device

Abstract

A stream processor, an operation method, a chip, and an electronic device. The stream processor comprises at least two calculation units and a main control unit. Each calculation unit is configured to execute one operation among a multiplication operation, an addition operation, a table look-up operation, and data transfer; and the main control unit is connected to each calculation unit, and is configured to allocate an operation instruction to the calculation unit, so that the calculation unit executes a corresponding operation of the calculation unit in response to the operation instruction.

Description

Stream processor, computing method, chip and electronic device Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a stream processor, a computing method, a chip, and an electronic device. Background Art

[0002] Because different network models perform different computational tasks, it's difficult to use a single computational module to handle multiple tasks. For example, the softmax (normalized exponential function) computation task differs significantly from the convolution or matrix multiplication computation tasks, making it difficult to directly compute the softmax using the convolution or matrix multiplication modules.

[0003] Currently, a dedicated computing module is typically set up for each network model, or calculations are performed using a GPGPU (General-Purpose Graphics Processing Unit) with stronger general computing capabilities. However, dedicated computing modules are designed only for a certain type of network and are often unable to compute other types of networks, making them inflexible. Furthermore, when supporting multiple network models, the computing modules corresponding to each network model need to be merged and optimized, resulting in a significant increase in area. While GPGPUs have extremely strong general computing capabilities, they require a large area.

[0004] Summary of the Invention

[0005] The present application provides a stream processor, a computing method, a chip, and an electronic device to alleviate the problems of low versatility of existing dedicated computing modules and the large area occupied by GPGPUs.

[0006] In a first aspect, the present application provides a stream processor comprising: at least two computing units and a main control unit, each of the computing units being configured to perform an operation selected from the group consisting of multiplication, addition, table lookup, and data transfer; the main control unit being connected to each of the computing units and being configured to assign an operation instruction to the computing unit so that the computing unit performs the corresponding operation of the computing unit in response to the operation instruction.

[0007] In the embodiments of the present application, different computing units can cooperate with each other to implement different computing logics, thereby processing a variety of different computing tasks. Therefore, the embodiments of the present application can support computing tasks of different network models through a single stream processor, thereby having higher versatility compared to dedicated computing modules. At the same time, because a single stream processor can support computing tasks of different network models, there is no need to set up multiple stream processors, which reduces the occupied area compared to GPGPU.

[0008] Since each computing unit is directly controlled by the main control unit in the stream processor, the instructions are directly distributed to the computing unit that performs a specific operation through the main control unit. Therefore, compared with GPGPU, the process of distributing operation instructions is reduced, and there is no need to set up a hardware unit for distributing operation instructions in GPGPU, thereby reducing the occupied area compared with GPGPU.

[0009] In combination with the technical solution provided in the first aspect above, in some possible implementations, the number of at least some types of computing units among the at least two types of computing units is multiple; the instruction receiving ends of multiple computing units of the same type are connected to each other and to the main control unit.

[0010] In the embodiments of the present application, because the instruction receiving terminals of multiple computing units of the same type are interconnected and connected to the main control unit, multiple computing units of the same type can synchronously perform the same arithmetic operation, thereby enabling multiple sets of data to be processed synchronously by multiple computing units of the same type, thereby improving data processing efficiency. Furthermore, the main control unit only needs to send an operation instruction once to control multiple computing units of the same type to synchronously process multiple sets of data. This eliminates the need to issue operation instructions multiple times, reducing the number of instruction issuances and improving data processing efficiency.

[0011] In combination with the technical solution provided in the first aspect above, in some possible implementations, the stream processor further includes: at least one data storage area; and the multiple computing units of the same type are respectively connected to different data storage areas.

[0012] In the embodiment of the present application, since multiple computing units of the same type are connected to different data storage areas respectively, multiple computing units of the same type will not repeatedly obtain data from the same data storage area, that is, they will not repeatedly obtain the same set of data, thereby reducing the probability of the same set of data being processed repeatedly and reducing the waste of computing resources.

[0013] In combination with the technical solution provided in the first aspect above, in some possible implementations, the stream processor further includes: a statistical operation unit, which is connected to the main control unit and to each of the data storage areas; the statistical operation unit is configured to perform maximum value processing or summation processing on the target data in the data storage area in response to the operation instructions assigned by the main control unit.

[0014] In the embodiment of the present application, since the statistical operation unit is connected to each data storage area, the statistical operation unit can obtain target data from each data storage area and then perform maximum value processing or summation processing on the target data. In this way, the provision of the statistical operation unit eliminates the need to use a second type of calculation unit that performs addition operations to perform multiple summations or to provide an additional comparator to obtain the maximum value, thereby improving data processing efficiency.

[0015] In combination with the technical solution provided in the first aspect above, in some possible implementations, the number of different types of computing units is the same.

[0016] In the embodiment of the present application, since the number of different types of computing units is the same, each data storage area is connected to each type of computing unit, so that all computing units connected to each data storage area can process the same computing task, and thus multiple groups of data can be processed synchronously by all computing units connected to each data storage area, and the processing logic executed by the computing unit corresponding to each data storage is the same, thereby improving the processing efficiency of multiple groups of data that require the same computing logic.

[0017] In combination with the technical solution provided in the first aspect above, in some possible implementations, the at least two computing units include a first computing unit, a second computing unit, a third computing unit, and a fourth computing unit; the first computing unit is a computing unit that performs multiplication operations, the second computing unit is a computing unit that performs addition operations, the third computing unit is a computing unit that performs table lookup operations, and the fourth computing unit is a computing unit that performs transfer operations.

[0018] In the embodiment of the present application, through the mutual cooperation of the first computing unit, the second computing unit, the third computing unit and the fourth computing unit, the processing logic of more computing tasks can be implemented, thereby increasing the application scenarios of this solution.

[0019] In combination with the technical solution provided in the first aspect above, in some possible implementations, the stream processor further includes: a table storage unit configured to store a function relationship table; the table storage unit is connected to each third computing unit, and the third computing unit is configured to perform a table lookup operation on the function relationship table in the table storage unit in response to an operation instruction assigned by the main control unit.

[0020] In an embodiment of the present application, the function relationship table is stored in a table storage unit, so that the third computing unit can perform a table lookup operation on the function relationship table in the table storage unit, which can reduce the amount of calculation of complex functions and improve the data processing efficiency of this solution.

[0021] In combination with the technical solution provided in the first aspect above, in some possible implementations, the stream processor further includes: an instruction storage unit, which is connected to the main control unit, and the instruction storage unit is configured to store operation instructions; the main control unit is also configured to obtain the operation instructions from the instruction storage unit.

[0022] In the embodiment of the present application, an instruction storage unit is provided to store operation instructions, thereby eliminating the need to obtain operation instructions from the outside world, enabling the present solution to operate independently and improving the scope of application of the present solution.

[0023] In a second aspect, the present application provides a computing method, which is applied to the stream processor described in the first aspect above and / or in combination with any embodiment of the first aspect above, and the computing method includes: allocating operation instructions to the computing unit through the main control unit; and executing the corresponding computing operation of the computing unit in response to the operation instruction through the computing unit.

[0024] In a third aspect, the present application provides a chip comprising the stream processor described in the first aspect above and / or in combination with any embodiment of the first aspect above.

[0025] In a fourth aspect, the present application provides an electronic device comprising the chip described in the third aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0027] FIG1 is a structural block diagram of a first stream processor shown in an embodiment of the present application;

[0028] FIG2 is a block diagram of a structure of an adder shown in an embodiment of the present application;

[0029] FIG3 is a structural block diagram of a second stream processor shown in an embodiment of the present application;

[0030] FIG4 is a structural block diagram of a third stream processor shown in an embodiment of the present application;

[0031] FIG5 is a structural block diagram of a fourth stream processor shown in an embodiment of the present application;

[0032] FIG6 is a structural block diagram of a fifth stream processor according to an embodiment of the present application;

[0033] FIG7 is a block diagram of a sixth stream processor according to an embodiment of the present application;

[0034] FIG8 is a structural block diagram of a seventh stream processor according to an embodiment of the present application;

[0035] FIG9 is a structural block diagram of an eighth stream processor according to an embodiment of the present application;

[0036] FIG10 is a block diagram of a ninth stream processor according to an embodiment of the present application;

[0037] FIG11 is a flow chart of a calculation method according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The terms "first", "second", "third", etc. are only used to distinguish and describe, and do not indicate the order of arrangement, nor can they be understood as indicating or implying relative importance.

[0039] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0040] Please refer to Figure 1, which is a structural block diagram of a stream processor shown in an embodiment of the present application. The stream processor includes at least two computing units and a main control unit, and the main control unit is connected to each computing unit.

[0041] Each of the at least two types of computing units is configured to perform one of multiplication, addition, table lookup, and data transfer operations.

[0042] Optionally, the at least two computing units mentioned above may include at least two computing units among a first computing unit, a second computing unit, a third computing unit and a fourth computing unit.

[0043] The first type of computing unit is a computing unit that performs a multiplication operation. For example, the first type of computing unit may be a computing unit such as a multiplier that performs a multiplication operation.

[0044] The second type of computing unit is a computing unit that performs addition operations. For example, the second type of computing unit may be an adder or other computing unit that performs addition operations.

[0045] It should be noted that, for subtraction in the conventional sense, it is essentially an addition operation performed after negating one of the numbers, that is, subtraction is essentially also an addition operation, which can be implemented by the second type of computing unit. For example, 3-1 can be regarded as the addition between 3 and -1. Therefore, by arranging the corresponding negation circuit in the second type of computing unit, the second type of computing unit can be utilized to implement subtraction. Exemplarily, as shown in Figure 2, one of the inputs of the adder (In_1 shown in Figure 2) can be connected by a multiplexer, one of the inputs of the multiplexer is the original data, and the other input is the negation circuit, and the input of the negation circuit is the original data. In this way, when it is necessary to do subtraction, the negation circuit can be enabled, but when it is necessary to do addition, the original data can be enabled.

[0046] The third type of computing unit performs a table lookup operation, where a table lookup is performed based on an input independent variable and the corresponding dependent variable is searched from a preset function relationship table. For example, if a function relationship table records the correspondence between A and B, the third type of computing unit can find B based on A by searching the preset function relationship table.

[0047] The fourth type of computing unit is a computing unit that performs a transfer operation, wherein the transfer operation is an operation to move the storage location of data in the data storage area, for example, an operation to transfer data A from a first location in the storage area to a second location for storage.

[0048] The main control unit is configured to distribute an operation instruction to the computing unit, so that the computing unit performs a corresponding calculation operation of the computing unit in response to the operation instruction.

[0049] The main control unit may be any circuit that can distribute operation instructions to the computing unit, and the specific circuit structure of the main control unit is not limited here.

[0050] Among them, different computing units perform computing operations corresponding to themselves, for example, the first computing unit performs multiplication operations, the second computing unit performs addition operations, the third computing unit performs table lookup operations, and the fourth computing unit performs transfer operations.

[0051] The connection manners of the at least two computing units and the main control unit may include but are not limited to the following implementations.

[0052] In the first embodiment, each computing unit is connected to the main control unit. For ease of understanding, please refer to Figure 3.

[0053] Each operation instruction sent by the main control unit controls only one computing unit to perform the corresponding computing operation of the computing unit.

[0054] In this way, the main control unit can independently control the execution of each computing unit, thereby being able to control the computing units more freely, avoiding the situation where the computing units perform meaningless calculations, and improving resource utilization within the stream processor.

[0055] In a second embodiment, at least some of the at least two types of computing units are multiple, and the instruction receiving terminals of the multiple computing units of the same type are interconnected and connected to the main control unit. Because the instruction receiving terminals of the multiple computing units of the same type are interconnected and connected to the main control unit, the multiple computing units of the same type can simultaneously execute the same computing operation, thereby enabling the simultaneous processing of multiple sets of data by the multiple computing units of the same type, thereby improving data processing efficiency.

[0056] For ease of understanding, please refer to Figure 4. Taking at least two computing units, including two first-type computing units and one second-type computing unit, as an example, the instruction receiving terminals of the two first-type computing units are interconnected and connected to the main control unit, so that the main control unit can simultaneously control the two first-type computing units to synchronously perform corresponding multiplication operations through a single instruction. In this way, the main control unit only needs to send an operation instruction once to control multiple computing units of the same type to synchronously perform the same operation. Therefore, when multiple sets of data are synchronously processed by multiple computing units of the same type, there is no need to issue operation instructions multiple times, reducing the number of instruction issuances and improving data processing efficiency.

[0057] It should be understood that the above examples are only for ease of understanding and are not intended to limit the present application.

[0058] In a third embodiment, at least some of the at least two types of computing units are multiple, wherein the instruction receiving terminals of the multiple computing units of the same type are interconnected and connected to the main control unit. The other types of computing units are each connected to the main control unit.

[0059] The specified type can be one type or multiple types, and there is no restriction on the specific type of the specified type.

[0060] For ease of understanding, refer to FIG5 . Taking at least two types of computing units, including two first-type computing units and three second-type computing units, as an example, the instruction receiving terminals of the two first-type computing units are connected to each other and to the main control unit, so that the main control unit can simultaneously control the two first-type computing units to synchronously perform corresponding multiplication operations through a single instruction. The three second-type computing units are separately connected to the main control unit.

[0061] It should be understood that the above examples are only for ease of understanding and are not intended to limit the present application.

[0062] In a fourth embodiment, the computing units are divided into a plurality of computing unit groups, wherein each computing unit group includes at least two types of computing units. The connection method between each computing unit group and the main control unit is the same as that of the second embodiment.

[0063] The instruction receiving ends of the same type of computing units in different computing unit groups are not connected to each other.

[0064] Optionally, the types and quantities of computing units included in each group of computing units may be the same or different.

[0065] For ease of understanding, please refer to FIG. 6 , which takes an example in which a total of three computing unit groups are included, and each computing unit group includes two first-type computing units and one second-type computing unit.

[0066] For each computing unit group (the portion enclosed by the dotted line in Figure 6 ), the instruction receiving terminals of the two first-type computing units are connected to each other and to the main control unit. The instruction receiving terminals of the first-type computing units in different computing unit groups are not connected to each other. One second-type computing unit is connected to the main control unit.

[0067] It should be understood that the above examples are only for ease of understanding and are not intended to limit the present application.

[0068] In one embodiment, the stream processor further includes at least one data storage area, wherein at least some of the at least two types of computing units are multiple, and the instruction receiving terminals of the multiple computing units of the same type are interconnected, and the multiple computing units of the same type are respectively connected to different data storage areas. Because the computing units of the same type are respectively connected to different data storage areas, the computing units of the same type do not repeatedly obtain the same set of data, thereby reducing the occurrence of the same set of data being processed multiple times.

[0069] The data storage areas may be different areas within the same memory, or each data storage area may be a memory. The memory herein may be a mobile hard disk, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk, among other media capable of storing data.

[0070] Optionally, the result calculated by each computing unit is stored in a data storage area connected to itself.

[0071] For ease of understanding, please refer to Figure 7, taking at least two computing units including a first computing unit A, a first computing unit B, a second computing unit A, a data storage area A, and a data storage area B as an example, the instruction receiving ends of the first computing unit A and the first computing unit B are connected to each other and to the main control unit, and the first computing unit A is connected to the data storage area A, and the first computing unit B is connected to the data storage area B.

[0072] The second type of computing unit A can be connected to either the data storage area A or the data storage area B. The examples here are only for ease of understanding and should not be construed as limiting the present application.

[0073] Optionally, the data storage area may include a scalar storage area and a vector storage area. The specific implementation of connecting the computing unit to the data storage area is that the computing unit is connected to the scalar storage area and the vector storage area included in the data storage area respectively.

[0074] The scalar storage area and the vector storage area may be different areas in the same memory, or the scalar storage area and the vector storage area may be independent memories. The specific implementation and principle of the memory here are consistent with those of the aforementioned memory and will not be repeated here for the sake of brevity.

[0075] Optionally, the number of different types of computing units may be different. In this case, part of the data storage area may be connected to each type of computing unit, and the remaining part of the data storage area may only be connected to some types of computing units.

[0076] For example, referring to FIG8 , when the at least two types of computing units include a first computing unit and a second computing unit, the stream processor may include n first computing units and m second computing units, where n and m are positive integers and n>m. Accordingly, the stream processor also includes n data storage areas.

[0077] In this case, each data storage area is connected to a first-type computing unit. Each of the m data storage areas is also connected to a second-type computing unit. Furthermore, the instruction receiving terminals of the n first-type computing units are interconnected, and the instruction receiving terminals of the m second-type computing units are interconnected. This example is provided for ease of understanding only and should not be construed as limiting the present application.

[0078] Optionally, the number of different types of computing units may be the same.

[0079] Since the number of different types of computing units is the same, each data storage area is connected to each type of computing unit, so that all computing units connected to each data storage area can process the same computing tasks, and multiple groups of data can be processed synchronously by all computing units connected to each data storage area, and the processing logic executed by the computing units corresponding to each data storage is the same, thereby improving the processing efficiency of multiple groups of data that require the same computing logic.

[0080] For example, referring to FIG9 , when the at least two types of computing units include a first computing unit and a second computing unit, the stream processor may include n first computing units and n second computing units, where n is a positive integer. Accordingly, the stream processor also includes n data storage areas.

[0081] In this case, each data storage area is connected to one first-type computing unit and one second-type computing unit, respectively. Furthermore, the instruction receiving terminals of n first-type computing units are interconnected, and the instruction receiving terminals of n second-type computing units are interconnected. This example is provided for ease of understanding only and should not be construed as limiting this application.

[0082] Optionally, when the at least two computing units include a first computing unit, a second computing unit, a third computing unit and a fourth computing unit, each data storage area is connected to a first computing unit, a second computing unit, a third computing unit and a fourth computing unit respectively.

[0083] Because the processing logic of most computing tasks can be implemented through multiplication, addition, table lookup, and transfer operations, a single computing task can be completed using four computing units connected to the same data storage area. By connecting four computing units to multiple data storage areas, multiple sets of data to be processed for the same computing task can be processed simultaneously, improving data processing efficiency.

[0084] Optionally, in the third embodiment, the stream processor may further include a statistical operation unit. The statistical operation unit is connected to the main control unit and to each data storage area.

[0085] The statistical operation unit is configured to perform maximum value processing or summation processing on the target data in the data storage area in response to the operation instruction assigned by the main control unit.

[0086] Because the statistical operation unit is connected to each data storage area, it can obtain target data from each data storage area and then perform maximum value calculation or summation on the target data. This eliminates the need to use the second type of calculation unit that performs addition operations to calculate the maximum value multiple times, thereby improving data processing efficiency.

[0087] The target data may be target data pre-stored in a data storage area. The statistical operation unit directly obtains the corresponding target data from each data storage area, and then performs maximum value processing or cumulative summation processing based on all the obtained target data.

[0088] Alternatively, the target data may be a calculation result obtained and stored in the data storage area after the calculation module performs the corresponding calculation operation. The statistical operation unit obtains the corresponding calculation result from each data storage area and then performs a maximum value processing or cumulative sum processing based on all the obtained calculation results.

[0089] The processing results obtained by the statistical operation unit through the maximum value processing or cumulative summation processing can also be stored in each data storage area, or the processing results can be directly output to a third-party device.

[0090] The statistical operation unit may be any circuit capable of performing maximum value calculation or cumulative summation processing, and the specific circuit structure of the statistical operation unit is not limited here.

[0091] In one implementation, the stream processor further includes a table storage unit, which is configured to store a function relationship table.

[0092] The table storage unit is connected to each third type computing unit, and the third type computing unit is configured to perform a table lookup operation on the function relationship table in the table storage unit in response to an operation instruction assigned by the main control unit.

[0093] Optionally, the function relationship table can be the coordinate values ​​of multiple points within a certain range of the independent variable of any complex function (each coordinate value includes an independent variable and a dependent variable corresponding to the independent variable). When the third computing unit performs a table lookup operation, the third computing unit obtains a target independent variable or a target dependent variable, and then searches the function relationship table for the dependent variable corresponding to the target independent variable, or the independent variable corresponding to the target dependent variable.

[0094] Optionally, the table storage unit includes a software-configurable table and a function relationship table pre-cured in the table storage unit.

[0095] By setting a software-configurable table, the corresponding function relationship table can be loaded into the software-configurable table according to actual needs, so that a table lookup operation can be implemented through the configured software-configurable table.

[0096] Because some functions are commonly used across multiple computing tasks, the function relationship tables corresponding to these functions can be pre-stored in table storage units to improve computing efficiency. This pre-stored function relationship table saves time loading the table, and because it remains unchanged, it occupies minimal memory.

[0097] For example, Tanh and sigmoid are very common activation functions in AI networks. To save table loading time when looking up the tanh / sigmoid table, a fixed sigmoid function relationship table and a fixed tanh function relationship table can be stored in the table storage unit.

[0098] When the target independent variable or target dependent variable exists in the function relationship table, the dependent variable corresponding to the target independent variable or the independent variable corresponding to the target dependent variable can be directly obtained.

[0099] When the target independent variable does not exist in the function relationship table, the third calculation unit obtains the two independent variables closest to the target independent variable from the function relationship table, and then takes the average value of the dependent variables corresponding to the two independent variables as the dependent variable corresponding to the target independent variable.

[0100] Similarly, when the target dependent variable does not exist in the function relationship table, the third calculation unit obtains the two dependent variables closest to the target dependent variable from the function relationship table, and then uses the average value of the independent variables corresponding to the two dependent variables as the independent variable corresponding to the target dependent variable.

[0101] Optionally, the table storage unit may store only one function relationship table, or the table storage unit may store multiple different function relationship tables.

[0102] The table storage unit may be any device with storage capability, for example, any type of storage medium. The specific structure of the table storage unit is not limited herein.

[0103] Optionally, the table storage unit may include multiple ones, and each third type of computing unit is connected to one table storage unit respectively.

[0104] The function relationship tables stored in different table storage units may be different or the same, or the function relationship tables stored in some table storage units may be the same.

[0105] Optionally, when there are multiple instruction receiving ends of the third computing units connected to each other and to the main control unit, the function relationship tables stored in the table storage units respectively connected to the multiple third computing units are the same.

[0106] In one embodiment, the stream processor may further include an instruction storage unit, connected to the main control unit, and configured to store operation instructions. The main control unit is further configured to retrieve operation instructions from the instruction storage unit. By configuring the instruction storage unit to store operation instructions, there is no need to retrieve operation instructions from an external source, allowing the present solution to operate independently and expanding its scope of application.

[0107] Among them, each operation instruction stored in the instruction storage unit may be an operation instruction for only one type of computing unit. In this case, after the main control unit obtains the operation instruction, it directly sends the operation instruction to the corresponding computing unit.

[0108] Alternatively, each operation instruction stored in the instruction storage unit may be an operation instruction set for multiple computing units. In this case, after the main control unit obtains the operation instruction, it splits the operation instruction according to the type of computing unit to obtain multiple sub-operation instructions, and then sends each sub-operation instruction to the corresponding computing unit to achieve synchronous control of the multiple computing units to perform calculations.

[0109] In one implementation, the stream processor can be set to two working modes: instruction mode and sharing mode.

[0110] When the stream processor is in instruction mode, the main control unit controls the computing unit to perform corresponding computing operations through the operation instructions stored in the instruction storage unit.

[0111] When the stream processor is in sharing mode, the stream processor shares its own computing units with other processors, so that other processors can control the computing units in the stream processor to perform computing operations.

[0112] To facilitate understanding of the above-mentioned stream processor, please refer to Figure 10, which is a structural block diagram of a stream processor shown in an embodiment of the present application. It should be noted that the stream processor shown in Figure 10 is only one of the many embodiments of the stream processor shown in the embodiment of the present application and should not be used as a limitation to the present application.

[0113] The stream processor includes a main control unit, a statistical operation unit, a table storage unit, an instruction storage unit, n first-type computing units, n second-type computing units, n third-type computing units, n fourth-type computing units, and n data storage areas, where n is a positive integer.

[0114] The main control unit is connected to each computing unit, the statistical operation unit and the instruction storage unit respectively, and the instruction receiving ends of the same computing units are connected to each other, and the same computing units are connected to different data storage areas respectively.

[0115] The n third type calculation units are all connected to the table storage unit, and the statistical operation unit is also connected to each data storage area.

[0116] Among them, the specific implementation methods and principles of the main control unit, statistical calculation unit, table storage unit, instruction storage unit, first calculation unit, second calculation unit, third calculation unit, fourth calculation unit, and data storage area have been clearly described in the previous article. For the sake of brief description, they will not be repeated here.

[0117] To facilitate understanding of the specific workflow of the above stream processor, the following is an example of a stream processor performing a softmax calculation task.

[0118] First, the main control unit controls the statistical operation unit to calculate the maximum value of the received data, and stores the calculated target maximum value (hereinafter represented by max) in each data storage area.

[0119] Then, for each second-type computing unit, the main control unit controls the second-type computing unit to calculate xi-max, and stores the calculation result (represented as A1 below) in the data storage area connected to the second-type computing unit, where xi is input data or data pre-stored in the data storage area connected to the second-type computing unit.

[0120] The main control unit controls the third type of computing unit corresponding to the second type of computing unit (connected to the same data storage area) to perform a table lookup operation to find the table lookup result corresponding to A1 (hereinafter represented as B1). The table storage unit stores the function relationship table of exp(xi-max).

[0121] The main control unit controls the statistical operation unit to accumulate and sum B1 in each data storage area, that is, calculate sum(exp(xi-max)), and stores the obtained result (hereinafter represented as C1) in each data storage area.

[0122] The main control unit controls the third type of calculation unit to perform a table lookup operation to find a table lookup result (hereinafter represented as D1) corresponding to C1, wherein the table storage unit stores a function relationship table of 1 / sum(exp(xi-max)).

[0123] The main control unit controls the first computing unit to calculate exp(xi-max)*(1 / sum(exp(xi-max))), that is, B1*D1, obtains the output result, and completes the calculation of softmax.

[0124] To facilitate understanding of the specific workflow of the aforementioned stream processor, the following description is made using an example of a stream processor executing an instance normalization computing task.

[0125] First, the main control unit controls the first type of calculation unit to calculate xij2, where xij is the input data. Wherein, xij represents the element in the i-th row and j-th column of the input data matrix, and i and j are both positive integers.

[0126] The main control unit then controls the statistical operation unit to obtain xij2 and xij from each data storage area respectively, and then calculates sum(xij) based on all the obtained xij, and calculates sum(xij2) based on all the obtained xij2, and stores the calculation results in the data storage area.

[0127] The main control unit controls the first calculation unit to calculate the average value μi of xij and stores the average value μi in the data storage area. Wherein, μi = sum(xij) ÷ number of elements, where the number of elements is the number of xij obtained when calculating sum(xij).

[0128] Then the main control unit controls the first type of calculation unit to calculate μi2, that is, to calculate (sum(xij)÷number of elements)2; and stores the calculation result in the data storage area.

[0129] The main control unit controls the second calculation unit to calculate sum(xij2)+μi2 and stores the calculation result in the data storage area.

[0130] The main control unit controls the third computing unit to calculate Among them, the table storage unit stores The function relationship table is created and the calculation results are stored in the data storage area. σi2 represents the variance. ε represents Epsilon, a small positive floating point number (0.000001) used to prevent the denominator of the formula from being 0.

[0131] The main control unit controls the second calculation unit to calculate xij-μi and stores the calculation results in the data storage area.

[0132] Finally, the main control unit controls the first computing unit to calculate the final result of instance normalization. That is, the main control unit controls the first computing unit to obtain xij-μi and Then calculate xij-μi and The product of is the final result.

[0133] The above examples are only for ease of understanding and should not be construed as limiting the present application.

[0134] Based on the same technical concept, the present application also provides an operation method, which is applied to the above-mentioned stream processor and will be described below in conjunction with Figure 11.

[0135] S100: Allocate operation instructions to the computing unit via the main control unit.

[0136] S200: The computing unit executes a corresponding operation of the computing unit in response to an operation instruction.

[0137] By repeatedly applying the aforementioned computational methods according to the computational logic corresponding to the computational task, different types of computational units can be combined to compute different computational tasks. The computational logic corresponding to the computational task is reflected in the order in which instructions are issued, and the order in which instructions are issued can be, but is not limited to, pre-configured by engineers.

[0138] The computing method provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned stream processor embodiment. For the sake of brief description, for matters not mentioned in the method embodiment, reference can be made to the corresponding content in the aforementioned stream processor embodiment.

[0139] Based on the same technical concept, the present application also provides a chip, which includes the above-mentioned stream processor.

[0140] Among them, the chip can be a chip with data processing capabilities, such as a SOC (System on Chip) chip, an AI (Artificial Intelligence) chip, a CPU (Central Processing Unit), a GPU (graphics processing unit), a GPGPU (General-purpose computing on graphics processing units), etc.

[0141] The specific implementation method and principle of the stream processor have been clearly described in the previous article. For the sake of brevity, they will not be repeated here.

[0142] In an optional implementation of the embodiment of the present application, a stream processor can be packaged in a chip to perform different computing tasks.

[0143] In another optional implementation of the embodiment of the present application, multiple stream processors can be packaged simultaneously in one chip.

[0144] At this time, in a feasible implementation, each stream processor may be independent of each other and independently complete different computing tasks.

[0145] In addition, in another feasible implementation, engineers or upper-level software can divide a computing task into multiple relatively independent small computing tasks, and then the upper-level distributor in the chip can distribute different small computing tasks to different stream processors for execution, or engineers can write relevant instructions according to the small computing tasks in the main control module in each stream processor, thereby achieving coordination between the stream processors and improving processing efficiency.

[0146] Based on the same technical concept, the present application also provides an electronic device comprising the above-mentioned chip.

[0147] The electronic device may be a complete device such as a computer, a mobile phone, or a server, or may be an electronic device such as a CPU board, a graphics card, or a controller that can be sold independently and installed in other devices.

[0148] The specific implementation method and principle of the chip have been clearly described in the previous article. For the sake of brevity, they will not be repeated here.

[0149] The technical features in the above embodiments can be freely combined to form new embodiments without conflict.

[0150] In the embodiments of the present application, a plurality refers to two or more.

[0151] The connection in the embodiments of the present application includes direct or indirect electrical connection.

[0152] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A stream processor, characterized in that: include: At least two types of computing units, each of which is configured to perform one of multiplication, addition, table lookup, and data transfer operations; A main control unit is connected to each of the computing units and is configured to distribute operation instructions to the computing units so that the computing units perform corresponding calculation operations of the computing units in response to the operation instructions.

2. The stream processor according to claim 1, characterized in that The number of at least some types of computing units among the at least two types of computing units is plural; The instruction receiving ends of a plurality of computing units of the same type are connected to each other and to the main control unit.

3. The stream processor according to claim 2, characterized in that The stream processor further includes: at least one data storage area; The multiple computing units of the same type are respectively connected to different data storage areas.

4. The stream processor according to claim 3, characterized in that The stream processor further includes: A statistical operation unit, the statistical operation unit is connected to the main control unit and to each of the data storage areas; the statistical operation unit is configured to perform maximum value processing or summation processing on the target data in the data storage area in response to the operation instruction assigned by the main control unit.

5. The stream processor according to claim 3, characterized in that The number of different types of computing units is the same.

6. The stream processor according to claim 5, characterized in that The at least two types of computing units include a first computing unit, a second computing unit, a third computing unit and a fourth computing unit; the first computing unit is a computing unit that performs multiplication operations, the second computing unit is a computing unit that performs addition operations, the third computing unit is a computing unit that performs table lookup operations, and the fourth computing unit is a computing unit that performs transport operations.

7. The stream processor according to claim 1, characterized in that The stream processor further includes: A table storage unit is configured to store a function relationship table; The table storage unit is connected to each of the third type of computing units, and the third type of computing units are configured to perform a table lookup operation on the function relationship table in the table storage unit in response to an operation instruction assigned by the main control unit.

8. The stream processor according to claim 1, characterized in that The stream processor further includes: An instruction storage unit, the instruction storage unit is connected to the main control unit, and the instruction storage unit is configured to store operation instructions; the main control unit is also configured to obtain the operation instructions from the instruction storage unit.

9. A computing method, characterized in that: Applied to the stream processor according to any one of claims 1 to 8, the computing method comprises: Allocating operation instructions to the computing unit through the main control unit; The computing unit executes a corresponding calculation operation of the computing unit in response to the operation instruction.

10. A chip, characterized in that: include: A stream processor as claimed in any one of claims 1 to 8.

11. An electronic device, characterized in that: include: The chip as claimed in claim 10.

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