Polynomial processing system and method

Abstract

Provided in the present application are a polynomial processing system and method, the system comprising a reverse processing unit. The reverse processing unit comprises a first register for storing a V-bit binary number, a transmission module connected to the first register, and a second register connected to the transmission module and used for storing a V-bit binary number, V being a positive integer, wherein the first register is configured to acquire, for each numerical value in an original sequence, a V-bit binary number of the numerical value; the transmission module is configured to transmit a vth binary digit in the first register to the position where a (Vv-1)th binary digit is stored in the second register, v being a natural number; the second register is configured to acquire the vth binary digit from the transmission module, so as to obtain a binary number of a reverse sequence number of the numerical value. The original sequence is determined on the basis of a first forward sequence number, and the first forward sequence number is the sorting sequence number of a plurality of coefficients of a target polynomial in the target polynomial from front to back.

Description

Polynomial processing system and method Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a polynomial processing system and method. Background Art

[0002] For polynomials involved in polynomial multiplication, both Fast Fourier Transform (FFT) and Number Theoretic Transforms (NTT) can convert polynomials expressed in coefficient notation into polynomials expressed in point value notation. Polynomials in point value notation can complete polynomial multiplication more quickly. Therefore, FFT and NTT are often used in polynomial multiplication operations.

[0003] When using FFT and NTT to process polynomials, a system such as a processor that executes FFT or NTT generally needs to perform a reverse transformation on the binary numbers of the polynomial coefficients in the polynomial to obtain the polynomial coefficients in reverse order, and then determine the polynomial in point value representation based on the polynomial coefficients in reverse order. However, currently, when performing the reverse transformation, a large number of shifts, judgments, or jump operations are required. For example, for a system with 2 6 For a polynomial with 10 coefficients, the calculation base for the inverse transformation is 6. Therefore, when performing the inverse calculation on the binary number corresponding to one coefficient, the instructions and operations required include: 6 comparison instructions, 6 jump instructions, 6 addition instructions, 12 subtraction instructions, 6 OR operations, 6 AND operations, 6 left shift operations, and 6 right shift operations, totaling 54 clock cycles. Obviously, this inverse transformation method is time-consuming and affects the efficiency of polynomial processing.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The present application provides a polynomial processing system, method, electronic device, storage medium, program product and computer program.

[0007] In a first aspect, a polynomial processing system is provided, the system including a reversal processing unit, the reversal processing unit including a first register storing a V-bit binary number, a transmission module connected to the first register, and a second register storing the V-bit binary number connected to the transmission module, where V is a positive integer; the first register is configured to obtain, for each value in an original sequence, a V-bit binary number of the value; the transmission module is configured to transmit the v-th binary number in the first register to a position storing a Vv-1-th binary number in the second register, where v is a natural number; the second register is configured to obtain the v-th binary number from the transmission module to obtain a binary number of a reversal number of the value; wherein the original sequence is determined based on a first positive sequence number, which is a sorting number of multiple coefficients of a target polynomial from front to back in the target polynomial.

[0008] In a second aspect, a polynomial processing method is provided, which is applied to a polynomial processing system. The system includes a reverse processing unit, which includes: a first register storing a V-bit binary number, a transmission module connected to the first register, and a second register storing the V-bit binary number connected to the transmission module, where V is a positive integer; the method includes: for each value in an original sequence, the first register obtains the V-bit binary number of the value; the transmission module transmits the v-th binary number in the first register to a position storing the Vv-1-th binary number in the second register, where v is a natural number; the second register obtains the v-th binary number from the transmission module to obtain the binary number of the reverse number of the value; wherein the original sequence is determined based on a first positive sequence number, and the first positive sequence number is a sorting number of multiple coefficients of a target polynomial from front to back in the target polynomial.

[0009] In a third aspect, an electronic device is provided, comprising: a processor and a memory, wherein the memory stores a computer program, and the processor calls and runs the computer program stored in the memory to execute the method as implemented in the second aspect.

[0010] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and the computer program enables a computer to execute the method in the implementation manner of the second aspect.

[0011] In a fifth aspect, a computer program product is provided, comprising computer program instructions, which enable a computer to execute the method as implemented in the second aspect.

[0012] In a sixth aspect, a computer program is provided, which enables a computer to execute the method as implemented in the second aspect.

[0013] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0014] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] FIG1 is a schematic diagram of a polynomial processing system provided in an embodiment of the present application;

[0017] FIG2 is a schematic diagram of a reverse order processing unit provided in an embodiment of the present application;

[0018] FIG3 is a schematic diagram of another polynomial processing system provided in an embodiment of the present application;

[0019] FIG4 is a schematic diagram of another polynomial processing system provided in an embodiment of the present application;

[0020] FIG5 is a schematic diagram of a butterfly operation provided in an embodiment of the present application;

[0021] FIG6 is a schematic diagram of another butterfly operation provided in an embodiment of the present application;

[0022] FIG7 is a schematic diagram of another polynomial processing system provided in an embodiment of the present application;

[0023] FIG8 is a schematic diagram of another polynomial processing system provided in an embodiment of the present application;

[0024] FIG9 is a schematic diagram of an adjustment unit provided in an embodiment of the present application;

[0025] FIG10 is a schematic diagram of another adjustment unit provided in an embodiment of the present application;

[0026] FIG11 is a schematic diagram of a reverse order processing provided by an embodiment of the present application;

[0027] FIG12 is a flow chart of a polynomial processing method provided in an embodiment of the present application;

[0028] FIG13 is a schematic block diagram of an electronic device 1300 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or precedence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] As described above, the related technology requires a large number of shifting, judging or jumping operations when performing inverse transformation. This inverse transformation method is time-consuming and affects the efficiency of polynomial processing.

[0032] In order to solve the above technical problems, the present application provides a polynomial processing system and method, the system includes a reverse processing unit, the reverse processing unit includes a first register storing a V-bit binary number, a transmission module connected to the first register, and a second register storing a V-bit binary number connected to the transmission module, where V is a positive integer; the first register is configured to obtain the V-bit binary number of each value in the original sequence, the transmission module is configured to transmit the v-th binary number in the first register to the position storing the Vv-1-th binary number in the second register, where v is a natural number, and the second register is configured to obtain the v-th binary number from the transmission module to obtain the binary number of the reverse number of the value; wherein the original sequence is determined based on a first positive sequence number, and the first positive sequence number is the sorting sequence number of multiple coefficients of the target polynomial from front to back in the target polynomial. In the above process, when the polynomial processing system determines the binary number of the reversed number, it can directly transmit the v-th binary number in the first register to the position where the Vv-1-th binary number is stored in the second register through the transmission module, that is, each binary number can be directly reversed without performing a large number of shifts, judgments or jump operations, thereby reducing the time consumption of the reverse transformation method, increasing the speed of calculating the reverse result, and thus improving the processing efficiency of the polynomial.

[0033] The technical solution of this application can be applied to the following scenarios, but not limited to:

[0034] In some implementations, the technical solution of the present application can be applied to scenarios where polynomial additive convolution is accelerated. For example, when using NTT or FFT to accelerate polynomial additive convolution, it is necessary to use NTT or FFT to transform the coefficients of the polynomial to obtain a transformation result. In the process of obtaining the transformation result, the technical solution of the present application can reverse the sorting sequence of the polynomial coefficients or the sorting sequence of the transformation result to achieve rearrangement of the polynomial coefficients or the transformation result, thereby improving the processing efficiency of the polynomial.

[0035] In some implementations, the polynomial processing system may be a chip, a central processing unit (CPU), or an electronic device on which the chip or CPU is installed, and this application does not impose any restrictions on this.

[0036] The following describes the technical solutions of the embodiments of the present application in detail through some embodiments. The following embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0037] In some implementations, FIG1 is a schematic diagram of a polynomial processing system provided by an embodiment of the present application. As shown in FIG1 , the polynomial processing system includes: a reversal processing unit, the reversal processing unit including a first register storing a V-bit binary number, a transmission module connected to the first register, and a second register storing a V-bit binary number connected to the transmission module, where V is a positive integer;

[0038] The first register is configured to obtain, for each value in the original sequence, a V-bit binary representation of the value;

[0039] A transmission module is configured to: transmit the v-th binary number in the first register to a position storing the Vv-1-th binary number in the second register, where v is a natural number;

[0040] The second register is set to: obtain the v-th binary number from the transmission module and obtain the binary number of the inverse number of the numerical value; wherein the original sequence is determined based on the first positive sequence number, and the first positive sequence number is the sorting sequence number of multiple coefficients of the target polynomial from front to back in the target polynomial.

[0041] As shown in Figure 1, assume that the V-bit binary number of a value in the original sequence is: V0V1...V V-1 , V0, V1, ..., V V-1is 0 or 1, the first register can store the V-bit binary number in sequence, the transmission module can obtain the v-th binary number in the first register, and transmit the v-th binary number to the position where the Vv-1-th binary number is stored in the second register. The second register can obtain the v-th binary number from the transmission module, and the binary number of the reverse number of the value is: V V-1 …V0V1.

[0042] It can be understood that for the polynomial Z(x)=x0+x1*x+x2*x 2 +……+x n-1 *x n-1 , the coefficients of the polynomial Z(x) are x0, x1, x2, ..., x n-1 , multiple coefficients can be processed by FFT or NTT to realize the transformation of polynomial Z(x), and the polynomial Z(x) in point value representation can be obtained as Z(x)={(g0, G(g0)),(g1, G(g1)),(g2, G(g2)),……,(g n-1 ,G(g n-1 ))}, where g0, ..., g n-1 It is the rotation factor in NTT or FFT. For FFT, g0, ..., g n-1 There are n different roots of unity; for NTT, g0, ..., g n-1 Specifically, when using FFT or NTT to transform the polynomial Z(x), multiple coefficients x0, x1, x2, ..., x n-1 and g0, ..., g n-1 Perform butterfly operations to obtain multiple transformation results: G(g0), G(g1), G(g2), ..., G(g n-1 ), then, we can calculate g0, ..., g n-1 and multiple transformation results G(g0), G(g1), G(g2), ..., G(g n-1 ) are combined to obtain the polynomial Z(x)={(g0, G(g0)),(g1, G(g1)),(g2, G(g2)),……,(g n-1 ,G(g n-1 ))}.

[0043] However, in butterfly operation, multiple coefficients x0, x1, x2, ..., x n-1 Multiple transformation results of different sorting can be obtained G(g0), G(g1), G(g2), ..., G(g n-1): When multiple coefficients are input in positive order, multiple transformation results can be obtained in reverse order; when multiple coefficients are input in reverse order, multiple transformation results can be obtained in positive order. This can be combined with the subsequent description of butterfly operations in this application.

[0044] Among them, for the multiple coefficients x0, x1, x2, ..., x of the polynomial Z(x) n-1 The order of the coefficients in the polynomial Z(x) from front to back is: 0, 1, 2, ..., n-1. The order of the coefficients according to the order can be called positive order. The coefficients arranged in positive order are x0, x1, x2, ..., x n-1 . The binary numbers of the sorting numbers from front to back are respectively reversed to obtain the binary numbers of the reversed numbers of the sorting numbers from front to back. The reversed numbers can be determined according to the binary numbers of the reversed numbers. The sorting of multiple coefficients according to the reversed numbers can be called reverse arrangement. When sorting multiple coefficients according to the reversed numbers, the reversed numbers of the sorting numbers of the coefficients from front to back in the polynomial can be determined as the sorting numbers of the coefficients in the reverse arrangement. For example, assuming the polynomial Z1(x) = x0+x1*x+x2*x 2 +x3*x 3 The polynomial Z1(x) has 4 coefficients: x0, x1, x2, x3. The order of these 4 coefficients in the polynomial Z1(x) from front to back is 0, 1, 2, 3. By sorting x0, x1, x2, x3 according to the order of 0, 1, 2, 3 from front to back, we can get the 4 coefficients in positive order: x0, x1, x2, x3. The binary numbers of the sorting numbers 0, 1, 2, and 3 from front to back are 00, 01, 10, and 11 respectively. Reversing these four binary numbers can obtain the following four binary numbers: 00, 10, 01, and 11. The decimal numbers corresponding to the four inverted binary numbers are 0, 2, 1, and 3 respectively. Therefore, it can be determined that the reverse numbers of the sorting numbers 0, 1, 2, and 3 from front to back are 0, 2, 1, and 3 respectively. Then, it can be determined that the sorting numbers of the four coefficients x0, x1, x2, and x3 in reverse order are 0, 1, 2, and 3 respectively. According to the sorting numbers of the four coefficients in reverse order, the four coefficients x0, x1, x2, and x3 can be sorted as: x0, x2, x1, and x3. That is, the four coefficients in reverse order are: x0, x2, x1, and x3.

[0045] Similarly, for the multiple transformation results G(g0), G(g1), G(g2), ..., G(g n-1), the order numbers of the multiple transformation results from front to back in the polynomial Z(x) in point value representation are: 0, 1, 2, ..., n-1, and the order of the multiple transformation results according to the order numbers can be called positive order arrangement. The multiple transformation results arranged in positive order are G(g0), G(g1), G(g2), ..., G(g n-1 ). The binary numbers of the sorting numbers from front to back are reversed respectively to obtain the binary numbers of the reversed numbers of each sorting number from front to back. The reversed numbers can be determined according to the binary numbers of the reversed numbers. The sorting of multiple transformation results according to the reversed numbers can be called reverse arrangement. When sorting multiple transformation results according to the reversed numbers, the reversed numbers of the sorting numbers of the transformation results from front to back in the polynomial under the point value representation can be determined as the sorting numbers of the transformation results in the reverse arrangement. For example, assuming the polynomial Z1(x) = x0+x1*x+x2*x 2 +x3*x 3 After using FFT or NTT to transform the polynomial Z1(x), four transformation results can be obtained: G(g0), G(g1), G(g2), G(g3). Among them, the sorting sequence of these four transformation results from front to back in the polynomial Z1(x) in point value representation is: 0, 1, 2, 3. According to the sorting sequence 0, 1, 2, 3 from front to back, G(g0), G(g1), G(g2), G(g3) are sorted, and the four transformation results in positive order can be obtained: G(g0), G(g1), G(g2), G(g3). The binary numbers of the sorted numbers 0, 1, 2, and 3 from front to back are: 00, 01, 10, and 11. The four binary numbers are reversed to obtain the following four binary numbers: 00, 10, 01, and 11. The decimal numbers corresponding to the four reversed binary numbers are: 0, 2, 1, and 3. Therefore, it can be determined that the reversed numbers of the sorted numbers 0, 1, 2, and 3 from front to back are: 0, 2, 1, and 3. Then the four transformation results G(g0) can be determined. ), G(g1), G(g2), G(g3) have the sorting numbers of 0, 1, 2, 3 in reverse order respectively. According to the sorting numbers of the four transformation results in reverse order, the four transformation results G(g0), G(g1), G(g2), G(g3) can be sorted as: G(g0), G(g2), G(g1), G(g3), that is, the four transformation results in reverse order are: G(g0), G(g2), G(g1), G(g3).

[0046] When obtaining a polynomial in point value representation according to FFT or NTT, the polynomial expression Z(x) = x0+x1*x+x2*x can be used. 2 +……+x n-1*x n-1 Directly obtain the polynomial coefficients in positive order: x0, x1, x2, ..., x n-1 , in the polynomial Z(x)={(g0, G(g0)),(g1, G(g1)),(g2, G(g2)),……,(g n-1 ,G(g n-1 ))}, the transformation results need to be arranged in positive order: G(g0), G(g1), G(g2), ..., G(g n-1 ). However, according to the above content, it can be seen that the input and output of the butterfly operation will not simultaneously have the polynomial coefficients arranged in positive order and the transformation results arranged in positive order. Therefore, it is necessary to perform an inverse transformation on the polynomial coefficients or the transformation results directly output by the butterfly operation, that is, it is necessary to process the polynomial coefficients arranged in positive order into the polynomial coefficients arranged in reverse order, or it is necessary to process the transformation results arranged in reverse order into the transformation results arranged in positive order. When performing the above-mentioned processing, the related art needs to perform a large number of operations such as displacement and judgment. Obviously, this processing method consumes a lot of time, which affects the processing efficiency of the polynomial. However, the polynomial processing system provided by the present application does not need to perform a large number of operations such as displacement and judgment, and can realize the inverse transformation more quickly through the inverse processing unit, thereby reducing the inverse transformation time and improving the processing efficiency of the polynomial. The present application will introduce the inverse processing process of the inverse processing unit in detail in the following embodiments.

[0047] In some implementations, as shown in FIG2 , the transmission module includes an arithmetic logic unit (ALU), and the ALU is configured to transmit the v-th binary number in the first register to a location in the second register where the Vv-1-th binary number is stored.

[0048] It can be understood that the ALU can perform operations on the values ​​in the register. Therefore, the polynomial processing system can transfer the v-th binary number in the first register to the position where the Vv-1-th binary number is stored in the second register based on the ALU, thereby quickly realizing the inverse transformation, improving the speed of calculating the inverse number, and improving the processing efficiency of the polynomial.

[0049] In some implementations, the first register includes V first flip-flops, and the second register includes V second flip-flops; the vth first flip-flop among the V first flip-flops is set to: obtain the vth binary number in the V-bit binary number based on the input end of the vth first flip-flop; the output end of the vth first flip-flop is connected to the ALU; the Vv-1th second flip-flop among the V second flip-flops is set to: output the vth binary number based on the output end of the Vv-1th second flip-flop; the input end of the vth second flip-flop is connected to the ALU.

[0050] A trigger is a binary information storage device, and each trigger can store one binary number. Therefore, the polynomial processing system can obtain the V-bit binary number of each value in the original sequence based on V first triggers, and obtain the binary number of the inverse number of each value based on V second triggers, so that the transmission module can separately process each binary number in the V-bit binary number of the value, and transmit each binary number in the V-bit binary number in the first register to the corresponding position in the second register, that is, transmit the v-th binary number in the V-bit binary number of the value to the position storing the Vv-1-th binary number in the second register, thereby quickly completing the inverse transformation of the values ​​in the original sequence, thereby achieving the effect of improving the speed of calculating the inverse number and improving the processing efficiency of the polynomial.

[0051] For example, as shown in FIG3 , the first register includes V first flip-flops, and the second register includes V second flip-flops. Each of the V first flip-flops and the V second flip-flops includes an input terminal and an output terminal. The input terminal is shown as “D” in FIG3 , and the output terminal is shown as “Q” in FIG3 . The output terminals of the V first flip-flops are all connected to the transmission module, and the input terminals of the V second flip-flops are all connected to the transmission module. For binary numbers: V0V1…V V-1 , V0, V1, ..., V V-1 is 0 or 1, the input terminals of the V first triggers can be obtained respectively: V0, V1, ..., V V-2 、V V-1 , V second flip-flops can output binary numbers "V0V1......V V-1 "The reverse result of "V V-1 ...V0V1", where the output terminals of the V second triggers can respectively output: V V-1 、V V-2 ,……,V1,V0.

[0052] In some implementations, the V first flip-flops and the V second flip-flops are triggered by a same clock signal.

[0053] Exemplarily, a clock control terminal of each of the V first flip-flops and the V second flip-flops is connected to the same clock control line.

[0054] For example, in combination with the above embodiment, as shown in FIG3 , the clock control terminal of the trigger may be represented by a “triangle” in the trigger in FIG3 , and the clock control line may be represented by a bold line in FIG3 .

[0055] In the above embodiment, the polynomial processing system can connect the clock control terminal of each trigger based on the same clock control line to use the same clock signal to control the operation of multiple triggers, so that the inverse transformation of a V-bit binary number can be completed in one clock cycle, reducing the inverse processing time and improving the inverse processing efficiency.

[0056] In some implementations, as shown in FIG4 , the polynomial processing system may further include a processor and a computing unit connected to the processor, wherein the processor includes a control unit and a reverse processing unit connected to the control unit. The control unit may send instructions or data to the reverse processing unit or the computing unit, and the reverse processing unit or the computing unit, upon receiving the instructions or data sent by the control unit, implements an operation corresponding to the instructions or operates on the data.

[0057] It should be noted that the above-mentioned inverse processing unit and calculation unit can be used as an independent functional unit in the polynomial processing system, or the inverse processing unit, calculation unit and other functional units can be integrated into the control unit. This application does not impose any specific restrictions on this.

[0058] When the control unit sends an instruction to the inverse processing unit, it can directly send the instruction to the transmission module of the inverse processing unit. After obtaining the instruction, the transmission module can process the V-bit binary number of each numerical value in the original sequence according to the instruction to determine the binary number of the inverse number of each numerical value, so that the inverse transformation of the V-bit binary number can be quickly completed through one instruction, which can not only reduce the inverse processing time and improve the inverse processing efficiency, but also improve the flexibility and controllability of the inverse transformation.

[0059] In some examples, the transmission module is configured to: obtain a reverse processing instruction, the reverse processing instruction including: a first field and a second field, the first field being configured to specify a first register as a source register, the source register being configured to store a source operand, the source operand including a V-bit binary number of each numerical value in the original sequence, the second field being configured to specify a second register as a destination register, the destination register being configured to store a destination operand, the destination operand including a binary number of a reversed number of each numerical value in the original sequence; executing the reverse processing instruction to obtain a specific result of the reverse processing instruction; executing the reverse processing instruction to obtain a specific result of the reverse processing instruction, including: for each V-bit binary number in the source operand, shifting the V-bit binary number right by i bits to obtain a first binary number, performing bitwise AND operation on the first binary number and the second binary number to obtain a third binary number, the second binary number being a binary number corresponding to the decimal number 1, shifting the third binary number left by Vi-1 bits to obtain a fourth binary number, i being an integer from 0 to V-1, and performing bitwise OR operation on each fourth binary number to obtain a binary number of a reversed number corresponding to the V-bit binary number in the destination operand.

[0060] The reverse processing instruction can be defined as follows:

[0061] bfly t1,t2,a1

[0062] Among them, "bfly" represents the name of the reverse processing instruction. "t1", "t2" and "a1" in the above reverse processing instruction are three fields of the reverse processing instruction respectively. Among them, "t1" is set to specify register t1 as the destination register, and the destination register is set to store the destination operand. The destination operand includes the binary number of each value in the original sequence; "t2" is set to specify register t2 as the first source register, and the first source register is set to store the first source operand. The first source operand includes the binary number of the reverse number of each value in the original sequence; "a1" is set to specify register a1 as the second source register, and the second source register is set to store the second source operand. The second source operand includes the logarithm of the reverse length with base 2, and the reverse length is the number of bits of the binary number of any value in the original sequence.

[0063] For example, assuming that a 64-bit binary number in the source operand is 00101110, its effective bit width is 8, that is, i is an integer from 0 to 7, after the transmission module obtains the reverse processing instruction, it executes: when i=0, the binary number "00101110" is shifted right by 0 bits to obtain the first binary number "00101110", the second binary number is determined to be "00000001", the first binary number "00101110" and the second binary number "00000001" are ANDed to obtain the third binary number "00000000", the third binary number "00000000" is shifted left by 7 bits to obtain the fourth binary number "00000000"; when i=1 , shift the binary number "00101110" right by 1 bit, and get the first binary number "0010111", determine the second binary number is "0000001", and add the first binary number "0010111" and the second binary number "0000001" to get the third binary number "0000001", shift the third binary number "0000001" left by 6 bits, and get the fourth binary number "10000000"; when i=2, shift the binary number "00101110" right by 2 bits, and get the first binary number "001011", determine the second binary number is "000001", and add the first binary number "001011" and the second binary number "000 001", and get the third binary number "000001". Shift the third binary number "000001" left by 5 bits to get the fourth binary number "10000000". When i=3, shift the binary number "00101110" right by 3 bits to get the first binary number "00101". Determine that the second binary number is "00001". AND the first binary number "00101" with the second binary number "00001" to get the third binary number "00001". Shift the third binary number "00001" left by 4 bits to get the fourth binary number "10000000". When i=4, shift the binary number "00101110" right by 4 bits to get the first binary number "00101". The binary number is "0010", the second binary number is determined to be "0001", the first binary number "0010" and the second binary number "0001" are ANDed together to obtain the third binary number "0000", the third binary number "0000" is shifted left by 3 bits to obtain the fourth binary number "000000000"; when i=5, the binary number "00101110" is shifted right by 5 bits to obtain the first binary number "001", the second binary number is determined to be "001", the first binary number "001" and the second binary number "001" are ANDed together to obtain the third binary number "001", the third binary number "001" is shifted left by 2 bits to obtain the fourth binary number "100000000";When i=6, the binary number "00101110" is shifted right by 6 bits to obtain the first binary number "00". The second binary number is determined to be "01". The first binary number "00" and the second binary number "01" are ANDed together to obtain the third binary number "00". The third binary number "00" is shifted left by 1 bit to obtain the fourth binary number "00000000". When i=7, the binary number "00101110" is shifted right by 7 bits to obtain the first binary number "0". The second binary number is determined to be "1". The first binary number "0" and the second binary number "1" are ANDed together to obtain the third binary number "0". The third binary number "0" is shifted left by 0 bit to obtain the fourth binary number "00000000". The ANDing of each of the above fourth binary numbers yields the binary number of the reversed digit corresponding to the binary number "00101110": 01110100.

[0064] It is understood that in the above embodiment, the first binary number and the second binary number are bitwise ANDed together to extract the i-th digit from the V-bit binary number in the source operand. The i-th digit refers to the i-th digit in the order from the lowest bit to the highest bit in the V-bit binary number. By left-shifting the third binary number by Vi-1, the corresponding position of the i-th digit extracted in the binary number of the reversed number can be determined. By performing a phase OR operation on each fourth binary number, each extracted i-th digit can be combined according to the corresponding position of the i-th digit in the binary number of the reversed number, thereby determining the binary number of the reversed number. Obviously, when executing the above reverse processing instruction, the transmission module needs to perform fewer operations than in the related art, thereby improving the efficiency of determining the reversed number.

[0065] For example, the reverse processing instruction may be a bfly instruction, and the pseudo code of the software implementation of the bfly instruction may be as follows. input: const uint64_t val; / / binary number const uint64_t loc; / / base number output: uint64_t dst; process: dst=0; for(int i=0;i<loc;i++){ dst|=(((val> >i)&0x01UL)<<(loc-i-1));}

[0066] The “0x01UL” in the above pseudocode indicates that the above pseudocode is implemented based on hexadecimal. When the “0x01UL” in the above pseudocode is modified to “0b1”, the modified pseudocode can be implemented based on binary.

[0067] Wherein, "64" represents the number of binary bits that can be stored in the first register and the second register, "val" represents the binary number of any value in the original sequence, and "loc" represents the number of bits of the binary number of any value in the original sequence.

[0068] In some implementations, the transmission module may include at least one logic unit configured to perform an operation corresponding to the aforementioned reverse order processing instruction. For example, the at least one logic unit may be configured to perform a shift operation, an AND operation, or an OR operation. The at least one logic unit may be integrated into an ALU in the transmission module. Alternatively, the ALU in the transmission module may perform an operation corresponding to the aforementioned reverse order processing instruction, such as a right shift operation, a left shift operation, an AND operation, or an OR operation.

[0069] The operations corresponding to the above-mentioned reverse processing instruction may specifically include: the operation of shifting the V-bit binary number right by i bits, the operation of performing bitwise AND operation on the first binary number and the second binary number, the operation of shifting the third binary number left by Vi-1 bits, and the operation of performing bitwise OR operation on each fourth binary number.

[0070] This application does not limit the type of at least one logical unit in the transmission module.

[0071] In some implementations, as shown in FIG5 , the system further includes: a sequence determination module, a reverse sequence number determination module, and a sorting module; the sequence determination module, the reverse sequence number determination module, and the sorting module can be integrated in the computing unit, the sequence determination module being configured to: determine a first positive sequence number, determine the original sequence according to the first positive sequence number, and send the original sequence to the first register; the reverse sequence number determination module being configured to: obtain from the second register the binary number of the reverse sequence number corresponding to each value in the original sequence, determine the reverse sequence number corresponding to each value in the original sequence according to the binary number of the reverse sequence number corresponding to each value in the original sequence, and send the reverse sequence number corresponding to each value in the original sequence to the sorting module; the sorting module being configured to: obtain, according to the reverse sequence number corresponding to each value in the original sequence, a plurality of transformation results arranged according to a second positive sequence number, the second positive sequence number being the sorting sequence number of the plurality of transformation results from front to back in the target polynomial under the point value expression method, and the plurality of transformation results being the results obtained by performing NTT or FFT on the target polynomial.

[0072] Combined with the above analysis, it can be seen that the multiple transformation results arranged according to the second positive sequence number are the multiple transformation results arranged in positive order. To obtain the multiple transformation results arranged in positive order, it is necessary to perform inverse transformation on the multiple coefficients arranged in positive order, or to perform inverse transformation on the multiple transformation results arranged in reverse order, that is, it is necessary to convert the multiple coefficients arranged in positive order into the multiple coefficients arranged in reverse order, or to convert the multiple transformation results arranged in reverse order into the multiple transformation results arranged in positive order. In other words, it is necessary to determine the inverse number of the sorting number of the multiple coefficients arranged in positive order in the positive order, or to determine the inverse number of the sorting number of the multiple transformation results arranged in positive order in the reverse order. Therefore, the above original sequence can include two categories: the sorting numbers of the multiple transformation results arranged in positive order in the reverse order, and the sorting numbers of the multiple coefficients arranged in positive order in the positive order.

[0073] In some examples, after determining the original sequence, the computing unit may directly send the original sequence to the reverse processing unit, which may determine the binary number of each value in the original sequence. Alternatively, after determining the original sequence, the computing unit may determine the binary number of each value in the original sequence and send the binary number of each value in the original sequence to the reverse processing unit.

[0074] The calculation unit can directly send the original sequence or the binary number of each value in the original sequence to the reverse processing unit, or can send the original sequence or the binary number of each value in the original sequence to the reverse processing unit based on the judgment unit. That is, the calculation unit can first send the original sequence or the binary number of each value in the original sequence to the judgment unit, and the judgment unit then sends the original sequence or the binary number of each value in the original sequence to the reverse processing unit. The judgment unit will be introduced in subsequent embodiments of this application and will not be described in detail here.

[0075] This application will introduce the above two types of original sequences and multiple transformation results of the positive sequence arrangement in detail in the following embodiments.

[0076] In some examples, the sequence determination module is specifically configured to: sort multiple coefficients according to a first positive sequence number, perform NTT or FFT on the sorted multiple coefficients to obtain multiple transformation results arranged according to the first sequence number, and combine the first sequence numbers into an original sequence; the reverse sequence number determination module is specifically configured to: obtain the binary number of the reverse sequence number corresponding to each sequence number in the first sequence number from the second register, determine the reverse sequence number corresponding to each sequence number in the first sequence number according to the binary number of the reverse sequence number corresponding to each sequence number in the first sequence number, and send the reverse sequence number corresponding to each sequence number in the first sequence number to the sorting module; the sorting module is specifically configured to: obtain multiple transformation results from the sequence determination module, for each transformation result in the multiple transformation results, determine the reverse sequence number of the transformation result when sorted according to the first sequence number as the sorting sequence number of the transformation result when arranged according to the second positive sequence number, and rearrange the multiple transformation results according to the sorting sequence numbers of the multiple transformation results when arranged according to the second positive sequence number to obtain multiple transformation results arranged according to the second positive sequence number.

[0077] It can be understood that the first positive sequence number is the sorting number of the multiple coefficients arranged in positive order in the positive sequence, the above-mentioned first sequence number is the sorting number of the multiple transformation results arranged in positive order in the reverse order, and the multiple transformation results arranged according to the second positive sequence number are the multiple transformation results arranged in positive order.

[0078] Exemplarily, the number of bits of the binary digit of each serial number in the first serial number may be consistent with the number of binary bits that can be stored in the first register.

[0079] For example, assume that the target polynomial is Z2(x)=x(0)+x(1)*x+x(2)*x 2 +x(3)*x 3 +x(4)*x 4 +x(5)*x 5 +x(6)*x 6 +x(7)*x 7 +x(8)*x 8 +x(9)*x 9 +x(10)*x 10 +x(11)*x 11 +x(12)*x1 2 +x(13)*x 13 +x(14)*x 14 +x(15)*x 15, the 16 coefficients of the target polynomial Z2(x) are: x(0), x(1), x(2), x(3), x(4), x(5), x(6), x(7), x(8), x(9), x(10), x(11), x(12), x(13), x(14), x(15). After performing NTT or FFT on the target polynomial Z2(x), the 16 transformation results of the target polynomial Z2(x) can be obtained: X(0), X(1), X(2), X(3), X(4), X(5), X(6), X(7), X(8), X(9), X(10), X(11), X(12), X(13), X(14), X(15). The order of the above 16 coefficients in the polynomial Z2(x) from front to back is: x(0), x(1), x(2), x(3), x(4), x(5), x(6), x(7), x(8), x(9), x(10), x(11), x(12), x(13), x(14), x(15). Then the order of the 16 coefficients in the polynomial Z2(x) from front to back is: 0, 1 , 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, that is, the first positive sequence number of the 16 coefficients is: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and the sorting sequence numbers of the 16 coefficients in the positive sequence are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15. The calculation unit can be configured to sort the 16 coefficients according to the first positive sequence number, and the 16 coefficients after sorting are: x(0), x(1), x(2), x(3), x(4), x(5), x(6), x(7), x(8), x(9), x(10), x(11), x(12), x(13), x(14), x(15). Then, as shown in FIG6 , the calculation unit can be configured to take the 16 coefficients after sorting as the input of the butterfly operation, using FIG6 The butterfly operation shown performs NTT or FFT on the sorted multiple coefficients, and 16 transformation results arranged according to the first serial number, that is, 16 transformation results arranged in reverse order, can be obtained: X(0), X(8), X(4), X(12), X(2), X(10), X(6), X(14), X(1), X(9), X(5), X(13), X(3), X(11), X(7), X(15), where "G" in Figure 6 is the rotation factor of NTT or FFT.The calculation unit can be configured to determine the first sequence number based on the plurality of coefficients arranged according to the first sequence number. For example, the calculation unit can be configured to determine the first sequence number as 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15 based on the 16 transformation results arranged according to the first sequence number, that is, the sorting sequence numbers of the 16 transformation results X(0), X(1), X(2), X(3), X(4), X(5), X(6), X(7), X(8), X(9), X(10), X(11), X(12), X(13), X(14), X(15) arranged in the forward order are respectively 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15 in the reverse order. Then, the calculation unit can be configured to send the first sequence number to the reverse order processing unit. For each serial number in the first serial number, the first register storing a 4-bit binary number in the inversion processing unit can obtain the binary number of the serial number. For example, for the serial number "1" in the first serial number, the binary number of the serial number "1" is 0001. The first register can store a 4-bit binary number. The position storing the 0th binary number, the position storing the 1st binary number, the position storing the 2nd binary number, and the position storing the 3rd binary number in the first register can be set to store the first numerical value "0", the second numerical value "0", the third numerical value "0", and the fourth numerical value "1" of the binary number "0001" of the serial number "1", respectively. Next, the inversion processing unit can be configured to transmit the vth binary number in the first register to the position storing the 4-v-1th binary number in the second register storing the 4-bit binary number based on the transmission module, where v is a natural number, to obtain the binary number of the inverse serial number of the serial number "1". Among them, when the first register includes 4 first triggers, the input ends of the 4 first triggers respectively obtain the first numerical value "0", the second numerical value "0", the third numerical value "0", and the fourth numerical value "1" of the binary number "0001", and the output ends of the 4 first triggers are all connected to the transmission module. When the second register includes 4 second triggers, the input ends of the 4 second triggers are all connected to the transmission module, and the input ends of the 4 second triggers respectively output the fourth numerical value "1", the third numerical value "0", the second numerical value "0", and the first numerical value "0" of the binary number "0001". In this way, the binary number "0001" of the sequence number "1" can be quickly reversed without a large number of shifts or judgment operations. At this time, the binary number stored in the second register is "1000", and the reverse processing unit can determine the binary number "1000" stored in the second register as the binary number of the reverse sequence number "1". Similarly, the reverse processing unit can determine the binary numbers of the reversed numbers of other sequence numbers in the first sequence number. Then, the reverse processing unit can be configured to send the binary number of the reversed number of each sequence number in the first sequence number to the calculation unit.Afterwards, the calculation unit can be configured to determine the decimal number corresponding to the binary number of the inverse digit of each sequence number in the above-mentioned first sequence number as the inverse digit of the sequence number after receiving the binary number of the inverse digit of the sequence number. For example, for the binary number "1000" which is the inverse digit of the sequence number "1", the calculation unit can be configured to determine that the decimal number corresponding to the binary number "1000" is "8". Similarly, the calculation unit can be configured to determine that the inverse digits of the first sequence numbers "0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15" are "0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15". Then, for any of the above-mentioned 16 transformation results, the calculation unit can be configured to determine the inverse digit of the sequence number of the transformation result when it is sorted according to the first sequence number as the sorting sequence number of the transformation result when it is arranged according to the second positive sequence number. For example, for the transformation result X(1), the sequence number of X(1) when it is sorted according to the first sequence number is "1", and the reverse sequence number of the sequence number "1" is "8". It can be determined that the sorting sequence number of X(1) when it is arranged according to the second positive sequence number is the reverse sequence number of the above sequence number "1". Similarly, the calculation unit can be set to be the 16 transformation results X(0), X(8), X(4), X(12), X(2), X(10), X(6), X(14), X(1), X(9), X(5), X(13), X(3), X(11), X(7), X(15) when they are arranged according to the first sequence number. The sorting numbers are: 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15. Then, the calculation unit can be set to rearrange the 16 transformation results according to the sorting numbers of the above 16 transformation results when they are arranged according to the second positive sequence number. As shown in Figure 6, the multiple transformation results arranged according to the second positive sequence number are: X(0), X(1), X(2), X(3), X(4), X(5), X(6), X(7), X(8), X(9), X(10), X(11), X(12), X(13), X(14), X(15).

[0080] In other examples, the sequence determination module is specifically configured to: combine the first positive sequence numbers into an original sequence; the reverse sequence number determination module is specifically configured to: obtain the binary number of the reverse sequence number corresponding to each positive sequence number in the first positive sequence number from the second register, determine the reverse sequence number corresponding to each positive sequence number in the first positive sequence number according to the binary number of the reverse sequence number corresponding to each positive sequence number in the first positive sequence number, and send the reverse sequence number corresponding to each positive sequence number in the first positive sequence number to the sorting module; the sorting module is specifically configured to: for each coefficient in a plurality of coefficients, determine the reverse number of the positive sequence number corresponding to the coefficient in the first positive sequence number as the rearranged sorting number of the coefficient, reorder the plurality of coefficients according to the rearranged sorting numbers corresponding to the plurality of coefficients, perform NTT or FFT on the plurality of reordered coefficients, and obtain a plurality of transformation results arranged according to the second positive sequence number.

[0081] It can be understood that the first positive sequence number is the sorting number of the multiple coefficients arranged in positive order in the positive sequence, the rearranged sorting number of the above coefficients is the sorting number of the multiple coefficients arranged in positive order in the reverse order, and the multiple transformation results arranged according to the second positive sequence number are the multiple transformation results arranged in positive order.

[0082] Exemplarily, the number of bits of the binary digit of each positive sequence number in the first positive sequence number may be consistent with the number of binary bits that can be stored in the first register.

[0083] For example, assume that the target polynomial is Z3(x)=x(0)+x(1)*x+x(2)*x 2 +x(3)*x 3, the four coefficients of the target polynomial Z3(x) are: x(0), x(1), x(2), x(3). After performing NTT or FFT on the target polynomial Z3(x), the four transformation results of the target polynomial Z3(x) can be obtained: X(0), X(1), X(2), X(3). The calculation unit can be set to determine the sorting sequence of the four coefficients from front to back in the polynomial Z3(x) as the first positive sequence number. For example, the sorting sequence of the above four coefficients from front to back in the polynomial Z3(x) is: x(0), x(1), x(2), x(3). The sorting sequence numbers of the four coefficients from front to back in the polynomial Z3(x) are: 0, 1, 2, 3. The calculation unit can determine the first positive sequence numbers of the four coefficients as: 0, 1, 2, 3, that is, the sorting sequence numbers of the four coefficients in the positive sequence are: 0, 1, 2, 3. Then, the calculation unit can be configured to send the first positive sequence number to the reverse processing unit. After obtaining the first positive sequence number, the reverse processing unit can input the binary number of the positive sequence number into the first register storing 2-bit binary numbers for any positive sequence number in the first positive sequence number. For example, for the positive sequence number "1" in the first positive sequence number, the binary number of the positive sequence number "1" is 01. The first register can store 2-bit binary numbers. The position storing the 0th binary number and the position storing the 1st binary number in the first register can be respectively set to store the first value "0" and the second value "1" of the binary number "01" of the positive sequence number "1". Then, the reverse processing unit can be configured to transmit the vth binary number in the first register to the position storing the 2-v-1th binary number in the second register storing the 2-bit binary number based on the transmission module, where v is a natural number, to obtain the binary number of the reverse number of the positive sequence number "1". Among them, when the first register includes two first triggers, the input ends of the two first triggers respectively obtain the first numerical value "0" and the second numerical value "1" of the binary number "01", and the output ends of the two first triggers are both connected to the transmission module. When the second register includes two second triggers, the input ends of the two second triggers are both connected to the transmission module, and the input ends of the two second triggers respectively output the second numerical value "1" and the first numerical value "0" of the binary number "01". In this way, the binary number "01" of the positive sequence number "1" can be quickly reversed without a large number of shifts or judgment operations. At this time, the binary number stored in the second register is "10", then the reverse processing unit can determine the binary number "10" stored in the second register as the binary number of the reverse number of the positive sequence number "1". The reverse processing unit can similarly determine the binary numbers of the reverse numbers of other positive sequence numbers in the first positive sequence number. Next, the reverse sequence processing unit may be configured to send the binary number of the reverse sequence number of each positive sequence number in the first positive sequence number to the calculation unit.Afterwards, the calculation unit can be configured to, after receiving the binary number of the reverse digit of each positive sequence number in the above-mentioned first positive sequence number, determine the decimal number corresponding to the binary number of the reverse digit of the positive sequence number as the reverse digit of the positive sequence number. For example, for the binary number "10" which is the reverse digit of the positive sequence number "1", the calculation unit can be configured to determine that the decimal number corresponding to the binary number "10" is "2". Similarly, the reverse processing unit can be configured to determine that the reverse digits of the first positive sequence numbers "0, 1, 2, 3" are respectively "0, 2, 1, 3". Then, for any coefficient among the four coefficients, the calculation unit can be configured to determine the reverse digit of the positive sequence number corresponding to the coefficient in the first positive sequence number as the rearranged sorting number of the coefficient. For example, for the coefficient x(1), the calculation unit can be configured to determine that the positive sequence number corresponding to x(1) in the first positive sequence number is "1", and then the rearranged sorting number of x(1) can be determined to be: 2. The calculation unit can be configured to similarly determine that the rearranged sorting numbers of the four coefficients x(0), x(1), x(2), and x(3) are respectively: 0, 2, 1, and 3, that is, the sorting numbers of the four coefficients in the positive order are respectively: 0, 2, 1, and 3 in the reverse order. Then, the calculation unit can be configured to rearrange the four coefficients according to their respective rearranged sorting numbers, and the four rearranged coefficients are: x(0), x(2), x(1), and x(3). Next, as shown in FIG7 , the calculation unit can be configured to use the rearranged four coefficients as the input of the butterfly operation, and perform NTT or FFT on the rearranged four coefficients using the butterfly operation shown in FIG7 . As shown in FIG7 , four transformation results arranged in the second positive sequence, i.e., four transformation results arranged in positive sequence, can be obtained: X(0), X(1), X(2), X(3), where “G” in FIG7 is the rotation factor of the NTT or FFT.

[0084] In some implementations, the computing unit may include a high-order accelerator, such as a 256-byte high-order accelerator, which may include a 256-byte register file. The computing unit may perform operations such as butterfly operations corresponding to FFT or NTT based on the high-order accelerator.

[0085] It is understandable that the butterfly operation corresponding to NTT requires the use of the modulus of the finite field in the zero-knowledge proof (ZKP), and ZKP generally uses an ultra-large prime number close to 256 bytes as the modulus of the finite field. Therefore, high-bit accelerators such as 256-byte high-bit accelerators can achieve higher bit-width data processing and realize polynomial processing in a wider range.

[0086] In some possible implementations, the above embodiments may be programmed to obtain programming codes, and then a polynomial processing system may be controlled based on the programming codes to implement the methods in the above embodiments.

[0087] For example, the methods in the above embodiments can be programmed to generate assembly language. This assembly language can then be compiled into a binary file, which can be stored in a polynomial processing system. The polynomial processing system can then decode the binary file to generate a decoded file, and the polynomial processing system can implement the methods in the above embodiments based on the decoded file. The decoded file can include instructions, and units or modules in the polynomial processing system can execute the methods in the above embodiments based on the instructions.

[0088] For example, for the embodiment of determining multiple transformation results arranged in positive order (i.e., multiple transformation results arranged in a second positive order) based on multiple coefficients arranged in positive order (i.e., multiple coefficients arranged in a first positive order), an assembly language comprising three loop layers can be determined: big_loop, middle_loop, and small_loop. The big_loop is the first loop layer, which determines the number of butterfly operations performed, L, where L is a positive integer and is the logarithm of the number of coefficients to the base 2. As shown in Figure 3, if the number of coefficients is 16, the number of layers can be determined to be 4. This number of layers is represented by the number of "arrow combinations" between the five columns of "small circles" in Figure 3, with the "arrows" between two columns of "small circles" forming one "arrow combination." The middle_loop is the second loop layer, which determines butterfly operation parameters such as the number of butterfly operations per layer, the twiddle factors, and the order of the coefficients in the butterfly operation input. The small_loop is the third-level loop, which performs specific computational operations, such as butterfly operations on multiple coefficients and twiddle factors. These operations include addition, subtraction, multiplication, modular addition, modular subtraction, and modular multiplication. The total number of second and third-level loops is half the number of coefficients in the polynomial.

[0089] The assembly code of big_loop can be shown as follows.

[0090] The power of the number of coefficients can be calculated first. Since the number of coefficients is a power of 2, the number of "0"s at the end of the binary number of the coefficients can be determined as the number of levels, L. "t1, t2, t3, t4, t5, t6" and "a1, a2, a3, a4, a5, a6" in the assembly program represent registers in the polynomial processing system.

[0091] The assembly code of middle_loop can be shown as follows.

[0092] The assembly code of small_loop can be shown as follows.

[0093] The small_loop retrieves the coefficients from memory into registers based on the index of the butterfly operation input calculated in the middle_loop, and then performs the butterfly operation. Since the subtraction, addition, and multiplication in butterfly operations are all performed over finite fields and their implementation is somewhat complex, specialized code can be used to implement these operations, as shown below.

[0094] For the modular subtraction (mod_sub) operation, you can first determine whether the minuend is less than the subtrahend. When the minuend is greater than or equal to the subtrahend, directly use the arithmetic subtraction instruction to get the result; when the minuend is less than the subtrahend, it is necessary to perform arithmetic addition on the minuend and the modulus Modulus of the finite field to ensure that the minuend is greater than the subtrahend and the difference between the minuend and the subtrahend is less than Modulus-1, and then perform arithmetic subtraction on the minuend and the subtrahend.

[0095] For the modular addition (mod_add) operation, you can directly perform arithmetic addition on the two addends and then determine whether the result is greater than or equal to the Modulus. If the result is greater than the Modulus, perform arithmetic subtraction on the result and the Modulus; if the result is less than or equal to the Modulus, retain the original result.

[0096] The assembly program for modular subtraction and modular addition operations can be shown as follows.

[0097] For modular multiplication operations, Montgomery modular multiplication can be used, and its assembly program is shown below.

[0098] Here, the constant INV = -Modulus^-1 mod 2^256 can be determined. Next, for the two numbers involved in the modular multiplication, the 512-byte arithmetic multiplication result is first calculated. The lower 256 bits of this result are then multiplied by the constant INV, retaining only the lower 256 bits and recording them as a temporary variable k. K is then multiplied by the Modulus, and this result is added to the arithmetic product of the two multipliers obtained previously. The lower 256 bits of the added result are all 0s, and the upper 256 bits of the added result are the result of the Montgomery modular multiplication. This result is numerically equal to the result of the 512-bit arithmetic product modulo the Modulus. However, arithmetic modulo requires arithmetic division, and arithmetic division on 256 bytes is approximately 60-70 times more complex than multiplication. Therefore, using Montgomery modular multiplication can improve computing performance.

[0099] After each small_loop completes, the following assembly program can be used to send the calculation results and other data from the data storage register back to the memory, and then retrieve the coefficients and other data from the memory to continue the loop until the loop ends. This ping-pong memory access method can fully utilize the computing components and improve computing efficiency.

[0100] Finally, the following assembly program can be used to process the multiple transformation results in reverse order obtained through the above three-layer loop into multiple transformation results in forward order based on the reverse processing instruction, such as the bfly instruction.

[0101] In the "bfly t1,t5,a6" section of the above assembly program, "bfly" represents the name of the bfly instruction, and "t1," "t2," and "a6" represent the three fields of the bfly instruction. "t1" is set to specify register t1 as the destination register, which is configured to store the destination operand, which includes the binary number of each value in the original sequence; "t2" is set to specify register t2 as the first source register, which is configured to store the first source operand, which includes the binary number of the reversed digit of each value in the original sequence; and "a6" is set to specify register a6 as the second source register, which is configured to store the second source operand, which includes the base-2 logarithm of the reversed length, which is the number of bits in the binary number of any value in the original sequence.

[0102] In some implementable methods, C language can also be written according to the above embodiment, and the C language can call the above assembly program or assembly language. Afterwards, the C language can be compiled into a binary file, and the binary file can be stored in the polynomial processing system. The polynomial processing system can decode the binary file to obtain a decoded file, and the polynomial processing system can implement the method in the above embodiment according to the decoded file.

[0103] Exemplarily, the following C language can be used to implement determining multiple transformation results based on multiple coefficients arranged in positive order.

[0104] Exemplarily, determining multiple transformation results based on multiple coefficients arranged in reverse order can be implemented using the following C language.

[0105] Among them, root is the rotation factor, low and high are two coefficients in the multiple coefficients arranged in positive order, sub_assign_fp_256, add_assign_fp_256, and mul_assign_fp_256 respectively call the modular subtraction operation, modular addition operation, and modular multiplication operation in the above assembly program.

[0106] In some possible implementations, as shown in FIG8 , the polynomial processing system further includes a judgment unit and an adjustment unit; the judgment unit is configured to: obtain an original sequence, determine a target binary number of the value for each value in the original sequence, judge the number of bits of the target binary number and the size of V, obtain a first judgment result, and send the first judgment result to the adjustment unit; the adjustment unit is configured to: when the first judgment result is that the number of bits of the target binary number is greater than V or less than V, adjust the target binary number to obtain a V-bit binary number of the value, send the V-bit binary number of the value to the inversion processing unit, and obtain the binary number of the inverse number of the value based on the inversion processing unit.

[0107] In some examples, the adjustment unit is configured to: when the first judgment result is that the number of bits of the target binary number is equal to V, send the target binary number of each numerical value in the original sequence to the inverse processing unit, and the inverse processing unit can determine the binary number of the inverse number of each numerical value according to the method in the above embodiment.

[0108] In some examples, the adjustment unit is configured to: after obtaining the binary number of the inverse number of the numerical value based on the inverse processing unit, the binary number of the inverse number of the numerical value can be sent to the calculation unit, and the calculation unit can be configured to use the method in the above embodiment to determine multiple transformation results arranged according to the second positive sequence number based on the binary number of the inverse number of each numerical value.

[0109] In some examples, the calculation unit may determine the original sequence according to the method in the above embodiment, and send the original sequence to the judgment unit, and the judgment unit may obtain the original sequence.

[0110] In other examples, the determination unit may determine the original sequence in a manner similar to the manner in which the calculation unit determines the original sequence, thereby obtaining the original sequence.

[0111] In some examples, as shown in Figure 9, the adjustment unit includes a zero-padding module, a transceiver module, and a shift module; the zero-padding module is configured to: when the first judgment result is that the number of bits of the target binary number is less than V, perform high-bit zero padding or low-bit zero padding on the target binary number to obtain a V-bit binary number of the numerical value; the transceiver module is configured to: obtain the V-bit binary number of the numerical value from the zero-padding module, send the V-bit binary number of the numerical value to the inversion processing unit, obtain the fifth binary number corresponding to the V-bit binary number of the numerical value from the inversion processing unit, and send the fifth binary number to the shift module; the shift module is configured to: remove the zeros corresponding to the high-bit zero padding or low-bit zero padding in the fifth binary number until the number of bits of the fifth binary number is equal to the number of bits of the target binary number, to obtain the binary number of the inverse number of the numerical value.

[0112] Exemplarily, when the zero-padding module is configured to pad the high-order bits of the target binary number with zeros, the shift module is configured to remove the least significant zero in the fifth binary number until the number of bits of the fifth binary number equals the number of bits of the target binary number, thereby obtaining the binary number of the reversed digit of the value. When the zero-padding module is configured to pad the low-order bits of the target binary number with zeros, the shift module is configured to remove the most significant zero in the fifth binary number until the number of bits of the fifth binary number equals the number of bits of the target binary number, thereby obtaining the binary number of the reversed digit of the value.

[0113] For example, assuming V is 4, the target binary number for the value "1" in the original sequence is 001. The judgment unit determines that the number of bits in the target binary number, "3," is less than 4, resulting in a first judgment result that the number of bits in the target binary number is less than 4. The zero-padding module is configured to pad the high-order bits of the target binary number "001" with zeros, resulting in a 4-bit binary number for the value "1" of 0001. The transceiver module is configured to obtain the 4-bit binary number "0001" from the zero-padding module and send the 4-bit binary number "0001" to the inversion processing unit. The inversion processing unit determines that the binary number of the inversion number corresponding to the 4-bit binary number "0001" is 1000, that is, determines the fifth binary number to be 1000. After obtaining the fifth binary number "1000" from the inversion processing unit, the transceiver module sends the fifth binary number "1000" to the shift module. The shift module is configured to remove the zeros corresponding to the high-order zero padding in the fifth binary number "1000" until the number of bits of the fifth binary number "1000" is equal to the number of bits of the target binary number "3", that is, the shift module is configured to remove the lowest-order 0 in the fifth binary number "1000" to obtain the binary number of the inverse of the numerical value, so that the binary number of the inverse of the numerical value "1" is "100".

[0114] In other examples, as shown in Figure 10, the adjustment unit includes a multiple module, a processing module, and a splicing module; the multiple module is configured to: when the first judgment result is that the number of bits of the target binary number is greater than V, determine whether the number of bits of the target binary number is an integer multiple of V, obtain a second judgment result, and send the second judgment result to the processing module; the processing module is configured to: process the target binary number according to the second judgment result to obtain multiple V-bit sixth binary numbers, and send the multiple V-bit sixth binary numbers to the splicing module; the splicing module is configured to: send the multiple V-bit sixth binary numbers to the inverse processing unit, and obtain the binary number of the inverse number of the numerical value based on the inverse processing unit.

[0115] Exemplarily, the processing module is specifically configured as follows: when the second judgment result is that the number of bits of the target binary number is an integer multiple of V, the target binary number is split into multiple V-bit sixth binary numbers in a first order, and the first order is the order from the highest bit of the target binary number to the lowest bit of the target binary number; the splicing module is specifically configured as follows: for each V-bit sixth binary number in the multiple V-bit sixth binary numbers, the V-bit sixth binary number is sent to the inverse processing unit, and the seventh binary number corresponding to the V-bit sixth binary number is obtained from the inverse processing unit. The seventh binary numbers corresponding to the multiple V-bit sixth binary numbers are combined in the order of the multiple V-bit sixth binary numbers from back to front in the first order to obtain the binary number of the inverse number of the numerical value.

[0116] For example, assuming V is 2, and the target binary number of the value "2" in the original sequence is 0010, the judgment unit determines that the number of digits "4" of the target binary number "0010" is greater than 2, obtaining a first judgment result that the number of digits of the target binary number is greater than 2, and sending the first judgment result to the multiple module. The multiple module is configured to, when the first judgment result is that the number of digits of the target binary number is greater than 2, determine that the number of digits of the target binary number "4" is an integer multiple of 2, obtain a second judgment result, and send the second judgment result to the processing module. The processing module is configured to split the target binary number "0010" into two 2-bit sixth binary numbers in order from the most significant bit to the least significant bit of the target binary number, the two 2-bit sixth binary numbers being 00 and 10, respectively, and send the two 2-bit sixth binary numbers to the splicing module. The splicing module is configured to, for each of the two sixth binary numbers, send the 2-bit sixth binary number to the inversion processing unit. The reverse processing unit determines that the binary numbers of the reversed numbers corresponding to the two sixth binary numbers "00" and "10" are 00 and 01, respectively. That is, the seventh binary numbers corresponding to the two sixth binary numbers "00" and "10" are 00 and 01, respectively. The splicing module obtains the seventh binary numbers corresponding to the two sixth binary numbers from the reverse processing unit, and combines the seventh binary numbers corresponding to the two sixth binary numbers in the order of the two sixth binary numbers from back to front in the target binary number, obtaining the binary number of the reversed number of the value: 0100.

[0117] Exemplarily, the processing module is specifically configured to: when the second judgment result is that the number of bits of the target binary number is not an integer multiple of V, padding the target binary number with zeros at the upper or lower bits to obtain an eighth binary number, the number of bits of the eighth binary number is an integer multiple of V, and splitting the eighth binary number into multiple V-bit sixth binary numbers in the second sequence, the second sequence being the order from the highest bit of the eighth binary number to the lowest bit of the target binary number; the splicing module is specifically configured to: for each V-bit sixth binary number in the multiple V-bit sixth binary numbers, send the V-bit sixth binary numbers to the inverse processing unit, obtain the ninth binary number corresponding to the V-bit sixth binary number from the inverse processing unit, combine the ninth binary numbers corresponding to the multiple V-bit sixth binary numbers in the order from back to front in the second sequence to obtain a tenth binary number corresponding to the numerical value, remove the zeros corresponding to the high-bit zero padding or the low-bit zero padding in the tenth binary number, until the number of bits of the tenth binary number is equal to the number of bits of the target binary number, and obtain the binary number of the inverse number of the numerical value.

[0118] For example, when the processing module is configured to pad the high-order bits of the target binary number with zeros, the splicing module is configured to remove the zeros of the lowest bit in the tenth binary number until the number of digits of the tenth binary number is equal to the number of digits of the target binary number, thereby obtaining the binary number of the reversed digit of the value. When the processing module is configured to pad the low-order bits of the target binary number with zeros, the splicing module is configured to remove the zeros of the highest bit in the tenth binary number until the number of digits of the tenth binary number is equal to the number of digits of the target binary number, thereby obtaining the binary number of the reversed digit of the value.

[0119] For example, assuming V is 2, and the target binary number for the value "3" in the original sequence is 011, the judgment unit determines that the number of digits "3" in the target binary number "011" is greater than 2, resulting in a first judgment result that the number of digits in the target binary number is greater than 2, and sends the first judgment result to the multiple module. The multiple module is configured to, when the first judgment result indicates that the number of digits in the target binary number is greater than 2, determine that the number of digits in the target binary number "3" is not an integer multiple of 2, and obtain a second judgment result that the number of digits in the target binary number is not an integer multiple of 2, and send the second judgment result to the processing module. The processing module is configured to pad the high-order bits of the target binary number "011" with zeros to obtain an eighth binary number "0011" whose number of digits is an integer multiple of 2, "4". The processing module splits the eighth binary number "0011" into two 2-bit sixth binary numbers: 00 and 11, in order from the most significant bit of the eighth binary number to the least significant bit of the target binary number. The concatenation module is specifically configured to send each of the two sixth binary numbers to the inversion processing unit. The inversion processing unit can determine that the binary numbers of the inverse numbers corresponding to the two sixth binary numbers "00" and "11" are respectively 00 and 11, that is, determine that the ninth binary numbers corresponding to the two sixth binary numbers "00" and "11" are respectively 00 and 11. The splicing module obtains the above-mentioned two ninth binary numbers "00" and "11" from the inversion processing unit, and combines the ninth binary numbers "00" and "11" corresponding to the two sixth binary numbers "00" and "11" in the order from back to front of the two sixth binary numbers "00" and "11" in the eighth binary number, thereby obtaining a tenth binary number corresponding to the value "3": 1100. The least significant zero in the tenth binary number "1100" is removed until the number of bits of the tenth binary number "1100" is equal to the number of bits of the target binary number "3", thereby obtaining a binary number of the inverse number of the value "110".

[0120] In the above embodiment, the polynomial processing system can judge the number of bits of the binary number of each value in the initial sequence, and when the number of bits of the binary number of the value is not the number of binary bits that can be stored by the inversion processing unit, the binary number of the value is processed, so that the inversion processing unit can perform inversion processing on binary numbers of any number of bits, thereby improving the flexibility of the inversion processing.

[0121] In some implementations, as shown in FIG11 , the V-bit binary number stored in the first register is: V0V1…V V-1 , V0, V1, ..., V V-1 is 0 or 1, the second register can store V-bit binary numbers "V0V1......V V-1 "The binary number corresponding to the reverse order number" V V-1 ...V0V1", the transmission module can connect the first register and the second register, and directly transmit the v-th binary number in the first register to the position where the Vv-1-th binary number is stored in the second register, thereby quickly realizing the reverse transformation and improving the efficiency of polynomial processing.

[0122] Figure 12 is a flowchart of a polynomial processing method provided in an embodiment of the present application. The method is applied to a polynomial processing system. The system includes a reverse processing unit, which includes: a first register storing a V-bit binary number, a transmission module connected to the first register, and a second register storing a V-bit binary number connected to the transmission module, where V is a positive integer. As shown in Figure 12, the polynomial processing method may include the following steps:

[0123] S1210: For each value in the original sequence, the first register obtains a V-bit binary number of the value, wherein the original sequence is determined based on a first positive sequence number, which is a sequence number of the coefficients of the target polynomial from front to back in the target polynomial;

[0124] S1220: The transmission module transmits the v-th binary number in the first register to the location where the Vv-1-th binary number is stored in the second register, where v is a natural number;

[0125] S1230: The second register obtains the v-th binary number from the transmission module, and obtains the binary number of the reverse digit of the value.

[0126] In some implementations, the transmission module includes an ALU; the ALU transmits the v-th binary number in the first register to a location in the second register where the Vv-1-th binary number is stored.

[0127] In some implementations, the first register includes V first flip-flops, and the second register includes V second flip-flops; the vth first flip-flop among the V first flip-flops obtains the vth binary number in the V-bit binary number based on the input end of the vth first flip-flop; the output end of the vth first flip-flop is connected to the ALU; the Vv-1th second flip-flop among the V second flip-flops outputs the vth binary number based on the output end of the Vv-1th second flip-flop; the input end of the vth second flip-flop is connected to the ALU.

[0128] In some implementations, the V first flip-flops and the V second flip-flops are triggered by a same clock signal.

[0129] In some implementations, a clock control terminal of each of the V first flip-flops and the V second flip-flops is connected to the same clock control line.

[0130] In some implementations, the inverse processing unit obtains a inverse processing instruction, the inverse processing instruction including: a first field and a second field, the first field specifies a first register as a source register, the source register stores a source operand, the source operand includes a V-bit binary number of each numerical value in the original sequence, the second field specifies a second register as a destination register, the destination register stores a destination operand, the destination operand includes the binary number of the inverse number of each numerical value in the original sequence; the inverse processing instruction is executed to obtain a specific result of the inverse processing instruction, and the inverse processing instruction is executed to obtain a specific result of the inverse processing instruction, including: for each V-bit binary number in the source operand, the V-bit binary number is shifted right by i bits to obtain a first binary number, the first binary number is bitwise ANDed with the second binary number to obtain a third binary number, the second binary number is a binary number corresponding to the decimal number 1, the third binary number is shifted left by Vi-1 bits to obtain a fourth binary number, i is an integer from 0 to V-1, and each fourth binary number is bitwise ORed to obtain the binary number of the inverse number corresponding to the V-bit binary number in the destination operand.

[0131] In some possible implementations, the system further includes: a sequence determination module, a reverse sequence number determination module, and a sorting module; the sequence determination module determines a first positive sequence number, determines the original sequence based on the first positive sequence number, and sends the original sequence to the first register; the reverse sequence number determination module obtains the binary number of the reverse sequence number corresponding to each value in the original sequence from the second register, determines the reverse sequence number corresponding to each value in the original sequence based on the binary number of the reverse sequence number corresponding to each value in the original sequence, and sends the reverse sequence number corresponding to each value in the original sequence to the sorting module; the sorting module obtains a plurality of transformation results arranged according to a second positive sequence number based on the reverse sequence number corresponding to each value in the original sequence, the second positive sequence number being the sorting number of the plurality of transformation results from front to back in the target polynomial under the point value expression method, and the plurality of transformation results being the results obtained by performing NTT or FFT on the target polynomial.

[0132] In some possible implementations, the sequence determination module sorts the multiple coefficients according to the first positive sequence number, performs NTT or FFT on the sorted multiple coefficients to obtain multiple transformation results arranged according to the first sequence number, and combines the first sequence numbers into the original sequence; the reverse sequence number determination module obtains the binary number of the reverse sequence number corresponding to each sequence number in the first sequence number from the second register, determines the reverse sequence number corresponding to each sequence number in the first sequence number according to the binary number of the reverse sequence number corresponding to each sequence number in the first sequence number, and sends the reverse sequence number corresponding to each sequence number in the first sequence number to the sorting module; the sorting module obtains multiple transformation results from the sequence determination module, and for each transformation result in the multiple transformation results, determines the reverse sequence number of the transformation result when sorted according to the first sequence number as the sorting sequence number of the transformation result when arranged according to the second positive sequence number, and rearranges the multiple transformation results according to the sorting sequence numbers of the multiple transformation results when arranged according to the second positive sequence number to obtain multiple transformation results arranged according to the second positive sequence number.

[0133] In some possible implementations, the sequence determination module combines the first positive sequence numbers into an original sequence; the reverse sequence number determination module obtains the binary number of the reverse sequence number corresponding to each positive sequence number in the first positive sequence number from the second register, determines the reverse sequence number corresponding to each positive sequence number in the first positive sequence number according to the binary number of the reverse sequence number corresponding to each positive sequence number in the first positive sequence number, and sends the reverse sequence number corresponding to each positive sequence number in the first positive sequence number to the sorting module; the sorting module determines, for each coefficient in the multiple coefficients, the reverse number of the positive sequence number corresponding to the coefficient in the first positive sequence number as the rearranged sorting number of the coefficient, reorders the multiple coefficients according to the rearranged sorting numbers corresponding to the multiple coefficients, performs NTT or FFT on the reordered multiple coefficients, and obtains multiple transformation results arranged according to the second positive sequence number.

[0134] In some possible implementations, the system further includes a judgment unit and an adjustment unit; the judgment unit obtains an original sequence, determines a target binary number of each value in the original sequence, judges the number of bits of the target binary number and the size of V, obtains a first judgment result, and sends the first judgment result to the adjustment unit; when the first judgment result is that the number of bits of the target binary number is greater than V or less than V, the adjustment unit adjusts the target binary number to obtain a V-bit binary number of the value, sends the V-bit binary number of the value to the inverse processing unit, and obtains the binary number of the inverse number of the value based on the inverse processing unit.

[0135] In some possible implementations, the adjustment unit includes a zero-padding module, a transceiver module, and a shift module; when the first judgment result is that the number of bits of the target binary number is less than V, the zero-padding module pads the target binary number with zeros at the upper or lower bits to obtain a V-bit binary number of the numerical value; the transceiver module obtains the V-bit binary number of the numerical value from the zero-padding module, sends the V-bit binary number of the numerical value to the inverse processing unit, obtains the fifth binary number corresponding to the V-bit binary number of the numerical value from the inverse processing unit, and sends the fifth binary number to the shift module; the shift module removes the zeros corresponding to the high-bit zero-padding or low-bit zero-padding in the fifth binary number until the number of bits of the fifth binary number is equal to the number of bits of the target binary number, to obtain the binary number of the inverse number of the numerical value.

[0136] In some possible implementations, the adjustment unit includes a multiple module, a processing module, and a splicing module. When the first judgment result of the multiple module is that the number of bits of the target binary number is greater than V, the multiple module judges whether the number of bits of the target binary number is an integer multiple of V, obtains a second judgment result, and sends the second judgment result to the processing module; the processing module processes the target binary number according to the second judgment result, obtains multiple V-bit sixth binary numbers, and sends the multiple V-bit sixth binary numbers to the splicing module; the splicing module sends the multiple V-bit sixth binary numbers to the inverse processing unit, and obtains the binary number of the inverse number of the numerical value based on the inverse processing unit.

[0137] In some possible implementations, when the second judgment result of the processing module is that the number of bits of the target binary number is an integer multiple of V, the processing module splits the target binary number into multiple V-bit sixth binary numbers in a first order, and the first order is the order from the highest bit of the target binary number to the lowest bit of the target binary number; the splicing module sends the V-bit sixth binary number to the inverse processing unit for each V-bit sixth binary number in the multiple V-bit sixth binary numbers, obtains the seventh binary number corresponding to the V-bit sixth binary number from the inverse processing unit, and combines the seventh binary numbers corresponding to the multiple V-bit sixth binary numbers in the order from back to front in the first order to obtain the binary number of the inverse number of the numerical value.

[0138] In some possible implementations, when the second judgment result is that the number of bits of the target binary number is not an integer multiple of V, the processing module pads the target binary number with zeros at the upper or lower bits to obtain an eighth binary number, where the number of bits of the eighth binary number is an integer multiple of V, and splits the eighth binary number into multiple V-bit sixth binary numbers in a second sequence, where the second sequence is the sequence from the highest bit of the eighth binary number to the lowest bit of the target binary number; the splicing module sends the V-bit sixth binary numbers to the inverse processing unit for each V-bit sixth binary number in the multiple V-bit sixth binary numbers, obtains the ninth binary number corresponding to the V-bit sixth binary number from the inverse processing unit, combines the ninth binary numbers corresponding to the multiple V-bit sixth binary numbers in the order from back to front in the second sequence, obtains a tenth binary number corresponding to the numerical value, removes the zeros corresponding to the high-bit zero padding or the low-bit zero padding in the tenth binary number, until the number of bits of the tenth binary number is equal to the number of bits of the target binary number, and obtains the binary number of the inverse number of the numerical value.

[0139] It should be noted that the embodiments of the polynomial processing method are similar to the embodiments of the above-mentioned polynomial processing system. The content and effects of the polynomial processing method can refer to the content and effects of the above-mentioned polynomial processing system, and this application will not repeat them here.

[0140] The preferred embodiments of the present application are described in detail above in conjunction with the accompanying drawings. However, the present application is not limited to the specific details in the above embodiments. Within the technical concept of the present application, a variety of simple modifications can be made to the technical solution of the present application, and these simple modifications all fall within the scope of protection of the present application. For example, the various specific technical features described in the above specific embodiments can be combined in any suitable manner unless there is any contradiction. In order to avoid unnecessary repetition, the present application will not further explain various possible combinations. For another example, the various different embodiments of the present application can also be arbitrarily combined, and as long as they do not violate the ideas of the present application, they should also be regarded as the contents disclosed in the present application.

[0141] FIG13 is a schematic block diagram of an electronic device 1300 provided in an embodiment of the present application.

[0142] As shown in FIG13 , the electronic device 1300 may include:

[0143] The memory 1310 and the processor 1320 are configured such that the memory 1310 stores a computer program and transmits the program code to the processor 1320. In other words, the processor 1320 can call and execute the computer program from the memory 1310 to implement the method in the embodiment of the present application.

[0144] For example, the processor 1320 may execute the above method embodiments according to the instructions in the computer program.

[0145] In some embodiments of the present application, the processor 1320 may include but is not limited to:

[0146] General-purpose processor, Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.

[0147] In some embodiments of the present application, the memory 1310 includes but is not limited to:

[0148] Volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DR RAM).

[0149] In some embodiments of the present application, the computer program may be divided into one or more modules, which are stored in the memory 1310 and executed by the processor 1320 to implement the method provided by the present application. The one or more modules may be a series of computer program instruction segments capable of implementing specific functions, and the instruction segments describe the execution process of the computer program in the electronic device.

[0150] As shown in FIG13 , the electronic device may further include:

[0151] The transceiver 1330 may be connected to the processor 1320 or the memory 1310 .

[0152] The processor 1320 may control the transceiver 1330 to communicate with other devices. Specifically, it may send information or data to other devices or receive information or data sent by other devices. The transceiver 1330 may include a transmitter and a receiver. The transceiver 1330 may further include an antenna, which may be one or more.

[0153] It should be understood that the various components in the electronic device are connected via a bus system, wherein the bus system includes not only a data bus but also a power bus, a control bus and a status signal bus.

[0154] The present application also provides a computer storage medium having a computer program stored thereon, which, when executed by a computer, enables the computer to perform the method of the above-mentioned method embodiment. In other words, the present application also provides a computer program product containing instructions, which, when executed by a computer, enables the computer to perform the method of the above-mentioned method embodiment.

[0155] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the computer can be caused to perform all or part of the corresponding processes in the various methods in the embodiments of the present application and generate the functions that can be realized by the various methods in the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0156] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0158] Modules described as separate components may or may not be physically separate, and components displayed as modules may or may not be physical modules, i.e., they may be located in one place or distributed across multiple network elements. Some or all of the modules may be selected based on actual needs to achieve the purpose of the present embodiment. For example, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module.

Claims

1. A polynomial processing system, wherein: The system includes a reverse processing unit, the reverse processing unit includes a first register storing a V-bit binary number, a transmission module connected to the first register, and a second register storing a V-bit binary number connected to the transmission module, where V is a positive integer; The first register is configured to: for each value in the original sequence, obtain a V-bit binary number of the value; The transmission module is configured to: transmit the v-th binary number in the first register to the position where the Vv-1-th binary number is stored in the second register, where v is a natural number; The second register is configured to: obtain the v-th binary number from the transmission module to obtain the binary number of the reverse digit of the value; The original sequence is determined based on a first positive sequence number, where the first positive sequence number is a sequence number of a plurality of coefficients of a target polynomial from front to back in the target polynomial.

2. The system according to claim 1, wherein: The transmission module includes an arithmetic logic unit ALU; The ALU is configured to transfer the v-th binary number in the first register to a location in the second register where the Vv-1-th binary number is stored.

3. The system according to claim 2, wherein: The first register includes V first flip-flops, and the second register includes V second flip-flops; The vth first trigger among the V first triggers is configured to: obtain the vth binary number among the V-bit binary numbers based on the input end of the vth first trigger; and the output end of the vth first trigger is connected to the ALU; The Vv-1th second flip-flop among the V second flip-flops is configured to: output the v-th binary number based on the output end of the Vv-1th second flip-flop; and the input end of the v-th second flip-flop is connected to the ALU.

4. The system according to claim 3, wherein: The V first flip-flops and the V second flip-flops are triggered by a same clock signal.

5. The system according to claim 4, wherein: The clock control terminal of each of the V first flip-flops and the V second flip-flops is connected to the same clock control line.

6. The system according to any one of claims 1 to 5, wherein: The transmission module is configured to: obtain a reverse processing instruction, the reverse processing instruction comprising: a first field and a second field, the first field being configured to specify the first register as a source register, the source register being configured to store a source operand, the source operand comprising a V-bit binary number of each value in the original sequence, the second field being configured to specify the second register as a destination register, the destination register being configured to store a destination operand, the destination operand comprising a binary number of a reversed number of each value in the original sequence; Executing the reverse processing instruction to obtain a specific result of the reverse processing instruction, wherein executing the reverse processing instruction to obtain a specific result of the reverse processing instruction includes: For each V-bit binary number in the source operand, the V-bit binary number is shifted right by i bits to obtain a first binary number, the first binary number is bitwise ANDed with the second binary number to obtain a third binary number, the second binary number is a binary number corresponding to the decimal number 1, the third binary number is shifted left by Vi-1 bits to obtain a fourth binary number, i is an integer from 0 to V-1, and each of the fourth binary numbers is bitwise ORed to obtain the binary number of the reverse number corresponding to the V-bit binary number in the destination operand.

7. The system according to any one of claims 1 to 5, wherein: The system further comprises: a sequence determination module, a reverse sequence number determination module, and a sorting module; The sequence determination module is configured to: determine the first positive sequence number, determine the original sequence according to the first positive sequence number, and send the original sequence to the first register; The reverse sequence number determination module is configured to: obtain the binary number of the reverse sequence number corresponding to each value in the original sequence from the second register, determine the reverse sequence number corresponding to each value in the original sequence according to the binary number of the reverse sequence number corresponding to each value in the original sequence, and send the reverse sequence number corresponding to each value in the original sequence to the sorting module; The sorting module is configured to obtain, according to the inverse number corresponding to each numerical value in the original sequence, a plurality of transformation results arranged according to a second positive sequence number, wherein the second positive sequence number is a sorting number from front to back of the plurality of transformation results in the target polynomial under the point value expression method, and the plurality of transformation results are results obtained by performing number theory transform NTT or fast Fourier transform FFT on the target polynomial.

8. The system according to claim 7, wherein: The sequence determination module is specifically configured to: sort the multiple coefficients according to the first positive sequence number, perform the NTT or the FFT on the sorted multiple coefficients to obtain multiple transformation results arranged according to the first sequence number, and combine the first sequence numbers into the original sequence; The reverse sequence number determination module is specifically configured to: obtain the binary number of the reverse sequence number corresponding to each sequence number in the first sequence number from the second register, determine the reverse sequence number corresponding to each sequence number in the first sequence number according to the binary number of the reverse sequence number corresponding to each sequence number in the first sequence number, and send the reverse sequence number corresponding to each sequence number in the first sequence number to the sorting module; The sorting module is specifically configured to: obtain the multiple transformation results from the sequence determination module, determine, for each transformation result in the multiple transformation results, the inverse number of the sequence number of the transformation result when sorted according to the first sequence number as the sorting sequence number of the transformation result when arranged according to the second positive sequence number, and rearrange the multiple transformation results according to the sorting sequences of the multiple transformation results when arranged according to the second positive sequence number, so as to obtain the multiple transformation results arranged according to the second positive sequence number.

9. The system according to claim 7, wherein: The sequence determination module is specifically configured to: combine the first positive sequence numbers into the original sequence; The reverse sequence number determination module is specifically configured to: obtain the binary number of the reverse sequence number corresponding to each positive sequence number in the first positive sequence number from the second register, determine the reverse sequence number corresponding to each positive sequence number in the first positive sequence number according to the binary number of the reverse sequence number corresponding to each positive sequence number in the first positive sequence number, and send the reverse sequence number corresponding to each positive sequence number in the first positive sequence number to the sorting module; The sorting module is specifically configured to: for each coefficient among the multiple coefficients, determine the inverse number of the positive sequence number corresponding to the coefficient in the first positive sequence number as the rearranged sorting number of the coefficient, reorder the multiple coefficients according to the rearranged sorting numbers respectively corresponding to the multiple coefficients, perform the NTT or the FFT on the reordered multiple coefficients, and obtain the multiple transformation results arranged according to the second positive sequence number.

10. The system according to any one of claims 1 to 5, wherein: The system also includes a judgment unit and an adjustment unit; The judgment unit is configured to: obtain the original sequence, determine a target binary number of each value in the original sequence, judge the number of bits of the target binary number and the size of V, obtain a first judgment result, and send the first judgment result to the adjustment unit; The adjustment unit is configured to: when the first judgment result is that the number of bits of the target binary number is greater than V or less than V, adjust the target binary number to obtain the V-bit binary number of the numerical value, send the V-bit binary number of the numerical value to the inverse processing unit, and obtain the binary number of the inverse number of the numerical value based on the inverse processing unit.

11. The system according to claim 10, wherein: The adjustment unit includes a zero-filling module, a transceiver module, and a shift module; The zero-padding module is configured to: when the first judgment result is that the number of bits of the target binary number is less than V, pad the target binary number with zeros at high or low positions to obtain a V-bit binary number of the value; The transceiver module is configured to: obtain the V-bit binary number of the value from the zero padding module, send the V-bit binary number of the value to the reverse processing unit, obtain the fifth binary number corresponding to the V-bit binary number of the value from the reverse processing unit, and send the fifth binary number to the shift module; The shift module is configured to remove the zeros corresponding to the high-order zero padding or the low-order zero padding in the fifth binary number until the number of bits of the fifth binary number is equal to the number of bits of the target binary number, thereby obtaining the binary number of the inverse number of the numerical value.

12. The system according to claim 10, wherein: The adjustment unit includes a multiple module, a processing module, and a splicing module; The multiple module is configured to: when the first judgment result is that the number of digits of the target binary number is greater than V, judge whether the number of digits of the target binary number is an integer multiple of V, obtain a second judgment result, and send the second judgment result to the processing module; The processing module is configured to: process the target binary number according to the second judgment result to obtain a plurality of V-bit sixth binary numbers, and send the plurality of V-bit sixth binary numbers to the splicing module; The splicing module is configured to: send the multiple V-bit sixth binary numbers to the inverse processing unit, and obtain the binary number of the inverse number of the numerical value based on the inverse processing unit.

13. The system according to claim 12, wherein: The processing module is specifically configured to: when the second judgment result is that the number of bits of the target binary number is an integer multiple of V, split the target binary number into the plurality of V-bit sixth binary numbers according to a first order, wherein the first order is an order from the highest bit of the target binary number to the lowest bit of the target binary number; The splicing module is specifically configured to: for each V-bit sixth binary number in the plurality of V-bit sixth binary numbers, send the V-bit sixth binary number to the inverse processing unit, and obtain the corresponding V-bit sixth binary number from the inverse processing unit. The seventh binary number of the V-bit sixth binary numbers is obtained by combining the seventh binary numbers corresponding to the multiple V-bit sixth binary numbers in the order of the multiple V-bit sixth binary numbers from back to front in the first order to obtain the binary number of the reverse number of the numerical value.

14. The system according to claim 12, wherein: The processing module is specifically configured to: when the second judgment result is that the number of bits of the target binary number is not an integer multiple of V, pad the target binary number with zeros at high bits or at low bits to obtain an eighth binary number, the number of bits of the eighth binary number is an integer multiple of V, and split the eighth binary number into the plurality of V-bit sixth binary numbers in a second order, the second order being an order from the highest bit of the eighth binary number to the lowest bit of the target binary number; The splicing module is specifically configured to: for each V-bit sixth binary number in the multiple V-bit sixth binary numbers, send the V-bit sixth binary number to the inverse processing unit, obtain the ninth binary number corresponding to the V-bit sixth binary number from the inverse processing unit, combine the ninth binary numbers corresponding to the multiple V-bit sixth binary numbers in the order of the multiple V-bit sixth binary numbers from back to front in the second sequence, to obtain a tenth binary number corresponding to the numerical value, remove the zeros corresponding to the high-bit zero padding or the low-bit zero padding in the tenth binary number, until the number of bits of the tenth binary number is equal to the number of bits of the target binary number, to obtain the binary number of the inverse number of the numerical value.

15. A polynomial processing method, wherein: The method is applied to a polynomial processing system, the system comprising a reverse processing unit, the reverse processing unit comprising: a first register storing a V-bit binary number, a transmission module connected to the first register, and a second register storing a V-bit binary number connected to the transmission module, where V is a positive integer; For each value in the original sequence, the first register obtains a V-bit binary number of the value; The transmission module transmits the v-th binary number in the first register to the position where the Vv-1-th binary number is stored in the second register, where v is a natural number; The second register obtains the v-th binary number from the transmission module to obtain the binary number of the reverse digit of the value; The original sequence is determined based on a first positive sequence number, where the first positive sequence number is a sequence number of a plurality of coefficients of a target polynomial from front to back in the target polynomial.

16. An electronic device, wherein: include: A processor and a memory, wherein the memory stores a computer program, and the processor calls and runs the computer program stored in the memory to execute the polynomial processing method according to claim 15.

17. A computer-readable storage medium, wherein: The computer-readable storage medium stores a computer program, and the computer program causes a computer to execute the polynomial processing method according to claim 15 .

18. A computer program product comprising instructions, wherein: When the computer program product runs on an electronic device, the electronic device is enabled to execute the polynomial processing method according to claim 15 .

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