Instruction processing method and apparatus based on blake2b algorithm, and electronic device and storage medium

Abstract

Provided in the present application are an instruction processing method and apparatus based on a Blake2b algorithm, and an electronic device and a storage medium. The method comprises: initializing initial information, so as to obtain initialized information, wherein the initialized information comprises initialized state vectors; pre-processing the initialized information on the basis of a compression function and a constant matrix, so as to obtain a set of pre-processed vectors, and storing the set of pre-processed vectors in a register, wherein the set of pre-processed vectors includes K groups of pre-processed vectors, each group of pre-processed vectors includes four pre-processed vectors, and the register consists of N 256-bit register units, N being an integer greater than or equal to 5; receiving a set of first compression instructions or a second compression instruction, acquiring pre-processed vectors from the register units on the basis of the set of first compression instructions or the second compression instruction, and performing compression calculation on the basis of the pre-processed vectors, so as to obtain compressed vectors; and on the basis of the compressed vectors and the initialized state vectors, performing calculation so as to obtain a target digest.

Description

Instruction processing method, device, electronic device and storage medium based on Blake2b algorithm Technical Field

[0001] The present application relates to the field of data processing, and more specifically, to an instruction processing method, device, electronic device and storage medium based on the Blake2b algorithm. Background Art

[0002] The Blake2b algorithm is widely used in generating digital signatures, message authentication codes, verifying the integrity of files or messages, identifying files or data, as well as generating pseudo-random numbers and deriving keys because it runs faster, is more efficient, and has higher security than the SHA algorithm or MD5 algorithm.

[0003] At present, the Blake2b algorithm is usually implemented using instructions or instruction sets. Commonly used Blake2b algorithm implementations using instructions or instruction sets mainly include the following three schemes: (1) 64-bit native instruction implementation schemes in various languages, which are implemented using the central processing unit (CPU) and graphics processing unit (GPU); (2) SIMD (single-input multiple-data) instruction implementation scheme; (3) Advanced Vector Extensions (AVX) or extended operation instruction set (XOP) instruction implementation scheme under the architecture. The Blake2b algorithm mainly includes two calculation processes: preprocessing process and round-robin calculation process. For scheme (1), although it can be applied to multiple 64-bit platforms and the instructions are easy to port, the instruction efficiency is low. Each calculation requires the use of four 64-bit vectors from the previous round for the next round of calculation. The calculation process of this scheme involves a large amount of data copying, that is, a large amount of memory access process, which is low in efficiency. Solutions (2) and (3) provide four 64-bit data parallel computations (SIMD) or 256-bit data computations (AVX, XOP), allowing the core compression process to be processed in 256-bit units. Compared to solution (1), this improves instruction efficiency and reduces the number of memory accesses, resulting in faster processing speeds. However, solutions (2) and (3) still require a large number of memory access operations during the computation process, and the computation speed still needs to be improved. Technical Solutions

[0004] Some embodiments of the present application provide an instruction processing method, device, electronic device, and storage medium based on the Blake2b algorithm.

[0005] According to one aspect of the present application, an instruction processing method based on the Blake2b algorithm is provided, which may include: initializing initial information to obtain initialization information, wherein the initialization information includes an initialization state vector; preprocessing the initialization information based on a compression function and a constant matrix to obtain a preprocessing vector set, and storing the preprocessing vector set in a register, wherein the preprocessing vector set includes K preprocessing vector groups, each of the preprocessing vector groups includes 4 preprocessing vectors, wherein the register is N 256-bit register units, and N is an integer greater than or equal to 5; receiving a first compression instruction set or a second compression instruction, obtaining the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain a compressed vector; performing calculation based on the compressed vector and the initialization state vector to obtain a target summary, wherein the length of the target summary is less than or equal to 64 bytes.

[0006] In one embodiment of the present application, the initialization information may further include: an initialization information block or a spliced ​​array, wherein the spliced ​​array is obtained by splicing the initialization state vector and the initialization information block.

[0007] In one embodiment of the present application, the initialization information is preprocessed based on a compression function and a constant matrix to obtain a preprocessing vector set, and the preprocessing vector set is stored in a register, which may include: organizing the initialization state vector into a first preprocessing vector group, wherein the first preprocessing vector group includes 4 256-bit first preprocessing vectors; receiving a first storage instruction, storing the first preprocessing vector group to the 4 corresponding register units, and recording the first storage address of the register unit corresponding to the first preprocessing vector group; based on the compression function and the constant matrix, the initialization information block is preprocessed to obtain at least one second preprocessing vector group, wherein each second preprocessing vector group includes 4 256-bit second preprocessing vectors; receiving a second storage instruction, storing the second preprocessing vector group to the corresponding register unit, and recording the second storage address of the register unit corresponding to the second preprocessing vector group.

[0008] In one embodiment of the present application, the register units corresponding to the first preprocessing vector group are consecutively adjacent register units, and the register units corresponding to each second preprocessing vector group are consecutively adjacent register units.

[0009] In one embodiment of the present application, the number of the second pre-processing vector groups is 48.

[0010] In one embodiment of the present application, receiving a first compression instruction set or a second compression instruction, obtaining the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain the compressed vector may include: receiving the first compression instruction set, completing a round of compression processing based on the first compression instruction set, repeating 12 rounds of compression processing to obtain the compressed vector; wherein, the first compression instruction set includes 4 first compression instructions, and during each round of compression processing, the first preprocessing vector group and / or the corresponding second preprocessing vector group are obtained in the register unit based on the first compression instruction.

[0011] In one embodiment of the present application, receiving a first compression instruction set or a second compression instruction, obtaining the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain the compressed vector may include: receiving the second compression instruction, completing 12 rounds of compression processing based on the second compression instruction to obtain the compressed vector; wherein the second compression instruction is one compression instruction, and based on the second compression instruction, obtaining the first preprocessing vector group and / or the corresponding second preprocessing vector group in the register unit.

[0012] On the other hand, the present application provides an instruction processing device based on the Blake2b algorithm, including an initialization unit, a braking control unit and a register, wherein the initialization unit can be used to initialize initial information to obtain initialization information, wherein the initialization information includes an initialization state vector; the braking control unit is connected to the initialization unit, and can be used to preprocess the initialization information based on a compression function and a constant matrix to obtain a preprocessing vector set, and store the preprocessing vector set in a register, wherein the preprocessing vector set includes K preprocessing vector groups, each of the preprocessing vector groups includes 4 preprocessing vectors, wherein the register is N 256-bit register units, and N is an integer greater than or equal to 5; receiving a first compression instruction set or a second compression instruction, obtaining the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain a compressed vector; performing calculation based on the compressed vector and the initialization state vector to obtain a target summary, wherein the length of the target summary is less than or equal to 64 bytes.

[0013] In one embodiment of the present application, the initialization information may further include: an initialization information block or a spliced ​​array, wherein the spliced ​​array is obtained by splicing the initialization state vector and the initialization information block.

[0014] In one embodiment of the present application, the braking control unit can be used to: organize the initialization state vector into a first preprocessing vector group, wherein the first preprocessing vector group includes four 256-bit first preprocessing vectors; receive a first storage instruction, store the first preprocessing vector group to the four corresponding register units, and record the first storage address of the register unit corresponding to the first preprocessing vector group; preprocess the initialization information block based on the compression function and the constant matrix to obtain at least one second preprocessing vector group, wherein each second preprocessing vector group includes four 256-bit second preprocessing vectors; receive a second storage instruction, store the second preprocessing vector group to the corresponding register unit, and record the second storage address of the register unit corresponding to the second preprocessing vector group.

[0015] In one embodiment of the present application, the register units corresponding to the first preprocessing vector group are consecutively adjacent register units, and the register units corresponding to each second preprocessing vector group are consecutively adjacent register units.

[0016] In one embodiment of the present application, the number of the second pre-processing vector groups is 48.

[0017] In one embodiment of the present application, the braking control unit can also be used to: receive the first compression instruction set, complete a round of compression processing based on the first compression instruction set, repeat 12 rounds of compression processing, and obtain the compression vector; wherein, the first compression instruction set includes 4 first compression instructions, and during each round of compression processing, based on the first compression instruction, the first pre-processing vector group and / or the corresponding second pre-processing vector group are obtained in the register unit.

[0018] In one embodiment of the present application, the braking control unit can also be used to: receive the second compression instruction, complete 12 rounds of compression processing based on the second compression instruction, and obtain the compression vector; wherein, the second compression instruction is 1 compression instruction, and based on the second compression instruction, obtain the first pre-processing vector group and / or the corresponding second pre-processing vector group in the register unit.

[0019] On the other hand, the present application provides a processor, including an instruction processing method based on the Blake2b algorithm as described in any embodiment of the present application.

[0020] On the other hand, the present application provides an electronic device, comprising: a memory, which non-transiently stores computer-executable instructions; and a processor, configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the instruction processing method based on the Blake2b algorithm described in any embodiment of the present application.

[0021] On the other hand, the present application provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the instruction processing method based on the Blake2b algorithm described in any embodiment of the present application is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0023] FIG1 is a flowchart of an instruction processing method 1000 based on the Blake2b algorithm according to an embodiment of the present application;

[0024] FIG2 is a schematic diagram of obtaining an initialization state vector during an initialization process according to an exemplary embodiment of the present application;

[0025] FIG3A is a schematic diagram of an initialization state vector data structure according to an exemplary embodiment of the present application;

[0026] FIG3B is a schematic diagram of the data structure of an initialization information block according to an exemplary embodiment of the present application;

[0027] FIG3C is a schematic diagram of a spliced ​​array data structure according to an exemplary embodiment of the present application;

[0028] FIG4A is a logic diagram of a compression function according to an exemplary embodiment of the present application;

[0029] FIG4B is a schematic diagram of a formula corresponding to a compression function according to an exemplary embodiment of the present application;

[0030] FIG4C is a schematic diagram of a corresponding SIMGA matrix according to an exemplary embodiment of the present application;

[0031] FIG5 is a logic block diagram based on the Blake2b algorithm according to an exemplary embodiment of the present application;

[0032] FIG6 is a flowchart of obtaining and storing a preprocessing vector group according to an exemplary embodiment of the present application;

[0033] FIG7A is a schematic diagram of an equivalent diagonal transformation according to an exemplary embodiment of the present application;

[0034] FIG7B is a schematic diagram of an equivalent inverse diagonal transformation according to an exemplary embodiment of the present application;

[0035] FIG8 is a schematic diagram of an instruction processing device 2000 based on the Blake2b algorithm according to an exemplary embodiment of the present application;

[0036] FIG9 is a schematic block diagram of a processor 3000 according to an exemplary embodiment of the present application;

[0037] FIG10 is a schematic block diagram of an electronic device 4000 according to an exemplary embodiment of the present application;

[0038] FIG. 11 is a schematic diagram of a non-transitory computer-readable storage medium 5000 according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0039] For a better understanding of the present application, each aspect of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It should be noted that, in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not mean any limitation to the features.

[0041] It should also be understood that the terms "comprises," "including," "having," "includes," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than modifying the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." And, the term "exemplary" is intended to refer to an example or illustration.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal manner unless expressly defined as such herein.

[0043] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] The features, principles and other aspects of the present application are described in detail below.

[0045] FIG1 is a flow chart of an instruction processing method 1000 based on the Blake2b algorithm according to an embodiment of the present application. As shown in FIG1 , the instruction processing method 1000 based on the Blake2b algorithm may include the following steps:

[0046] Step S100: Initializing initial information to obtain initialization information, wherein the initialization information includes an initialization state vector;

[0047] Step S200: preprocessing the initialization information based on the compression function and the constant matrix to obtain a preprocessing vector set, and storing the preprocessing vector set in a register, wherein the preprocessing vector set includes K preprocessing vector groups, each preprocessing vector group includes 4 preprocessing vectors, wherein the register is N 256-bit register units, where N is an integer greater than or equal to 5;

[0048] Step S300: receiving a first compression instruction set or a second compression instruction, obtaining a preprocessing vector in a register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain a compressed vector; and

[0049] Step S400: Calculate based on the compression vector and the initialization state vector to obtain a target digest, wherein the length of the target digest is less than or equal to 64 bytes.

[0050] The following will describe in detail the various steps of the instruction processing method 1000 based on the Blake2b algorithm.

[0051] Step S100

[0052] In an exemplary embodiment of the present application, the initial information is first initialized to obtain initialization information, wherein the initialization information includes an initialization state vector and an initialization information block. Figure 2 is a schematic diagram of obtaining an initialization state vector according to the initialization process of an exemplary embodiment of the present application. As shown in Figure 2, the initial information can be a matrix consisting of initial hash values ​​h0~h7, constant groups IV0~IV7, compressed information length values ​​t0, t1 and compression inversion flags f0, f1, wherein the initial hash values ​​h0~h7 are 8 64-bit data, obtained by assigning values ​​to constant groups IV0~IV7, specifically, h(h0,h1,h2,h3,h4,h5,h6,h7)=(IV0xor 0x0101kknn,IV1,IV2,IV3,IV4,IV5,IV6,IV7), wherein kk is the calculated information length and nn is the summary length to be output. The initialization process yields the initial matrix on the left. Each row in the matrix represents an initialization state vector: a(v0, v1, v2, v3), b(v4, v5, v6, v7), c(v8, v9, v10, v11), and d(v12, v13, v14, v15). Each initialization state vector contains 256 bits of data. The initial information also includes the data to be compressed. The initialization process standardizes data of varying lengths. For example, by padding the data with zeros, a fixed length is obtained. The data is then divided into 128-byte blocks and mapped into 16 64-bit initialization blocks, m0 through m15.

[0053] In an exemplary embodiment of the present application, the initialization information can also be a spliced ​​array. Figure 3A is a schematic diagram of the data structure of the initialized state vector according to an exemplary embodiment of the present application; Figure 3B is a schematic diagram of the data structure of the initialized information block according to an exemplary embodiment of the present application; and Figure 3C is a schematic diagram of the data structure of the spliced ​​array according to an exemplary embodiment of the present application. As shown in Figures 3A-3C, an initialization instruction set can be constructed based on the initialized state vector data structure, the initialization information block data structure, and the spliced ​​array data structure, and the initialization process of the above-mentioned initial data is implemented by executing the instructions in the initialization instruction set. Exemplarily, the starting addresses of the initialized state vector data structure, the initialization information block data structure, and the spliced ​​array data structure are first saved. For example, the following instructions are used: blk2b_sv_init Rn; blk2b_mm_init Rn; blk2b_init Rn; where sv_init is the data corresponding to the initialized state vector, mm_init is the data corresponding to the initialization information block, init is the data corresponding to the spliced ​​array, and Rn is a general register of the 64-bit CPU that stores the starting addresses of sv_init, mm_init, and init.

[0054] According to an exemplary embodiment of the present application, by processing the initial information, an initialization state vector, an initialization information block or a spliced ​​array is obtained, and an initialization instruction set is constructed through its corresponding data structure. By executing the instructions in the initialization instruction set, the initialization of the initial information is completed, which facilitates subsequent preprocessing of the initialization information.

[0055] Step S200

[0056] In an exemplary embodiment of the present application, after obtaining the initialization information, the corresponding initialization information can also be obtained, and the initialization information can be preprocessed based on the compression function and the constant matrix to obtain a preprocessing vector set, wherein the preprocessing vector set includes K preprocessing vector groups, 5≤K≤52, and K is an integer, and the preprocessing vector group can include 4 first preprocessing vector groups and no more than 48 second preprocessing vector groups. Each preprocessing vector group contains 4 preprocessing vectors. Figure 4A is a logical diagram of the compression function according to an exemplary embodiment of the present application. Figure 4B is a schematic diagram of the formula corresponding to the compression function according to an exemplary embodiment of the present application. Figure 4C is a schematic diagram of the corresponding SIMGA matrix according to an exemplary embodiment of the present application. Figure 5 is a logical block diagram based on the Blake2b algorithm according to an exemplary embodiment of the present application. In an exemplary embodiment of the present application, after obtaining the preprocessing vector set, the preprocessing vector set can also be stored in a register in units of preprocessing vector groups. Figure 6 is a flowchart of obtaining and storing preprocessing vector groups according to an exemplary embodiment of the present application. As shown in Figure 6, obtaining and storing preprocessing vector groups can include the following steps:

[0057] Step S210: Arrange the initialized state vector into a first pre-processing vector group, wherein the first pre-processing vector group includes four 256-bit first pre-processing vectors;

[0058] Step S220: receiving a first storage instruction, storing the first pre-processing vector group into four corresponding register units, and recording a first storage address of the register unit corresponding to the first pre-processing vector group;

[0059] Step S230: preprocessing the initialization information block based on the compression function and the constant matrix to obtain at least one second preprocessing vector group, wherein each second preprocessing vector group includes four 256-bit second preprocessing vectors;

[0060] Step S240: receiving a second storage instruction, storing the second pre-processing vector group into a corresponding register unit, and recording a second storage address of the register unit corresponding to the second pre-processing vector group.

[0061] The above steps are exemplarily described with reference to Figures 4A to 4C and Figure 5. The compression function may include a first compression function G1 and a second compression function G2. Each time the compression function is used for calculation, the initialization state vectors a, b, c, d and the corresponding initialization information blocks are subjected to logical operations to obtain the corresponding compression vectors. The Blake2b algorithm requires 12 rounds of compression, and the input vectors of the compression function in each round are the initialization state vectors a, b, c, d and the corresponding initialization information blocks m output from the previous round. σr(2i) and mσr(2i+1) . In each round of compression calculation, the initialization state vector is organized into a first preprocessing vector group based on the mapping relationship. The first preprocessing vector group includes four 256-bit first preprocessing vectors, namely a, b, c, and d. When the first storage instruction is received, the first preprocessing vector group is stored in four corresponding register units (GF00-GF03), and the first storage address of the register unit corresponding to the first preprocessing vector group is recorded. Based on the constant matrix of Figure 4C, namely the SIMGA matrix and the compression function, the initialization information block is preprocessed to obtain at least one second preprocessing vector group. Each second preprocessing vector group contains the second preprocessing vector required for each round of compression calculation, that is, the corresponding initialization information block required for each round of compression function. For example, in this application, each second preprocessing vector group contains four second preprocessing vectors, and 12 rounds of compression require 12 second preprocessing vector groups, that is, 48 ​​second preprocessing vectors. When the second storage instruction is received, the second preprocessing vector group is stored in the corresponding register unit, and the second storage address of the register unit corresponding to the second preprocessing vector group is recorded. For example, the second pre-processing vector group is stored in GF04 to GF51 respectively. For example, Table 1 shows the second pre-processing vector.

[0062] Table 1

[0063] In an exemplary embodiment of the present application, the register units corresponding to the first preprocessing vector group are consecutively adjacent registers, namely GF00-GF03, and the register units corresponding to each second preprocessing vector group are consecutively adjacent register units, for example, GF04-GF07; GF08-GF11, ...GF48-GF51.

[0064] According to an exemplary embodiment of the present application, by preprocessing the initialization information, a preprocessing vector set is obtained, the preprocessing vector set includes multiple preprocessing vector groups, and the preprocessing vector groups are stored in corresponding register units in advance, and each preprocessing vector group is stored in an adjacent register unit. In the subsequent compression calculation process, the preprocessing vector required for each compression round can be directly read based on the storage address, which can reduce the number of register accesses and improve data processing efficiency.

[0065] Step S300 and Step S400

[0066] In an exemplary embodiment of the present application, after the preprocessing vector is stored in the register, a first compression instruction set or a second compression instruction may be received, and the preprocessing vector in the register unit is obtained based on the first compression instruction set or the second compression instruction, and compression calculation is performed based on the preprocessing vector to obtain a compressed vector. Exemplarily, when the first compression instruction set is received, a round of compression processing is completed based on the first compression instruction set, and the compression processing is repeated 12 times to obtain a compressed vector; wherein the first compression instruction set includes 4 first compression instructions, and during each round of compression processing, the first preprocessing vector group and / or the corresponding second preprocessing vector group are obtained from the register unit based on the first compression instruction. Specifically, the four first compression instructions of the first compression instruction set are blk2b_g1, blk2b_g2, blk2b_diag, and blk2b_undiag. In combination with Figures 4A-4C and 5, blk2b_g1 is based on the first compression function G1, and the first preprocessing vector group and the corresponding second preprocessing vector group are compressed and calculated to obtain an updated first preprocessing vector group (a', b', c', d'); blk2b_g2 is based on the second compression function G2, and the updated first preprocessing vector group (a', b', c', d') and the corresponding second preprocessing vector group are compressed and calculated to obtain an updated first preprocessing vector group (a, b, c, d). Based on the round number i of the compression calculation, the corresponding second preprocessing vector (M) can be directly obtained in the register. i -M i+3 ). After each round of compression calculation is completed, an updated first preprocessing vector can be obtained, and the updated first preprocessing vector can be temporarily stored in registers GF00-GF03 for use in the next round of compression calculation. The first compression instruction may also include an equivalent diagonal transformation instruction blk2b_diag and an equivalent anti-diagonal transformation instruction blk2b_undiag. Figure 7A is a schematic diagram of an equivalent diagonal transformation according to an exemplary embodiment of the present application; Figure 7B is a schematic diagram of an equivalent anti-diagonal transformation according to an exemplary embodiment of the present application. As shown in Figures 7A and 7B, the diagonal transformation of the equivalent matrix of the first preprocessing vector can be achieved through the equivalent diagonal transformation instruction, and the anti-diagonal transformation of the equivalent matrix of the first preprocessing vector can be achieved through the anti-diagonal transformation instruction. Through the first compression instruction, 12 rounds of compression calculation are completed, and the corresponding compression vectors are obtained.

[0067] According to an exemplary embodiment of the present application, the first preprocessing vector and the second preprocessing vector required for each compression round are directly obtained through the first compression instruction, the first storage address and the second storage address. While reducing the number of data loading and memory access, the corresponding first preprocessing vector and the second preprocessing vector can be obtained. By reducing the number of data loading and memory access, the efficiency of data processing is improved.

[0068] Exemplarily, upon receiving a second compression instruction, 12 rounds of compression processing are completed based on the second compression instruction to obtain a compressed vector. The second compression instruction is a single compression instruction, and based on the second compression instruction, the first preprocessing vector group and / or the corresponding second preprocessing vector group are obtained from the register unit. For example, the second compression instruction is blk2b_cmprss, which can complete the compression process in one go and obtain the corresponding compressed vector. The code corresponding to the second compression instruction blk2b_cmprss is shown below:

[0069] Input a,b,c,d,M

[0070] Output a,b

[0071] Blake2b_Compress{

[0072] GF52=a

[0073] GF53=b

[0074] For(i=0;i<12;i+=4){

[0075] Blake2b_Compress_Round(i)

[0076] }

[0077] a=a xor GF52

[0078] b=b xor GF53

[0079] }

[0080] The second compression instruction can directly use the first pre-processing vector and the second pre-processing vector corresponding to registers GF00-GF51 without using memory access instructions or operations, thereby improving the efficiency of data compression by further reducing the number of instructions and the number of data memory access times.

[0081] In an exemplary embodiment of the present application, after obtaining the compression vector, a target digest may be obtained by performing a calculation based on the compression vector and the initialization state vector, wherein the target digest has a length of less than or equal to 64 bytes. For example, the compression vector and the initialization vector may be XORed to generate the target digest, wherein the target digest, also known as a hash value, has a length of less than or equal to 64 bytes.

[0082] According to an exemplary embodiment of the present application, by constructing a corresponding initialization instruction set, compression instruction or instruction set, etc., and by executing the corresponding instructions, the first preprocessing vector and the second preprocessing vector are stored in the designated register unit of the register in advance. In the subsequent data compression process, the corresponding first preprocessing vector and the second preprocessing vector are directly obtained from the register based on the instruction. By constructing the instruction or instruction set, the complexity of the Blake2b algorithm implementation is greatly reduced, the memory access process in the calculation process of the Blake2b algorithm is reduced, and the running speed and efficiency of the Blake2b algorithm are improved.

[0083] Another aspect of the present application provides an instruction processing device 2000 based on the Blake2b algorithm. FIG8 is a schematic diagram of an instruction processing device 2000 based on the Blake2b algorithm according to an exemplary embodiment of the present application. As shown in FIG8 , the instruction processing device 2000 based on the Blake2b algorithm may include an initialization unit 2100, a braking control unit 2200, and a register 2300. Among them, the initialization unit 2100 is used to initialize the initial information to obtain the initialization information, wherein the initialization information includes the initialization state vector; the braking control unit 2200 is used to preprocess the initialization information based on the compression function and the constant matrix to obtain a preprocessing vector set, and store the preprocessing vector set in the register 2300, wherein the preprocessing vector set includes K preprocessing vector groups, each preprocessing vector group includes 4 preprocessing vectors, wherein the register is N 256-bit register units, and N is an integer greater than or equal to 5; receive a first compression instruction set or a second compression instruction, obtain the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and perform compression calculation based on the preprocessing vector to obtain a compressed vector; and perform calculation based on the compressed vector and the initialization state vector to obtain a target summary, wherein the length of the target summary is less than or equal to 64 bytes.

[0084] In an exemplary embodiment of the present application, the initialization information may further include: an initialization information block or a spliced ​​array, wherein the spliced ​​array is obtained by splicing the initialization state vector and the initialization information block.

[0085] In an exemplary embodiment of the present application, the braking control unit 2200 can be used to: organize the initialization state vector into a first preprocessing vector group, wherein the first preprocessing vector group includes four 256-bit first preprocessing vectors; receive a first storage instruction, store the first preprocessing vector group to four corresponding register units, and record the first storage address of the register unit corresponding to the first preprocessing vector group; preprocess the initialization information block based on the compression function and the constant matrix to obtain at least one second preprocessing vector group, wherein each second preprocessing vector group includes four 256-bit second preprocessing vectors; receive a second storage instruction, store the second preprocessing vector group to the corresponding register unit, and record the second storage address of the register unit corresponding to the second preprocessing vector group.

[0086] In an exemplary embodiment of the present application, the register units corresponding to the first preprocessing vector group are consecutively adjacent register units, and the register units corresponding to each second preprocessing vector group are consecutively adjacent register units.

[0087] In one embodiment of the present application, the number of the second pre-processing vector groups is 48.

[0088] In one embodiment of the present application, the braking control unit 2200 can also be used to: receive a first compression instruction set, complete a round of compression processing based on the first compression instruction set, repeat 12 rounds of compression processing, and obtain a compressed vector; wherein, the first compression instruction set includes 4 first compression instructions, and during each round of compression processing, based on the first compression instruction, obtain the first preprocessing vector group and / or the corresponding second preprocessing vector group in the register unit.

[0089] In one embodiment of the present application, the braking control unit 2200 can also be used to: receive a second compression instruction, complete 12 rounds of compression processing based on the second compression instruction, and obtain a compression vector; wherein the second compression instruction is 1 compression instruction, and based on the second compression instruction, obtain the first preprocessing vector group and / or the corresponding second preprocessing vector group in the register unit.

[0090] The specific contents of the corresponding implementations of the initialization unit 2100, the braking control unit 2200 and the register 2300 in the instruction processing device 2000 of the Blake2b algorithm have been described in detail in the instruction processing method based on the Blake2b algorithm, and will not be repeated here.

[0091] The present application also provides a processor 3000. FIG9 is a schematic block diagram of a processor 3000 according to an exemplary embodiment of the present application. As shown in FIG9 , the processor 3000 includes an instruction processing device 2000 based on the Blake2b algorithm as in any exemplary embodiment of the present application. Regarding the structure, function, and technical effects of the instruction processing device 2000 based on the Blake2b algorithm, please refer to the above-mentioned instruction processing device 2000 based on the Blake2b algorithm, and no further details will be given here.

[0092] Among them, the processor 3000 can be implemented as a central processing unit, such as a central processing unit of an X86 architecture, according to actual needs. It should be noted that in the exemplary embodiment of the present application, the processor 3000 may include more or fewer circuits or units, for example, it may also include related components such as an instruction cache, an instruction scheduler, and an instruction cache area, and this application does not impose specific restrictions on this. The connection relationship between each circuit or unit is not restricted and can be determined according to actual needs. The specific configuration of each circuit or unit is not restricted and can be composed of analog devices according to circuit principles, or it can be composed of digital chips, or it can be composed in other applicable ways. The processor provided in at least one exemplary embodiment of the present application can achieve technical effects similar to those of the aforementioned data processing device, which will not be described in detail here.

[0093] The present application also provides an electronic device 4000. Figure 10 is a schematic block diagram of an electronic device 4000 according to an exemplary embodiment of the present application. As shown in Figure 10, the electronic device 4000 includes a processor 4100 and a memory 4200. It should be noted that the components of the electronic device 4000 shown in Figure 10 are only exemplary and non-restrictive. According to actual application needs, the electronic device 4000 may also have other components. For example, the processor 4100 and the memory 4200 can communicate with each other directly or indirectly. The processor 4100 and the memory 4200 can communicate through a network. The network may include a wireless network, a wired network, and / or any combination of a wireless network and a wired network. The processor 4100 and the memory 4200 can also communicate with each other through a system bus, which is not limited by the present application.

[0094] Exemplarily, the memory 4200 is used to store computer-readable instructions non-transiently. When the processor 4100 is used to execute the computer-readable instructions, the computer-readable instructions are executed by the processor 4100 to implement the instruction processing method based on the Blake2b algorithm according to any of the above exemplary embodiments. For the specific implementation of each step of the instruction processing method based on the Blake2b algorithm and related explanations, please refer to the embodiment of the instruction processing method 1000 based on the Blake2b algorithm above, and the repeated parts will not be repeated here.

[0095] For example, processor 4100 can control other components in electronic device 4000 to perform desired functions. Processor 4100 can be a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be of X86 or ARM architecture, etc.

[0096] Exemplarily, the memory 4200 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor 4100 may execute the computer-readable instructions to implement various functions of the electronic device 4000. Various applications and various data may also be stored in the storage medium.

[0097] For example, in some embodiments, the electronic device 4000 may be a mobile phone, a tablet computer, an electronic paper, a television, a display, a laptop computer, a digital photo frame, a navigator, a wearable electronic device, a smart home device, etc. For example, the electronic device 4000 may include a display panel, and the display panel may be used to display interactive content, etc. For example, the display panel may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel, etc. In addition, the display panel may be not only a flat panel, but also a curved panel, or even a spherical panel. For example, the electronic device 4000 may have a touch function, that is, the electronic device 4000 may be a touch device. For a detailed description of the process of the electronic device 4000 executing the instruction processing method based on the Blake2b algorithm, reference may be made to the relevant description in the embodiment of the instruction processing method based on the Blake2b algorithm, and the repeated parts will not be repeated.

[0098] Figure 11 is a schematic diagram of a non-transitory computer-readable storage medium 5000 according to an exemplary embodiment of the present application. As shown in Figure 11, one or more computer-readable instructions 5100 can be non-temporarily stored on the non-transitory computer-readable storage medium 5000. Exemplarily, when the computer-readable instructions 5100 are executed by the processor, one or more steps in the instruction processing method based on the Blake2b algorithm can be executed. Exemplarily, the storage medium 5000 can be applied to the above-mentioned electronic device 4000. For example, the storage medium 5000 may include the memory 4200 in the electronic device 4000. For the description of the storage medium 5000, reference can be made to the description of the memory 4200 in the embodiment of the electronic device 4000, and the repeated parts will not be repeated.

[0099] Exemplarily, the storage device may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor may execute the computer-readable instructions to implement various functions of the processor. Various applications and various data may also be stored in the storage medium.

[0100] Exemplarily, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media.

[0101] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of application of the present application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the concept of the application. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. An instruction processing method based on the Blake2b algorithm, comprising: Initializing initial information to obtain initialization information, wherein the initialization information includes an initialization state vector; Based on the compression function and the constant matrix, preprocessing the initialization information to obtain a preprocessing vector set, and storing the preprocessing vector set in a register, wherein the preprocessing vector set includes K preprocessing vector groups, each of the preprocessing vector groups includes 4 preprocessing vectors, wherein the register is N 256-bit register units, and N is an integer greater than or equal to 5; receiving a first compression instruction set or a second compression instruction, acquiring the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain a compressed vector; A target digest is obtained by performing calculation based on the compression vector and the initialization state vector, wherein a length of the target digest is less than or equal to 64 bytes.

2. The instruction processing method based on the Blake2b algorithm according to claim 1, wherein: The initialization information further includes: an initialization information block or a splicing array, wherein the splicing array is obtained by splicing the initialization state vector and the initialization information block.

3. The instruction processing method based on the Blake2b algorithm according to claim 2, wherein: Preprocessing the initialization information based on the compression function and the constant matrix to obtain a preprocessing vector set, and storing the preprocessing vector set in a register, including: Arrange the initialization state vector into a first preprocessing vector group, wherein the first preprocessing vector group includes four 256-bit first preprocessing vectors; receiving a first storage instruction, storing the first preprocessing vector group into the four corresponding register units, and recording a first storage address of the register unit corresponding to the first preprocessing vector group; Preprocessing the initialization information block based on the compression function and the constant matrix to obtain at least one second preprocessing vector group, wherein each second preprocessing vector group includes four 256-bit second preprocessing vectors; A second storage instruction is received, the second preprocessing vector group is stored in the corresponding register unit, and a second storage address of the register unit corresponding to the second preprocessing vector group is recorded.

4. The instruction processing method based on the Blake2b algorithm according to claim 3, wherein: The register units corresponding to the first preprocessing vector group are continuously adjacent register units, and the register units corresponding to each of the second preprocessing vector groups are continuously adjacent register units.

5. The instruction processing method based on the Blake2b algorithm according to claim 3, wherein: The number of the second preprocessing vector groups is 48.

6. The instruction processing method based on the Blake2b algorithm according to claim 3, wherein: Receiving a first compression instruction set or a second compression instruction, acquiring the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain a compressed vector, including: Receive the first compression instruction set, complete a round of compression processing based on the first compression instruction set, repeat 12 rounds of compression processing to obtain the compressed vector; wherein the first compression instruction set includes 4 first compression instructions, and during each round of compression processing, based on the first compression instruction, obtain the first preprocessing vector group and / or the corresponding second preprocessing vector group in the register unit.

7. The instruction processing method based on the Blake2b algorithm according to claim 3, wherein: Receiving a first compression instruction set or a second compression instruction, acquiring the preprocessing vector in the register unit based on the first compression instruction set or the second compression instruction, and performing compression calculation based on the preprocessing vector to obtain a compressed vector, including: Receive the second compression instruction, complete 12 rounds of compression processing based on the second compression instruction, and obtain the compressed vector; wherein the second compression instruction is 1 compression instruction, and based on the second compression instruction, obtain the first preprocessing vector group and / or the corresponding second preprocessing vector group in the register unit.

8. An instruction processing device based on the Blake2b algorithm, comprising an initialization unit, a brake control unit and a register, wherein: The initialization unit is used to initialize the initial information to obtain the initialization information, wherein the initialization information includes an initialization state vector; The braking control unit is connected to the initialization unit and is used to preprocess the initialization information based on a compression function and a constant matrix to obtain a preprocessing vector set, and store the preprocessing vector set in a register, wherein the preprocessing vector set includes K preprocessing vector groups, each of which includes 4 preprocessing vectors, wherein the register is N 256-bit register units, and N is an integer greater than or equal to 5; receiving a first compression instruction set or a second compression instruction, and based on the first compression instruction set or the second compression instruction The preprocessing vector in the register unit is obtained, and compression calculation is performed based on the preprocessing vector to obtain a compressed vector; calculation is performed based on the compressed vector and the initialization state vector to obtain a target summary, wherein the length of the target summary is less than or equal to 64 bytes.

9. The instruction processing device based on the Blake2b algorithm according to claim 8, wherein: The initialization information further includes: an initialization information block or a splicing array, wherein the splicing array is obtained by splicing the initialization state vector and the initialization information block.

10. The instruction processing device based on the Blake2b algorithm according to claim 9, wherein: The brake control unit is used for: Arrange the initialization state vector into a first preprocessing vector group, wherein the first preprocessing vector group includes four 256-bit first preprocessing vectors; receiving a first storage instruction, storing the first preprocessing vector group into the four corresponding register units, and recording a first storage address of the register unit corresponding to the first preprocessing vector group; Preprocessing the initialization information block based on the compression function and the constant matrix to obtain at least one second preprocessing vector group, wherein each second preprocessing vector group includes four 256-bit second preprocessing vectors; A second storage instruction is received, the second preprocessing vector group is stored in the corresponding register unit, and a second storage address of the register unit corresponding to the second preprocessing vector group is recorded.

11. A processor, comprising an instruction processing device based on the Blake2b algorithm as claimed in any one of claims 8 to 10.

12. An electronic device comprising: Memory, non-transitory storage of computer executable instructions: a processor configured to execute the computer executable instructions, in, When the computer executable instructions are executed by the processor, the instruction processing method based on the Blake2b algorithm according to any one of claims 1 to 7 is implemented.

13. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the instruction processing method based on the Blake2b algorithm according to any one of claims 1 to 7 is implemented.

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