Instruction processing method and apparatus based on blake2s algorithm, electronic device and storage medium

Abstract

The present application provides an instruction processing method and apparatus based on a Blake2s algorithm, an electronic device and a storage medium. The method comprises: initializing initial information to obtain initialized information, wherein the initialized information comprises an initialized state vector and an initialized information block; on the basis of a compression function and a constant matrix, preprocessing the initialized state vector and the initialized information block to obtain a corresponding first preprocessed vector and second preprocessed vector; storing the first preprocessed vector into a first register unit, and storing the second preprocessed vector into a second register unit, wherein the first register unit and the second register unit are 128 bits; and receiving at least one compression instruction, and on the basis of the compression instruction, performing ten rounds of compression processing on the first preprocessed vector and the second preprocessed vector to obtain a compressed vector.

Description

Instruction processing method, device, electronic device and storage medium based on Blake2s algorithm Technical Field

[0001] The present application relates to the field of data processing, and more specifically, to an instruction processing method, device, electronic device and storage medium based on the Blake2s algorithm. Background Art

[0002] The Blake2s algorithm is faster, more efficient, and more secure than the SHA or MD5 algorithms. Therefore, it is widely used in generating digital signatures, message authentication codes, verifying the integrity of files or messages, identifying files or data, and generating pseudo-random numbers and derivation of keys.

[0003] At present, the Blake2s algorithm is usually implemented using instructions or instruction sets. Commonly used Blake2s algorithm implementations using instructions or instruction sets mainly include the following three schemes: (1) 32-bit native instruction implementation schemes in various languages, which are implemented using the central processing unit (CPU) and graphics processing unit (GPU); (2) SIMD (single-input multiple-data) instruction implementation scheme; (3) Advanced Vector Extensions (AVX) or extended operation instruction set (XOP) instruction implementation scheme under the architecture. The Blake2s algorithm mainly includes two calculation processes: preprocessing process and round-robin calculation process. For scheme (1), although it can be applied to multiple 32-bit platforms and the instructions are easy to port, the instruction efficiency is low. Each calculation requires the use of four 32-bit vectors from the previous round for the next round of calculation. The calculation process of this scheme involves a large amount of data copying, that is, a large amount of memory access process, which is low in efficiency. Schemes (2) and (3) can process data in 128-bit units. Compared with scheme (1), they have improved instruction efficiency and reduced memory access, resulting in faster processing speed. However, schemes (2) and (3) still require a large number of memory access operations during the calculation process, and the calculation speed still needs to be improved. Technical Solutions

[0004] Some embodiments of the present application provide an instruction processing method, device, electronic device and storage medium based on the Blake2s algorithm.

[0005] According to one aspect of the present application, an instruction processing method based on the Blake2s algorithm is provided, which may include: initializing initial information to obtain initialization information, wherein the initialization information includes an initialization state vector and an initialization information block; preprocessing the initialization state vector and the initialization information block based on a compression function and a constant matrix to obtain corresponding first preprocessing vectors and second preprocessing vectors; storing the first preprocessing vector in a first register unit and storing the second preprocessing vector in a second register unit, wherein the first register unit and the second register unit are 128 bits; receiving at least one compression instruction, and performing 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain a compressed vector.

[0006] In one embodiment of the present application, the initialization information may be a spliced ​​array, wherein the spliced ​​array is obtained by splicing the initialization state vector and the initialization information block.

[0007] In one embodiment of the present application, preprocessing the initialization state vector and the initialization information block based on a compression function and a constant matrix to obtain corresponding first preprocessing vectors and second preprocessing vectors may include: arranging the initialization state vector into four first preprocessing vectors; preprocessing the initialization information block based on the compression function and the constant matrix to obtain the second preprocessing vector corresponding to each round, wherein each round corresponds to four second preprocessing vectors.

[0008] In one embodiment of the present application, storing the first preprocessing vector to a first register unit and storing the second preprocessing vector to a second register unit may include: receiving a storage instruction, storing the first preprocessing vector to the first register unit, and recording a first storage address of the first register unit; storing the second preprocessing vector to the second register unit, and recording a second storage address of the second register unit.

[0009] In one embodiment of the present application, receiving at least one compression instruction, and performing 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain a compressed vector may include: receiving multiple first compression instructions, wherein the first compression instruction includes a first compression function instruction, a second compression function instruction, a first transformation instruction, and a second transformation instruction; performing a first level of compression and a diagonal transformation based on the first compression function instruction, the second compression function instruction, the first transformation instruction, the first preprocessing vector, and the second preprocessing vector to obtain a first sub-compressed vector; performing a second level of compression and an anti-diagonal transformation based on the first sub-compressed vector, the second transformation instruction, the first compression function instruction, and the second compression function instruction to obtain a second sub-compressed vector, completing one round of compression processing; and repeating 10 rounds of compression processing based on the second sub-compressed vector and the first compression instruction to obtain the compressed vector.

[0010] In one embodiment of the present application, receiving at least one compression instruction and performing 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain a compressed vector may include: receiving a second compression instruction, wherein the second compression instruction is one compression instruction; and completing 10 rounds of compression based on the first preprocessing vector, the second preprocessing vector, and the second compression instruction to obtain the compressed vector.

[0011] On the other hand, the present application provides an instruction processing device based on the Blake2s algorithm, including an initialization unit, a braking control unit and a register, wherein the initialization unit is used to initialize the initial information to obtain the initialization information, wherein the initialization information includes an initialization state vector and an initialization information block; the braking control unit is connected to the initialization unit, and is used to preprocess the initialization state vector and the initialization information block based on a compression function and a constant matrix to obtain corresponding first preprocessing vectors and second preprocessing vectors; the first preprocessing vector is stored in a first register unit, and the second preprocessing vector is stored in a second register unit, wherein the first register unit and the second register unit are 128 bits; at least one compression instruction is received, and based on the compression instruction, 10 rounds of compression processing are performed on the first preprocessing vector and the second preprocessing vector to obtain a compressed vector.

[0012] In one embodiment of the present application, the braking control unit can be used to: organize the initialization state vector into 4 first preprocessing vectors; preprocess the initialization information block based on the compression function and the constant matrix to obtain the second preprocessing vector corresponding to each round, wherein each round corresponds to 4 second preprocessing vectors.

[0013] In one embodiment of the present application, the braking control unit can be used to: receive multiple first compression instructions, wherein the first compression instruction includes a first compression function instruction, a second compression function instruction, a first transformation instruction, and a second transformation instruction; perform a first level of compression and a diagonal transformation based on the first compression function instruction, the second compression function instruction, the first transformation instruction, the first preprocessing vector, and the second preprocessing vector to obtain a first sub-compression vector; perform a second level of compression and an anti-diagonal transformation based on the first sub-compression vector, the second transformation instruction, the first compression function instruction, and the second compression function instruction to obtain a second sub-compression vector, completing one round of compression processing; repeat 10 rounds of compression processing based on the second sub-compression vector and the first compression instruction to obtain the compression vector.

[0014] In one embodiment of the present application, the braking control unit can be used to: receive a second compression instruction, wherein the second compression instruction is 1 compression instruction; complete 10 rounds of compression process based on the first preprocessing vector, the second preprocessing vector and the second compression instruction to obtain the compression vector.

[0015] On the other hand, the present application provides a processor, including an instruction processing device based on the Blake2s algorithm as described in any embodiment of the present application.

[0016] On the other hand, the present application provides an electronic device, comprising: a memory, which non-transiently stores computer-executable instructions; and a processor, configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the instruction processing method based on the Blake2s algorithm described in any embodiment of the present application.

[0017] On the other hand, the present application provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the instruction processing method based on the Blake2s algorithm described in any embodiment of the present application is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0019] FIG1 is a flowchart of an instruction processing method 1000 based on the Blake2s algorithm according to an embodiment of the present application;

[0020] FIG2 is a schematic diagram of obtaining an initialization state vector during an initialization process according to an exemplary embodiment of the present application;

[0021] FIG3A is a schematic diagram of an initialization state vector data structure according to an exemplary embodiment of the present application;

[0022] FIG3B is a schematic diagram of the data structure of an initialization information block according to an exemplary embodiment of the present application;

[0023] FIG3C is a schematic diagram of a spliced ​​array data structure according to an exemplary embodiment of the present application;

[0024] FIG4A is a logic diagram of a compression function according to an exemplary embodiment of the present application;

[0025] FIG4B is a schematic diagram of a formula corresponding to a compression function according to an exemplary embodiment of the present application;

[0026] FIG4C is a schematic diagram of a corresponding SIMGA matrix according to an exemplary embodiment of the present application;

[0027] FIG5 is a logic block diagram based on the Blake2s algorithm according to an exemplary embodiment of the present application;

[0028] FIG6 is a flowchart of obtaining a first pre-processing vector and a second pre-processing vector according to an exemplary embodiment of the present application;

[0029] FIG7 is a flowchart of obtaining a compressed vector according to an exemplary embodiment of the present application;

[0030] FIG8A is a schematic diagram of diagonal transformation according to an exemplary embodiment of the present application;

[0031] FIG8B is a schematic diagram of an inverse diagonal transformation according to an exemplary embodiment of the present application;

[0032] FIG9 is a flowchart of obtaining a compressed vector according to another exemplary embodiment of the present application;

[0033] FIG10 is a schematic diagram of an instruction processing device 2000 based on the Blake2s algorithm according to an exemplary embodiment of the present application;

[0034] FIG11 is a schematic block diagram of a processor 3000 according to an exemplary embodiment of the present application;

[0035] FIG12 is a schematic block diagram of an electronic device 4000 according to an exemplary embodiment of the present application;

[0036] FIG. 13 is a schematic diagram of a non-transitory computer-readable storage medium 5000 according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0037] For a better understanding of the present application, each aspect of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of the present application and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] It should be noted that, in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not mean any limitation to the features.

[0039] It should also be understood that the terms "comprises," "including," "having," "includes," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, rather than modifying the individual elements in the list. Furthermore, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application." Furthermore, the term "exemplary" is intended to refer to an example or illustration.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal manner unless expressly defined as such herein.

[0041] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] The features, principles and other aspects of the present application are described in detail below.

[0043] FIG1 is a flow chart of an instruction processing method 1000 based on the Blake2s algorithm according to an embodiment of the present application. As shown in FIG1 , the instruction processing method 1000 based on the Blake2s algorithm may include the following steps:

[0044] Step S100: Initializing initial information to obtain initialization information, wherein the initialization information includes an initialization state vector and an initialization information block;

[0045] Step S200: preprocessing the initialization state vector and the initialization information block based on the compression function and the constant matrix to obtain corresponding first preprocessing vector and second preprocessing vector;

[0046] Step S300: storing the first pre-processing vector into the first register unit, and storing the second pre-processing vector into the second register unit, wherein the first register unit and the second register unit are 128 bits; and

[0047] Step S400: receiving at least one compression instruction, and performing 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain a compressed vector.

[0048] The following will describe in detail the various steps of the instruction processing method 1000 based on the Blake2s algorithm.

[0049] In an exemplary embodiment of the present application, in step S100, initial information is initialized to obtain initialization information, wherein the initialization information may include an initialization state vector and an initialization information block. FIG2 is a schematic diagram of obtaining an initialization state vector according to the initialization process of an exemplary embodiment of the present application. As shown in Figure 2, the initial information can be a matrix consisting of initial hash values ​​h0~h7, constant groups IV0~IV7, compressed information length values ​​t0, t1 and compression reversal flags f0, f1, where the length of t0 and t1 is 64 bits, the length of the compression reversal flags f0 and f1 is 64 bits, and the initial hash values ​​h0~h7 are 8 32-bit data, which can be obtained by assigning values ​​to constant groups IV0~IV7. Specifically, h(h0,h1,h2,h3, h4,h5,h6,h7)=(IV0xor 0x0101kknn,IV1,IV2,IV3,IV4,IV5,IV6,IV7), where IV0~IV7 are 8 32-bit constant groups, kk is the calculated information length, and nn is the digest length to be output. The initialization process yields the initial matrix on the left. Each row in the matrix represents an initialization state vector: a(v0, v1, v2, v3), b(v4, v5, v6, v7), c(v8, v9, v10, v11), and d(v12, v13, v14, v15). Each initialization state vector contains 128 bits of data. The initial information also includes the data to be compressed. The initialization process standardizes data of varying lengths. For example, by padding the data with zeros, a fixed length is obtained. The data is then divided into 64-byte blocks and mapped into 16 32-bit initialization blocks, m0 through m15.

[0050] In an exemplary embodiment of the present application, the initialization information can also be a spliced ​​array. Figure 3A is a schematic diagram of the data structure of the initialized state vector according to an exemplary embodiment of the present application; Figure 3B is a schematic diagram of the data structure of the initialized information block according to an exemplary embodiment of the present application; and Figure 3C is a schematic diagram of the data structure of the spliced ​​array according to an exemplary embodiment of the present application. As shown in Figures 3A-3C, an initialization instruction set can be constructed based on the initialized state vector data structure, the initialization information block data structure, and the spliced ​​array data structure, and the initialization process of the above-mentioned initial data is implemented by executing the instructions in the initialization instruction set. Exemplarily, the starting addresses of the initialized state vector data structure, the initialization information block data structure, and the spliced ​​array data structure are first saved. For example, the following instructions are used: blk2s_sv_init Rn; blk2s_mm_init Rn; blk2s_init Rn; where sv_init is the data corresponding to the initialized state vector, mm_init is the data corresponding to the initialization information block, init is the data corresponding to the spliced ​​array, and Rn is a general register of the 64-bit CPU that stores the starting addresses of sv_init, mm_init, and init.

[0051] According to an exemplary embodiment of the present application, by processing the initial information, an initialization state vector, an initialization information block or a spliced ​​array is obtained, and an initialization instruction set is constructed through its corresponding data structure. By executing the instructions in the initialization instruction set, the initialization of the initial information is completed, which facilitates subsequent preprocessing of the initialization information.

[0052] In an exemplary embodiment of the present application, after obtaining the initialization information, step S200 can also be performed to preprocess the initialization state vector and the initialization information block based on the compression function and the constant matrix to obtain the corresponding first preprocessing vector and the second preprocessing vector, wherein the first preprocessing vector is 4 and the second preprocessing vector is 40. Figure 4A is a logical schematic diagram of the compression function according to the exemplary embodiment of the present application. Figure 4B is a schematic diagram of the formula corresponding to the compression function according to the exemplary embodiment of the present application. Figure 4C is a schematic diagram of the corresponding SIMGA matrix according to the exemplary embodiment of the present application. Figure 5 is a logical block diagram based on the Blake2s algorithm according to the exemplary embodiment of the present application. Figure 6 is a flowchart of obtaining the first preprocessing vector and the second preprocessing vector according to the exemplary embodiment of the present application. As shown in Figure 6, obtaining the first preprocessing vector and the second preprocessing vector may include the following steps:

[0053] Step S210: Arrange the initialized state vector into four first pre-processing vectors;

[0054] Step S220: pre-processing the initialization information block based on the compression function and the constant matrix to obtain a second pre-processing vector corresponding to each round, wherein each round corresponds to 4 second pre-processing vectors.

[0055] The above steps are exemplarily described with reference to Figures 4A to 6. The compression function may include a first compression function G1 and a second compression function G2. Each time the compression function is used for calculation, the initialization state vectors a, b, c, d and the corresponding initialization information blocks are subjected to logical operations to obtain the corresponding compression vectors. The Blake2s algorithm requires 10 rounds of compression, and the input vectors of the compression function in each round are the initialization state vectors a, b, c, d and the corresponding initialization information blocks m output from the previous round. σr(2i) and m σr(2i+1) During each round of compression calculation, the initialization state vector is organized into four 128-bit first preprocessing vectors, namely a, b, c, and d, based on the mapping relationship. Based on the compression function and the constant matrix, the initialization information block is preprocessed to obtain the second preprocessing vector corresponding to each round. For example, the second preprocessing vectors M1-M4 for the first round, M5-M8 for the second round, and M37-M40 for the tenth round are obtained. Table 1 shows the second preprocessing vectors corresponding to the ten rounds.

[0056] Table 1

[0057] In an exemplary embodiment of the present application, upon receiving a storage instruction, the first pre-processing vector is stored in four corresponding first register units (GF00-GF03), and the first storage addresses of the first register units are recorded. The second pre-processing vector is stored in the corresponding second register units, and the second storage addresses of the second register units corresponding to the second pre-processing vectors required for each round of compression are recorded. The first register units are four, and the second register units are 4-40, i.e., the number of second register units is sufficient to meet the second pre-processing vector requirements for at least one compression round. Exemplarily, the number of units of the second register is 4, and before the current compression round is performed, the required second preprocessing vectors are stored in the second register in advance; exemplarily, the number of units of the second register is 40, and the second register can store all the second preprocessing vectors required for 10 rounds of compression calculations, and store the second preprocessing vectors required for each round to the corresponding second storage address, for example, the second preprocessing vectors required for the first round correspond to the second storage addresses GF04-GF07, the second preprocessing vectors required for the second round correspond to the second storage addresses GF08-GF11... and the second preprocessing vectors required for the second round correspond to the second storage addresses GF40-GF43.

[0058] According to an exemplary embodiment of the present application, by preprocessing the initialization information to obtain the first preprocessing vector and the second preprocessing vector, and storing the first preprocessing vector and the second preprocessing vector in the corresponding first register unit and the second register unit in advance, the preprocessing vector required for each compression round can be directly obtained based on the storage address during the subsequent compression calculation process, which can reduce the number of register accesses and improve data processing efficiency.

[0059] In an exemplary embodiment of the present application, after the first preprocessing vector and the second preprocessing vector are stored in the first register unit and the second register unit, step S400 may be further executed to receive at least one compression instruction, and perform 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain a compressed vector.

[0060] FIG7 is a flow chart of obtaining a compressed vector according to an exemplary embodiment of the present application. As shown in FIG7 , obtaining a compressed vector may include the following steps:

[0061] Step S410: receiving a plurality of first compression instructions, wherein the first compression instructions include a first compression function instruction, a second compression function instruction, a first transformation instruction, and a second transformation instruction;

[0062] Step S430: performing first-level compression and diagonal transformation based on the first compression function instruction, the second compression function instruction, the first transformation instruction, the first preprocessing vector, and the second preprocessing vector to obtain a first sub-compressed vector;

[0063] Step S450: performing a second level of compression and an anti-diagonal transformation based on the first sub-compression vector, the second transformation instruction, the first compression function instruction, and the second compression function instruction to obtain a second sub-compression vector, thus completing one round of compression processing;

[0064] Step S470: Based on the second sub-compression vector and the first compression instruction, repeat 10 rounds of compression processing to obtain a compressed vector.

[0065] Exemplarily, upon receiving multiple first compression instructions, wherein the first compression instructions include a first compression function instruction blk2s_g1, a second compression function instruction blk2s_g2, a first transformation instruction blk2s_diag, and a second transformation instruction blk2s_undiag, the first and second preprocessing vectors can first be compressed using the first and second compression function instructions blk2s_g1 and blk2s_g2, and then the matrix composed of the compressed vectors is diagonally transformed. Based on the diagonally transformed matrix, a corresponding first sub-compressed vector is obtained. Figure 8A is a schematic diagram of a diagonal transformation according to an exemplary embodiment of the present application; as shown in Figure 8A, the diagonal transformation of the equivalent matrix of the first preprocessing vector can be implemented using the diagonal transformation instructions. The first sub-compressed vector is then compressed again using the first and second compression function instructions blk2s_g1 and blk2s_g2, and the matrix composed of the compressed vectors is anti-diagonally transformed. Based on the anti-diagonally transformed matrix, a corresponding second sub-compressed vector is obtained. Figure 8B is a schematic diagram of the anti-diagonal transformation according to an exemplary embodiment of the present application. As shown in Figure 8B, the anti-diagonal transformation of the equivalent matrix of the first preprocessing vector can be implemented by the anti-diagonal transformation instruction. Through the above steps, one round of compression can be completed, and the compression process is repeated for 10 rounds to obtain a compressed vector. Among them, blk2s_g1 is based on the first compression function G1, and the first preprocessing vector and the corresponding second preprocessing vector group are compressed and calculated to obtain an updated first preprocessing vector (a', b', c', d'); blk2s_g2 is based on the second compression function G2, and the updated first preprocessing vector (a', b', c', d') and the corresponding second preprocessing vector group are compressed and calculated to obtain an updated first preprocessing vector (a, b, c, d), wherein, based on the number of rounds i of compression calculation, the corresponding second preprocessing vector (M) can be directly obtained in the second register. i -M i+3After each round of compression calculation is completed, an updated first pre-processing vector can be obtained and temporarily stored in registers GF00-GF03 for use in the next round of compression calculation.

[0066] According to an exemplary embodiment of the present application, when multiple first compression instructions are received, the first preprocessing vector and the second preprocessing vector required for each compression round are directly obtained based on the first storage address and the second storage address. While reducing the number of data loading and memory access, the corresponding first preprocessing vector and the second preprocessing vector can be obtained. By reducing the number of data loading and memory access, the efficiency of data processing is improved.

[0067] FIG9 is a flowchart of obtaining a compressed vector according to another exemplary embodiment of the present application. As shown in FIG9 , obtaining a compressed vector may include the following steps:

[0068] Step S420: receiving a second compression instruction, wherein the second compression instruction is one compression instruction;

[0069] Step S440: completing 10 rounds of compression based on the first preprocessing vector, the second preprocessing vector, and the second compression instruction to obtain a compressed vector.

[0070] Exemplarily, upon receiving a second compression instruction, 10 rounds of compression processing are completed based on the second compression instruction to obtain a compressed vector. The second compression instruction is a single compression instruction, and based on the second compression instruction, a first preprocessing vector group and a second preprocessing vector of the corresponding round are obtained in the first register unit and the second register unit. For example, the second compression instruction is blk2s_cmprss, which can complete the compression process in one go and obtain the corresponding compressed vector. The code corresponding to the second compression instruction blk2s_cmprss is shown below:

[0071] Input a,b,c,d,M

[0072] Output a,b

[0073] Blake2s_Compress{

[0074] GF44=a

[0075] GF45=b

[0076] For(i=0;i<10;i+=4){

[0077] Blake2s_Compress_Round(i)

[0078] }

[0079] a=a xor GF44

[0080] b=b xor GF45

[0081] }

[0082] The second compression instruction can directly use the first pre-processing vector and the second pre-processing vector corresponding to registers GF00-GF43 without using memory access instructions or operations, thereby improving the efficiency of data compression by further reducing the number of instructions and the number of data memory access times.

[0083] In an exemplary embodiment of the present application, after obtaining the compression vector, a target digest may be obtained by performing a calculation based on the compression vector and the initialization state vector, wherein the target digest has a length of less than or equal to 32 bytes. For example, the compression vector and the initialization vector may be XORed to generate the target digest, wherein the target digest, also known as a hash value, has a length of less than or equal to 32 bytes.

[0084] According to an exemplary embodiment of the present application, by constructing corresponding initialization instructions, compression instructions, etc., and executing the corresponding instructions, the first preprocessing vector and the second preprocessing vector are stored in the designated register unit of the register in advance. In the subsequent data compression process, the corresponding first preprocessing vector and the second preprocessing vector are directly obtained from the register based on the instructions. By constructing instructions, the complexity of the implementation of the Blake2s algorithm is greatly reduced, the memory access process in the calculation process of the Blake2s algorithm is reduced, and the running speed and efficiency of the Blake2s algorithm are improved.

[0085] On the other hand, the present application provides an instruction processing device 2000 based on the Blake2s algorithm. Figure 10 is a schematic diagram of the instruction processing device 2000 based on the Blake2s algorithm according to an exemplary embodiment of the present application. As shown in Figure 10, the instruction processing device 2000 based on the Blake2s algorithm may include an initialization unit 2100, a braking control unit 2200 and a register 2300. The register 2300 may include a first register unit and a second register unit. The initialization unit 2100 is used to initialize initial information to obtain initialization information, wherein the initialization information includes an initialization state vector and an initialization information block; the braking control unit 2200 is used to pre-process the initialization state vector and the initialization information block based on a compression function and a constant matrix to obtain corresponding first pre-processing vectors and second pre-processing vectors; store the first pre-processing vector in the first register unit and store the second pre-processing vector in the second register unit, wherein the first register unit and the second register unit are 128 bits; and receive at least one compression instruction, and perform 10 rounds of compression processing on the first pre-processing vector and the second pre-processing vector based on the compression instruction to obtain a compressed vector.

[0086] In an exemplary embodiment of the present application, the initialization information may be a spliced ​​array, wherein the spliced ​​array is obtained by splicing the initialization state vector and the initialization information block.

[0087] In an exemplary embodiment of the present application, the braking control unit 2200 can be used to: organize the initialization state vector into 4 first preprocessing vectors; preprocess the initialization information block based on the compression function and the constant matrix to obtain the second preprocessing vector corresponding to each round, wherein each round corresponds to 4 second preprocessing vectors.

[0088] In an exemplary embodiment of the present application, the braking control unit 2200 can be used to: receive a storage instruction, store the first preprocessing vector to the first register unit, and record the first storage address of the first register unit; store the second preprocessing vector to the second register unit, and record the second storage address of the second register unit.

[0089] In one embodiment of the present application, the braking control unit 2200 can be used to: receive multiple first compression instructions, wherein the first compression instruction includes a first compression function instruction, a second compression function instruction, a first transformation instruction, and a second transformation instruction; perform a first level of compression and a diagonal transformation based on the first compression function instruction, the second compression function instruction, the first transformation instruction, the first preprocessing vector, and the second preprocessing vector to obtain a first sub-compression vector; perform a second level of compression and an anti-diagonal transformation based on the first sub-compression vector, the second transformation instruction, the first compression function instruction, and the second compression function instruction to obtain a second sub-compression vector, completing one round of compression processing; repeat 10 rounds of compression processing based on the second sub-compression vector and the first compression instruction to obtain a compression vector.

[0090] In one embodiment of the present application, the braking control unit 2200 can also be used to: receive a second compression instruction, wherein the second compression instruction is 1 compression instruction; complete 10 rounds of compression process based on the first preprocessing vector, the second preprocessing vector and the second compression instruction to obtain a compression vector.

[0091] The specific contents of the corresponding implementations of the initialization unit 2100, the braking control unit 2200 and the register 2300 in the instruction processing device 2000 of the Blake2s algorithm have been described in detail in the instruction processing method based on the Blake2s algorithm, and will not be elaborated here.

[0092] The present application also provides a processor 3000. FIG11 is a schematic block diagram of a processor 3000 according to an exemplary embodiment of the present application. As shown in FIG11 , the processor 3000 includes an instruction processing device 2000 based on the Blake2s algorithm as in any exemplary embodiment of the present application. Regarding the structure, function, and technical effects of the instruction processing device 2000 based on the Blake2s algorithm, please refer to the above-mentioned instruction processing device 2000 based on the Blake2s algorithm, and no further details will be given here.

[0093] Among them, the processor 3000 can be implemented as a central processing unit, such as a central processing unit of an X86 architecture, according to actual needs. It should be noted that in the exemplary embodiment of the present application, the processor 3000 may include more or fewer circuits or units, for example, it may also include related components such as an instruction cache, an instruction scheduler, and an instruction cache area, and this application does not impose specific restrictions on this. The connection relationship between each circuit or unit is not restricted and can be determined according to actual needs. The specific configuration of each circuit or unit is not restricted and can be composed of analog devices according to circuit principles, or it can be composed of digital chips, or it can be composed in other applicable ways. The processor provided in at least one exemplary embodiment of the present application can achieve technical effects similar to those of the aforementioned data processing device, which will not be described in detail here.

[0094] The present application also provides an electronic device 4000. Figure 12 is a schematic block diagram of an electronic device 4000 according to an exemplary embodiment of the present application. As shown in Figure 12, the electronic device 4000 includes a processor 4100 and a memory 4200. It should be noted that the components of the electronic device 4000 shown in Figure 12 are only exemplary and non-restrictive. According to actual application needs, the electronic device 4000 may also have other components. For example, the processor 4100 and the memory 4200 can communicate with each other directly or indirectly. The processor 4100 and the memory 4200 can communicate through a network. The network may include a wireless network, a wired network, and / or any combination of a wireless network and a wired network. The processor 4100 and the memory 4200 can also communicate with each other through a system bus, which is not limited by the present application.

[0095] Exemplarily, the memory 4200 is used to store computer-readable instructions non-transiently. When the processor 4100 is used to execute the computer-readable instructions, the computer-readable instructions are executed by the processor 4100 to implement the instruction processing method based on the Blake2s algorithm according to any of the above exemplary embodiments. For the specific implementation of each step of the instruction processing method based on the Blake2s algorithm and related explanations, please refer to the embodiment of the instruction processing method 1000 based on the Blake2s algorithm above, and the repeated parts will not be repeated here.

[0096] For example, processor 4100 can control other components in electronic device 4000 to perform desired functions. Processor 4100 can be a central processing unit (CPU), a graphics processing unit (GPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The central processing unit (CPU) can be of X86 or ARM architecture, etc.

[0097] Exemplarily, the memory 4200 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor 4100 may execute the computer-readable instructions to implement various functions of the electronic device 4000. Various applications and various data may also be stored in the storage medium.

[0098] For example, in some embodiments, the electronic device 4000 may be a mobile phone, a tablet computer, an electronic paper, a television, a display, a laptop computer, a digital photo frame, a navigator, a wearable electronic device, a smart home device, etc. For example, the electronic device 4000 may include a display panel, and the display panel may be used to display interactive content, etc. For example, the display panel may be a rectangular panel, a circular panel, an elliptical panel, or a polygonal panel, etc. In addition, the display panel may be not only a flat panel, but also a curved panel, or even a spherical panel. For example, the electronic device 4000 may have a touch function, that is, the electronic device 4000 may be a touch device. For a detailed description of the process of the electronic device 4000 executing the instruction processing method based on the Blake2s algorithm, reference may be made to the relevant description in the embodiment of the instruction processing method based on the Blake2s algorithm, and the repeated parts will not be repeated.

[0099] Figure 13 is a schematic diagram of a non-transitory computer-readable storage medium 5000 according to an exemplary embodiment of the present application. As shown in Figure 13, one or more computer-readable instructions 5100 can be non-temporarily stored on the non-transitory computer-readable storage medium 5000. Exemplarily, when the computer-readable instructions 5100 are executed by the processor, one or more steps in the instruction processing method based on the Blake2s algorithm can be executed. Exemplarily, the storage medium 5000 can be applied to the above-mentioned electronic device 4000. For example, the storage medium 5000 may include the memory 4200 in the electronic device 4000. For the description of the storage medium 5000, reference can be made to the description of the memory 4200 in the embodiment of the electronic device 4000, and the repeated parts will not be repeated.

[0100] Exemplarily, the storage device may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor may execute the computer-readable instructions to implement various functions of the processor. Various applications and various data may also be stored in the storage medium.

[0101] Exemplarily, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media.

[0102] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of application of the present application is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the concept of the application. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. An instruction processing method based on the Blake2s algorithm, comprising: Initializing initial information to obtain initialization information, wherein the initialization information includes an initialization state vector and an initialization information block; Preprocessing the initialization state vector and the initialization information block based on the compression function and the constant matrix to obtain corresponding first preprocessing vector and second preprocessing vector; Storing the first preprocessing vector in a first register unit, and storing the second preprocessing vector in a second register unit, wherein the first register unit and the second register unit are 128 bits; At least one compression instruction is received, and based on the compression instruction, 10 rounds of compression processing are performed on the first preprocessing vector and the second preprocessing vector to obtain a compressed vector.

2. The instruction processing method based on the Blake2s algorithm according to claim 1, wherein: The initialization information is a spliced ​​array, wherein the spliced ​​array is obtained by splicing the initialization state vector and the initialization information block.

3. The instruction processing method based on the Blake2s algorithm according to claim 1, wherein: Based on the compression function and the constant matrix, the initialization state vector and the initialization information block are preprocessed to obtain corresponding first preprocessing vectors and second preprocessing vectors, including: Arrange the initialization state vector into four first preprocessing vectors; Based on the compression function and the constant matrix, the initialization information block is preprocessed to obtain the second preprocessing vector corresponding to each round, wherein each round corresponds to 4 second preprocessing vectors.

4. The instruction processing method based on the Blake2s algorithm according to claim 1, wherein: Storing the first preprocessing vector into a first register unit and storing the second preprocessing vector into a second register unit comprises: A storage instruction is received, the first preprocessing vector is stored in the first register unit, and a first storage address of the first register unit is recorded; the second preprocessing vector is stored in the second register unit, and a second storage address of the second register unit is recorded.

5. The instruction processing method based on the Blake2s algorithm according to claim 3, wherein: Receiving at least one compression instruction, and performing 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain a compressed vector, including: Receiving a plurality of first compression instructions, wherein the first compression instructions include a first compression function instruction, a second compression function instruction, a first transformation instruction, and a second transformation instruction; Performing first-level compression and diagonal transformation based on the first compression function instruction, the second compression function instruction, the first transformation instruction, the first preprocessing vector, and the second preprocessing vector to obtain a first sub-compression vector; Performing second-level compression and anti-diagonal transformation based on the first sub-compression vector, the second transformation instruction, the first compression function instruction, and the second compression function instruction to obtain a second sub-compression vector, completing one round of compression processing; Based on the second sub-compression vector and the first compression instruction, 10 rounds of compression processing are repeated to obtain the compressed vector.

6. The instruction processing method based on the Blake2s algorithm according to claim 3, wherein: Receiving at least one compression instruction, and performing 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain a compressed vector, including: receiving a second compression instruction, wherein the second compression instruction is one compression instruction; Ten rounds of compression are completed based on the first preprocessing vector, the second preprocessing vector and the second compression instruction to obtain the compressed vector.

7. An instruction processing device based on the Blake2s algorithm, comprising an initialization unit, a brake control unit and a register, wherein: The initialization unit is used to initialize the initial information to obtain the initialization information, wherein the initialization information includes an initialization state vector and an initialization information block; The braking control unit is connected to the initialization unit and is used to preprocess the initialization state vector and the initialization information block based on a compression function and a constant matrix to obtain corresponding first preprocessing vectors and second preprocessing vectors; store the first preprocessing vector in a first register unit and store the second preprocessing vector in a second register unit, wherein the first register unit and the second register unit are 128 bits; receive at least one compression instruction, and perform 10 rounds of compression processing on the first preprocessing vector and the second preprocessing vector based on the compression instruction to obtain compressed vectors.

8. A processor, comprising the instruction processing device based on the Blake2s algorithm as claimed in claim 7.

9. An electronic device comprising: Memory, non-transitory storage of computer executable instructions: a processor configured to execute the computer executable instructions, in, When the computer executable instructions are executed by the processor, the instruction processing method based on the Blake2s algorithm according to any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the instruction processing method based on the Blake2s algorithm according to any one of claims 1 to 6 is implemented.

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