Circuit and method for generating labeled image

Abstract

The present application relates to a circuit and method for generating a labeled image. The circuit for generating a labeled image comprises: a plurality of pixels arranged in an array, wherein the pixels each comprise a photosensitive structure and a voltage reader, the photosensitive structure is provided with a photoelectric sensing area and an equivalent capacitance area, and the voltage reader is electrically connected to the equivalent capacitance area; a dual-correlation sampler, wherein a first input end of the dual-correlation sampler is electrically connected to the voltage readers, and a second input end of the dual-correlation sampler is used for allowing a threshold value voltage to access same; a counter, wherein a counting control end of the counter is electrically connected to an output end of the dual-correlation sampler; and a processor, which is electrically connected to the counter, wherein the processor is used for forming a label. The circuit for generating a labeled image is based on physically unclonable features of photosensitive structures, thereby facilitating the attachment of reliable and accurate labels to images.

Description

Circuit and method for generating labeled images

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311043517.4, filed on August 17, 2023, entitled “Circuit and method for generating labeled images,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of information verification technology, and in particular to a circuit and method for generating labeled images. Background Art

[0004] It is common to use image sensors to generate image data and then transmit it. However, image data may be tampered with during transmission, making it difficult for the receiver to confirm the authenticity of the received image.

[0005] In addition to ensuring the security of the transmission path, data-device hashing technology based on a physically unclonable function is also used to verify the authenticity of image data. This technology leverages the physical unclonability of image sensors and combines it with image-aware hashing technology to generate a label for the image that contains both image and device information.

[0006] In image sensors, the dark response nonuniformity of fixed-pattern noise can serve as a basis for physically unclonable functions. However, the physically unclonable function based on this parameter requires a completely dark operating environment to ensure stability. In the context of mobile device cameras, for example, which commonly use electronic shutters without physical shielding, this approach cannot shield the signal from the effects of ambient light, significantly reducing recognition accuracy.

[0007] Summary of the Invention

[0008] Therefore, it is necessary to provide a circuit and method for generating labeled images to generate image data that can be reliably verified.

[0009] It is necessary to provide a verification device and method that can reliably verify image data.

[0010] The present application provides a circuit for generating a labeled image, which includes: multiple pixels in an array, each pixel including a photosensitive structure and a voltage reader, the photosensitive structure having a photoelectric sensing area and an equivalent capacitance area, and the voltage reader electrically connected to the equivalent capacitance area; a dual-correlation sampler, a first input end of the dual-correlation sampler electrically connected to the voltage reader, and a second input end of the dual-correlation sampler for accessing a threshold voltage; a counter, a count control end of the counter electrically connected to an output end of the dual-correlation sampler; and a processor electrically connected to the counter, the processor being used to form a label.

[0011] The above-mentioned circuit for generating labeled images can identify the voltage drop in the equivalent capacitance area because a voltage reader is provided to collect the charge in the equivalent capacitance area. This voltage drop information is insensitive to light, and the voltage drop characteristics are based on the physical non-clonable characteristics of the photosensitive structure. Using this voltage drop characteristic for sampling and counting helps to achieve reliable and accurate labeling of images.

[0012] In some embodiments, the circuit further includes a temperature sensor for measuring the temperature of a plurality of pixels, the temperature sensor being electrically connected to the processor; the processor being configured to: in response to a count value of a first pixel in a pair of pixels being greater than a count value of a second pixel, set the comparison result to a first comparison value; in response to a count value of the first pixel in a pair of pixels being less than or equal to a count value of the second pixel, set the comparison result to a second comparison value; and form a label based on the temperature and the comparison result.

[0013] This setting helps eliminate deviations caused by temperature and facilitates more reliable labeling.

[0014] In some embodiments, the circuit further includes a pseudo-random number generator for generating a pseudo-random number based on the temperature; the processor is configured to: sample a preset number of pixels, and obtain a comparison result based on each pair of predetermined pixels, wherein the first comparison value is 1 and the second comparison value is 0; sort the comparison results into a numerical string in a preset order; and perform an XOR calculation on the numerical string and the pseudo-random number to obtain an encrypted numerical string.

[0015] Such an arrangement can form a label with better confidentiality and help ensure that the pixel selection process in the circuit is not clonable.

[0016] In some embodiments, the circuit further includes an amplifier, an analog-to-digital converter, and timing control logic, the amplifier is connected in parallel with the voltage reader, the analog-to-digital converter is electrically connected to the amplifier, the timing control logic is electrically connected to the amplifier, the voltage reader, the dual-correlated sampler, and the counter, and the voltage reader includes a transistor.

[0017] Such an arrangement helps to accurately form image data and corresponding labels.

[0018] An embodiment of the present application also provides a method for generating a labeled image, which includes: obtaining image data in response to light sensing of multiple pixels of an array, wherein the pixels include a photosensitive structure and a voltage reader, the photosensitive structure has a photoelectric sensing area and an equivalent capacitance area, and the voltage reader is electrically connected to the equivalent capacitance area; performing double-correlation sampling on the equivalent capacitance area based on a threshold voltage; counting according to the results of the double-correlation sampling step; and forming a label based on the count value of the counting step.

[0019] The method provided in the embodiment of the present application utilizes the physical non-clonable property of the photosensitive structure to form a label, which helps to verify the reliability of image data; at the same time, the equivalent capacitance area utilized is insensitive to light and can be better applied in practice.

[0020] In some embodiments, the method further includes: measuring the temperature of a plurality of pixels; the step of forming a label includes: comparing the values ​​of the counting step, the step of comparing including: in response to the count value of the first pixel in a pair of pixels being greater than the count value of the second pixel, setting the comparison result to a first comparison value; in response to the count value of the first pixel in a pair of pixels being less than or equal to the count value of the second pixel, setting the comparison result to a second comparison value; and forming a label based on the temperature and the comparison result.

[0021] Such a setting can form a label with better confidentiality and help ensure the non-cloning of the pixel selection process.

[0022] In some embodiments, the method further includes: generating a pseudo-random number based on the temperature; and sampling a preset number of pixels; the step of forming a label includes: obtaining a comparison result based on each pair of predetermined pixels, wherein the first comparison value is 1 and the second comparison value is 0; sorting the comparison results into a numerical string in a preset order; and performing an XOR calculation on the numerical string and the pseudo-random number to obtain an encrypted numerical string.

[0023] This configuration can form an encrypted value string, which helps to ensure the reliability of the tag and realize decryption verification.

[0024] In some embodiments, the method further includes: obtaining a preprocessed image based on image data formed by a plurality of pixels; dividing the preprocessed image into a preset number of blocks, performing feature extraction on each block to obtain a feature group; and mapping and determining the coordinates of a preset number of pixels in the image data based on the feature group.

[0025] With this arrangement, pixels are selected based on the features of the image data, which ensures the correlation between the image data and the features and guarantees the reliability of verification.

[0026] In some embodiments, the method further includes: sequentially scaling, smoothing, grayscale, and histogram equalization processing the image data formed by a plurality of pixels to obtain a preprocessed image; dividing the preprocessed image into a preset number of blocks, performing feature extraction on each block through discrete cosine transform to obtain a feature group; and mapping and determining the coordinates of a preset number of pixels in the image data based on the feature group.

[0027] With this arrangement, pixels can be selected with a relatively balanced probability, and the discrete cosine transform method makes the pixel selection process reliable, sensitive, and difficult to be disguised.

[0028] In some embodiments, the double correlation sampling step includes: determining the sign of the output value of the double correlation sampling by subtracting the threshold voltage from the voltage provided by the equivalent capacitance region; starting counting when performing the double correlation sampling; and stopping counting and obtaining the count value in response to the output value sign being a negative sign.

[0029] With this arrangement, the count value can be obtained simply and sensitively to accurately reflect the voltage drop characteristics of the equivalent capacitance area, ensuring the accuracy and reliability of the tag.

[0030] In a second aspect, an embodiment of the present application further provides a verification method, which includes: confirming a circuit model corresponding to the claimed circuit of the label to be verified based on the image data to be verified and the label to be verified; performing simulated photosensitization corresponding to the image data to be verified on the circuit model, and generating a comparison label through the circuit model; and in response to the bit error rate between the comparison label and the label to be verified being less than or equal to a qualified threshold, determining that the image data to be verified is generated by the claimed circuit.

[0031] The verification method provided in the embodiment of the present application verifies the tag to be verified and the image data to be verified, and uses the unclonable correlation between the tag to be verified and the real image data to accurately and securely verify whether the image data to be verified is the real image data generated by the claimed circuit.

[0032] In some embodiments, the verification method also includes: utilizing a pseudo-random number generator model in a circuit model to decrypt a numerical string to be verified according to a temperature value in a label to be verified to obtain a decrypted numerical string; performing scaling, smoothing, grayscale, and histogram equalization processing on the image data in sequence to obtain a preprocessed image; dividing the preprocessed image into a preset number of blocks, performing feature extraction on each block through discrete cosine transform to obtain a feature group; mapping the coordinates of a preset number of pixel models in the circuit model in the image data according to the feature group; sampling a preset number of pixel models, and obtaining a comparison result based on each pair of predetermined pixel models; wherein the step of forming a label includes: sorting the comparison results into a comparison numerical string in a preset order.

[0033] With this arrangement, the steps performed by the verification method on the circuit model are the same as the steps when the circuit is labeled, thereby ensuring the accuracy of the comparison value string, which in turn helps to ensure the accuracy of the verification conclusion.

[0034] An embodiment of the present application further provides a verification device, which includes: a verification memory storing a computer program; and a verification processor electrically connected to the verification memory, wherein the computer program implements the steps of the aforementioned verification method when executed by the verification processor.

[0035] An embodiment of the present application provides a verification device, which includes: a matching module, configured to confirm the circuit model corresponding to the claimed circuit of the label to be verified based on the image data to be verified and the label to be verified; a simulation module, configured to perform simulated photosensitization corresponding to the image data to be verified on the circuit model, and generate a comparison label through the circuit model; and a verification module, configured to determine that the image data to be verified is generated by the claimed circuit in response to the bit error rate between the comparison label and the label to be verified being less than or equal to a qualified threshold.

[0036] An embodiment of the present application provides a non-volatile storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the aforementioned verification method can be implemented.

[0037] An embodiment of the present application provides a computer program product, including a computer program, which can implement the steps of the aforementioned verification method when executed by a processor.

[0038] The verification device, verification apparatus, non-volatile storage medium, and computer program product provided in the embodiments of the present application can be used to implement the steps of the aforementioned verification method and can determine whether the image data to be verified is truly generated by the claimed circuit.

[0039] In a third aspect, the embodiments of the present application further provide an electronic device, which includes the aforementioned circuit for generating a labeled image.

[0040] The electronic device provided in the embodiments of the present application can generate image data, and the image data has a corresponding label. The image data provided by the electronic device can be verified to determine whether the image data has been tampered with. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0042] FIG1 is a schematic diagram of a circuit for generating a labeled image according to an embodiment of the present application;

[0043] FIG2 is a schematic diagram of the structure of the photosensitive branch in the pixel;

[0044] FIG3 is an equivalent circuit diagram of the photosensitive shunt shown in FIG2 ;

[0045] FIG4 is a local equivalent circuit topology diagram of a circuit provided in an embodiment of the present application;

[0046] FIG5 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0047] FIG6 is a schematic flowchart of a method for generating labeled images provided in an embodiment of the present application;

[0048] FIG7 is a schematic flowchart of a method for generating labeled images provided in an embodiment of the present application;

[0049] FIG8 is a schematic diagram of the structure of a verification device provided in an embodiment of the present application;

[0050] FIG9 is a schematic diagram of a network for communication verification;

[0051] FIG10 is a schematic signaling diagram of the communication verification process;

[0052] FIG11 is a schematic flow chart of a verification method provided in an embodiment of the present application;

[0053] FIG12 is a schematic structural block diagram of a verification device provided in an embodiment of the present application;

[0054] Figure 13 is a data diagram of simulation verification;

[0055] Figure 14 is an original image;

[0056] FIG15 is a tampered image of FIG14 .

[0057] Description of reference numerals:

[0058] 1. Pixel; 101. Photosensitive shunt; 2. Row line; 3. Column line; 4. Row selector; 5. Column selector; 6. Dual-correlated sampler; 601. First input terminal; 602. Second input terminal; 7. Timing control logic; 8. Counter; 81. Count control terminal; 82. Count trigger terminal; 83. Count output terminal; 9. Analog-to-digital converter; 10. Processor;

[0059] 11. Photosensitive structure; 111. Photoelectric sensing region; 112. Equivalent capacitance region; 12. Substrate; 13. First doped region; 14. Second doped region; 15. Third doped region; 16. Gate; 17. Amplifier; 18. Reset transistor; 19. Amplifier transistor; 20. Select transistor; 21. Voltage reader;

[0060] 22. First switching tube; 23. Second switching tube; 24. Third switching tube; 25. Fourth switching tube; 26. First bypass capacitor; 27. Second bypass capacitor; 28. First sampling tube; 29. ​​Second sampling tube; 30. Arithmetic unit; 301. Arithmetic output terminal;

[0061] 31. Memory; 32. First internal memory; 33. First non-volatile storage medium; 34. First system bus; 35. First communication interface; 36. Pseudo-random number generator; 37. Temperature sensor; 401. Verification memory; 402. Second internal memory; 403. Second non-volatile storage medium; 404. Second system bus; 405. Second communication interface; 406. Verification processor; 610. Matching module; 620. Simulation module; 630. Verification module;

[0062] 100. Circuit for generating labeled images; 200. Electronic device; 300. Communication network; 400. Server; 500. Data storage system; 600. Verification device. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0064] The accompanying drawings illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0066] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first pixel may be referred to as a second pixel, and similarly, a second pixel may be referred to as a first pixel, without departing from the scope of this application. Both the first pixel and the second pixel are pixels, but they are not the same pixel.

[0067] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0068] It will be understood that "at least one" refers to one or more, "a plurality" refers to two or more, and "at least a portion of an element" refers to a portion or all of an element. The singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0069] The terms "include / comprising" or "having" etc. specify the presence of stated features, integers, steps, operations, components, parts or their combinations, but do not exclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts or their combinations. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0070] 1 , an embodiment of the present application provides a circuit for generating a labeled image. In some embodiments, the circuit 100 for generating a labeled image includes a plurality of pixels 1 , a dual correlation sampler 6 , a counter 8 , and a processor 10 .

[0071] For example, a plurality of pixels 1 are arranged in an array, each pixel 1 being used to obtain light-sensing data, which constitutes image data according to the array position. The circuit 100 for generating a labeled image may include a row selector 4, a column selector 5, row lines 2, and column lines 3. The row selector 4 is electrically connected to each pixel 1 via the row lines 2, and the column selector 5 is electrically connected to each pixel 1 via the column lines 3. The row selector 4 and the column selector 5 can select pixels 1 at various positions.

[0072] 2 , pixel 1 includes a photosensitive shunt 101, which can be designed based on a common pixel structure, such as a 4T-type pixel structure. Pixel 1 also includes a photosensitive structure 11 and an amplifier 17. Amplifier 17 outputs an amplified signal to column line 3 based on a power supply signal VDD and a light-sensing signal from photosensitive structure 11.

[0073] Exemplarily, the photosensitive structure 11 may include an integrated semiconductor structure. The semiconductor structure of the photosensitive structure 11 may include a substrate 12, a first doping region 13, a second doping region 14, and a third doping region 15. The photosensitive structure 11 also includes an insulating layer (not shown) and a gate 16. The substrate 12 and the first doping region 13 may have a first doping type, such as hole doping. The second doping region 14 and the third doping region 15 may have a second doping type, such as electron doping.

[0074] The photosensitive structure 11 has a photoelectric sensing region 111 and an equivalent capacitance region 112. In the photoelectric sensing region 111, the second doping region 14 extends into the substrate 12, the substrate 12 may have p-type doping, and the second doping region 14 may have n+ type doping. The first doping region 13 extends into the second doping region 14, and the first doping region 13 may have p+ type doping. The photoelectric sensing region 111 can generate photogenerated carriers under the irradiation of light. In the equivalent capacitance region 112, the third doping region 15 extends into the substrate 12, the third doping region 15 may extend from the same side as the second doping region 14, and the third doping region 15 has n+ type doping. The gate 16 is used to form a channel in the portion of the substrate 12 located between the third doping region 15 and the second doping region 14 for the flow of photogenerated carriers. The amplifier 17 can be electrically connected to the third doping region 15.

[0075] Referring to Figure 3, which shows the equivalent circuit diagram of Figure 2, in the photosensitive structure 11, the structure at the gate 16 is a metal-oxide semiconductor field-effect transistor (MOSFET), the structure at the photosensitive region 111 is a photodiode, and the structure at the equivalent capacitor region 112 is a capacitor. These three equivalent components in the photosensitive structure 11 form a circuit.

[0076] As shown in FIG4 and with reference to FIG1 , in an embodiment of the present application, pixel 1 further includes a voltage reader 21. Voltage reader 21 is electrically connected to equivalent capacitance region 112. Voltage reader 21 can be electrically connected to column line 3. A first input 601 of dual-correlation sampler 6 is electrically connected to voltage reader 21, for example, via column line 3. A second input 602 of dual-correlation sampler 6 is used to access threshold voltage TLV. Exemplarily, dual-correlation sampler 6 includes an operator 30, and an output 301 of operator 30 can serve as an output of dual-correlation sampler 6.

[0077] The counter 8 has a count trigger terminal 82, a count control terminal 81, and a count output terminal 83. The count control terminal 81 is electrically connected to the output terminal of the dual correlation sampler 6. The count output terminal 83 can be electrically connected to the processor 10.

[0078] The processor 10 is used to form a label. Specifically, the processor 10 can form a label according to the output signal of the counter 8.

[0079] When the circuit 100 for generating a labeled image is in use, the pixel 1 is sensitive to light. When an image needs to be generated, the voltage reader 21 is turned off, and the photosensitive structure 11 can transmit a signal to the column line 3 through the amplifier 17. After the pixel 1 is sensitive to light, the photosensitive region 111 generates photogenerated carriers, such as photogenerated electrons. The photogenerated electrons can be captured by the reverse bias electric field in the PN junction of the photosensitive region 111 and retained in the potential well. Specifically, these photogenerated electrons can be gathered in the partial structure corresponding to the equivalent capacitance region 112 in the MOSFET at the gate 16. In order to generate a label, the amplifier 17 can be turned off and the voltage reader 21 can be turned on according to the acquisition signal PW. Since the photosensitive structure 11 forms a discharge circuit, the PN junction in the discharge circuit has an equivalent resistance. The equivalent capacitance region 112 will slowly discharge, and the voltage value collected by the voltage reader 21 will gradually decrease.

[0080] Due to the limited precision of semiconductor material processing, the physical properties of the photosensitive structure 11 may vary slightly within the same product model. This can manifest as, for example, different delays within the same path, different threshold voltages of transistors, or different maximum capacitance values ​​of capacitors. The physical properties of each different photosensitive structure 11 are random and uncontrollable; however, the physical properties of the same photosensitive structure 11 are deterministic and repeatable.

[0081] The circuit for generating a labeled image provided in the embodiments of the present application utilizes a voltage reader to collect the charge of an equivalent capacitance region, thereby identifying the voltage drop in the equivalent capacitance region. This voltage drop information is insensitive to light, and the voltage drop characteristics are based on the physical unclonable characteristics of the photosensitive structure. Using this voltage drop characteristic for sampling and counting facilitates the reliable and accurate labeling of images. The label can be a physically unclonable function, which utilizes behavioral differences caused by differences in the physical characteristics of integrated circuit chips as a unique encryption key to identify an integrated circuit chip, thus providing high security.

[0082] Exemplarily, the amplifier 17 includes a reset tube 18, an amplifier tube 19 and a selection tube 20. The reset tube 18 is electrically connected to the third doping region 15, and uses the power supply signal VDD to reset the photosensitive structure 11 in response to the reset signal RS. The gate 16 is closed during the reset. The amplifier tube 19 amplifies the power supply signal VDD according to the signal of the photosensitive structure 11 to obtain an amplified signal. The selection tube 20 can transmit the amplified signal to the column line 3 according to the selection signal SEL. The voltage reader 21 includes a triode. The amplifier 17 is connected in parallel with the voltage reader 21. The amplifier 17 is conducive to amplifying the photosensitive signal and reducing noise. The voltage reader 21 collects the photosensitive structure 11, which is conducive to avoiding the influence of the amplifier 17 on the collected signal and ensuring the verifiability of the photosensitive structure 11.

[0083] 1 and 4 , circuit 100 for generating a labeled image further includes an analog-to-digital converter 9 and timing control logic 7. Analog-to-digital converter 9 can be electrically connected to amplifier 17. Timing control logic 7 can be electrically connected to amplifier 17, voltage reader 21, dual-correlated sampler 6, and counter 8. Timing control logic 7 can be electrically connected to count trigger terminal 82 of counter 8. Timing control logic 7 can issue timing control signals to various devices.

[0084] For example, in the circuit 100 for generating a labeled image, the dual correlation sampler 6 is configured to perform dual correlation sampling on the output signal of the voltage reader 21 and the threshold voltage TLV, and also to perform dual correlation sampling on a photosensitive signal, such as the amplified signal output by the amplifier 17. This configuration makes the circuit 100 for generating a labeled image compact.

[0085] Specifically, the analog-to-digital converter 9 is electrically connected to the amplifier 17 via the dual-correlated sampler 6, which has a composite function. In other embodiments, different dual-correlated samplers may be provided. The analog-to-digital converter 9 is used to perform analog-to-digital conversion on a sampling result obtained based on the photosensitive signal or the amplified signal. The photosensitive data output by the analog-to-digital converter 9 can be used to form image data.

[0086] Referring to Figure 4 , illustratively, the operator 30 of the dual-correlation sampler 6 can perform subtraction on two input signals and output the result. The non-inverting input of the operator 30 is electrically connected to the first sampling tube 28, and the inverting input is electrically connected to the second sampling tube 29. The first sampling tube 28 can be turned on in response to the first sampling signal CDS1, and the second sampling tube 29 can be turned on in response to the second sampling signal CDS2. The first input 601 of the dual-correlation sampler 6 is electrically connected to the first sampling tube 28 via the first switch 22 and the third switch 24, respectively, and to the second sampling tube 29 via the fourth switch 25. The second input 602 of the dual-correlation sampler 6 is electrically connected to the second sampling tube 29 via the second switch 23. Illustratively, a first bypass capacitor 26 is connected between the third switch 24 and the first sampling tube 28, and a second bypass capacitor 27 is connected between the fourth switch 25 and the second sampling tube 29 to filter noise signals.

[0087] The dual-correlated sampler 6 can be controlled by the timing control logic 7. When dual-correlated sampling of the light-sensing signal is required, the timing control logic 7 generates a first sampling control signal S1 and a second sampling control signal S2, turning on the third switch 24 and the fourth switch 25, while turning off the first switch 22 and the second switch 23. When dual-correlated sampling of the signal from the voltage reader 21 is required, the timing control logic 7 generates a third sampling control signal S3 and a fourth sampling control signal S0, turning on the first switch 22 and the second switch 23, while turning off the third switch 24 and the fourth switch 25.

[0088] Referring to FIG5 , an embodiment of the present application provides an electronic device. For example, electronic device 200 may be, but is not limited to, various personal computers, laptops, smartphones, tablet computers, IoT devices, and portable wearable devices. IoT devices may include smart monitoring devices and smart vehicle-mounted devices, while portable wearable devices may include smart watches and head-mounted devices. Electronic device 200 includes the aforementioned circuit 100 for generating labeled images.

[0089] For example, the electronic device 200 may include multiple circuits 100 for generating labeled images. For example, a mobile phone may include a front camera and a main camera, each of which may be a different circuit. The labeled image obtained by the electronic device 200 can be declared to the specific circuit that generated it.

[0090] In some embodiments, the circuit 100 for generating a labeled image further includes a temperature sensor 37. The temperature sensor 37 is used to measure the temperature of the plurality of pixels 1, and the temperature sensor 37 is electrically connected to the processor 10. The processor 10 may be configured to: in response to the count value of the first pixel in a pair of pixels 1 being greater than the count value of the second pixel, set the comparison result to a first comparison value; in response to the count value of the first pixel in a pair of pixels being less than or equal to the count value of the second pixel, set the comparison result to a second comparison value; and form a label based on the temperature and the comparison result. Measuring the temperature through the temperature sensor 37 can reliably ensure the verifiability of each photosensitive structure 11; and forming a label based on the comparison value can ensure the physical unclonability while making the label data reliable and sensitive, thereby ensuring the identification of tampering.

[0091] In some embodiments, the circuit 100 for generating a labeled image further includes a pseudo-random number generator 36. The pseudo-random number generator 36 is configured to generate a pseudo-random number based on the temperature. The processor 10 can be configured to: sample a preset number of pixels 1, obtain a comparison result for each pair of predetermined pixels, wherein the first comparison value is 1 and the second comparison value is 0; sort the comparison results into a numerical string in a preset order; and perform an XOR operation on the numerical string and the pseudo-random number to obtain an encrypted numerical string. This configuration can increase the confidentiality of the label while ensuring reliable decryption. The setting of the comparison value can make the numerical string robust and the verification result more intuitive.

[0092] Exemplarily, the electronic device 200 further includes a memory 31, an input / output interface (I / O, not shown), and a first communication interface 35. The electronic device 200 may also include an input device (not shown) and a display unit (not shown) for forming a visually visible image. The processor 10, memory 31, and input / output interface are connected via a first system bus 34; exemplarily, the first communication interface 35, the display unit, and the input device are connected to the system bus via the input / output interface. The processor 10 of the electronic device 200 is used to provide computing and control capabilities. The memory 31 includes a first non-volatile storage medium 33 and a first internal memory 32. The first non-volatile storage medium 33 stores an operating system and computer programs. The first internal memory 32 provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the electronic device 200 is used to exchange information between the processor 10 and external devices. The first communication interface 35 is used to communicate with external devices via wired or wireless communication. The wireless communication can be implemented via Wi-Fi, a mobile cellular network, NFC (near field communication), or other technologies. When the computer program is executed by a processor, it implements a method for generating labeled images.

[0093] Referring to FIG6 , an embodiment of the present application provides a method for generating a labeled image. Method 1000 for generating a labeled image provided in an embodiment of the present application can be performed using the aforementioned circuit 100 or electronic device 200 for generating a labeled image. Exemplarily, method 1000 for generating a labeled image includes the following steps S110 to S140.

[0094] In step S110 , image data is obtained in response to light sensing by multiple pixels of the array. For example, the photosensitive structure 11 of the pixel 1 includes a photoelectric sensing region 111 and an equivalent capacitance region 112 . The photoelectric sensing region 111 is used for light sensing, and the voltage of the equivalent capacitance region 112 can be transmitted by the voltage reader 21 .

[0095] Step S120, performing double-correlated sampling on the equivalent capacitance area. Double-correlated sampling can be performed based on the voltage signal of the equivalent capacitance area 112 and the threshold voltage TLV, for example, a subtraction operation. The threshold voltage TLV can be set as needed to obtain a corresponding sampling result. Exemplarily, since it takes a certain amount of time for the voltage of the equivalent capacitance area 112 to drop, the voltage reader 21 can be periodically turned on and the voltage of the equivalent capacitance area 112 can be periodically read. The reading cycle is shorter than the voltage drop time of the equivalent capacitance area 112.

[0096] In step S130, counting is performed based on the results of the dual-correlated sampling step. For example, the operation of each device can be controlled by timing control logic 7. For example, a read signal PW can be issued to turn on voltage reader 21, and a start count signal ST can be issued to count trigger terminal 82 to start counter 8. The dual-correlated sampler 6 is electrically connected to count control terminal 81. For example, in response to the result of the subtraction operation becoming negative, counter 8 outputs a count value.

[0097] In step S140, a label is formed based on the count value obtained in the counting step. The processor 10 is electrically connected to the count output terminal. Photosensitive structures 11 with different physical properties have different voltage drop characteristics, which can then generate corresponding count values ​​based on the physical properties. Based on these values, a physical unclonable function can be designed to generate a label. The label includes the physical unclonable function and states that the image data obtained during this photosensitive process was generated by the circuit 100 for generating labeled images.

[0098] The method provided in the embodiment of the present application is used to generate labeled images. The method is based on the physical non-clonable characteristics of the photosensitive structure and is less affected by ambient light. The label formed outside the image data is reliable and can be effectively used to verify whether the image data has been tampered with.

[0099] Exemplarily, the dual-correlation sampling process includes: determining the sign of the output value of the dual-correlation sampling by subtracting the threshold voltage TLV from the voltage provided by the equivalent capacitance region 112; starting counting when performing the dual-correlation sampling; and stopping counting in response to the output value being negative, thereby obtaining the count value. Alternatively, other methods may be used to process the voltage provided by the equivalent capacitance region 112 and obtain a value based on the physically unclonable feature.

[0100] 7 , illustratively, the method 1000 for generating a labeled image further includes step S105 of measuring the temperature of a plurality of pixels 1. The labeled data may include temperature, which helps to ensure verification accuracy.

[0101] Exemplarily, the step of forming a label includes comparing the values ​​from the counting step and forming a label based on the temperature and the comparison result. This comparison step includes setting the comparison result to a first comparison value in response to the count value of the first pixel in a pair of pixels 1 being greater than the count value of the second pixel; and setting the comparison result to a second comparison value in response to the count value of the first pixel in the pair of pixels 1 being less than or equal to the count value of the second pixel. Each pair of pixels 1 can be defined by a specific method rather than randomly selected to ensure verifiability.

[0102] In some embodiments, the method 1000 for generating a labeled image further includes: obtaining a preprocessed image based on image data formed by a plurality of pixels; dividing the preprocessed image into a predetermined number of blocks, performing feature extraction on each block to obtain a feature group; and mapping the coordinates of a predetermined number of pixels in the image data based on the feature group. Selecting pixels 1 based on the image features helps ensure the relevance of the label to the image data, thereby enhancing the ability to identify tampered image data.

[0103] Exemplarily, the pixel 1 of the array can achieve an image resolution of 1920×1080. After the circuit 100 for generating a labeled image generates image data, the image data can be recorded as an initial matrix M^(1920×1080). The image data can be scaled to a scaled image with an image resolution of 400×320 using bilinear interpolation. Afterwards, a Gaussian filtering operation with a convolution kernel of 3×3 and a Gaussian function δ=1.5 can be used to smooth the scaled image, which can reduce the high-frequency details of the scaled image and improve the stability of the image feature extraction results. The smoothed image can then be converted into a grayscale image and histogram equalization can be performed. This can make the difficult-to-detect features in the scaled image due to the uneven distribution of pixel values ​​clearer and more obvious, which is beneficial to improving the accuracy of feature extraction of the image data. A preprocessed image can be obtained by such processing, which is recorded as a preprocessing matrix M^(400×320).

[0104] Exemplarily, discrete cosine transform can be used to extract features from pre-processed images. The pre-processed image can be divided into N blocks, where N is a preset number. N can be a positive integer, not exceeding the number of pixels 1. For example, it can be 32, 64, or 128. Exemplarily, N is 128, which can ensure the complexity of the formed label while taking into account the calculation time. The discrete cosine transform method represents the pixel value as the sum of cosine curves of different frequencies and amplitudes. The features extracted from these blocks can be recorded as F = {F1, F2, ..., F N The block is transformed into a feature matrix by discrete cosine transformation, in which the elements of the first row and the first column are called DC coefficients, and the remaining elements are called AC coefficients. In the feature matrix of each block, the DC coefficient and the AC coefficients adjacent to the DC coefficient contain the most original image information. The embodiment of the present application stipulates that the feature F of the block i The calculation method is:

[0105] Where i is an integer from 1 to N, C j，k is the element value of the jth row and kth column in the feature matrix. Feature F i The value of can be rounded.

[0106] The feature F obtained by the method provided in this embodiment iVery sensitive. Modifications to the image data can affect the discrete cosine transform coefficients, causing features to be mapped to different pixels1, which in turn can lead to significant deviations in the response to the physical unclonable function contained in the label.

[0107] For example, graying the image data can reduce the impact of the color adjustment step on feature extraction during post-processing of the image data. In some embodiments, it is believed that, for example, the electronic device 200 can perform harmless processing on the image data, thereby eliminating the need for label verification. By transforming the feature F from a continuous type to a discrete type, the probability of changes in the mapping result caused by small errors in the discrete cosine transform coefficients can be reduced, which is conducive to mapping the features extracted during label generation and label verification to the same pixel point, ensuring the robustness of the method 1000 for generating labeled images and the circuit 100 for generating labeled images.

[0108] Exemplarily, the method of converting the feature F into a discrete type can be implemented using the following software program.

[0109] In order to locate a specific pixel in a pixel array formed by a plurality of pixels 1 of the array, row coordinates and column coordinates can be used. The result of the above feature extraction step is a one-dimensional array, and then the feature F can be upgraded. For example, the coordinate P can be obtained by normalizing the maximum value based on the length and width of the pixel array. x .

[0110] Among them, F min is the minimum value after discrete cosine transform, F max = is the maximum value after discrete cosine transform, and the brackets represent rounding the numbers therein. Thus, feature F has been mapped to N / 2 pixels 1 in the pixel array. These pixels 1 are regarded as predetermined pixels 1, and the coordinates of these pixels 1 can be recorded as P.

[0111] Exemplarily, the method 1000 for generating a labeled image further includes: step S160, generating a pseudo-random number based on the temperature; sampling a preset number of pixels, wherein step S170 may be executed, obtaining a feature group based on the image data, and determining the coordinates of a predetermined number of pixels by mapping the feature group in the image data; the step of forming a label includes: step S141, obtaining a comparison result based on each pair of predetermined pixels, wherein the first comparison value is 1 and the second comparison value is 0; step S142, sorting the comparison results into a numerical string in a preset order; and step S143, performing an XOR calculation on the numerical string and the pseudo-random number to obtain an encrypted numerical string.

[0112] The pixels 1, the dual correlation sampler 6 and the counter 8 can be controlled by the timing control logic 7. In the method 1000 for generating a labeled image, the pixels 1 can be powered according to the predetermined coordinates P of the pixels 1. When N is 128, the number of the pixels 1 is 64, and then P can be y The pixel at position 1 is considered as the first pixel, P y+32 The pixel at position y is considered the second pixel, where 1≤y≤32.

[0113] For each predetermined pixel 1, the following steps may be performed to generate a physical unclonable function response.

[0114] In the reset step, the timing control logic 7 generates a reset signal RS, the reset transistors 18 of all pixels 1 in the pixel array are turned on, the voltage reader 21 is turned off, the MOSFET at the gate 16 is turned off, and a reverse voltage is applied to the photodiode at the photosensitive region 111.

[0115] After a short delay, reset signal RS becomes inactive, powering off the pixel array and turning off reset transistor 18. Charge accumulates in the portion of the MOSFET structure at gate 16 corresponding to equivalent capacitance region 112. At this point, a discharge loop is formed in photosensitive structure 11, consisting of an equivalent capacitor and a PN junction equivalent resistor. Self-discharge occurs in equivalent capacitance region 112, causing its voltage to gradually decrease.

[0116] Timing control logic 7 can generate a start count signal ST, a third sampling control signal S3, and a fourth sampling control signal S0, and illustratively, a periodic acquisition signal PW. Counter 8 begins counting. When voltage reader 21 is turned on, the voltage at equivalent capacitance region 112 is read to first input terminal 601 of dual-correlation sampler 6. First and second switches 22 and 23 are turned on, while third and fourth switches 24 and 25 are turned off. The read voltage can be subtracted from threshold voltage TLV. When count control terminal 81 receives a negative value, counter 8 stops counting and outputs the count value.

[0117] For example, the processor may compare the count values ​​of each pair of predetermined pixels 1. In other embodiments, the comparison may be performed by the processor 10. In the comparison step, if the count value of the first pixel is less than or equal to the count value of the second pixel, the comparison result may be recorded as 1; if the count value of the first pixel is greater than the count value of the second pixel, the comparison result may be recorded as 0.

[0118] For example, the comparison results of thirty-two pairs of pixels 1 form a binary value string of a certain bit length, which can be recorded as B32. This value string is the physical unclonable function response of the multiple pixels 1 in the array.

[0119] The numerical string can be encrypted. For example, the temperature Temp of the pixel array is used as a random number seed, and a pseudo-random number generator 36 can be used to generate a thirty-two-bit pseudo-random number D. The pseudo-random number D is combined with the numerical string B. 32 Perform XOR calculation to obtain the encrypted value string R 32 By also recording the temperature value in the tag, it helps to decrypt and verify more reliably.

[0120] Referring to Figure 8, Figure 8 shows a verification device further provided in an embodiment of the present application. The verification device may be a server 400, and the verification device may include a verification memory 401 and a verification processor 406. Referring to Figure 9, the electronic device 200 provided in an embodiment of the present application may be communicatively connected to the server 400 via a communication network 300. In other embodiments, the verification device and the electronic device 200 may also utilize a non-volatile storage medium to transmit a labeled image. The verification device may be an electronic device 200 or a device implemented by a manufacturer of a circuit 100 for generating a labeled image, and the manufacturer may determine feature data of the circuit 100 for generating a labeled image and utilize these data to verify the image.

[0121] The verification device can be a server 400, which illustratively includes a verification processor 406, a verification memory 401, an input / output interface (I / O, not shown), and a second communication interface 405. The verification processor 406, the verification memory 401, and the input / output interface (I / O, not shown) are connected via a second system bus 404, and the second communication interface 405 can be connected to the system bus via the I / O interface. The verification processor 406 is used to provide computing and control capabilities. The verification memory 401 includes a second non-volatile storage medium 403 and a second internal memory 402. The second non-volatile storage medium 403 stores an operating system, computer programs, and a database. The second internal memory 402 provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the verification device is used to store data related to the electronic device 200 and / or the circuit 100 used to generate the labeled image. Exemplarily, the data can be stored using a data storage system 500. The I / O interface is used to exchange information between the verification processor 406 and external devices. The second communication interface 405 of the verification device can be used to communicate with external terminals via a network connection. When the computer program is executed by the verification processor 406 , the computer program implements the steps of the method for verifying the authenticity of image data.

[0122] Exemplarily, the verification device may include an analog pseudo-random number generator (not shown) having the same pseudo-random number generation rule as the pseudo-random number generator 36 .

[0123] Referring to Figure 10 , the verifier may possess a verification device, such as server 400, which can be provided by the electronic device 200 or the manufacturer of the circuit 100 used to generate the labeled image. During the circuit production process, multiple pixels 1 in the array can be measured to obtain relevant physical data. The parameters of the circuit 100 used to generate the labeled image can then be registered with a database. Furthermore, a verification device or apparatus can be obtained. Generally, this relevant physical data is kept confidential.

[0124] The verification applicant can provide a labeled image. The image data in the labeled image is the image to be verified, and the label therein can be called the verification label. For example, the label can include a source device identification code, which declares the source device or source circuit of the image to be verified.

[0125] The verifier can use a verification device or verification apparatus to calculate the verification label based on the data of the image to be verified and data such as temperature in the label to be verified.

[0126] The verifier compares the verification tag with the tag to be verified, for example, by comparing the physical unclonable function in each. Based on the resulting bit errors, the verifier can calculate the bit error rate. The verifier then compares the bit error rate with a passing threshold to obtain a verification result. The verifier then sends the verification result to the verification requester.

[0127] 11 , an embodiment of the present application provides a verification method for verifying whether a labeled image is generated by a claimed source. The verification method 2000 may include steps S210 to S230 .

[0128] Step S210: Confirm the circuit model corresponding to the circuit to be verified. The tag to be verified may include, for example, a device identification code. The tag to be verified claims which circuit 100 is used to generate the labeled image and from which the image data to be verified originates. The claimed circuit can be called the circuit to be verified. Then, the circuit model corresponding to the circuit to be verified can be determined.

[0129] Exemplarily, the data format of the image data to be verified can also be used to confirm the circuit model. For example, if the resolution is different, it can be considered that it is not generated by the claimed circuit to be verified, or the image data to be verified has been modified.

[0130] In step S220, a verification label may be generated by simulating light exposure. For example, the circuit model is simulated and light-exposed corresponding to the image data to be verified, and the verification label is generated based on the circuit model.

[0131] Step S230, in response to the bit error rate being less than or equal to the qualified threshold, it is determined to be true. The bit error rate can be obtained by dividing the number of bit errors by the number of bits of the numerical string in the verification tag. The number of bit errors can also be directly determined, and the qualified threshold actually used can be set according to the number of bits of the numerical string. For a certain number of bits in the numerical string, the effects of using the bit error rate and using the number of bit errors are equivalent, except that the setting of the qualified threshold is different. If the bit error rate or the number of bit errors between the verification tag and the tag to be verified is less than or equal to the qualified threshold, it is determined that the image data to be verified is generated by the circuit to be verified. If the bit error rate or the number of bit errors between the verification tag and the tag to be verified is greater than the qualified threshold, it is determined that the image data to be verified is not generated by the claimed circuit, i.e., the circuit to be verified.

[0132] Exemplarily, the verification method 2000 also includes the following steps. Using the pseudo-random number generator model in the circuit model, the numerical string to be verified is decrypted according to the temperature value in the label to be verified to obtain a decrypted numerical string. The image data is sequentially scaled, smoothed, grayscaled, and histogram-equalized to obtain a preprocessed image. The preprocessed image is divided into a preset number of blocks, and features are extracted from each block by discrete cosine transform to obtain a feature group. According to the feature group, the coordinates of a preset number of pixel models in the circuit model are mapped in the image data. The preset number of pixel models are sampled, and a verification comparison result is obtained based on each pair of predetermined pixel models. The step of forming a label includes: sorting the verification comparison results into a verification numerical string in a preset order.

[0133] The steps performed by verification method 2000 using the circuit model can be the same as those used when the circuit to be verified generates a labeled image. However, a tamperer cannot physically clone the circuit 100 for generating labeled images provided in the embodiments of this application. After tampering with the image data, the tamperer cannot determine how to disguise the label. The verifier can then execute verification method 2000 to verify whether the image data has been tampered with based on the label.

[0134] 12 , an embodiment of the present application provides a verification device 600, which includes: a matching module 610, configured to confirm a circuit model of a claimed circuit of a label to be verified based on the image data to be verified and the label to be verified; a simulation module 620, configured to perform simulated photosensitization corresponding to the image data to be verified on the circuit model, and generate a comparison label through the circuit model; and a verification module 630, configured to determine that the image data to be verified is generated by the claimed circuit in response to a bit error rate between the comparison label and the label to be verified being less than or equal to a qualified threshold.

[0135] The circuit model can be implemented in software. The simulation module 620 is at least partially implemented in software, for example, including a software-implemented photosensitive module to replicate the corresponding photosensitive state when the circuit model generates the image data to be verified. The remaining modules in the verification device 600 can be implemented in whole or in part in software, hardware, or a combination thereof. Each of the modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a computer device memory in software form, so that the processor can call and execute the corresponding operations of each module.

[0136] The authenticator can use the authentication device 600 to authenticate the image to be authenticated.

[0137] Referring to Figure 13, five different circuits 100 for generating labeled images are selected, and each circuit generates ten images to be labeled. Ten images are selected, and the source of the error is declared, and then these erroneously claimed images are verified. In addition, the ten images are modified to be harmless to obtain ten control images, and then these control images are also verified. 10 is used as the reference threshold. As shown in Figure 13, the control images of the harmless operation are basically qualified, and the number of errors is basically below 10; after verification, the number of errors of the images of the erroneous source is close to 30. It can be seen that the number of errors in the group of images with the declared source of the error is much higher than the number of errors in the images with the harmless operation, and there is enough range between the two to set the qualified threshold, for example, set to 15, 20, 25.

[0138] Referring to Figures 14 and 15, Figure 14 shows the original image, in which the rightmost number in the original image is "69". Figure 15 shows the tampered image, in which the rightmost number in the tampered image is tampered with to "89". Through verification, the number of bit errors between the verification label obtained based on the tampered image and the original label exceeds the qualified threshold. The number of bit errors between the verification label obtained based on the original image or the harmless processed image and the original label is less than or equal to the qualified threshold. The method for generating a labeled image provided in the embodiment of the present application can generate a reliable label, and the verification method provided in the embodiment of the present application can verify a tampered image.

[0139] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions.

[0140] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Any reference to memory, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in the various embodiments provided herein may be, but are not limited to, a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, and the like.

[0141] In the description of this application, reference to terms such as "some embodiments" or "other embodiments" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of this application. In this application, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0142] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A circuit for generating a labeled image, characterized in that include: A plurality of pixels of the array, the pixels comprising a photosensitive structure and a voltage reader, the photosensitive structure having a photoelectric sensing region and an equivalent capacitance region, the voltage reader being electrically connected to the equivalent capacitance region; A double correlation sampler, wherein a first input terminal of the double correlation sampler is electrically connected to the voltage reader, and a second input terminal of the double correlation sampler is used to access a threshold voltage; A counter, wherein a counting control terminal of the counter is electrically connected to an output terminal of the dual correlation sampler; as well as A processor is electrically connected to the counter, and the processor is used to form a label.

2. The circuit for generating a labeled image according to claim 1, wherein: Also comprising a temperature sensor, the temperature sensor is used to measure the temperature of the plurality of pixels, the temperature sensor is electrically connected to the processor; The processor is configured to: In response to a count value of a first pixel in a pair of pixels being greater than a count value of a second pixel, setting a comparison result to a first comparison value; in response to a count value of the first pixel in the pair of pixels being less than or equal to a count value of the second pixel, setting the comparison result to a second comparison value; and The label is formed according to the temperature and the comparison result.

3. The circuit for generating a labeled image according to claim 2, wherein: Also included is a pseudo-random number generator, the pseudo-random number generator is used to generate a pseudo-random number according to the temperature; The processor is configured to: Sampling a preset number of pixels, and obtaining a comparison result according to each pair of the predetermined pixels, wherein the first comparison value is 1 and the second comparison value is 0; sorting the comparison results into a numerical string according to a preset order; and An XOR calculation is performed on the numerical string and the pseudo-random number to obtain an encrypted numerical string.

4. The circuit for generating a labeled image according to claim 1, wherein: It also includes an amplifier, an analog-to-digital converter and a timing control logic. The amplifier is connected in parallel with the voltage reader. The analog-to-digital converter is electrically connected to the amplifier. The timing control logic is electrically connected to the amplifier, the voltage reader, the dual-correlation sampler and the counter. The voltage reader includes a triode.

5. A method for generating labeled images, characterized in that include: Responsive to light sensing of a plurality of pixels of the array, image data is obtained, wherein the pixels include a light sensing structure and a voltage reader, the light sensing structure has a photoelectric sensing region and an equivalent capacitance region, and the voltage reader is electrically connected to the equivalent capacitance region; Performing double correlation sampling on the equivalent capacitance region based on a threshold voltage; Counting according to the result of the double correlation sampling step; and A label is formed based on the count value of the counting step.

6. The method for generating a labeled image according to claim 5, wherein: Also included is: measuring the temperature of the plurality of pixels; The steps of forming the label include: Comparing the values ​​of the counting step, the comparing step comprising: in response to the count value of the first pixel in a pair of pixels being greater than the count value of the second pixel, setting the comparison result to a first comparison value; in response to the count value of the first pixel in the pair of pixels being less than or equal to the count value of the second pixel, setting the comparison result to a second comparison value; and The label is formed according to the temperature and the comparison result.

7. The method for generating a labeled image according to claim 6, wherein: Also includes: generating a pseudo-random number according to the temperature; and Sampling a preset number of pixels; The step of forming the label comprises: obtaining a comparison result according to each predetermined pair of pixels, wherein the first comparison value is 1 and the second comparison value is 0; sorting the comparison results into a numerical string according to a preset order; and An XOR calculation is performed on the numerical string and the pseudo-random number to obtain an encrypted numerical string.

8. The method for generating a labeled image according to claim 7, wherein: Also includes: Obtaining a preprocessed image according to the image data formed by the plurality of pixels; Dividing the preprocessed image into the preset number of blocks, performing feature extraction on each of the blocks to obtain a feature group; and According to the feature group, coordinates of the preset number of pixels are mapped and determined in the image data.

9. The method for generating a labeled image according to claim 5, wherein: The step of double correlation sampling comprises: Determine the sign of the output value of the double correlation sampling by subtracting the threshold voltage from the voltage provided by the equivalent capacitance region; When performing the double correlation sampling, starting the counting; and In response to the output value having a negative sign, counting is stopped and the count value is obtained.

10. An electronic device, characterized in that A circuit for generating a labeled image according to any one of claims 1 to 4 is included.

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