Pixel circuit and driving method therefor, and display device

Abstract

Provided are a pixel circuit and a driving method therefor, and a display device. The pixel circuit comprises a driving circuit, a first compensation circuit, a light-emitting element, a second light-emitting control circuit, and a reset control circuit. The first compensation circuit comprises a first storage capacitor. A control end of the reset control circuit is configured to receive a reset control signal; a first end of the reset control circuit is electrically connected to a first end of the driving circuit; a second end of the reset control circuit is electrically connected to a reset signal end to receive a reset signal; and a third end of the reset control circuit is electrically connected to a first electrode of the light-emitting element. The reset control circuit is configured to apply the reset signal to the first electrode of the light-emitting element and / or the first end of the driving circuit in response to the reset control signal. In the pixel circuit, the reset control circuit is arranged between the driving circuit and the reset signal end, so that the impact of the fluctuation of the reset signal on the voltage of the first end of the driving circuit can be reduced, thereby reducing the risk of introducing noise to the pixel circuit.

Description

Pixel circuit, driving method thereof and display device

[0001] This application claims priority to Patent Application No. PCT / CN2023 / 113514 filed on August 17, 2023, the disclosure of which is hereby incorporated by reference in its entirety into this application for all purposes. TECHNICAL FIELD

[0002] At least one embodiment of the present disclosure relates to a pixel circuit, a driving method thereof, and a display device. BACKGROUND

[0003] With the continuous development of display technology, organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost.

[0004] SUMMARY

[0005] At least one embodiment of the present disclosure provides a pixel circuit, a driving method thereof, and a display device.

[0006] At least one embodiment of the present disclosure provides a pixel circuit, which comprises a driving circuit, a first compensation circuit, a light emitting element, a second light emitting control circuit and a reset control circuit, the driving circuit comprises a control terminal, a first terminal and a second terminal, and is configured to control the size of a driving current flowing through the first terminal and the second terminal; the first compensation circuit is configured to apply a reference signal to the control terminal of the driving circuit in response to a first compensation control signal, the first compensation circuit comprises a first storage capacitor, a first pole of the first storage capacitor is electrically connected to the control terminal of the driving circuit, and a second pole of the first storage capacitor is electrically connected to the first terminal of the driving circuit; the light emitting element is configured to emit light under the driving of the driving current, a second electrode of the light emitting element is electrically connected to a second voltage terminal to receive a second power voltage; a control terminal of the second light emitting control circuit is configured to receive a second light emitting control signal, a first terminal of the second light emitting control circuit is electrically connected to the first terminal of the driving circuit, a second terminal of the second light emitting control circuit is electrically connected to a first electrode of the light emitting element, and the second light emitting control circuit is configured to apply the driving current to the light emitting element and allow the reset signal to be applied to the first terminal of the driving circuit in response to the second light emitting control signal; a control terminal of the reset control circuit is configured to receive a reset control signal, a first terminal of the reset control circuit is electrically connected to the first terminal of the driving circuit, a second terminal of the reset control circuit is electrically connected to a reset signal terminal to receive a reset signal, a third terminal of the reset control circuit is electrically connected to the first electrode of the light emitting element, and the reset control circuit is configured to apply the reset signal to the first electrode of the light emitting element and / or the first terminal of the driving circuit in response to the reset control signal.

[0007] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the reset control circuit comprises a second compensation circuit and a reset circuit, the second compensation circuit comprises a second storage capacitor, the second compensation circuit is electrically connected between the first terminal of the driving circuit and the reset signal terminal, a control terminal of the reset circuit serves as the control terminal of the reset control circuit and is configured to receive the reset control signal, a first terminal of the reset circuit serves as the third terminal of the reset control circuit and is electrically connected to the first electrode of the light emitting element, and a second terminal of the reset circuit serves as the second terminal of the reset control circuit and is electrically connected to the reset signal terminal to receive the reset signal.

[0008] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the value of the reset signal is adjustable.

[0009] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes at least a first reset signal and a second reset signal, the first reset signal corresponds to a first display temperature, the second reset signal corresponds to a second display temperature, the first display temperature is lower than the second display temperature, and a value of the first reset signal is less than a value of the second reset signal.

[0010] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes a reset signal adjustment period, the reset signal is adjusted to the second reset signal during the reset signal adjustment period, the pixel circuit corresponds to a plurality of display frame periods, the reset signal adjustment period is located between two adjacent display frame periods; or the reset signal adjustment period is located within one display frame period, and the display frame period includes at least a reset stage, a compensation stage, a data writing stage, and a light emitting stage, the reset signal adjustment period at least partially overlaps with any one of the reset stage, the compensation stage, the data writing stage, and the light emitting stage, or does not overlap.

[0011] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes a reference signal, and a value of the reference signal is adjustable.

[0012] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes a second storage capacitor, a first electrode of the second storage capacitor is electrically connected to a first end of the reset control circuit and a first end of the driving circuit, and a second electrode of the second storage capacitor is electrically connected to a first end of the reset circuit.

[0013] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes a first light emitting control circuit, a control end of the first light emitting control circuit is configured to receive a first light emitting control signal, a first end of the first light emitting control circuit is electrically connected to a second end of the driving circuit, and a second end of the first light emitting control circuit is electrically connected to a first voltage end to receive a first power voltage, the first light emitting control circuit is configured to apply the first power voltage to the second end of the driving circuit in response to the first light emitting control signal.

[0014] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes a first light emitting control circuit, a control end of the first light emitting control circuit is configured to receive a first light emitting control signal, a first end of the first light emitting control circuit is electrically connected to a second end of the driving circuit, and a second end of the first light emitting control circuit is electrically connected to a first voltage end to receive a first power voltage, the first light emitting control circuit is configured to apply the first power voltage to the second end of the driving circuit in response to the first light emitting control signal.

[0015] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the second end of the driving circuit is directly electrically connected with the first voltage end to receive the first power voltage.

[0016] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the reset circuit comprises a reset transistor, a gate of the reset transistor is electrically connected with a reset control end to receive the reset control signal, a first pole of the reset transistor is electrically connected with a second pole of the second storage capacitor and the first end of the driving circuit, and a second pole of the reset transistor is electrically connected with the reset signal end to receive the reset signal.

[0017] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the second light emitting control circuit comprises a second light emitting control transistor, a gate of the second light emitting control transistor is electrically connected with a second light emitting control end to receive the second light emitting control signal, a first pole of the second light emitting control transistor is electrically connected with the first end of the driving circuit, and a second pole of the second light emitting control transistor is electrically connected with the first electrode of the light emitting element.

[0018] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit further comprises an auxiliary compensation circuit, a control end of the auxiliary compensation circuit is configured to receive an auxiliary compensation signal, a first end of the auxiliary compensation circuit is electrically connected with the second pole of the second storage capacitor, and a second end of the auxiliary compensation circuit is electrically connected with the first electrode of the light emitting element.

[0019] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the first end of the auxiliary compensation circuit is further electrically connected with the second end of the second light emitting control circuit and the first end of the reset circuit.

[0020] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the auxiliary compensation circuit comprises an auxiliary compensation transistor, a gate of the auxiliary compensation transistor serves as the control end of the auxiliary compensation circuit to receive the auxiliary compensation control signal, a first pole of the auxiliary compensation transistor is electrically connected with the second pole of the second compensation capacitor and the second pole of the second light emitting control transistor, and a second pole of the auxiliary compensation transistor is electrically connected with the first electrode of the light emitting element.

[0021] For example, the pixel circuit provided by at least one embodiment of the present disclosure, the first end of the auxiliary compensation circuit is further electrically connected with the first end of the reset circuit, and the second end of the auxiliary compensation circuit is further electrically connected with the second end of the second light emitting control circuit.

[0022] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes an auxiliary compensation circuit, the auxiliary compensation circuit includes an auxiliary compensation transistor, a gate of the auxiliary compensation transistor is electrically connected with an auxiliary compensation control end to receive an auxiliary compensation control signal, a first pole of the auxiliary compensation transistor is electrically connected with a second pole of the second compensation capacitor and a first pole of the reset transistor, and a second pole of the auxiliary compensation transistor is electrically connected with a first electrode of the light-emitting element.

[0023] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes an auxiliary compensation transistor, a gate of the auxiliary compensation transistor is electrically connected with a gate of the second light-emitting control transistor, the auxiliary compensation transistor shares the gate with the second light-emitting control transistor, the second light-emitting control signal is used as the auxiliary compensation control signal, and the auxiliary compensation transistor is of the same type as the second light-emitting control transistor; or the gate of the auxiliary compensation transistor is independent of and not electrically connected with the gate of the second light-emitting control transistor.

[0024] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes an auxiliary compensation transistor, a gate of the auxiliary compensation transistor is electrically connected with a gate of the reset transistor, the auxiliary compensation transistor shares the gate with the reset transistor, the reset control signal is used as the auxiliary compensation control signal, and the auxiliary compensation transistor is of the same type as the reset transistor; or the gate of the auxiliary compensation transistor is independent of and not electrically connected with the gate of the reset transistor.

[0025] For example, the pixel circuit provided by at least one embodiment of the present disclosure includes a driving circuit, the driving circuit includes a driving transistor, a gate of the driving transistor is used as a control end of the driving circuit and is electrically connected with a first node, a first pole of the driving transistor is used as a first end of the driving circuit and is electrically connected with a first pole of the second storage capacitor at a second node, and a second pole of the driving transistor is used as a second end of the driving circuit and is electrically connected with a first voltage end to receive a first power voltage; the pixel circuit further includes a data writing circuit, a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected with a data signal end to receive a data signal, a second end of the data writing circuit is electrically connected with the first node, and the data writing circuit is configured to write the data signal to the control end of the driving circuit in response to the data scanning signal.

[0026] For example, the pixel circuit provided by at least one embodiment of the present disclosure is configured such that the control terminal of the first compensation circuit is configured to receive the first compensation control signal, the first terminal of the first compensation circuit is electrically connected to the reference signal terminal to receive the reference signal, and the second terminal of the first compensation circuit is electrically connected to the second node. The first compensation circuit further includes a first compensation transistor, the gate of the first compensation transistor is configured as the control terminal of the first compensation circuit and is electrically connected to the first compensation control signal terminal to receive the first compensation control signal, the first pole of the first compensation transistor is configured as the first terminal of the first compensation circuit and is electrically connected to the reference signal terminal to receive the reference signal, and the second pole of the first compensation transistor is electrically connected to the first node. The data write circuit includes a data write transistor, the gate of the data write transistor is electrically connected to the data scan signal terminal to receive the data scan signal, the first pole of the data write transistor is electrically connected to the data signal terminal to receive the data signal, and the second pole of the data write transistor is electrically connected to the first node.

[0027] For example, the pixel circuit provided by at least one embodiment of the present disclosure is configured such that the data write transistor and the first compensation transistor are respectively independently controlled transistors, the data scan signal terminal and the first compensation control signal terminal are respectively different signal terminals, and the data signal terminal and the reference signal terminal are respectively different signal terminals. Alternatively, the data write transistor is multiplexed as the first compensation transistor, the data scan signal is multiplexed as the first compensation control signal, the first pole of the data write transistor is further electrically connected to the reference signal terminal to receive the reference signal, the data signal terminal is multiplexed as the reference signal terminal, and is configured to provide the data signal or the reference signal in different time periods, respectively.

[0028] At least one embodiment of the present disclosure further provides a display device including the pixel circuit of any one of the above.

[0029] At least one embodiment of the present disclosure further provides a driving method of a pixel circuit, which is applicable to the pixel circuit of any one of the above. The driving method includes: configuring the reset control signal as an open signal to enable the reset signal to pass through the reset control circuit and be applied to the first electrode of the light emitting element and / or the first terminal of the driving circuit.

[0030] For example, according to the driving method of the pixel circuit provided by at least one embodiment of the present disclosure, the reset control circuit includes a second compensation circuit and a reset circuit, the second compensation circuit includes a second storage capacitor, a first pole of the second storage capacitor is electrically connected to a first end of the reset control circuit and a first end of the driving circuit, a second pole of the second storage capacitor is electrically connected to a first end of the reset circuit; a control end of the reset circuit is configured as a control end of the reset control circuit and configured to receive the reset control signal, a first end of the reset circuit is configured as a third end of the reset control circuit and electrically connected to a first electrode of the light emitting element, a second end of the reset circuit is configured as a second end of the reset control circuit and electrically connected to the reset signal end to receive the reset signal, the driving method includes a reset stage, a compensation stage, a data writing stage and a light emitting stage, in the reset stage, the reset control signal is an open signal in at least part of the time period to make the first end and the second end of the reset circuit conductive, the reset signal is sequentially applied to the second pole of the second storage capacitor, the first end of the driving circuit and the first electrode of the light emitting element through the second end and the first end of the reset circuit; in the compensation stage and the data writing stage, the reset control signal is an open signal, and the reset signal is sequentially applied to the second pole of the second storage capacitor and the first electrode of the light emitting element through the second end and the first end of the reset circuit; in the light emitting stage, the reset control signal is a closed signal in at least part of the time period to make the second pole of the second storage capacitor and the reset signal end disconnected.

[0031] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure further comprises a data writing circuit and a first light emitting control circuit; a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected with a data signal end to receive a data signal, and a second end of the data writing circuit is electrically connected with a control end of the driving circuit; a control end of the first light emitting control circuit is configured to receive a first light emitting control signal, a first end of the first light emitting control circuit is electrically connected with a second end of the driving circuit, and a second end of the first light emitting control circuit is electrically connected with a first voltage end so that the second end of the driving circuit receives a first power voltage from the first voltage end; in the light emitting stage, the driving method comprises sequentially performing the following steps S101-S104: step S101: making the data scanning signal a turn-off signal to turn off the data writing circuit; step S102: making the second light emitting control signal a turn-on signal to turn on the second light emitting control circuit, and making the first light emitting control signal remain a turn-off signal to turn off the first light emitting control circuit; and step S104: making the first light emitting control signal a turn-on signal to turn on the first light emitting control circuit, so that the second end of the driving circuit receives the first power voltage from the first voltage end via the first light emitting control circuit.

[0032] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure further comprises a data writing circuit and a first light emitting control circuit; a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected with a data signal end to receive a data signal, and a second end of the data writing circuit is electrically connected with a control end of the driving circuit; a control end of the first light emitting control circuit is configured to receive a first light emitting control signal, a first end of the first light emitting control circuit is electrically connected with a second end of the driving circuit, and a second end of the first light emitting control circuit is electrically connected with a first voltage end so that the second end of the driving circuit receives a first power voltage from the first voltage end; in the light emitting stage, the driving method comprises sequentially performing the following steps S101-S104: step S101: making the data scanning signal a turn-off signal to turn off the data writing circuit; step S102: making the second light emitting control signal a turn-on signal to turn on the second light emitting control circuit, and making the first light emitting control signal remain a turn-off signal to turn off the first light emitting control circuit; and step S104: making the first light emitting control signal a turn-on signal to turn on the first light emitting control circuit, so that the second end of the driving circuit receives the first power voltage from the first voltage end via the first light emitting control circuit.

[0033] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure includes the following steps S2010-S2020 in the compensation phase: S2010, making the second light-emitting control signal a turn-off signal to turn off the second light-emitting control circuit, and making the first light-emitting control signal remain a turn-off signal to turn off the first light-emitting control circuit; and S2020, making the first light-emitting control signal a turn-on signal to turn on the first light-emitting control circuit, and keeping the second light-emitting control signal a turn-off signal; and in the compensation phase, the data scanning signal remains a turn-off signal to keep the data writing circuit turned off, and the first compensation control signal remains a turn-on signal to keep the first compensation circuit turned on.

[0034] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure further includes a data writing circuit, a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected with a data signal end to receive a data signal, and a second end of the data writing circuit is electrically connected with the control end of the driving circuit, wherein the driving method includes the following steps S3010-S3030 in the data writing phase: S3010, making the first compensation control signal a turn-off signal to turn off the first compensation circuit, and keeping the second end of the driving circuit to receive a first power voltage; and S3030, making the data scanning signal a turn-on signal to turn on the data writing circuit, wherein in the data writing phase, the second light-emitting control signal remains a turn-off signal to keep the second light-emitting control circuit turned off.

[0035] For example, the driving method of the pixel circuit provided by at least one embodiment of the present disclosure further includes a first light-emitting control circuit, a control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first end of the first light-emitting control circuit is electrically connected with the second end of the driving circuit, and a second end of the first light-emitting control circuit is electrically connected with a first voltage end to make the second end of the driving circuit receive a first power voltage; and the step S3030 further includes: making the first light-emitting control signal a turn-on signal to turn on the first light-emitting control circuit, so that the second end of the driving circuit receives the first power voltage. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0037] FIG. 1 is a schematic block diagram of a pixel circuit according to at least one embodiment of the present disclosure.

[0038] FIG. 2 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 1.

[0039] FIG. 3 is a signal timing diagram of a driving method according to at least one embodiment of the present disclosure.

[0040] FIG. 4A is a schematic diagram of the pixel circuit in FIG. 2 in a third sub-reset stage.

[0041] FIG. 4B is a schematic diagram of the pixel circuit in FIG. 2 in a second sub- compensation stage.

[0042] FIG. 4C is a schematic diagram of the pixel circuit in FIG. 2 in a third sub-data write stage.

[0043] FIG. 4D is a schematic diagram of the pixel circuit in FIG. 2 in a fourth sub-emission stage.

[0044] FIG. 4E is a signal timing diagram of another driving method according to at least one embodiment of the present disclosure.

[0045] FIG. 5 is a schematic diagram of another pixel circuit according to an embodiment of the present disclosure.

[0046] FIG. 6 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 5.

[0047] FIG. 7A is a schematic diagram of the pixel circuit in FIG. 5 in a third sub-reset stage.

[0048] FIG. 7B is a schematic diagram of the pixel circuit in FIG. 5 in a second sub- compensation stage.

[0049] FIG. 7C is a schematic diagram of the pixel circuit in FIG. 5 in a third sub-data write stage.

[0050] FIG. 7D is a schematic diagram of the pixel circuit in FIG. 5 in a fourth sub-emission stage.

[0051] FIG. 8 is a schematic block diagram of another pixel circuit according to at least one embodiment of the present disclosure.

[0052] FIG. 9 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 8.

[0053] FIG. 10 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 9.

[0054] FIG. 11A is a schematic diagram of the pixel circuit shown in FIG. 9 in a third sub-reset stage.

[0055] FIG. 11B is a schematic diagram of the pixel circuit shown in FIG. 9 in a second sub- compensation stage.

[0056] FIG. 11C is a schematic diagram of the pixel circuit shown in FIG. 9 in a third sub-data write stage.

[0057] FIG. 11D is a schematic diagram of the pixel circuit shown in FIG. 9 in a fourth sub-emission stage.

[0058] FIG. 12 is a schematic diagram of yet another pixel circuit provided by embodiments of the present disclosure.

[0059] FIG. 13 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 12.

[0060] FIG. 14A is a schematic diagram of the pixel circuit in FIG. 12 in a second sub- compensation stage.

[0061] FIG. 14B is a schematic diagram of the pixel circuit in FIG. 12 in a third sub-data write stage.

[0062] FIG. 14C is a schematic diagram of the pixel circuit in FIG. 12 in a fourth sub- emission stage.

[0063] FIG. 15 is a schematic diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0064] FIG. 16 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 15.

[0065] FIG. 17 is a signal timing diagram of yet another driving method provided by at least one embodiment of the present disclosure.

[0066] FIG. 18A is a schematic diagram of the pixel circuit shown in FIG. 15 in a third sub- reset stage.

[0067] FIG. 18B is a schematic diagram of the pixel circuit shown in FIG. 15 in a second sub- compensation stage.

[0068] FIG. 18C is a schematic diagram of the pixel circuit shown in FIG. 15 in a third sub- data write stage.

[0069] FIG. 18D is a schematic diagram of the pixel circuit shown in FIG. 15 in a fourth sub- emission stage.

[0070] FIG. 19 is a schematic diagram of yet another pixel circuit provided by at least one embodiment of the present disclosure.

[0071] FIG. 20 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 19.

[0072] FIG. 21 is a signal timing diagram of yet another driving method provided by at least one embodiment of the present disclosure.

[0073] FIG. 22A is a schematic diagram of the pixel circuit in FIG. 20 in a third sub-reset stage.

[0074] FIG. 22B is a schematic diagram of the pixel circuit in FIG. 20 in a second sub- compensation stage.

[0075] FIG. 22C is a schematic diagram of the pixel circuit in FIG. 20 in a third sub- data write stage.

[0076] FIG. 22D is a schematic diagram of the pixel circuit in FIG. 20 in a fourth sub- light emitting stage.

[0077] FIG. 23 is a schematic block diagram of yet another pixel circuit provided in at least one embodiment of the present disclosure.

[0078] FIG. 24 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 23.

[0079] FIG. 25 is a signal timing diagram of yet another driving method provided in at least one embodiment of the present disclosure.

[0080] FIG. 26A is a schematic diagram of the pixel circuit in FIG. 24 in a third sub- reset stage.

[0081] FIG. 26B is a schematic diagram of the pixel circuit in FIG. 24 in a second sub- compensation stage.

[0082] FIG. 26C is a schematic diagram of the pixel circuit in FIG. 24 in a third sub- data write stage.

[0083] FIG. 26D is a schematic diagram of the pixel circuit in FIG. 24 in a fourth sub- light emitting stage.

[0084] FIG. 27 is a schematic diagram of a reset voltage varying with temperature in at least one embodiment of the present disclosure.

[0085] FIG. 28 is a schematic diagram of luminance of a light emitting element varying with gray scale in at least one embodiment of the present disclosure.

[0086] FIG. 29 is a schematic diagram of a reset voltage varying with temperature in at least one embodiment of the present disclosure.

[0087] FIG. 30 is a schematic diagram of a reference voltage varying with temperature in at least one embodiment of the present disclosure.

[0088] FIG. 31 is a structural schematic diagram of yet another pixel driving circuit provided in an embodiment of the present disclosure.

[0089] FIG. 32 is an equivalent circuit diagram one including the third control sub-circuit shown in FIG. 31.

[0090] FIG. 33 is an equivalent circuit diagram two including the third control sub-circuit shown in FIG. 31.

[0091] FIG. 34 is an equivalent circuit diagram three including the third control sub-circuit shown in FIG. 31.

[0092] Fig. 35 is an equivalent circuit diagram four of the pixel driving circuit including the third control sub-circuit shown in Fig. 31.

[0093] Fig. 36 is an equivalent circuit diagram five of the pixel driving circuit including the third control sub-circuit shown in Fig. 31.

[0094] Fig. 37 is an equivalent circuit diagram six of the pixel driving circuit including the third control sub-circuit shown in Fig. 31.

[0095] Fig. 38 is a partial equivalent circuit diagram of another pixel driving circuit provided by the embodiments of the present disclosure.

[0096] Fig. 39 is an equivalent circuit diagram one of the pixel driving circuit shown in Fig. 38.

[0097] Fig. 40 is an equivalent circuit diagram two of the pixel driving circuit shown in Fig. 38.

[0098] Fig. 41 is an equivalent circuit diagram three of the pixel driving circuit shown in Fig. 38.

[0099] Fig. 42 is an equivalent circuit diagram four of the pixel driving circuit shown in Fig. 38.

[0100] Fig. 43 is an equivalent circuit diagram five of the pixel driving circuit shown in Fig. 38.

[0101] Fig. 44 is an equivalent circuit diagram six of the pixel driving circuit shown in Fig. 38.

[0102] Fig. 45 is a working timing diagram of the pixel driving circuit provided by Figs. 39 and 40.

[0103] Fig. 46 is a working timing diagram of the pixel driving circuit provided by Fig. 41.

[0104] Fig. 47 is a working timing diagram of the pixel driving circuit provided by Fig. 42.

[0105] Fig. 48 is a working timing diagram of the pixel driving circuit provided by Figs. 43 and 44. DETAILED DESCRIPTION

[0106] So that the objectives, technical solutions and superiorities of the embodiments of the present disclosure are more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative effort belong to the scope of protection of the present disclosure.

[0107] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not imply any order, quantity, or importance, but are used to distinguish one element from another, and the terms "include" or "comprise" and the like are intended to mean the inclusion of the elements or objects listed after the terms and not to exclude other elements or objects.

[0108] The terms "vertical", "parallel", and "same" and the like used in the embodiments of the present disclosure include not only the strict "vertical", "parallel", "same" and the like, but also the "approximately vertical", "approximately parallel", "approximately same" and the like with a certain error, which, considering the measurement and the error related to the measurement of a specific amount (i.e., the limitation of the measurement system), indicates the acceptable deviation range for a specific value determined by those of ordinary skill in the art. The "center" in the embodiments of the present disclosure can include not only the position strictly at the geometric center, but also the position approximately at the center within a small area around the geometric center.

[0109] In some cases, a short-term residual image can occur when a display device displays an image, that is, when the display device displays the same image for a period of time, the original image can be partially left in the next image when the current display image is switched to the next image, and then the residual image can disappear after a period of time. The cause of the short-term residual image can be that the driving transistor in the pixel circuit has a hysteresis effect, which is mainly caused by the threshold voltage (Vth) shift caused by the movable ions remaining in the holes, and when the display device performs the image switching, the Vgs (voltage difference between the gate and the source of the driving transistor) of the initialization stage of the driving transistor can be different, so the threshold voltage shift of the driving transistor can occur.

[0110] For example, when the display device displays an initial image for a period of time, the initial image can still be partially left for several hours when the display device is switched to a new image, thereby affecting the display. Therefore, the problem of eliminating the threshold voltage (Vth) shift of the driving transistor needs to be solved.

[0111] The oxide pixel circuit is applied on the display device more and more, the refresh rate of the pixel circuit is high, and the process has high uniformity. In some pixel circuits, the first electrode of the driving transistor is directly connected with the reset signal end, so that the fluctuation of the reset signal will affect the stability of the voltage of the first electrode of the driving circuit. In some other pixel circuits, the first electrode of the driving transistor is electrically connected with the first light-emitting control transistor, the second electrode of the driving transistor is electrically connected with the light-emitting element through the second light-emitting control transistor, the first electrode of the storage capacitor is electrically connected with the first electrode of the driving transistor, and the second electrode of the storage capacitor is electrically connected with the constant signal end to receive a constant signal. For example, the constant signal can be a reset signal. When the above constant signal is unstable, the voltage of the second electrode of the storage capacitor is prone to fluctuate, thereby introducing external noise into the pixel circuit. For example, when the pixel circuit enters the light-emitting stage from the data writing stage, the reset signal needs to be switched from the on signal to the off signal, thereby easily increasing the risk of introducing noise into the pixel circuit, and further making the driving current unstable, affecting the display effect.

[0112] At least one embodiment of the present disclosure provides a pixel circuit and a driving method thereof, and a display device.

[0113] At least one embodiment of the present disclosure provides a pixel circuit, which comprises a driving circuit, a first compensation circuit, a light-emitting element, a second light-emitting control circuit, and a reset control circuit. The driving circuit comprises a control end, a first end, and a second end, and is configured to control the size of a driving current flowing through the first end and the second end. The first compensation circuit is configured to apply a reference signal to the control end of the driving circuit in response to a first compensation control signal. The first compensation circuit comprises a first storage capacitor, a first electrode of the first storage capacitor being electrically connected with the control end of the driving circuit, and a second electrode of the first storage capacitor being electrically connected with the first end of the driving circuit. The light-emitting element is configured to emit light under the driving of the driving current, a second electrode of the light-emitting element being electrically connected with a second voltage end to receive a second power voltage. A control end of the second light-emitting control circuit is configured to receive a second light-emitting control signal, a first end of the second light-emitting control circuit being electrically connected with the first end of the driving circuit, a second end of the second light-emitting control circuit being electrically connected with a first electrode of the light-emitting element, and the second light-emitting control circuit being configured to apply the driving current to the light-emitting element and allow the reset signal to be applied to the first end of the driving circuit in response to the second light-emitting control signal. A control end of the reset control circuit is configured to receive a reset control signal, a first end of the reset control circuit being electrically connected with the first end of the driving circuit, a second end of the reset control circuit being electrically connected with a reset signal end to receive a reset signal, a third end of the reset control circuit being electrically connected with the first electrode of the light-emitting element, and the reset control circuit being configured to apply the reset signal to the first electrode of the light-emitting element and / or the first end of the driving circuit in response to the reset control signal.

[0114] At least one embodiment of the present disclosure provides a pixel circuit provided with a reset control circuit, a first end of the reset control circuit is electrically connected with a first end of a driving circuit, and a second end of the reset control circuit is electrically connected with a reset signal end. In this way, the reset signal needs to pass through the reset control circuit before being applied to the first electrode of the light emitting element and / or the first end of the driving circuit, thereby reducing the influence of the fluctuation of the reset signal on the voltage of the first electrode of the light emitting element and the first end of the driving circuit, reducing the risk of introducing noise to the pixel circuit, and thereby making the driving current more stable to improve the display effect.

[0115] The pixel circuit and the driving method thereof and the display device provided by the embodiments of the present disclosure will be described below in combination with the accompanying drawings.

[0116] FIG. 1 is a schematic block diagram of a pixel circuit according to at least one embodiment of the present disclosure.

[0117] As shown in FIG. 1, the pixel circuit 10 includes a driving circuit 100, a first compensation circuit 300, a second light emitting control circuit 500, a light emitting element 600, and a reset control circuit 780.

[0118] As shown in FIG. 1, the driving circuit 100 includes a control end 100m, a first end 100a, and a second end 100b. The control end 100m of the driving circuit 100 is electrically connected with a first node N1, the first end 100a of the driving circuit 100 is electrically connected with a second node N2, and the second end 100b of the driving circuit 100 is electrically connected with a third node N3. The driving circuit 100 is configured to control the size of the driving current flowing through the first end 100a and the second end 100b, for example, which can be used to drive the light emitting element 600 to emit light. For example, in the light emitting stage, the driving circuit 100 can provide a driving current to the light emitting element 600 to drive the light emitting element 600 to emit light.

[0119] As shown in FIG. 1, the first compensation circuit 300 includes a control terminal 300m, a first terminal 300a, a second terminal 300b, and a third terminal 300c. The control terminal 300m of the first compensation circuit 300 is configured to receive a first compensation control signal G2, the first terminal 300a of the first compensation circuit 300 is electrically connected with the reference signal terminal REF to receive a reference signal REF, the second terminal 300b of the first compensation circuit 300 is electrically connected with the second node N2, and the third terminal 300c of the first compensation circuit 300 is electrically connected with the first node N1. The first compensation circuit 300 is configured to apply the reference signal REF to the control terminal 100m of the driving circuit 100 in response to the first compensation control signal G2. For example, the first compensation circuit 300 can include a first storage capacitor C1 (see FIG. 2), a first pole of the first storage capacitor C1 is electrically connected with the control terminal 100m of the driving circuit 100, and a second pole of the first storage capacitor C1 is electrically connected with the first terminal 100a of the driving circuit 100, but embodiments of the present disclosure are not limited thereto.

[0120] For example, as shown in FIG. 1, the second light-emitting control circuit 500 includes a control terminal 500m, a first terminal 500a, and a second terminal 500b. The control terminal 500m of the second light-emitting control circuit 500 is configured to receive a second light-emitting control signal EM2, the first terminal 500a of the second light-emitting control circuit 500 is electrically connected with the first terminal 100a of the driving circuit 100, and the second terminal 500b of the second light-emitting control circuit 500 is electrically connected with the first electrode 600a of the light-emitting element 600. The second light-emitting control circuit 500 is configured to apply a driving current to the light-emitting element 600 and allow the reset signal VINI to be applied to the first terminal 100a of the driving circuit 100 in response to the second light-emitting control signal EM2. For example, in the light-emitting stage, the second light-emitting control circuit 500 is turned on in response to the second light-emitting control signal EM2, so that the driving circuit 100 can apply a driving current to the light-emitting element 600 through the second light-emitting control circuit 500 to make it emit light.

[0121] For example, as shown in FIG. 1, the light emitting element 600 includes a first electrode 600a and a second electrode 600b, the first electrode 600a of the light emitting element 600 is electrically connected to the first end 100a of the driving circuit 100, the second electrode 600b of the light emitting element 600 is electrically connected to the second voltage end VSS to receive the second power voltage VSS, and the light emitting element 600 is configured to emit light under the driving of the driving current. For example, the second voltage end VSS can be grounded, i.e., the second power voltage VSS can be 0V. For example, the second power voltage VSS can be a negative voltage. For example, the light emitting element 600 can be an organic light emitting diode (OLED). In the embodiments described below, the light emitting element 600 is taken as an example of an OLED, and the light emitting element 600 can also be other types of electroluminescent devices such as inorganic light emitting diodes, quantum dot light emitting elements, etc., and the embodiments of the present disclosure do not limit the type of light emitting element.

[0122] As shown in FIG. 1, the reset control circuit 780 includes a control end 780m, a first end 780a, a second end 780b, and a third end 780c. The control end 780m of the reset control circuit 780 is configured to receive a reset control signal G3, the first end 780a of the reset control circuit 780 is electrically connected to the first end 100a of the driving circuit 100, the second end 780b of the reset control circuit 780 is electrically connected to the reset signal end VINI to receive the reset signal VINI, the third end 780c of the reset control circuit 780 is electrically connected to the first electrode 600a of the light emitting element 600, and the reset control circuit 780 is configured to apply the reset signal VINI to the first electrode 600a of the light emitting element 600 and / or the first end 100a of the driving circuit 100 in response to the reset control signal G3. For example, in the reset phase, the second light emitting control circuit 500 can be turned on in response to the second light emitting control signal EM2, so as to allow the reset signal VINI to be applied to the first end 100a of the driving circuit 100 in combination with other circuit elements (for example, the reset circuit 700 described in the embodiments below), so as to realize the reset operation and other operations of the driving circuit 100 and the light emitting element 600. For example, in the compensation phase and the data writing phase, the second light emitting control circuit 500 is turned off in response to the second light emitting control signal EM2, the reset signal VINI is applied to the first electrode of the light emitting element 600, and the light emitting element 600 can be prevented from emitting light in this phase to meet the display requirements of the display device. For example, the reset signal VINI can be a reset voltage VINI.

[0123] As shown in FIG. 1, a first end 780a of the reset control circuit 780 is electrically connected to the first end 100a of the driving circuit 100, and a second end 780b of the reset control circuit 780 is electrically connected to the reset signal terminal VINI. Thus, the reset signal from the reset signal terminal VINI needs to pass through the reset control circuit 780 before being applied to the first electrode 600a of the light emitting element 600 and / or the first end of the driving circuit 100. In this way, the influence of the fluctuation of the reset signal on the voltage of the first electrode 600a of the light emitting element 600 and the first end 100a of the driving circuit 100 can be reduced, and the risk of introducing noise to the pixel circuit 10 can be reduced. In this way, the driving current can be more stable, and the display effect can be improved.

[0124] For example, as shown in FIG. 1, the reset control circuit 780 includes the reset circuit 700 and the second compensation circuit 800, and the reset signal VINI is applied to the first electrode 600a of the light emitting element 600 and / or the first end 100a of the driving circuit 100 through the reset circuit 700 and the second compensation circuit 800. For example, in some embodiments of the present disclosure, the reset control circuit 780 can further include other sub-circuits, and the embodiments of the present disclosure do not limit the specific structure of the reset control circuit 780.

[0125] For example, as shown in FIG. 1, the second compensation circuit 800 includes a first end 800a and a second end 800b, and the second compensation circuit 800 includes a second storage capacitor C2, which is electrically connected between the first end 100a of the driving circuit 100 and the reset signal terminal VINI. For example, the reset circuit 700 includes a control end 700m, a first end 100a, and a second end 700b. The control end 700m of the reset circuit 700 serves as the control end 780m of the reset control circuit 780 and is configured to receive a reset control signal G3. The first end 100a of the reset circuit 700 serves as the third end 780c of the reset control circuit 780 and is electrically connected to the first electrode 600a of the light emitting element 600. The second end 700b of the reset circuit 700 serves as the second end 780b of the reset control circuit 780 and is electrically connected to the reset signal terminal VINI to receive the reset signal VINI. For example, in combination with FIGS. 1 and 2, the first pole of the second storage capacitor C2 serves as the first end 780a of the reset control circuit 780 and is electrically connected to the first end 100a of the driving circuit 100. The second pole of the second storage capacitor C2 is electrically connected to the first end 700a of the reset circuit 700. Thus, in this scheme, the second pole of the second storage capacitor C2 is indirectly electrically connected to the reset signal terminal VINI through the reset circuit 700.

[0126] Since the second pole of the second storage capacitor C2 is connected with the first end 700a of the reset circuit 700 instead of the second end 700b of the reset circuit 700, the reset signal VINI needs to pass through the second end 700b and the first end 700a of the reset circuit 700 in sequence before being applied to the second pole of the second storage capacitor C2 and the first electrode 600a of the light emitting element 600, thereby being able to reduce the risk of introducing noise to the pixel circuit 101 due to the fluctuation of the reset signal VINI.

[0127] Of course, in another embodiment of the present disclosure, the second pole of the second storage capacitor C2 can also be directly electrically connected with the reset signal end VINI, so that the form of structural design of the pixel circuit is more flexible, and the embodiment of the present disclosure does not limit this.

[0128] For example, as shown in FIG. 1, the pixel circuit 10 further includes a data writing circuit 200 and a first light emitting control circuit 400.

[0129] For example, as shown in FIG. 1, the data writing circuit 200 includes a control end 200m, a first end 200a and a second end 200b. The control end 200m of the data writing circuit 200 is configured to receive a data scanning signal G1, the first end 200a of the data writing circuit 200 is electrically connected with the data signal end DATA to receive a data signal DATA, and the second end 200b of the data writing circuit 200 is electrically connected with the first node N1. The data writing circuit 200 is configured to write the data signal DATA to the control end 100m of the driving circuit 100 in response to the data scanning signal G1. For example, in the data writing stage, the data writing circuit 200 is turned on in response to the data scanning signal G1, so that the data signal DATA can be written to the control end 100m of the driving circuit 100 through the data writing circuit 200.

[0130] As shown in FIG. 1, the first light-emitting control circuit 400 includes a control terminal 400m, a first terminal 400a, and a second terminal 400b. The control terminal 400m of the first light-emitting control circuit 400 is configured to receive the first light-emitting control signal EM1, the first terminal 400a of the first light-emitting control circuit 400 is electrically connected with the second terminal 100b of the driving circuit 100, and the second terminal 400b of the first light-emitting control circuit 400 is electrically connected with the first voltage terminal ELVDD to receive the first power voltage ELVDD. The first light-emitting control circuit 400 is configured to apply the first power voltage ELVDD to the second terminal 100b of the driving circuit 100 in response to the first light-emitting control signal EM1. For example, in the compensation phase, the first light-emitting control circuit 400 can be turned on in response to the first light-emitting control signal EM1, so that the first power voltage ELVDD can be applied to the second terminal 100b of the driving circuit 100 through the first light-emitting control circuit 400. The second electrode 600b of the light-emitting element 600 receives the second power voltage VSS. For example, the first power voltage ELVDD can be a high voltage, and the second power voltage VSS can be a low voltage, but embodiments of the present disclosure are not limited thereto.

[0131] FIG. 2 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 1; and FIG. 3 is a signal timing diagram of a driving method provided by at least one embodiment of the present disclosure.

[0132] For example, the pixel circuit shown in FIG. 1 can be implemented as the pixel circuit structure shown in FIG. 2. As shown in FIG. 2, the pixel circuit 101 includes a driving transistor DT, a data writing transistor T1, a first light-emitting control transistor T2, a first compensation transistor T3, a second light-emitting control transistor T4, a reset transistor T5, a first storage capacitor C1, a second storage capacitor C2, and a light-emitting element OLED. For example, the data writing transistor T1, the first light-emitting control transistor T2, the first compensation transistor T3, the second light-emitting control transistor T4, and the reset transistor T5 are used as switching transistors. For example, the light-emitting element is an OLED, which can be of various types, such as top emission, bottom emission, etc., and can emit red light, green light, blue light, or white light, etc., and embodiments of the present disclosure do not limit thereto.

[0133] As shown in FIG. 1 and FIG. 2, the driving circuit 100 includes a driving transistor DT, the gate of the driving transistor DT serving as the control terminal 100m of the driving circuit 100 and being electrically connected with the first node N1. The first pole of the driving transistor DT serving as the first terminal 100a of the driving circuit 100 and being electrically connected with the first pole of the second storage capacitor C2 at the second node N2. The second pole of the driving transistor DT serving as the second terminal 100b of the driving circuit 100 and being electrically connected with the first voltage terminal ELVDD to receive the first power voltage ELVDD.

[0134] As shown in FIG. 1 and FIG. 2, the first compensation circuit 300 includes a first compensation transistor T3 and a first storage capacitor C1. The gate of the first compensation transistor T3 serves as a control terminal 300m of the first compensation circuit 300 and is electrically connected with a first compensation control signal terminal G2 to receive a first compensation control signal G2. The first pole of the first compensation transistor T3 serves as a first terminal 300a of the first compensation circuit 300 and is electrically connected with a reference signal terminal REF to receive a reference signal REF; the second pole of the first compensation transistor T3 is electrically connected with the first node N1. The first pole of the first storage capacitor C1 is electrically connected with the gate of the driving transistor DT, and the second pole of the first storage capacitor C1 is electrically connected with the first pole of the driving transistor DT.

[0135] For example, as shown in FIG. 1 and FIG. 2, the second light-emitting control circuit 500 includes a second light-emitting control transistor T4, and the gate of the second light-emitting control transistor T4 is electrically connected with a second light-emitting control terminal EM2 to receive a second light-emitting control signal EM2. The first pole of the second light-emitting control transistor T4 is electrically connected with the first terminal 100a of the driving circuit 100. The second pole of the second light-emitting control transistor T4 is electrically connected with the first electrode 600a of the light-emitting element 600.

[0136] As shown in FIG. 1 and FIG. 2, the reset circuit 700 includes a reset transistor T5, and the gate of the reset transistor T5 is electrically connected with a reset control terminal G3 to receive a reset control signal G3. The first pole of the reset transistor T5 is electrically connected with the second pole of the second storage capacitor C2 and the first terminal 100a of the driving circuit 100, and the second pole of the reset transistor T5 is electrically connected with a reset signal terminal VINI to receive a reset signal VINI.

[0137] As shown in FIG. 1 and FIG. 2, in the pixel circuit provided by at least one embodiment of the present disclosure, the first pole of the reset transistor T5 is indirectly electrically connected with the first terminal 100a of the driving circuit 100, that is, the first pole of the reset transistor T5 is electrically connected with the first terminal 100a of the driving circuit 100 through the second light-emitting control transistor T4.

[0138] As shown in FIG. 1 and FIG. 2, the reset signal from the reset signal terminal VINI needs to pass through the first pole and the second pole of the reset transistor T5 before being applied to the first electrode of the light-emitting element OLED and / or the first terminal of the driving circuit 100, so as to reduce the influence of the fluctuation of the reset signal on the voltage of the first electrode of the light-emitting element OLED and the first terminal 100a of the driving circuit 100, and reduce the risk of introducing noise to the pixel circuit 10, thereby making the driving current more stable to improve the display effect.

[0139] For example, as shown in FIGS. 1 and 2, the second compensation circuit 800 includes a second storage capacitor C2, a first pole of the second storage capacitor C2 serving as a first end 800a of the second compensation circuit 800 and electrically connected with the first end 100a of the driving circuit 100 (i.e., a first pole of the driving transistor DT). A second pole of the second storage capacitor C2 serves as a second end 800b of the second compensation circuit 800 and electrically connected with the first end 700a of the reset circuit 700 (i.e., a first pole of the reset transistor T5).

[0140] In the technical solution of this embodiment, since the second pole of the second storage capacitor C2 is electrically connected with the first pole of the reset transistor T5 instead of the second pole of the reset transistor T5, the reset signal VINI is applied to the second pole of the second storage capacitor C2 and the first electrode 600a of the light emitting element 600 through the second pole and the first pole of the reset transistor T5 in sequence, thereby being able to reduce the risk of introducing noise to the pixel circuit 101 due to the fluctuation of the reset signal VINI.

[0141] For example, as shown in FIGS. 1 and 2, the data writing circuit 200 includes a data writing transistor T1, a gate of the data writing transistor T1 electrically connected with the data scanning signal end G1 to receive the data scanning signal G1, a first pole of the data writing transistor T1 electrically connected with the data signal end DATA to receive the data signal DATA, and a second pole of the data writing transistor T1 electrically connected with the first node N1.

[0142] For example, as shown in FIGS. 1 and 2, the first light emitting control circuit 400 includes a first light emitting control transistor T2, a gate of the first light emitting control transistor T2 electrically connected with the first light emitting control end EM1 to receive the first light emitting control signal EM1. A first pole of the first light emitting control transistor T2 is electrically connected with the second end 100b of the driving circuit 100. A second pole of the first light emitting control transistor T2 is electrically connected with the first voltage end ELVDD to receive the first power voltage ELVDD.

[0143] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2 and the third node N3 do not necessarily represent actual components, but represent the convergence points of circuit connection in the circuit diagram. In the description of the embodiments of the present disclosure, the symbol DATA can represent both a data signal terminal and a data signal; similarly, the symbol G1 can represent both a data scanning signal terminal and a data scanning signal; the symbol REF can represent both a reference signal terminal and a reference signal; the symbol G2 can represent both a first compensation control signal terminal and a first compensation control signal; the symbol EM1 can represent both a first light-emitting control terminal and a first light-emitting control signal; the symbol ELVDD can represent both a first voltage terminal and a first power voltage; the symbol EM2 can represent both a second light-emitting control terminal and a second light-emitting control signal; the symbol G3 can represent both a reset control terminal and a reset control signal; the symbol VINI can represent both a reset signal terminal and a reset signal, and can also represent a reset voltage; the symbol VSS can represent both a second voltage terminal and a second power voltage, and the same applies to the following embodiments, which will not be described again.

[0144] It should be noted that the transistors used in the embodiments of the present disclosure can be thin film transistors, field effect transistors or other switching devices with the same characteristics, and the embodiments of the present disclosure are described by taking thin film transistors as an example. The source and drain of the transistor used here can be symmetrical in structure, so that the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other is the second pole.

[0145] In addition, the transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). However, the type of transistor is not limited in the embodiments of the present disclosure, and the connection relationship in the circuit can be adjusted accordingly when the type of transistor changes.

[0146] The working principle of the pixel circuit 101 shown in FIG. 2 will be described below in combination with the signal timing diagram shown in FIG. 3. As shown in FIG. 3, the display process of each frame of image includes four stages, which are a reset stage 1, a compensation stage 2, a data writing stage 3 and a light-emitting stage 4.

[0147] For example, in the pixel circuit 101 shown in FIG. 2, the driving transistor DT, the data writing transistor T1, the first light emitting control transistor T2, the first compensation transistor T3, the second light emitting control transistor T4, and the reset transistor T5 are all N-type transistors, i.e., each transistor is turned on when a high-level signal is applied to the gate, and is turned off when a low-level signal is applied to the gate. Of course, in other embodiments, the above-mentioned transistors can also be P-type transistors, and the type of each transistor is not limited in the embodiments of the present disclosure and can be selected as needed. Here, the N-type transistors are taken as an example.

[0148] As shown in FIGS. 1-3, the embodiments of the present disclosure provide a driving method, which includes: making the reset control signal G3 an open signal, so that the reset signal VINI is sequentially applied to the first electrode 600a of the light emitting element 600 and / or the first end 100a of the driving circuit 100 through the reset control circuit 780.

[0149] For example, as shown in FIGS. 1-3, the first end 100a of the driving circuit 100 is not directly connected to the reset signal end VINI, i.e., the two are electrically connected through the reset control circuit 780. For example, when the reset control signal G3 is a closed signal, the first end 100a of the driving circuit 100 is disconnected from the reset signal end VINI.

[0150] In this way, the reset signal from the reset signal end needs to pass through the reset control circuit before being applied to the first electrode of the light emitting element and / or the first end of the driving circuit, so that the influence of the fluctuation of the reset signal on the voltage of the first electrode of the light emitting element and the first end of the driving circuit can be reduced, the risk of introducing noise to the pixel circuit can be reduced, and the driving current can be made more stable, so as to improve the display effect.

[0151] For example, as shown in FIGS. 1-3, in the reset stage 1, the driving method of the pixel circuit includes: making the reset control signal G3 an open signal in at least part of the period to turn on the first end 700a and the second end 700b of the reset circuit 700, and making the reset signal VINI sequentially pass through the second end 700b and the first end 700a of the reset circuit 700 to be applied to the second electrode of the second storage capacitor C2, the first end 100a of the driving circuit 100, and the first electrode 600a of the light emitting element 600, so as to realize the reset operation. For example, the above-mentioned at least part of the period can be the entire period of the reset stage 1, or can be a part of the period of the reset stage 1, and the embodiments of the present disclosure are not limited in this regard.

[0152] Correspondingly, as shown in FIGS. 1-3, in the reset stage 1, the reset control signal G3 is a high-level signal in at least a part of the period, to turn on the reset transistor T5, so that the reset signal VINI can be applied to the second electrode of the second storage capacitor C2 and the first electrode 600a of the light emitting element 600. In this stage, the second light emitting control signal EM2 is a high-level signal, to turn on the second light emitting control transistor T4, and then the reset signal VINI is applied to the first end 100a of the driving circuit 100 through the second light emitting control transistor T4.

[0153] For example, as shown in FIGS. 1-3, in the compensation stage 2 and the data writing stage 3, the driving method of the pixel circuit includes: making the reset control signal G3 an on signal, and the reset signal VINI is applied to the second electrode of the second storage capacitor C2 and the first electrode 600a of the light emitting element 600 in sequence through the second end 700b and the first end 700a of the reset circuit 700.

[0154] Correspondingly, as shown in FIGS. 1-3, in the compensation stage 2 and the data writing stage 3, the reset control signal G3 is a high-level signal in at least a part of the period, to turn on the reset transistor 5. For example, the second light emitting control signal EM2 is a low-level signal, to turn off the second light emitting control transistor T4. Therefore, the voltage of the second electrode of the second storage capacitor C2 and the first electrode 600a of the light emitting element 600 can be kept as the reset voltage VINI.

[0155] For example, as shown in FIGS. 1-3, in the light emitting stage 4, the driving method of the pixel circuit includes: making the reset control signal G3 a turn-off signal in at least a part of the period, to disconnect the second electrode of the second storage capacitor C2 from the reset signal end VINI. For example, the at least a part of the period can be the entire period of the light emitting stage 4, or a part of the period of the light emitting stage 4, and the embodiments of the present disclosure are not limited thereto.

[0156] Correspondingly, as shown in FIGS. 1-3, in the light emitting stage 4, the reset control signal G3 is a low-level signal in at least a part of the period, to turn off the reset transistor 5, so that the second electrode of the second storage capacitor C2 and the first electrode of the light emitting element OLED are both disconnected from the reset signal end VINI, to facilitate keeping the voltage of the first electrode of the light emitting element OLED as the voltage when the light emitting element OLED is in the light emitting state.

[0157] In this way, as shown in FIGS. 1-3, when the reset control signal G3 is an on signal, the reset signal VINI enters the inside of the pixel circuit 101 through the reset control circuit 780, for example, being applied to the first electrode 600a of the light emitting element 600 and the second electrode of the second storage capacitor C2. When the reset control signal G3 is an off signal, the reset signal VINI is disconnected from the first electrode 600a of the light emitting element 600, the second electrode of the second storage capacitor C2, and the first end 100a of the drive circuit 100. While meeting the working needs of each stage, the influence of the fluctuation of the reset signal VINI on the voltage of the first end 100a of the drive circuit 100 can be reduced, the risk of introducing noise to the pixel circuit 101 is reduced, and thus the drive current can be made more stable, so as to improve the display effect.

[0158] For example, as shown in FIG. 3, the reset stage 1 includes a first sub-reset stage P1, a second sub-reset stage P2, and a third sub-reset stage P3 performed in sequence. For example, the compensation stage 2 includes a first sub-compensation stage P4 and a second sub-compensation stage P5 performed in sequence. For example, the data writing stage 3 includes a first sub-data writing stage P6, a second sub-data writing stage P7, and a third sub-data writing stage P8 performed in sequence. For example, the light emitting stage 4 includes a first sub-light emitting stage P9, a second sub-light emitting stage P10, a third sub-light emitting stage P11, and a fourth sub-light emitting stage P12 performed in sequence.

[0159] FIG. 4A is a schematic diagram of the pixel circuit in FIG. 2 in the third sub-reset stage, FIG. 4B is a schematic diagram of the pixel circuit in FIG. 2 in the second sub-compensation stage, FIG. 4C is a schematic diagram of the pixel circuit in FIG. 2 in the third sub-data writing stage, and FIG. 4D is a schematic diagram of the pixel circuit in FIG. 2 in the fourth sub-light emitting stage. In addition, the transistors identified by dashed lines in FIGS. 4A-4D are in an off state in the corresponding stage.

[0160] Specifically, for example, as shown in FIGS. 1 and 3, in the reset stage 1, the driving method of the pixel circuit includes:

[0161] Step S1010: disconnecting the second end 100b of the drive circuit 100 from the first voltage end ELVDD;

[0162] Step S1020: making the reset control signal G3 an on signal to turn on the reset circuit 700; and

[0163] Step S1030: making the first compensation control signal G2 an on signal to turn on the first compensation circuit 300.

[0164] In the reset stage, the data scanning signal G1 remains as a turn-off signal to turn off the data write-in circuit 200, and the second light emitting control signal EM2 remains as a turn-on signal to turn on the second light emitting control circuit 500.

[0165] For example, as shown in FIG. 1 and FIG. 3, in the first sub-reset stage P1, the data scanning signal G1 remains as a turn-off signal to turn off the data write-in circuit 200; the second light emitting control signal EM2 remains as a turn-on signal to turn on the second light emitting control circuit 500; the first compensation control signal G2 and the reset control signal G3 both remain as turn-off signals, so that the first compensation circuit 300 and the reset circuit 700 are both in a turn-off state; in addition, corresponding to step S1010, the first light emitting control signal EM1 is switched to a turn-off signal to turn off the first light emitting control circuit 400, so that the second end 100b of the driving circuit 100 is disconnected from the first voltage end ELVDD.

[0166] For example, as shown in FIG. 1 and FIG. 3, in the second sub-reset stage P2, the data scanning signal G1 remains as a turn-off signal to turn off the data write-in circuit 200; the second light emitting control signal EM2 remains as a turn-on signal to turn on the second light emitting control circuit 500; the first light emitting control signal EM1 remains as a turn-off signal to turn off the first light emitting control circuit 400; the first compensation control signal G2 remains as a turn-off signal to make the first compensation circuit 300 in a turn-off state; in addition, corresponding to step S1020, the reset control signal G3 is switched to a turn-on signal to turn on the reset circuit 700, so that the reset signal VINI can be applied to the second pole of the second storage capacitor C2, the first electrode 600a of the light emitting element 600 and the first end 100a of the driving circuit 100.

[0167] For example, as shown in FIG. 1 and FIG. 3, in the third sub-reset stage P3, the data scanning signal G1 remains as a turn-off signal to turn off the data write-in circuit 200; the second light emitting control signal EM2 remains as a turn-on signal to turn on the second light emitting control circuit 500; the first light emitting control signal EM1 remains as a turn-off signal to turn off the first light emitting control circuit 400; the reset control signal G3 remains as a turn-on signal to turn on the reset circuit 700; in addition, corresponding to step S1030, the first compensation control signal G2 is switched to a turn-on signal to turn on the first compensation circuit 300, so that the reference signal REF can be applied to the control end 100m of the driving circuit 100.

[0168] For example, as shown in FIG. 1 and FIG. 3, by making the reset circuit 700 conductive in the case that the first light emitting control circuit 400 is turned off, that is, in the case that the first light emitting control circuit 400 is turned off in the first sub-reset stage P1, the reset circuit 700 is further made conductive in the second sub-reset stage P2, so that the first light emitting control circuit 400 can be prevented from being conductive with the reset circuit 700 through the driving circuit 100 and the second light emitting control circuit 500, so that the driving current can be more stable, which is conducive to the safety of the device.

[0169] Correspondingly, as shown in FIG. 2 and FIG. 3, in the first sub-reset stage P1, the data scanning signal G1 remains a low-level signal to turn off the data writing transistor T1; the second light emitting control signal EM2 remains a high-level signal to turn on the second light emitting control transistor T4; the first compensation control signal G2 and the reset control signal G3 both remain low-level signals to make the first compensation transistor T3 and the reset transistor T5 both in the on state; in addition, corresponding to step S1010, the first light emitting control signal EM1 is switched to a low-level signal to turn off the first light emitting control transistor T2, so that the second electrode of the driving transistor DT is disconnected with the first voltage terminal ELVDD.

[0170] Correspondingly, as shown in FIG. 2 and FIG. 3, in the second sub-reset stage P2, the data scanning signal G1 remains a low-level signal to turn off the data writing transistor T1; the second light emitting control signal EM2 remains a high-level signal to turn on the second light emitting control transistor T4; the first light emitting control signal EM1 remains a low-level signal to turn off the first light emitting control transistor T2; the first compensation control signal G2 remains a low-level signal to make the first compensation transistor T3 in the off state; in addition, corresponding to step S1020, the reset control signal G3 is switched to a high-level signal to turn on the reset transistor T5, so that the reset signal VINI can be applied to the second electrode of the second storage capacitor C2, the first electrode of the light emitting element OLED and the first electrode of the driving transistor DT.

[0171] Correspondingly, as shown in FIG. 3 and FIG. 4A, in the third sub-reset stage P3, the data scanning signal G1 remains a low-level signal to turn off the data writing transistor T1; the second light emitting control signal EM2 remains a high-level signal to turn on the second light emitting control transistor T4; the first light emitting control signal EM1 remains a low-level signal to turn off the first light emitting control transistor T2; the reset control signal G3 remains a high-level signal to make the reset transistor T5 in the on state; in addition, corresponding to step S1030, the first compensation control signal G2 is switched to a high-level signal to turn on the first compensation transistor T3, so that the reference signal REF can be applied to the gate electrode of the driving transistor DT.

[0172] Therefore, as shown in FIG. 3 and FIG. 4A, the reset transistor T5 is turned on in the case that the first light emitting control transistor T2 is turned off, thereby preventing the first light emitting control transistor T2 from being turned on through the driving transistor DT and the second light emitting control transistor T4 with the reset transistor T5, so that the driving current can be more stable, which is conducive to the safety of the device.

[0173] For example, as shown in FIG. 3 and FIG. 4A, the reference signal REF is a reference voltage, and its value is VREF; the reset signal VINI is a reset voltage, and its value is VINI. The difference between the voltage value of the gate of the driving transistor DT and the voltage value of its first pole is the gate-source voltage Vgs, and the threshold voltage of the driving transistor DT is Vth. After the steps in the above-mentioned first sub-reset stage P1, second sub-reset stage P2 and third sub-reset stage P3 are completed, Vgs≥Vth, that is, VREF-VINI≥Vth. For example, when Vgs>Vth, the driving transistor DT is in the on state.

[0174] It should be noted that the steps corresponding to the above-mentioned first sub-reset stage P1, second sub-reset stage P2 and third sub-reset stage P3 are executed in sequence, so that the driving current in the pixel circuit can be well controlled, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to at least two of the above-mentioned first sub-reset stage P1, second sub-reset stage P2 and third sub-reset stage P3 can be executed synchronously. For example, the steps corresponding to the first sub-reset stage P1, second sub-reset stage P2 and third sub-reset stage P3 can be executed synchronously, and the embodiments of the present disclosure do not limit this.

[0175] For example, as shown in FIG. 1 and FIG. 3, in the compensation stage 2, the driving method of the pixel circuit comprises:

[0176] Step S2010: let the second light emitting control signal EM2 be a closing signal to turn off the second light emitting control circuit 500, and let the first light emitting control signal EM1 be a closing signal to turn off the first light emitting control circuit 400; and

[0177] Step S2020: let the first light emitting control signal EM1 be an opening signal to turn on the first light emitting control circuit 400, and keep the second light emitting control signal EM2 as a closing signal.

[0178] For example, in the compensation stage 2, the data scanning signal G1 keeps as a closing signal to keep the data writing circuit 200 turned off, the first compensation control signal G2 keeps as an opening signal to keep the first compensation circuit 300 turned on, and the reset control signal G3 is an opening signal to turn on the reset circuit 700.

[0179] For example, as shown in FIG. 1 and FIG. 3, in the first sub-compensation phase P4, the data scanning signal G1 remains as a closing signal to turn off the data writing circuit 200; the first compensation control signal G2 and the reset control signal G3 both remain as opening signals, so that the first compensation circuit 300 and the reset circuit 700 are both in the opening state; the first light-emitting control signal EM1 remains as a closing signal to turn off the first light-emitting control circuit 400; in addition, corresponding to step S2010, the second light-emitting control signal EM2 is switched to a closing signal to turn off the second light-emitting control circuit 500.

[0180] For example, as shown in FIG. 1 and FIG. 3, in the second sub-compensation phase P5, the data scanning signal G1 remains as a closing signal to turn off the data writing circuit 200; the first compensation control signal G2 and the reset control signal G3 both remain as opening signals, so that the first compensation circuit 300 and the reset circuit 700 are both in the opening state; the second light-emitting control signal EM2 remains as a closing signal to turn off the second light-emitting control circuit 500; in addition, corresponding to step S2020, the first light-emitting control signal EM1 is switched to an opening signal to turn on the first light-emitting control circuit 400.

[0181] For example, as shown in FIG. 1 and FIG. 3, in the case that the second light-emitting control circuit 500 is turned off in the first sub-compensation phase P4 and remains off in the second sub-compensation phase P5, the first light-emitting control circuit 400 is also turned on in the second sub-compensation phase P5, so that in the case that the reset circuit 700 is in the opening state, the first light-emitting control circuit 400 can be prevented from being turned on through the driving circuit 100 and the second light-emitting control circuit 500 and the reset circuit 700, and thus the driving current can be more stable, which is beneficial to the safety of the device.

[0182] Correspondingly, as shown in FIG. 2 and FIG. 3, in the first sub-compensation phase P4, the data scanning signal G1 remains as a closing signal to turn off the data writing transistor T1; the first compensation control signal G2 and the reset control signal G3 both remain as opening signals, so that the first compensation transistor T3 and the reset transistor T5 are both in the opening state; the first light-emitting control signal EM1 remains as a closing signal to turn off the first light-emitting control transistor T2; in addition, corresponding to step S2010, the second light-emitting control signal EM2 is switched to a closing signal to turn off the second light-emitting control transistor T4.

[0183] Correspondingly, as shown in FIG. 3 and FIG. 4B, in the second sub-compensation phase P5, the data scanning signal G1 remains as a closing signal to close the data writing transistor T1; the first compensation control signal G2 and the reset control signal G3 both remain as opening signals, so that the first compensation transistor T3 and the reset transistor T5 are both in an opening state; the second light-emitting control signal EM2 remains as a closing signal to close the second light-emitting control transistor T4; in addition, corresponding to step S2020, the first light-emitting control signal EM1 is switched to an opening signal to open the first light-emitting control transistor T2, so that the first power supply voltage ELVDD is applied to the second electrode of the driving transistor DT.

[0184] For example, as shown in FIG. 2, FIG. 3 and FIG. 4B, in the case that the second light-emitting control transistor T4 is turned off in the first sub-compensation phase P4 and remains off in the second sub-compensation phase P5, the first light-emitting control transistor T2 is also turned on in the second sub-compensation phase P5, so that in the case that the reset transistor T5 is in a conducting state, the first light-emitting control transistor T2 can be prevented from being turned on through the driving transistor DT and the second light-emitting control transistor T4 and the reset transistor T5, and thus the driving current can be more stable, which is conducive to the safety of the device.

[0185] For example, as shown in FIG. 3 and FIG. 4B, at the beginning of the compensation phase 2, the voltage value of the first electrode of the driving transistor DT is equal to the value Vini of the reset voltage, and Vgs-Vth>0. After the steps in the above-mentioned first sub-compensation phase P4 and second sub-compensation phase P5 are completed, the voltage value of the gate electrode of the driving transistor DT is VREF, and the voltage of the second electrode of the driving transistor DT is the first power supply voltage ELVDD, since the value of the first power supply voltage ELVDD is greater than the voltage value of the first electrode of the driving transistor DT (i.e. Vini), the driving transistor DT can be charged by the first power supply voltage ELVDD until the driving transistor DT is turned off, so that the voltage value Vs of the first end of the driving transistor DT is equal to Vref-Vth.

[0186] It should be noted that the steps corresponding to the above-mentioned first sub-reset phase P4 and second sub-compensation phase P5 are executed in sequence, so that the driving current in the pixel circuit can be well controlled, but embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to the above-mentioned first sub-reset phase P4 and second sub-compensation phase P5 can also be executed synchronously, and embodiments of the present disclosure do not limit this.

[0187] For example, as shown in FIG. 1 and FIG. 3, in the data writing phase 3, the driving method of the pixel circuit comprises:

[0188] Step S3010: let the first compensation control signal G2 be a turn-off signal to turn off the first compensation circuit 300, and let the second end of the driving circuit 100 keep receiving the first power voltage ELVDD;

[0189] Step S3020: let the first light-emitting control signal EM1 be a turn-off signal to turn off the first light-emitting control circuit 400, so that the second end of the driving circuit 100 is disconnected from the first voltage terminal ELVDD; and

[0190] Step S3030: let the data scanning signal G1 be a turn-on signal to turn on the data writing circuit 200.

[0191] In the data writing phase 2, the second light-emitting control signal EM2 keeps being a turn-off signal to keep the second light-emitting control circuit 500 turned off, and the reset control signal G3 keeps being a turn-on signal to keep the reset circuit 700 turned on.

[0192] For example, as shown in FIG. 1 and FIG. 3, in the first sub-data writing phase P6, the data scanning signal G1 keeps being a turn-off signal to turn off the data writing circuit 200; the first light-emitting control signal EM1 keeps being a turn-on signal to turn on the first light-emitting control circuit 400, so that the second end of the driving circuit 100 keeps receiving the first power voltage ELVDD; the second light-emitting control signal EM2 keeps being a turn-off signal to turn off the second light-emitting control circuit 500; the reset control signal G3 keeps being a turn-on signal to keep the reset circuit 700 turned on; in addition, corresponding to step S3010, the first compensation control signal G2 is switched to a turn-off signal to turn off the first compensation circuit 300, so that the reference signal REF stops being applied to the control electrode 100m of the driving circuit 100.

[0193] For example, as shown in FIG. 1 and FIG. 3, in the second sub-data writing phase P7, the data scanning signal G1 keeps being a turn-off signal to turn off the data writing circuit 200; the second light-emitting control signal EM2 keeps being a turn-off signal to turn off the second light-emitting control circuit 500; the reset control signal G3 keeps being a turn-on signal to keep the reset circuit 700 turned on; the first compensation control signal G2 is a turn-off signal to turn off the first compensation circuit 300; in addition, corresponding to step S3020, the first light-emitting control signal EM1 is switched to a turn-off signal to turn off the first light-emitting control circuit 400, so that the second end of the driving circuit 100 stops receiving the first power voltage ELVDD.

[0194] For example, as shown in FIG. 1 and FIG. 3, in the third sub-data writing stage P8, the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control circuit 500; the reset control signal G3 remains as a turn-on signal to make the reset circuit 700 all in the turn-on state; the first compensation control signal G2 is a turn-off signal to turn off the first compensation circuit 300; the first light-emitting control signal EM1 remains as a turn-off signal to turn off the first light-emitting control circuit 400; in addition, corresponding to step S3030, the data scanning signal G1 is switched to a turn-on signal to turn on the data writing circuit 200, so that the data signal DATA is applied to the control electrode 100m of the driving circuit 100.

[0195] For example, as shown in FIG. 1 and FIG. 3, the third sub-data writing stage P8 corresponds to the step after the step corresponding to the first sub-data writing stage P6, that is, after the first compensation circuit 300 is turned off, the data writing circuit 200 is turned on. By using this driving method, the data writing circuit 200 can be turned on after the first compensation circuit 300 is turned off, so that the data signal DATA is not applied to the control electrode 100m of the driving circuit 100 at the same time when the reference signal REF is applied to the control electrode 100m of the driving circuit 100 by the first compensation circuit 300, thereby making the control method of the driving circuit more reliable and making the driving current more stable.

[0196] Correspondingly, as shown in FIG. 2 and FIG. 3, in the first sub-data writing stage P6, the data scanning signal G1 remains as a turn-off signal to turn off the data writing transistor T1; the first light-emitting control signal EM1 remains as a turn-on signal to turn on the first light-emitting control transistor T2, so that the second electrode of the driving transistor DT keeps receiving the first power supply voltage ELVDD; the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control transistor T4; the reset control signal G3 remains as a turn-on signal to make the reset transistor T5 all in the turn-on state; in addition, corresponding to step S3010, the first compensation control signal G2 is switched to a turn-off signal to turn off the first compensation transistor T3.

[0197] Correspondingly, as shown in FIG. 2 and FIG. 3, in the second sub-data writing stage P7, the data scanning signal G1 remains as a turn-off signal to turn off the data writing transistor T1; the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control transistor T4; the reset control signal G3 remains as a turn-on signal to make the reset transistor T5 in the turn-on state; the first compensation control signal G2 remains as a turn-off signal to turn off the first compensation transistor T3. In addition, corresponding to step S3020, the first light-emitting control signal EM1 is switched to a turn-off signal to turn off the first light-emitting control transistor T2, so that the second electrode of the driving transistor DT is disconnected with the first power supply voltage terminal ELVDD.

[0198] Correspondingly, as shown in FIG. 3 and FIG. 4C, in the third sub-data writing stage P8, the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control transistor T4; the reset control signal G3 remains as a turn-on signal to make the reset transistor T5 in a turn-on state; the first compensation control signal G2 remains as a turn-off signal to turn off the first compensation transistor T3; and the first light-emitting control signal EM1 remains as a turn-off signal to turn off the first light-emitting control transistor T2, so as to disconnect the second electrode of the driving transistor DT from the first power supply voltage terminal ELVDD. In addition, corresponding to step S3030, the data scanning signal G1 is switched to a turn-on signal to turn on the data writing transistor T1, so as to write the data signal DATA to the gate electrode of the driving transistor DT.

[0199] For example, as shown in FIG. 2, FIG. 3 and FIG. 4C, after the first compensation transistor T3 is turned off in the first sub-data writing stage P6, the data writing transistor T1 is turned on. By using this driving method, the data writing transistor T1 can be prevented from applying the data signal DATA to the gate electrode of the driving transistor DT at the same time when the first compensation transistor T3 applies the reference signal REF to the gate electrode of the driving transistor DT, so as to make the control method of the driving circuit more reliable and make the driving current more stable.

[0200] For example, as shown in FIG. 3 and FIG. 4C, after the steps in the above-mentioned first sub-data writing stage P6, second sub-data writing stage P7 and third sub-data writing stage P8 are completed, the voltage value of the gate electrode of the driving transistor DT and the voltage value of the first electrode of the first storage capacitor C1 are both equal to the value Vdata of the data voltage DATA, and the voltage value of the first electrode of the driving transistor DT is Vref-Vth+C1 / (C1+C2)×(Vdata-Vref). Here, for the sake of clear illustration, the same reference sign C1 is used for the capacitance value of the first storage capacitor and the first storage capacitor, and the same reference sign C2 is used for the capacitance value of the second storage capacitor and the second storage capacitor.

[0201] It should be noted that the steps corresponding to the above-mentioned first sub-data writing stage P6, second sub-data writing stage P7 and third sub-data writing stage P8 are sequentially executed to make the driving current in the pixel circuit be well controlled, but embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the steps corresponding to at least two of the above-mentioned first sub-data writing stage P6, second sub-data writing stage P7 and third sub-data writing stage P8 can be synchronously executed. For example, the steps corresponding to the first sub-data writing stage P6, second sub-data writing stage P7 and third sub-data writing stage P8 can be synchronously executed, and embodiments of the present disclosure do not limit this.

[0202] For example, as shown in FIG. 2 and FIG. 3, in the light emitting stage 4, the driving method of the pixel circuit includes:

[0203] Step S101: let the data scanning signal G1 be a closing signal to turn off the data writing circuit 200;

[0204] Step S102: let the second light emitting control signal EM2 be an opening signal to turn on the second light emitting control circuit 500, and let the first light emitting control signal EM1 remain a closing signal to turn off the first light emitting control circuit 400;

[0205] Step S103: let the reset control signal G3 be a closing signal to turn off the reset circuit 700;

[0206] Step S104: let the first light emitting control signal EM1 be an opening signal to turn on the first light emitting control circuit 400, so that the second end 100b of the driving circuit 100 receives the first power voltage ELVDD via the first light emitting control circuit 400.

[0207] In the light emitting stage 4, the first compensation control signal G2 remains a closing signal to turn off the first compensation circuit 300.

[0208] For example, as shown in FIG. 1 and FIG. 3, in the first sub-light emitting stage P9, the first light emitting control signal EM1 is a closing signal to turn off the first light emitting control circuit 400; the second light emitting control signal EM2 is a closing signal to turn off the second light emitting control circuit 500; the first compensation control signal G2 is a closing signal to turn off the first compensation circuit 300; and the reset control signal G3 is an opening signal to turn on the reset circuit 700. In addition, corresponding to step S101, the data scanning signal G1 is switched to a closing signal to turn off the data writing circuit 200, so that the data writing circuit 200 stops applying the data signal DATA to the control end 100m of the driving circuit 100.

[0209] For example, as shown in FIG. 1 and FIG. 3, in the second sub-light emitting stage P10, the first light emitting control signal EM1 is a closing signal to turn off the first light emitting control circuit 400; the first compensation control signal G2 is a closing signal to turn off the first compensation circuit 300; the reset control signal G3 is an opening signal to turn on the reset circuit 700; and the data scanning signal G1 is a closing signal to turn off the data writing circuit 200. In addition, corresponding to step S102, the second light emitting control signal EM2 is switched to an opening signal to turn on the second light emitting control circuit 500.

[0210] For example, as shown in FIG. 1 and FIG. 3, in the third sub-emitting stage P11, the first emitting control signal EM1 is a closing signal to turn off the first emitting control circuit 400; the first compensation control signal G2 is a closing signal to turn off the first compensation circuit 300; the data scanning signal G1 is a closing signal to turn off the data writing circuit 200; and the second emitting control signal EM2 is an opening signal to turn on the second emitting control circuit 500. In addition, corresponding to step S103, the reset control signal G3 is switched to a closing signal to turn off the reset circuit 700.

[0211] For example, as shown in FIG. 1 and FIG. 3, in the fourth sub-emitting stage P12, the first compensation control signal G2 is a closing signal to turn off the first compensation circuit 300; the data scanning signal G1 is a closing signal to turn off the data writing circuit 200; the second emitting control signal EM2 is an opening signal to turn on the second emitting control circuit 500; and the reset control signal G3 is a closing signal to turn off the reset circuit 700. In addition, corresponding to step S104, the first emitting control signal EM1 is switched to an opening signal to turn on the first emitting control circuit 400.

[0212] For example, as shown in FIG. 1 and FIG. 3, the steps corresponding to the fourth sub-emitting stage P12 are executed after the steps corresponding to the second sub-emitting stage P10. For example, when the second emitting control circuit 500 is turned on, the voltage of the first end 100a of the driving circuit 100, the voltage of the first electrode 600a of the light emitting element 600, and the voltage of the second pole of the second storage capacitor C2 are all reset to the reset voltage VINI, the voltage value of the first end 100a of the driving circuit 100 has a first change amount, and the voltage of the first pole of the first storage capacitor C1 also has the first change amount. Since the voltage between the two poles of the first storage capacitor C1 does not change abruptly, the voltage of the second pole of the first storage capacitor C1 (i.e., the voltage of the control end 100m of the driving circuit 100) also changes by the first change amount, so that the gate-source voltage Vgs of the driving transistor DT (as shown in FIG. 4D) in the driving circuit 100 does not change. Then, in the fourth sub-emitting stage P12, the first emitting control circuit 400 is turned on to make the light emitting element 600 emit light. By using this driving method, the voltage difference between the first end 100a of the driving circuit 100 and the first electrode 600a of the light emitting element 600 can be eliminated when the light emitting element 600 emits light, so as to reduce the risk of the voltage of the first end 100a of the driving circuit 100 jumping.

[0213] Correspondingly, as shown in FIGS. 2 and 3, in the first sub-emitting stage P9, the first emitting control signal EM1 is a closing signal to close the first emitting control transistor T2; the second emitting control signal EM2 is a closing signal to close the second emitting control transistor T4; the first compensation control signal G2 is a closing signal to close the first compensation transistor T3; and the reset control signal G3 is an opening signal to open the reset transistor T5. In addition, corresponding to step S101, the data scanning signal G1 is switched to a closing signal to close the data writing transistor T1, so that the data signal DATA stops being applied to the control terminal 100m of the driving circuit 100.

[0214] Correspondingly, as shown in FIGS. 2 and 3, in the second sub-emitting stage P10, the first emitting control signal EM1 is a closing signal to close the first emitting control transistor T2; the first compensation control signal G2 is a closing signal to close the first compensation transistor T3; the reset control signal G3 is an opening signal to open the reset transistor T5; and the data scanning signal G1 is a closing signal to close the data writing transistor T1. In addition, corresponding to step S102, the second emitting control signal EM2 is switched to an opening signal to open the second emitting control transistor T4.

[0215] Correspondingly, as shown in FIGS. 2 and 3, in the third sub-emitting stage P11, the first emitting control signal EM1 is a closing signal to close the first emitting control transistor T2; the first compensation control signal G2 is a closing signal to close the first compensation transistor T3; the data scanning signal G1 is a closing signal to close the data writing transistor T1; and the second emitting control signal EM2 is an opening signal to open the second emitting control transistor T4. In addition, corresponding to step S103, the reset control signal G3 is switched to a closing signal to close the reset transistor T5.

[0216] Correspondingly, as shown in FIGS. 3 and 4D, in the fourth sub-emitting stage P12, the first compensation control signal G2 is a closing signal to close the first emitting control transistor T3; the data scanning signal G1 is a closing signal to close the data writing transistor T1; the second emitting control signal EM2 is an opening signal to open the second emitting control transistor T4; and the reset control signal G3 is a closing signal to close the reset transistor T5. In addition, corresponding to step S104, the first emitting control signal EM1 is switched to an opening signal to open the first emitting control transistor T2.

[0217] For example, as shown in FIG. 2, FIG. 3 and FIG. 4D, the steps corresponding to the fourth sub-emitting stage P12 are executed after the steps corresponding to the second sub-emitting stage P10. For example, after the second emitting control transistor T4 is turned on, so that the voltage of the first electrode of the driving transistor DT, the voltage of the first electrode of the light emitting element OLED and the voltage of the second electrode of the second storage capacitor C2 are all reset to the reset voltage VINI, the voltage value of the first electrode of the driving transistor DT has a first change amount, and the voltage of the first electrode of the first storage capacitor C1 also has the first change amount, and further, the voltage of the second electrode of the first storage capacitor C1 (i.e. the voltage of the gate electrode of the driving transistor DT) also has the first change amount, so that the gate-source voltage Vgs of the driving transistor DT does not change. Then, in the fourth sub-emitting stage P12, the first emitting control transistor T3 is turned on to make the light emitting element OLED emit light. By using this driving method, when the light emitting element OLED emits light, the voltage difference between the first electrode of the driving transistor DT and the first electrode of the light emitting element OLED can be eliminated, so as to reduce the risk of the voltage of the first electrode of the driving transistor DT jumping.

[0218] For example, as shown in FIG. 3 and FIG. 4D, after the steps in the first sub-emitting stage P9, the second sub-emitting stage P10, the third sub-emitting stage P11 and the fourth sub-emitting stage P12 are completed, the voltage value of the first electrode of the driving transistor DT is VINI, and the change amount AV = VINI - [Vref - Vth + (Vdata - Vref) x C1 / (C1 + C2)], so that the voltage value of the gate electrode of the driving transistor DT and the voltage value of the first electrode of the first storage capacitor C1 are both equal to Vdata - [Vref - Vth + C1 / (C1 + C2) x (Vdata - Vref) - VINI], and the gate-source voltage Vgs of the driving transistor DT is Vdata - Vref + Vth - C1 / (C1 + C2) x (Vdata - Vref).

[0219] The value I of the driving current flowing through the light emitting element can be obtained according to the following formula:

[0220] I = K x (Vgs - Vth) 2 , K is the conductive coefficient of the driving transistor DT. That is: I = K x [(Vdata - Vref) x C2 / (C1 + C2)] 2

[0221] According to the above formula, the value of the driving current I flowing through the light emitting element is no longer related to the threshold voltage Vth of the driving transistor, thereby realizing compensation of the pixel circuit, solving the problem of threshold voltage Vth drift of the driving transistor due to process and long time operation, and eliminating the influence on the driving current, so as to improve the display effect of the display device using the pixel circuit.

[0222] FIG. 5 is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure; FIG. 6 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 5; FIG. 7A is a schematic diagram of the pixel circuit in FIG. 5 in a third sub-reset stage; FIG. 7B is a schematic diagram of the pixel circuit in FIG. 5 in a second sub-compensation stage; FIG. 7C is a schematic diagram of the pixel circuit in FIG. 5 in a third sub-data writing stage; and FIG. 7D is a schematic diagram of the pixel circuit in FIG. 5 in a fourth sub-light emitting stage. In addition, the transistors identified by dashed lines in FIGS. 7A-7D are in an off state in the corresponding stage.

[0223] For example, as shown in FIG. 5, the pixel circuit 102 is different from the pixel circuit 101 shown in FIG. 2 in that the structures of the data transistor T1 and the first compensation transistor T3 are different. For other structures in the pixel circuit 102, please refer to the related description of FIG. 2 in the above embodiment, which will not be repeated here.

[0224] For example, in the pixel circuit 101 shown in FIG. 2, the data writing transistor T1 and the first compensation transistor T3 are transistors controlled independently of each other, the data scanning signal end G1 and the first compensation control signal end G2 are different signal ends independent of each other, and the data signal end DATA and the reference signal end REF are different signal ends independent of each other. For example, the data writing transistor T1 is controlled to be turned on or off under the control of the data scanning signal G1, the first compensation transistor T3 is controlled to be turned on or off under the control of the first compensation control signal G2, and the data writing transistor T1 and the first compensation transistor T3 are independently controlled.

[0225] For example, as shown in FIG. 5, the data writing transistor T1 is multiplexed as the first compensation transistor T3, the data scanning signal G1 is multiplexed as the first compensation control signal G2, the first electrode of the data writing transistor T1 is further electrically connected to the reference signal end REF to receive the reference signal REF, the data signal end DATA is multiplexed as the reference signal end REF, and is configured to provide the data signal DATA or the reference signal REF in different time periods, respectively.

[0226] For example, as shown in FIG. 6, the working states (e.g., open state or closed state) of each transistor in the driving process of the pixel circuit 102 are the same as those of the pixel circuit 101 shown in FIG. 2. Compared with the timing diagram shown in FIG. 3, the timing states of the first emission control signal EM1, the second emission control signal EM2 and the reset control signal G3 in the timing diagram of FIG. 6 are the same, and the difference lies in that the timing distribution of the first compensation control signal G2 is cancelled, and the timing state of the data scanning signal G1 is different.

[0227] For example, as shown in FIG. 6 and FIG. 7A, in the first sub-reset stage P1 and the second sub-reset stage P2, the data scanning signal G1 is a closed signal to make the data writing transistor T1 in a closed state. In the third sub-reset stage P3, the data scanning signal G1 is an open signal to make the data writing transistor T1 in an open state, the first electrode of the data writing transistor T1 is electrically connected with the reference signal end REF to receive the reference signal REF, and the reference signal REF is applied to the gate of the driving transistor DT.

[0228] For example, as shown in FIG. 6 and FIG. 7B, in the first sub-compensation stage P4 and the second sub-compensation stage P5, the data scanning signal G1 remains an open signal to make the data writing transistor T1 in an open state, the first electrode of the data writing transistor T1 is electrically connected with the reference signal end REF to receive the reference signal REF, and the reference signal REF is applied to the gate of the driving transistor DT.

[0229] For example, as shown in FIG. 6 and FIG. 7C, in the first sub-data writing stage P6 and the second sub-data writing stage P7, the data scanning signal G1 is a closed signal to make the data writing transistor T1 in a closed state. In the third sub-data writing stage P8, the data scanning signal G1 is an open signal to open the data writing transistor T1, the first electrode of the data writing transistor T1 is electrically connected with the data signal end DATA to receive the data signal DATA, and the data signal DATA is applied to the gate of the driving transistor DT.

[0230] For example, as shown in FIG. 6 and FIG. 7D, in the emission stage 4, the data scanning signal G1 is a closed signal to make the data writing transistor T1 in a closed state.

[0231] As described above, by multiplexing the data writing transistor as the first compensation transistor, the data signal end can receive different signals in different working stages, so as to simplify the structure of the pixel circuit and make the control mode more flexible while meeting the working needs of the pixel circuit.

[0232] FIG. 8 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0233] For example, as shown in FIG. 8, compared with the pixel circuit 10 shown in FIG. 1, the pixel circuit 20 is different in that the first light emitting control circuit 400 is removed, and other structures in the pixel circuit 20 can refer to the related description of the pixel circuit 101 in the above embodiment, which will not be repeated here.

[0234] For example, as shown in FIG. 8, the second end of the driving circuit 100 is directly electrically connected with the first voltage terminal ELVDD to receive the first power voltage ELVDD, that is, no other transistor or capacitor or other element is arranged between the second end of the driving circuit 100 and the first voltage terminal ELVDD, and the second end of the driving circuit 100 is electrically connected with the first voltage terminal ELVDD through a wire.

[0235] FIG. 9 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 8; FIG. 10 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 9; FIG. 11A is a schematic diagram of the pixel circuit shown in FIG. 9 in a third sub-reset stage; FIG. 11B is a schematic diagram of the pixel circuit shown in FIG. 9 in a second sub-compensation stage; FIG. 11C is a schematic diagram of the pixel circuit shown in FIG. 9 in a third sub-data writing stage; and FIG. 11D is a schematic diagram of the pixel circuit shown in FIG. 9 in a fourth sub-light emitting stage. In addition, the transistors identified by dashed lines in FIGS. 11A-11D are in an off state in the corresponding stage.

[0236] For example, as shown in FIG. 9, the pixel circuit 103 is different from the pixel circuit 101 shown in FIG. 1 in that the first light emitting control transistor T2 is removed, and the rest of the structures are the same.

[0237] For example, as shown in FIG. 9 and FIG. 10, in the driving process of the pixel circuit 103, the working state (for example, the on state or the off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG. 2. Compared with the timing diagram shown in FIG. 3, the timing diagram shown in FIG. 10 cancels the timing distribution corresponding to the first light emitting control signal EM1.

[0238] For example, as shown in FIG. 10 and FIG. 11A, in the third sub-reset stage P3, the data scanning signal G1 remains a low-level signal to turn off the data writing transistor T1; the second light emitting control signal EM2 is a high-level signal to turn on the second light emitting control transistor T4; the reset control signal G3 is a high-level signal to make the reset transistor T5 in an on state; and the first compensation control signal G2 is a high-level signal to turn on the first compensation transistor T3. Since the gate-source voltage Vgs of the driving transistor DT is greater than its threshold voltage Vth in this stage, the driving transistor DT is in a conductive state, and in addition, the second end of the driving transistor DT receives the first power voltage ELVDD, so that the driving transistor DT is charged.

[0239] For example, as shown in FIGS. 10 and 11B, in the second sub-compensation stage P5, the data scanning signal G1 remains as a turn-off signal to turn off the data writing circuit 200; the first compensation control signal G2 and the reset control signal G3 are both turn-on signals to make the first compensation circuit 300 and the reset circuit 700 both in the turn-on state; and the second light-emitting control signal EM2 remains as a turn-off signal to turn off the second light-emitting control circuit 500. The first power supply voltage ELVDD charges the driving transistor DT until the driving transistor DT is turned off, and the voltage at the first end of the driving transistor DT is equal to Vref-Vth.

[0240] For example, as shown in FIGS. 10 and 11C, in the third sub-data writing stage P8, the second light-emitting control signal EM2 is a turn-off signal to turn off the second light-emitting control transistor T4; the reset control signal G3 is a turn-on signal to make the reset transistor T5 in the turn-on state; the first compensation control signal G2 is a turn-off signal to turn off the first compensation transistor T3; and the data scanning signal G1 is switched to a turn-on signal to turn on the data writing transistor T1, so that the data signal DATA is written to the gate of the driving transistor DT. In addition, the second end of the driving transistor DT receives the first power supply voltage ELVDD, so that the driving transistor DT is charged.

[0241] For example, as shown in FIGS. 10 and 11D, in the fourth sub-light-emitting stage P12, the first compensation control signal G2 is a turn-off signal to turn off the first light-emitting control transistor T3; the data scanning signal G1 is a turn-off signal to turn off the data writing transistor T1; the second light-emitting control signal EM2 is a turn-on signal to turn on the second light-emitting control transistor T4; the reset control signal G3 is a turn-off signal to turn off the reset transistor T5; and the second end of the driving transistor DT keeps receiving the first power supply voltage ELVDD to make the light-emitting element OLED emit light.

[0242] For example, as shown in FIGS. 10 and 11C, the mobility of the driving transistor is positively correlated with the temperature, that is, when the temperature rises, the mobility increases; and the driving current is positively correlated with the gate-source voltage Vgs of the driving circuit. In the third sub-data writing stage P8, in the process of writing the data signal DATA to the gate of the driving transistor DT and charging the driving transistor DT, for example, when the temperature of the pixel circuit 103 is high, the mobility is large, and accordingly, the voltage at the first end of the driving transistor DT can be made higher in a certain charging time, so that the gate-source voltage Vgs of the driving transistor DT is smaller, and thus the driving current is not too large. For example, when the temperature of the pixel circuit 103 is low, the mobility is small, and accordingly, the voltage at the first end of the driving transistor DT can be made lower in a certain charging time, so that the gate-source voltage Vgs of the driving transistor DT is larger, and thus the driving current is not too small.

[0243] Therefore, in the third sub-data writing stage P8, by removing the first light emitting control transistor T2 (i.e. removing the first light emitting control circuit), so that the second end of the driving transistor DT keeps receiving the first power supply voltage ELVDD, the mobility of the driving transistor DT at different temperatures can be compensated to reduce the influence of temperature change on the driving current in the pixel circuit.

[0244] FIG. 4E is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure. For example, the difference between the signal timing diagram shown in FIG. 4E and the signal timing diagram shown in FIG. 3 is that the timing distribution of the first light emitting control signal EM1 in the third sub-data writing stage P8 is different, and the timing distributions of the other signals are the same.

[0245] For example, for some pixel circuits provided by embodiments of the present disclosure, such as the pixel circuits in FIGS. 2 and 5 described above, step S3030 in the driving method of the pixel circuit further includes: making the first light emitting control signal an on signal to turn on the first light emitting control circuit, so that the second end of the driving circuit receives the first power supply voltage.

[0246] For example, as shown in FIGS. 1 and 4E, in the third sub-data writing stage P8, when the data scanning signal G1 is an on signal to turn on the data writing circuit 200, the first light emitting control signal EM1 is an on signal to turn on the first light emitting control circuit 400, so that the second end 100b of the driving circuit 100 receives the first power supply voltage ELVDD; the second light emitting control signal EM2 remains an off signal to turn off the second light emitting control circuit 500; the reset control signal G3 remains an on signal to make the reset circuit 700 in an on state; and the first compensation control signal G2 is an off signal to turn off the first compensation circuit 300.

[0247] Correspondingly, as shown in FIGS. 4C and 4E, in the third sub-data writing stage, the data scanning signal G1 is switched to an on signal to turn on the data writing transistor T1, so that the data signal DATA is written to the gate of the driving transistor DT; the first light emitting control signal EM1 is switched to an on signal to turn on the first light emitting control transistor T2 and make the first power supply voltage ELVDD applied to the second end 100b of the driving circuit 100; and the second light emitting control signal EM2 remains an off signal to turn off the second light emitting control transistor T4; the reset control signal G3 remains an on signal to make the reset transistor T5 in an on state; and the first compensation control signal G2 remains an off signal to turn off the first compensation transistor T3.

[0248] In this way, when the temperature of the pixel circuit is high, the mobility is large, and correspondingly, the voltage at the first terminal of the driving transistor can be made high, so that the gate-source voltage Vgs of the driving transistor DT is small, and the driving current is not too large. Conversely, when the temperature of the pixel circuit is low, the mobility is small, and correspondingly, the voltage at the first terminal of the driving transistor can be made low, so that the gate-source voltage Vgs of the driving transistor is large, and the driving current is not too small.

[0249] Therefore, in the third sub-data writing stage, by canceling the first light-emitting control transistor T2 and keeping the second terminal of the driving transistor to receive the first power supply voltage, the mobility of the driving transistor DT at different temperatures can be compensated to reduce the influence of temperature change on the driving current in the pixel circuit.

[0250] FIG. 12 is a schematic diagram of another pixel circuit provided by an embodiment of the present disclosure; FIG. 13 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 12; FIG. 14A is a schematic diagram of the pixel circuit in FIG. 12 in a second sub-compensation stage; FIG. 14B is a schematic diagram of the pixel circuit in FIG. 12 in a third sub-data writing stage; and FIG. 14C is a schematic diagram of the pixel circuit in FIG. 12 in a fourth sub-light-emitting stage. In addition, the transistors identified by dashed lines in FIGS. 14A-14C are in an off state in the corresponding stage.

[0251] For example, as shown in FIG. 12, the pixel circuit 104 differs from the pixel circuit 103 shown in FIG. 9 in that the structures of the data transistor T1 and the first compensation transistor T3 are different. For other structures in the pixel circuit 104, please refer to the related descriptions about FIG. 9 in the above embodiments, which are not repeated here.

[0252] For example, in the pixel circuit 103 shown in FIG. 9, the data writing transistor T1 and the first compensation transistor T3 are transistors controlled independently of each other, the data scanning signal end G1 and the first compensation control signal end G2 are different signal ends independently of each other, and the data signal end DATA and the reference signal end REF are different signal ends independently of each other. For example, the data writing transistor T1 is controlled to be turned on or off under the control of the data scanning signal G1, the first compensation transistor T3 is controlled to be turned on or off under the control of the first compensation control signal G2, and the data writing transistor T1 and the first compensation transistor T3 are independently controlled.

[0253] For example, as shown in FIG. 12, the data write transistor T1 is multiplexed as the first compensation transistor T3, the data scanning signal G1 is multiplexed as the first compensation control signal G2 (see FIG. 9), the first electrode of the data write transistor T1 is further electrically connected to the reference signal end REF to receive the reference signal REF, the data signal end DATA is multiplexed as the reference signal end REF, and is configured to provide the data signal DATA or the reference signal REF at different time periods, respectively.

[0254] For example, as shown in FIG. 13, during the driving process of the pixel circuit 104, the working states (e.g., the open state or the closed state) of the respective transistors are the same as those of the pixel circuit 103 shown in FIG. 9. Compared with the timing diagram shown in FIG. 10, the timing states of the second emission control signal EM2 and the reset control signal G3 in the timing diagram of FIG. 13 are unchanged, and the difference lies in that the timing distribution of the first compensation control signal G2 is cancelled, and the timing state of the data scanning signal G1 is different.

[0255] For example, as shown in FIG. 13 and FIG. 12, during the first sub-reset stage P1 and the second sub-reset stage P2, the data scanning signal G1 is a closed signal to make the data write transistor T1 in the closed state. During the third sub-reset stage P3, the data scanning signal G1 is an open signal to make the data write transistor T1 in the open state, the first electrode of the data write transistor T1 is electrically connected to the reference signal end REF to receive the reference signal REF, and the reference signal REF is applied to the gate electrode of the driving transistor DT.

[0256] For example, as shown in FIG. 13 and FIG. 14A, during the first sub-compensation stage P4 and the second sub-compensation stage P5, the data scanning signal G1 remains an open signal to make the data write transistor T1 in the open state, the first electrode of the data write transistor T1 is electrically connected to the reference signal end REF to receive the reference signal REF, and the reference signal REF is applied to the gate electrode of the driving transistor DT.

[0257] For example, as shown in FIG. 13 and FIG. 14B, during the first sub-data write stage P6 and the second sub-data write stage P7, the data scanning signal G1 is a closed signal to make the data write transistor T1 in the closed state. During the third sub-data write stage P8, the data scanning signal G1 is an open signal to open the data write transistor T1, the first electrode of the data write transistor T1 is electrically connected to the data signal end DATA to receive the data signal DATA, and the data signal DATA is applied to the gate electrode of the driving transistor DT.

[0258] For example, as shown in FIG. 13 and FIG. 14C, during the fourth emission stage P4, the data scanning signal G1 is a closed signal to make the data write transistor T1 in the closed state.

[0259] As described above, by multiplexing the data writing transistor as the first compensation transistor, the data signal end can receive different signals in different working stages, so as to simplify the structure of the pixel circuit and make the control mode more flexible while meeting the working needs of the pixel circuit. For other structures and technical effects of the pixel circuit 104 shown in FIG. 12, please refer to the related description about FIG. 9 in the above embodiment, which will not be repeated here.

[0260] FIG. 15 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure.

[0261] For example, as shown in FIG. 15, compared with the pixel circuit 10 shown in FIG. 1, the pixel circuit 30 is different in that an auxiliary compensation circuit 900 is added. For other structures in the pixel circuit 30, please refer to the related description about FIG. 1 in the above embodiment, which will not be repeated here.

[0262] For example, as shown in FIG. 15 and FIG. 18A, the pixel circuit 30 includes the auxiliary compensation circuit 900, the control end 900m of the auxiliary compensation circuit 900 is configured to receive an auxiliary compensation signal EM3, the first end 900a of the auxiliary compensation circuit 900 is electrically connected with the second pole of the second storage capacitor C2, the second end 500b of the second light emitting control circuit 500 and the first end 700a of the reset circuit 700, and the second end of the auxiliary compensation circuit 900 is electrically connected with the first electrode 600a of the light emitting element 600.

[0263] FIG. 16 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 15; FIG. 17 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure; FIG. 18A is a schematic diagram of the pixel circuit shown in FIG. 15 in a third sub-reset stage; FIG. 18B is a schematic diagram of the pixel circuit shown in FIG. 15 in a second sub-compensation stage; FIG. 18C is a schematic diagram of the pixel circuit shown in FIG. 15 in a third sub-data writing stage; FIG. 18D is a schematic diagram of the pixel circuit shown in FIG. 15 in a fourth sub-light emitting stage, and in addition, the transistors identified by the dashed lines in FIG. 18A-FIG. 18D are in the off state in the corresponding stage.

[0264] For example, as shown in FIG. 16, the pixel circuit 105 is different from the pixel circuit 101 shown in FIG. 2 in that an auxiliary compensation transistor T6 is added. For other structures in the pixel circuit 105 and technical effects, please refer to the related description about FIG. 2 in the above embodiment, which will not be repeated here.

[0265] For example, as shown in FIG. 16, the auxiliary compensation circuit 900 (see FIG. 15) includes an auxiliary compensation transistor T6, a gate of the auxiliary compensation transistor T6 is electrically connected with the auxiliary compensation control terminal EM3 to receive the auxiliary compensation control signal EM3, a first pole of the auxiliary compensation transistor T6 is electrically connected with a second pole of the second compensation capacitor C2 and a second pole of the second light-emitting control transistor T4, and a second pole of the auxiliary compensation transistor T6 is electrically connected with the first electrode 600a of the light-emitting element 600. For example, the gate of the auxiliary compensation transistor T6 and the gate of the second light-emitting control transistor T4 are independent of each other and not electrically connected with each other, for example, the auxiliary compensation transistor T6 is turned on or turned off under the control of the auxiliary compensation control signal EM3, the auxiliary compensation control terminal EM3 is an independent control terminal, and the auxiliary compensation control signal EM3 and the second light-emitting control signal EM2 are different signals. For example, the auxiliary compensation transistor T6 can be an N-type transistor, which can be of the same type or different type as other transistors in the pixel circuit 105, and the embodiments of the present disclosure are not limited thereto.

[0266] For example, as shown in FIG. 17, during the driving process of the pixel circuit 105, the working state (for example, the on state or the off state) of each transistor is the same as that of the pixel circuit 101 shown in FIG. 2. Compared with the timing diagram shown in FIG. 3, the timing diagram in FIG. 17 adds the timing distribution of the auxiliary compensation control signal EM3.

[0267] For example, as shown in FIGS. 17-18D, during the reset phase 1, the compensation phase 2 and the light-emitting phase 4, the auxiliary compensation control signal EM3 is an on signal, so that the auxiliary compensation transistor T6 is in an on state. For example, during the first sub-data writing phase P6 and the second sub-data writing phase P7, the auxiliary compensation control signal EM3 is an on signal, but the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, during the first sub-data writing phase P6 and the second sub-data writing phase P7, the auxiliary compensation control signal EM3 can also be an off signal.

[0268] For example, as shown in FIGS. 17 and 18C, during the third sub-data writing phase P8, the auxiliary compensation control signal EM3 is an off signal, so that the auxiliary compensation transistor T6 is in an off state. Since the light-emitting element OLED has a capacitance, and when the auxiliary compensation transistor T6 is turned on, the capacitance in the light-emitting element OLED is in series with the second compensation capacitor C2.

[0269] Therefore, as shown in FIG. 17 and FIG. 18C, in the third sub-data writing stage P8, when the data writing transistor T1 is turned on and the data signal DATA is written to the gate of the driving transistor DT, by turning off the auxiliary compensation transistor T6, the influence of the capacitance in the light emitting element OLED on the voltage of the second end of the second compensation capacitor C2 can be reduced, so that the voltage value of the second end of the second compensation capacitor C2 is equal to the value Vini of the reset voltage, and the voltage of the first end of the driving transistor DT can be more stable.

[0270] FIG. 19 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure. FIG. 20 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 19; and FIG. 21 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0271] For example, as shown in FIG. 19, compared with the pixel circuit 30 shown in FIG. 15, the difference of the pixel circuit 40 is that the connection mode of the control electrode 900m of the auxiliary compensation circuit 900 is different, and the other structures in the pixel circuit 40 can refer to the related descriptions about FIG. 15 in the above embodiments, which will not be repeated here.

[0272] For example, as shown in FIG. 20, the gate of the auxiliary compensation transistor T6 is electrically connected with the gate of the second light emitting control transistor T4, the auxiliary compensation transistor T6 and the second light emitting control transistor T4 share the gate, the second light emitting control signal EM2 is used as the auxiliary compensation control signal EM3, and the type of the auxiliary compensation transistor T6 is the same as that of the second light emitting control transistor T4. Therefore, when the second light emitting control signal EM2 is an on signal, the auxiliary compensation transistor T6 and the second light emitting control transistor T4 are both turned on in response to the second light emitting control signal EM2; when the second light emitting control signal EM2 is an off signal, the auxiliary compensation transistor T6 and the second light emitting control transistor T4 are both turned off in response to the second light emitting control signal EM2.

[0273] FIG. 22A is a schematic diagram of the pixel circuit in FIG. 20 in the third sub-reset stage; FIG. 22B is a schematic diagram of the pixel circuit in FIG. 20 in the second sub-compensation stage; FIG. 22C is a schematic diagram of the pixel circuit in FIG. 20 in the third sub-data writing stage; and FIG. 22D is a schematic diagram of the pixel circuit in FIG. 20 in the fourth sub-light emitting stage.

[0274] For example, as shown in FIG. 21 and FIG. 22A, in the reset stage 1, the second light emitting control signal EM2 is a high-level signal, and the auxiliary compensation transistor T6 and the second light emitting control transistor T4 are both in an on state, so that the reset signal VINI can be applied to the first end of the light emitting element OLED through the auxiliary compensation transistor T6.

[0275] For example, as shown in FIG. 21 and FIG. 22B, in the compensation stage 2, the second light-emitting control signal EM2 is a low-level signal, and the auxiliary compensation transistor T6 and the second light-emitting control transistor T4 are both in the off state to avoid the light-emitting element OLED from emitting light in this stage.

[0276] For example, as shown in FIG. 21 and FIG. 22C, in the data writing stage 3, the second light-emitting control signal EM2 is a low-level signal, and the auxiliary compensation transistor T6 and the second light-emitting control transistor T4 are both in the off state, and the voltage value of the second end of the second compensation capacitor C2 is equal to the value Vini of the reset voltage, so as to make the voltage of the first end of the driving transistor DT more stable.

[0277] For example, as shown in FIG. 21 and FIG. 22D, in the first sub-light-emitting stage P9, the data scanning signal G1 is switched from a high-level signal in the third sub-data writing stage P8 to a low-level signal, and the data writing transistor T1 is switched from an on state in the third sub-data writing stage P8 to an off state, so as to stop the gate of the driving transistor DT from receiving the data signal DATA. The second light-emitting control signal EM2 remains a low-level signal, and the auxiliary compensation transistor T6 and the second light-emitting control transistor T4 are both in the off state.

[0278] In this way, the auxiliary compensation transistor T6 and the second light-emitting control transistor T4 are both controlled by the second light-emitting control signal EM2, which can simplify the pixel structure and make the driving method more convenient. At the same time, the risk of the auxiliary compensation transistor T6 being in the on state during the switching of the data writing transistor T1 to the off state can be reduced, and thus the stability of the voltage of the second end of the second compensation capacitor C2 is good.

[0279] FIG. 23 is a schematic block diagram of another pixel circuit provided by at least one embodiment of the present disclosure. FIG. 24 is a circuit diagram of an implementation example of the pixel circuit shown in FIG. 23; and FIG. 25 is a signal timing diagram of another driving method provided by at least one embodiment of the present disclosure.

[0280] For example, as shown in FIG. 23, compared with the pixel circuit 30 shown in FIG. 15, the difference between the pixel circuit 50 is that the connection mode of the auxiliary compensation circuit 900 is different, and other structures of the pixel circuit 50 can refer to the related descriptions of FIG. 15 in the above embodiments, which are not repeated here.

[0281] For example, as shown in FIG. 23, the pixel circuit 50 comprises an auxiliary compensation circuit 900, a control end 900m of the auxiliary compensation circuit 900 is configured to receive an auxiliary compensation signal EM3, a first end 900a of the auxiliary compensation circuit 900 is electrically connected with the second pole of the second storage capacitor C2, the first end 700a of the reset circuit 700, a second end 900b of the auxiliary compensation circuit 900 is electrically connected with the first electrode 600a of the light emitting element 600 and the second end 500b of the second light emitting control circuit 500. For example, the control end 900m of the auxiliary compensation circuit 900 can be an independent control end, and the auxiliary compensation signal EM3 is an independent control signal to control the conduction or turn-off of the auxiliary compensation circuit 900, but the embodiments of the present disclosure are not limited thereto.

[0282] For example, as shown in FIG. 23 and FIG. 24, the pixel circuit 107 is different from the pixel circuit 105 shown in FIG. 16 in that the connection mode of the auxiliary compensation transistor T6 is different, and the remaining structure and technical effects please refer to the related description of the above-mentioned embodiments, which will not be repeated here.

[0283] For example, as shown in FIG. 23 and FIG. 24, the auxiliary compensation circuit 900 comprises an auxiliary compensation transistor T6, a gate of the auxiliary compensation transistor T6 is electrically connected with the auxiliary compensation control end EM3 to receive the auxiliary compensation control signal EM3, a first pole of the auxiliary compensation transistor T6 is electrically connected with the second pole of the second compensation capacitor C2 and the first pole of the reset transistor T5, and a second pole of the auxiliary compensation transistor T6 is electrically connected with the first electrode 600a of the light emitting element 600 and the second pole of the second light emitting control transistor T4.

[0284] For example, as shown in FIG. 24, the gate of the auxiliary compensation transistor T6 is electrically connected with the gate of the reset transistor T5, the auxiliary compensation transistor T6 shares the gate with the reset transistor T5, the reset control signal G3 is used as the auxiliary compensation control signal EM3, and the type of the auxiliary compensation transistor T6 is the same as that of the reset transistor T5. For example, when the reset control signal G3 is an opening signal, the auxiliary compensation transistor T6 and the reset transistor T5 are both opened in response to the reset control signal G3; when the reset control signal G3 is a closing signal, the auxiliary compensation transistor T6 and the reset transistor T5 are both closed in response to the reset control signal G3.

[0285] FIG. 26A is a schematic diagram of the pixel circuit in FIG. 24 in a third sub-reset stage; FIG. 26B is a schematic diagram of the pixel circuit in FIG. 24 in a second sub-compensation stage; FIG. 26C is a schematic diagram of the pixel circuit in FIG. 24 in a third sub-data writing stage; and FIG. 26D is a schematic diagram of the pixel circuit in FIG. 24 in a fourth sub-light emitting stage.

[0286] For example, as shown in FIG. 25 and FIG. 26A, in the first sub-reset stage P1, the first emission control signal EM1 is switched from a high level signal to a low level signal at the fourth sub-emission stage P12, and the reset control signal G3 remains a low level signal, thereby avoiding the risk of forming a current path between the second end of the driving transistor DT, the second emission control transistor T4 and the auxiliary compensation transistor T6, and the second end of the reset transistor T5 in this stage, so as to improve the safety of the devices in the driving circuit 107. In the second sub-reset stage P2 and the third sub-reset stage P3, the reset control signal G3 is switched to a high level signal to turn on the auxiliary compensation transistor T6 and the reset transistor T5, so as to enable the reset voltage to be applied to the first electrode of the light emitting element OLED.

[0287] For example, as shown in FIG. 25, FIG. 26B and FIG. 26C, in the compensation stage 2 and the data writing stage 3, the reset control signal G3 remains a high level signal to enable the auxiliary compensation transistor T6 and the reset transistor T5 to be in an open state, so as to enable the voltage at the second end of the second compensation capacitor C2 to remain the reset voltage.

[0288] For example, as shown in FIG. 25 and FIG. 26D, in the first sub-emission stage P9 and the second sub-emission stage P10, the reset control signal G3 remains a high level signal to enable the auxiliary compensation transistor T6 and the reset transistor T5 to be in an open state. In the third sub-emission stage P11 and the fourth sub-emission stage P12, the reset control signal G3 is a low level signal to enable the auxiliary compensation transistor T6 and the reset transistor T5 to be in a closed state. In the first sub-emission stage P9, the second sub-emission stage P10 and the third sub-emission stage P11, the first emission control signal EM1 is a low level signal to enable the first emission control transistor T2 to be in a closed state; in the fourth sub-emission stage P12, the first emission control signal EM1 is switched to a high level signal to enable the first power voltage ELVDD to be applied to the second end of the driving transistor DT, and the light emitting element OLED is in an emission state.

[0289] By arranging the auxiliary compensation transistor between the first electrode of the light emitting element and the second end of the second storage capacitor, the influence of the capacitance of the light emitting element on the voltage of the second end of the second storage capacitor can be reduced, so as to make the voltage of the second end of the second storage capacitor more stable, and further make the voltage of the first end of the driving transistor more stable.

[0290] For example, in some embodiments, when the first pole of the auxiliary compensation transistor T6 is electrically connected with the second pole of the second compensation capacitor C2 and the first pole of the reset transistor T5, the second pole of the auxiliary compensation transistor T6 is electrically connected with the first electrode 600a of the light emitting element 600 and the second pole of the second light emitting control transistor T4, the gate of the auxiliary compensation transistor T6 and the gate of the reset transistor T5 can also be independent of each other and not electrically connected. For example, the auxiliary compensation transistor T6 can also share the gate with the second light emitting control transistor T4. In this way, when the data write transistor T1 is turned on and the data signal DATA is written to the gate of the driving transistor DT, the influence of the capacitance in the light emitting element OLED on the voltage of the second pole of the second compensation capacitor C2 can be reduced by turning off the auxiliary compensation transistor T6, so that the voltage value of the second pole of the second compensation capacitor C2 is equal to the value Vini of the reset voltage, and the voltage of the first pole of the driving transistor DT can be more stable.

[0291] For example, in some embodiments of the present disclosure, when the first pole of the auxiliary compensation transistor T6 is electrically connected with the second pole of the second compensation capacitor C2 and the first pole of the reset transistor T5, the second pole of the auxiliary compensation transistor T6 is electrically connected with the first electrode 600a of the light emitting element 600 and the second pole of the second light emitting control transistor T4, the gate of the auxiliary compensation transistor T6 can be an independent electrode, and the embodiments of the present disclosure do not limit the setting mode of the gate of the auxiliary compensation transistor T6.

[0292] Embodiments of the present disclosure also provide a method for reducing the influence of temperature change on the size of the driving current.

[0293] For example, as shown in FIGS. 3 and 4A, when the reset stage 1 is completed, the voltage of the first pole of the driving transistor DT is the reset voltage VINI when entering the compensation stage 2. In the compensation stage 2, for example, in the second sub-compensation stage P5, the first light emitting control transistor T2 is turned on, so that the driving transistor DT is charged until the driving transistor DT is cut off, and then the gate-source voltage Vgs of the driving transistor DT is equal to its threshold voltage Vth, that is, the voltage Vs of the first pole of the driving transistor DT is equal to Vref-Vth.

[0294] However, in some cases, the pixel circuit may be disturbed by some factors in actual operation, as shown in FIG. 3 and FIG. 4A. For example, the charging time of the driving transistor DT may be insufficient, which may cause the driving transistor DT not to be completely turned off, and the voltage Vs of the first electrode of the driving transistor DT is less than the theoretical value Vref-Vth derived above, so that the driving current in the light emitting stage is small. In addition, for the pixel circuit using oxide material, the light emitting brightness of the light emitting element may be affected by temperature change, mainly because the mobility of the oxide transistor changes with temperature. For example, when the temperature rises, the mobility of the oxide transistor will rise, which may cause the driving current to increase; on the contrary, when the temperature drops, the mobility of the oxide transistor will decrease, which may cause the driving current to decrease. Therefore, the voltage value of the first electrode of the driving transistor DT is crucial to the light emitting brightness of the light emitting element when the compensation stage is completed.

[0295] It should be noted that the method for reducing the influence of temperature change on the driving current provided by the embodiments of the present disclosure is applicable to the pixel circuit provided by the embodiments of the present disclosure, and the following will be described taking the pixel circuit 101 shown in FIG. 2 as an example.

[0296] FIG. 27 is a schematic diagram of the reset voltage changing with temperature in at least one embodiment of the present disclosure.

[0297] For example, in at least one embodiment of the present disclosure, the value of the reset signal is adjustable. For example, the reset signal is a non-constant signal, which can be adjusted according to the operation needs of the pixel circuit. For example, the reset signal can be a direct current signal, or a non-direct current signal.

[0298] For example, as shown in FIG. 4A, the reset signal VINI is the reset voltage. The method for reducing the influence of temperature change on the driving current provided by the embodiments of the present disclosure includes: as the ambient temperature of the pixel circuit rises, the reset voltage Vini increases accordingly.

[0299] For example, the reset signal VINI at least includes a first reset signal and a second reset signal, the first reset signal corresponds to a first display temperature, the second reset signal corresponds to a second display temperature, and the first display temperature is lower than the second display temperature, and the value of the first reset signal is less than the value of the second reset signal. For example, when the temperature of the pixel circuit rises from the first display temperature to the second display temperature, the value of the reset signal rises from the value of the first reset signal to the value of the second reset signal.

[0300] For example, as shown in FIG. 4A and FIG. 27, the value of the first reset signal can be Vini1, the value of the second reset signal can be Vini2, the first display temperature can be 300C, and the second display temperature can be 600C. For example, when the temperature at which the pixel circuit 102 is located increases, for example, from the first display temperature to the second display temperature, the value of the reset voltage can be increased accordingly, i.e., from Vini1 to Vini2. Thus, when the reset stage is completed, the voltage value of the first electrode of the driving transistor DT can be increased to Vini2 accordingly.

[0301] For example, as shown in FIG. 4B, when the initial value of the voltage of the first electrode of the driving transistor DT is Vini1 before charging, after the charging time D, the voltage value of the first electrode of the driving transistor DT is Vs1. For example, when the initial value of the voltage of the first electrode of the driving transistor DT is Vini2 before charging, after the charging time D, the voltage value of the first electrode of the driving transistor DT is Vs2, and Vs2 is greater than Vs1. Also, when the compensation stage is completed, and the driving transistor DT is not completely cut off (for example, due to insufficient charging time, etc.), the voltage value of the first electrode of the driving transistor DT (i.e., Vs1 and Vs2) is less than Vref-Vth.

[0302] For example, as shown in FIG. 4C, when the data writing stage is completed, the voltage value of the first electrode of the driving transistor DT is increased from Vs1+(Vdata-Vref)xC1 / (C1+C2) to Vs2+(Vdata-Vref)xC1 / (C1+C2). Thus, as shown in FIG. 4D, when entering the light emitting stage, since the voltage value of the gate of the driving transistor DT is Vdata, the gate-source voltage Vgs of the driving transistor DT is reduced from Vdata-[Vs1+(Vdata-Vref)xC1 / (C1+C2)] to Vdata-[Vs2+(Vdata-Vref)xC1 / (C1+C2)].

[0303] The value I of the driving current flowing through the light emitting element can be obtained according to the following formula:

[0304] I=K×(Vgs-Vth) 2 K is the conductive coefficient of the driving transistor DT.

[0305] That is, when the gate-source voltage Vgs of the driving transistor DT is reduced, the value I of the driving current is reduced.

[0306] Therefore, when the temperature of the pixel circuit increases, the mobility of the driving transistor increases, and the driving current also increases. By increasing the reset voltage, the increase of the driving current can be inhibited, and the driving current in the pixel circuit can be kept in a reasonable range, so that the driving current is more stable.

[0307] Table 1 shows the data distribution between the reset voltage and the driving current in the embodiment of the present disclosure. For example, as shown in Table 1, in the compensation stage, when the charging time of the driving transistor is 50 μs, when the reset voltage increases from 1.2 V to 1.4 V, the voltage value Vs of the second end of the driving transistor increases from 1.711 V to 1.739 V, and the stable driving current in the light-emitting stage decreases from 72.4 nA to 70.3 nA. When the reset voltage increases from 1.4 V to 1.6 V, the voltage value of the second end of the driving transistor increases from 1.739 V to 1.784 V, and the stable driving current in the light-emitting stage decreases from 70.3 nA to 67.3 nA. As can be seen, increasing the reset voltage can effectively inhibit the increase of the driving current in the light-emitting stage.

[0308] Table 1

[0309] FIG. 28 is a schematic view of the luminance of the light-emitting element varying with the gray scale in at least one embodiment of the present disclosure.

[0310] For example, as shown in FIG. 28, the curve L1 represents the variation curve between the luminance and the gray scale of the light-emitting element at 300 C; the curve L2 and the curve L3 represent the variation curves between the luminance and the gray scale of the light-emitting element at 500 C, and the reset voltage value corresponding to the curve L1 is equal to the reset voltage value corresponding to the curve L2, and both are less than the reset voltage value corresponding to the curve L3.

[0311] For example, as shown in FIG. 28, by comparing the curve L1 with the curve L2, it can be seen that when the temperature of the pixel circuit increases from 300 C to 500 C, the luminance of the light-emitting element at the same gray scale deviates obviously, that is, the luminance of the light-emitting element at 500 C is greater than that at 300 C. By comparing the curve L1 with the curve L3, it can be seen that when the temperature of the pixel circuit increases from 300 C to 500 C, by increasing the reset voltage, the luminance deviation of the pixel circuit at 300 C and 500 C can be reduced, which is beneficial to the uniformity of the luminance of the light-emitting element.

[0312] For example, when the temperature or the driving current of the pixel circuit changes is monitored by the detection means, the size of the reset signal can be changed to keep the driving current to a reasonable value, so as to reduce the influence of temperature change.

[0313] For example, the pixel circuit corresponds to a plurality of display frame periods, and each display frame period at least includes a reset phase, a compensation phase, a data writing phase and a light emitting phase described in the embodiments of the present disclosure. For example, in some embodiments, one display frame period can include at least one refresh frame, for example, can include a plurality of refresh frames, but the embodiments of the present disclosure are not limited thereto. For example, the reset phase, the compensation phase, the data writing phase and the light emitting phase in the embodiments of the present disclosure are all located in the refresh frame. For example, in another embodiment, one display frame period can include at least one refresh frame and at least one holding frame. For example, the holding frame can include a holding reset phase, a holding stress applying phase and a holding light emitting phase.

[0314] For example, in the case that the display frame period only has a plurality of refresh frames without holding frames, the driving mode of the display panel using the pixel circuit is a high refresh driving mode, for example, the refresh frequency thereof is above 120Hz. For example, in the case that the display frame period has a plurality of refresh frames and at least one holding frame, the plurality of refresh frames and the at least one holding frame are arranged alternately, and the driving mode of the display panel using the pixel circuit is a low refresh driving mode. For example, the duration of the holding frame can be 1 / 2, 1 / 3, 1 / 10, 1 / 20, 1 / 30 or 1 / 60 of the duration of the refresh frame, and the embodiments of the present disclosure are not limited thereto.

[0315] For example, in at least one embodiment of the present disclosure, the first reset signal is adjusted to the second reset signal in a reset signal adjusting period. For example, the reset signal adjusting period can be located between two adjacent display frame periods, so that the second reset signal can be written before the next display frame period starts, and the value of the second reset signal remains Vini2 in the next display frame period, and after a certain charging time, the voltage value of the first electrode of the driving transistor is Vs2, and Vs2 is greater than the voltage value Vs1 of the first electrode of the driving transistor corresponding to the first reset signal.

[0316] For example, in at least one embodiment of the present disclosure, the reset signal adjusting period is located within one display frame period, and the reset signal adjusting period can at least partially overlap with any one of the reset stage, the compensation stage, the data writing stage, and the light emitting stage. For example, the reset signal adjusting period can at least partially overlap with the reset stage within one display frame period. For example, in a part of the reset stage (e.g., the second sub-reset stage in the foregoing embodiment), the value of the reset signal is equal to the value Vini1 of the first reset signal, and in another part of the reset stage (e.g., the third sub-reset stage in the foregoing embodiment), the reset signal is adjusted to the second reset signal whose value is equal to the value Vini2 of the second reset signal. Thus, through the reset signal adjusting period, the voltage value of the first electrode of the driving transistor is adjusted from Vs1 to Vs2, and Vs2 is greater than Vs1.

[0317] For example, in at least one embodiment of the present disclosure, the reset signal adjusting period is located within one display frame period, and the reset signal adjusting period can at least partially overlap with any one of the reset stage, the compensation stage, the data writing stage, and the light emitting stage. For example, the reset signal adjusting period can at least partially overlap with the reset stage within one display frame period. For example, in a part of the reset stage (e.g., the second sub-reset stage in the foregoing embodiment), the value of the reset signal is equal to the value Vini1 of the first reset signal, and in another part of the reset stage (e.g., the third sub-reset stage in the foregoing embodiment), the reset signal is adjusted to the second reset signal whose value is equal to the value Vini2 of the second reset signal. Thus, through the reset signal adjusting period, the voltage value of the first electrode of the driving transistor is adjusted from Vs1 to Vs2, and Vs2 is greater than Vs1.

[0318] FIG. 29 is a schematic diagram of the change of the reset voltage with temperature in at least one embodiment of the present disclosure.

[0319] For example, in some embodiments of the present disclosure, the area of the light emitting region of the light emitting element is different, and the parasitic capacitance of the light emitting element itself is different. For example, when the light emitting region of the light emitting element is larger, the parasitic capacitance of the light emitting element itself is larger. For example, for some display panel, the display panel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel is configured to emit red light, the second sub-pixel is configured to emit green light, and the third sub-pixel is configured to emit blue light. The light emitting region of the light emitting element of the first sub-pixel has a first light emitting area, the light emitting region of the light emitting element of the second sub-pixel has a second light emitting area, the light emitting region of the light emitting element of the third sub-pixel has a third light emitting area, and the first light emitting area is smaller than the second light emitting area, and the second light emitting area is smaller than the third light emitting area. The first parasitic capacitance of the light emitting element of the first sub-pixel is smaller than the second parasitic capacitance of the light emitting element of the second sub-pixel, and the second parasitic capacitance of the light emitting element of the second sub-pixel is smaller than the third parasitic capacitance of the light emitting element of the third sub-pixel.

[0320] For example, when the reset voltages of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all equal to the value Vini1 of the first reset signal when the three sub-pixels are in the reset stage, and the driving currents are all the same, when the temperature of the pixel circuit of the three sub-pixels rises from the first display temperature to the second display temperature, the first electrode and the second electrode of the light emitting element of the first sub-pixel have a first voltage rise amount, the first electrode and the second electrode of the light emitting element of the second sub-pixel have a second voltage rise amount, the first electrode and the second electrode of the light emitting element of the third sub-pixel have a third voltage rise amount, and the first voltage rise amount is greater than the second voltage rise amount, and the second voltage rise amount is greater than the third voltage rise amount. Therefore, the first current increase amount of the driving current of the light emitting element of the first sub-pixel is greater than the second current increase amount of the driving current of the light emitting element of the second sub-pixel, and the second current increase amount of the driving current of the light emitting element of the second sub-pixel is greater than the current increase amount of the driving current of the light emitting element of the third sub-pixel.

[0321] In order to balance the influence of the temperature rise on the driving current, the value of the reset signal received by the first sub-pixel, the second sub-pixel and the third sub-pixel is respectively increased, and the increase amount of the reset signal corresponding to the first sub-pixel is greater than the increase amount of the reset signal corresponding to the second sub-pixel, and the increase amount of the reset signal corresponding to the second sub-pixel is greater than the increase amount of the reset signal corresponding to the third sub-pixel, so that the gate-source voltage in the pixel circuit of the first sub-pixel is reduced by a greater amount than the gate-source voltage in the pixel circuit of the second sub-pixel, and the gate-source voltage in the pixel circuit of the second sub-pixel is reduced by a greater amount than the gate-source voltage in the pixel circuit of the third sub-pixel. Accordingly, the driving current of the first sub-pixel is reduced by a greater amount than the driving current of the second sub-pixel, and the driving current of the second sub-pixel is reduced by a greater amount than the driving current of the third sub-pixel, so that the driving current of each sub-pixel is in a stable state.

[0322] Therefore, when the light emitting areas of the light emitting elements of the plurality of pixel circuits are not the same, and when the temperature of the pixel current rises, by increasing the value of the reset signal corresponding to the light emitting element with a smaller light emitting area by a greater amount, the influence of the temperature rise on the driving current can be balanced.

[0323] For example, in some embodiments of the present disclosure, the display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the first sub-pixel is configured to emit red light, the second sub-pixel is configured to emit green light, and the third sub-pixel is configured to emit blue light. The light emitting element of the first sub-pixel has a first light emitting efficiency, the light emitting element of the second sub-pixel has a second light emitting efficiency, the light emitting element of the third sub-pixel has a third light emitting efficiency, and the first light emitting efficiency is greater than the second light emitting efficiency, and the second light emitting efficiency is greater than the third light emitting efficiency.

[0324] For example, when the reset voltages of the first sub-pixel, the second sub-pixel and the third sub-pixel in the reset stage are all equal to the value Vini1 of the first reset signal, and the driving currents are all the same, when the temperature of the pixel circuit of the three sub-pixels rises from a first display temperature to a second display temperature, in order to ensure that the light emitting brightness does not change, the voltage increase required by the light emitting element of the first sub-pixel is less than the voltage increase required by the light emitting element of the second sub-pixel, and the voltage increase required by the light emitting element of the second sub-pixel is less than the voltage increase required by the light emitting element of the third sub-pixel. Therefore, the increase amount of the driving current of the light emitting element of the first sub-pixel is less than the increase amount of the driving current of the light emitting element of the second sub-pixel, and the increase amount of the driving current of the light emitting element of the second sub-pixel is less than the increase amount of the driving current of the light emitting element of the third sub-pixel.

[0325] In order to balance the influence of the temperature rise on the driving current, the value of the reset signal received by the first, second and third sub-pixels is respectively increased, and the increase amount of the reset signal corresponding to the first sub-pixel is less than that of the reset signal corresponding to the second sub-pixel, and the increase amount of the reset signal corresponding to the second sub-pixel is less than that of the reset signal corresponding to the third sub-pixel, so that the decrease amount of the gate-source voltage in the pixel circuit of the first sub-pixel is less than that of the second sub-pixel, and the decrease amount of the gate-source voltage in the pixel circuit of the second sub-pixel is less than that of the third sub-pixel. Accordingly, the decrease amount of the driving current of the first sub-pixel is less than that of the second sub-pixel, and the decrease amount of the driving current of the second sub-pixel is less than that of the third sub-pixel, so that the driving current of each sub-pixel can be kept stable.

[0326] Therefore, when the light emitting efficiency of the light emitting element of the plurality of pixel circuits is different, and when the temperature of the pixel current rises, by increasing the value of the reset signal corresponding to the light emitting element with smaller light emitting efficiency, the influence of the temperature rise on the driving current can be balanced.

[0327] For example, as shown in FIG. 29, in some embodiments of the present disclosure, the first sub-pixel corresponds to the curve R, the second sub-pixel corresponds to the curve G, and the first sub-pixel corresponds to the curve B. On the one hand, since the first light emitting area corresponding to the first sub-pixel is smaller than the second light emitting area of the second sub-pixel, and the second light emitting area of the second sub-pixel is smaller than the third light emitting area. When the temperature rises, for example, from 300C to 600C, the reset voltage of the first sub-pixel is increased more than the reset voltage of the second sub-pixel and the reset voltage of the third sub-pixel. On the other hand, since the light emitting efficiency of the light emitting element of the third sub-pixel is lower than that of the light emitting element of the second sub-pixel, and the light emitting efficiency of the first sub-pixel is basically the same as that of the light emitting element of the second sub-pixel, when the temperature rises, the reset voltage of the third sub-pixel is increased more than the reset voltage of the second sub-pixel, so that the driving current of the sub-pixel emitting light of different colors can be kept stable.

[0328] For example, in some embodiments of the present disclosure, referring to FIG. 29, since the reset voltages of the first color sub-pixel and the third color sub-pixel are relatively close, the first color sub-pixel and the third color sub-pixel can correspond to the same reset voltage, and the second color sub-pixel corresponds to a reset voltage alone, so that the adjustment difficulty can be reduced.

[0329] FIG. 30 is a schematic diagram of the change of the reference voltage with temperature in at least one embodiment of the present disclosure.

[0330] For example, as shown in FIG. 4A, the value of the reference signal REF can also be adjustable, which can be a direct current signal or a non-direct current signal. For example, the reference signal REF can be a reference voltage Vref, and the method provided by the embodiment of the present disclosure for reducing the influence of temperature change on the luminance of the light-emitting element includes: as the ambient temperature of the pixel circuit increases, the reference voltage Vref decreases accordingly.

[0331] For example, as shown in FIG. 4A and FIG. 27, when the temperature of the pixel circuit increases, for example, from 00C to 300C, or from 300C to 600C, at this time, the reference voltage Vref can be increased, for example, from Vref1 to Vref2. For example, when the reset phase is completed, the driving transistor DT tends to be in the cut-off state, and therefore, the voltage value of the first electrode of the driving transistor DT decreases from Vref1-Vth to Vref2-Vth accordingly, so that the gate-source voltage Vgs of the driving transistor DT decreases, and the driving current in the light-emitting phase decreases.

[0332] Since the mobility of the driving transistor increases when the temperature of the pixel circuit increases, and the driving current also increases, by decreasing the reference voltage, the increase of the driving current can be inhibited, and the size of the driving current in the pixel circuit can be within a reasonable range, so that the driving current is more stable.

[0333] For example, in at least one embodiment of the present disclosure, the first power supply voltage can be a constant voltage or a non-constant voltage. For example, the value of the first power supply voltage can also be adjustable. For example, the power consumption can be reduced by reducing the first power supply voltage under the condition that the working needs of the pixel circuit are met.

[0334] For example, in at least one embodiment of the present disclosure, the second power supply voltage can be a constant voltage or a non-constant voltage. For example, the value of the second power supply voltage can also be adjustable. For example, the luminance adjustment of the light-emitting element can be adjusted by adjusting the second power supply voltage under the condition that the working needs of the pixel circuit are met.

[0335] The pixel circuit provided by at least one embodiment of the present disclosure also includes a driving circuit 100, a first compensation circuit 300, a light-emitting element 600, and a reset control circuit 780. That is, the pixel circuit can also not include the second light-emitting control circuit of the pixel circuit in the above-mentioned embodiments, and other structures and driving methods of the pixel circuit can be referred to the related descriptions of the above-mentioned embodiments, which will not be repeated here.

[0336] As shown in FIG. 1, the driving circuit 100 includes a control terminal 100m, a first terminal 100a and a second terminal 100b. The control terminal 100m of the driving circuit 100 is electrically connected with the first node N1. The first terminal 100a of the driving circuit 100 is electrically connected with the second node N2. The second terminal 100b of the driving circuit 100 is electrically connected with the third node N3. The driving circuit 100 is configured to control the size of the driving current flowing through the first terminal 100a and the second terminal 100b. For example, the driving current can be used to drive the light emitting element 600 to emit light. For example, in the light emitting stage, the driving circuit 100 can provide the driving current to the light emitting element 600 to drive the light emitting element 600 to emit light.

[0337] As shown in FIG. 1, the first compensation circuit 300 includes a control terminal 300m, a first terminal 300a, a second terminal 300b and a third terminal 300c. The control terminal 300m of the first compensation circuit 300 is configured to receive a first compensation control signal G2. The first terminal 300a of the first compensation circuit 300 is electrically connected with the reference signal terminal REF to receive the reference signal REF. The second terminal 300b of the first compensation circuit 300 is electrically connected with the second node N2. The third terminal 300c of the first compensation circuit 300 is electrically connected with the first node N1. The first compensation circuit 300 is configured to apply the reference signal REF to the control terminal 100m of the driving circuit 100 in response to the first compensation control signal G2. For example, the first compensation circuit 300 can include a first storage capacitor C1 (see FIG. 2). A first pole of the first storage capacitor C1 is electrically connected with the control terminal 100m of the driving circuit 100. A second pole of the first storage capacitor C1 is electrically connected with the first terminal 100a of the driving circuit 100. However, embodiments of the present disclosure are not limited thereto.

[0338] For example, as shown in FIG. 1, the light emitting element 600 includes a first electrode 600a and a second electrode 600b. The first electrode 600a of the light emitting element 600 is electrically connected with the first terminal 100a of the driving circuit 100. The second electrode 600b of the light emitting element 600 is electrically connected with the second voltage terminal VSS to receive the second power voltage VSS. The light emitting element 600 is configured to emit light under the driving of the driving current. For example, the second voltage terminal VSS can be grounded, i.e., the second power voltage VSS can be 0V. For example, the second power voltage VSS can be a negative voltage. For example, the light emitting element 600 can be an organic light emitting diode (OLED). For example, the light emitting element 600 can also be other types of electroluminescent devices such as inorganic light emitting diodes, quantum dot light emitting elements, etc. Embodiments of the present disclosure do not limit the type of light emitting element.

[0339] As shown in FIG. 1, the reset control circuit 780 includes a control terminal 780m, a first terminal 780a, a second terminal 780b, and a third terminal 780c. The control terminal 780m of the reset control circuit 780 is configured to receive a reset control signal G3, the first terminal 780a of the reset control circuit 780 is electrically connected to the first terminal 100a of the driving circuit 100, the second terminal 780b of the reset control circuit 780 is electrically connected to the reset signal terminal VINI to receive the reset signal VINI, and the third terminal 780c of the reset control circuit 780 is electrically connected to the first electrode 600a of the light emitting element 600. The reset control circuit 780 is configured to apply the reset signal VINI to the first electrode 600a of the light emitting element 600 and / or the first terminal 100a of the driving circuit 100 in response to the reset control signal G3.

[0340] As shown in FIG. 1, the first terminal 780a of the reset control circuit 780 is electrically connected to the first terminal 100a of the driving circuit 100, and the second terminal 780b of the reset control circuit 780 is electrically connected to the reset signal terminal VINI. Thus, the reset signal from the reset signal terminal VINI needs to pass through the reset control circuit 780 before being applied to the first electrode 600a of the light emitting element 600 and / or the first terminal of the driving circuit 100. This can reduce the influence of the fluctuation of the reset signal on the voltage of the first electrode 600a of the light emitting element 600 and the first terminal 100a of the driving circuit 100, and reduce the risk of introducing noise to the pixel circuit 10. This can make the driving current more stable, thereby improving the display effect.

[0341] With the development of OLED display technology, oxide process is often used in OLED display products due to its high uniformity. The coupling effect of the partial capacitance of the pixel driving circuit made by the oxide process can introduce noise in the display stage, making the driving current output by the pixel driving circuit unstable, and affecting the reliability of the pixel driving circuit.

[0342] FIGS. 31-48 are schematic diagrams of other implementation examples of the pixel circuit shown in FIG. 1.

[0343] FIG. 31 is a structural schematic diagram of another pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG. 31, the pixel driving circuit provided by an embodiment of the present disclosure can include a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit.

[0344] For example, in some embodiments of the present disclosure, the driving circuit and the connection relationship in FIG. 1 correspond to the driving sub-circuit in FIG. 31 and subsequent embodiments; the data writing circuit and the first compensation circuit and the connection relationship in FIG. 1 correspond to the first control sub-circuit and the storage sub-circuit in FIG. 31 and subsequent embodiments; the first light emitting control circuit and the second light emitting control circuit in FIG. 1 correspond to the second control sub-circuit in FIG. 31 and subsequent embodiments; the light emitting element in FIG. 1 corresponds to the light emitting device in FIG. 31 and subsequent embodiments; the reset control circuit and the connection relationship in FIG. 1 correspond to the third control sub-circuit in FIG. 31 and subsequent embodiments.

[0345] As shown in FIG. 31, the driving sub-circuit is electrically connected with the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving current to the third node N3 under the control of signals of the first node N1 and the second node N2; the first control sub-circuit is electrically connected with the first scan signal line G1, the second scan signal line G2, the data signal line Data, the reference signal line REF and the first node N1 respectively, and is configured to provide a signal of the data signal line Data or the reference signal line REF to the first node N1 under the control of signals of the first scan signal line G1 and the second scan signal line G2; the second control sub-circuit is electrically connected with the first light emitting signal line EM1, the second light emitting signal line EM2, the first power supply line VDD, the second node N2, the third node N3 and the fourth node N4 respectively, and is configured to provide a signal of the first power supply line VDD to the second node N2 and a signal of the third node N3 to the fourth node N4 under the control of signals of the first light emitting signal line EM1 and the second light emitting signal line EM2; the third control sub-circuit is electrically connected with the first reset signal line Reset1, the auxiliary signal line VX and the third node N3 respectively, and is configured to control the signal of the third node N3 under the control of a signal of the first reset signal line Reset1 and the driving of a signal of the auxiliary signal line VX; the storage sub-circuit is electrically connected with the first node N1 and the third node N3 respectively, and is configured to store a voltage difference of the signal between the first node N1 and the third node N3.

[0346] In an exemplary embodiment, as shown in FIG. 31, the pixel driving circuit is electrically connected with the light emitting device L through the fourth node N4.

[0347] In an exemplary embodiment, the light emitting device L can include a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked. Exemplarily, the anode of the light emitting device L is electrically connected with the fourth node N4, and the cathode of the light emitting device L is electrically connected with the second power supply line VSS.

[0348] In an example embodiment, the light emitting device L can include a current driven device, and can employ a current type light emitting diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED) or a Quantum Light Emitting Diode (QLED). A typical size (e.g., length) of a Micro LED can be less than 100 pm, such as 10 pm to 50 pm. A typical size (e.g., length) of a Mini LED can be about 100 pm to 300 pm, such as 120 pm to 260 pm.

[0349] In an example embodiment, the organic light emitting layer can include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Block Layer (EBL), an Emitting Layer (EML), a Hole Block Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked. In an example embodiment, the HIL of all sub-pixels can be a common layer connected together, the EIL of all sub-pixels can be a common layer connected together, the HTL of all sub-pixels can be a common layer connected together, the ETL of all sub-pixels can be a common layer connected together, the HBL of all sub-pixels can be a common layer connected together, the EML of adjacent sub-pixels can have a small amount of overlap or can be isolated, and the EBL of adjacent sub-pixels can have a small amount of overlap or can be isolated.

[0350] In an example embodiment, the first power line VDD continuously provides a high level signal, and the signal of the first power line VDD is a direct current signal.

[0351] In an example embodiment, the second power line VSS continuously provides a low level signal, and the signal of the second power line VSS is a direct current signal.

[0352] In an example embodiment, the reference signal line REF continuously provides a low-level signal, and the signal of the reference signal line REF is a direct current signal. For example, the voltage of the signal of the reference signal line REF can be 0V.

[0353] In an example embodiment, the pixel driving circuit is located in a display substrate, and the content displayed by the display substrate includes a plurality of display frames. In any display frame, the signal of the first scan signal line G1 is a pulse signal, and the signal of the second scan signal line G2 is a pulse signal. The time period during which the second scan signal line G2 is an active level signal occurs before the time period during which the first scan signal line G1 is an active level signal.

[0354] The pixel driving circuit provided by the embodiments of the present disclosure includes a driving sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a storage sub-circuit. The driving sub-circuit is electrically connected to a first node, a second node, and a third node, and is configured to provide a driving current to the third node under the control of the signals of the first node and the second node. The first control sub-circuit is electrically connected to a first scan signal line, a second scan signal line, a data signal line, a reference signal line, and the first node, and is configured to provide the signal of the data signal line or the reference signal line to the first node under the control of the signals of the first scan signal line and the second scan signal line. The second control sub-circuit is electrically connected to a first emission signal line, a second emission signal line, a first power supply line, the second node, the third node, and a fourth node, and is configured to provide the signal of the first power supply line to the second node and the signal of the third node to the fourth node under the control of the signals of the first emission signal line and the second emission signal line. The third control sub-circuit is electrically connected to a first reset signal line, an auxiliary signal line, and the third node, and is configured to control the signal of the third node under the control of the signal of the first reset signal line and the signal of the auxiliary signal line. The storage sub-circuit is electrically connected to the first node and the third node, and is configured to store the voltage difference between the signals of the first node and the third node. The third control sub-circuit can control the signal of the third node through the signals of the first reset signal line and the auxiliary signal line, so as to avoid introducing noise in the display stage, maintain the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0355] In an example embodiment, the working process of the pixel driving circuit includes a display stage, and the display stage includes a writing stage and an emission stage. The emission stage occurs after the writing stage, and the signal of the first scan signal line G1 is an active level signal in the writing stage. The signals of the first emission signal line EM1 and the second emission signal line EM2 are active level signals in the emission stage, and the writing stage occurs in a writing time period.

[0356] Fig. 32 is an equivalent circuit diagram I including the third control sub-circuit shown in Fig. 31. As shown in Fig. 32, in an exemplary embodiment, the third control sub-circuit can also be electrically connected with the third reset signal line Reset3 and the initial signal line INIT respectively, and configured to provide the signal of the initial signal line to the fourth node N4 under the control of the signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit can include a sixth transistor T6, an eighth transistor T8 and a second capacitor C2. Wherein, the control electrode of the sixth transistor T6 is electrically connected with the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected with the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the first end of the second capacitor C2 is electrically connected with the fifth node N5, and the second end of the second capacitor C2 is electrically connected with the third node N3; the first electrode of the eighth transistor T8 is electrically connected with the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4.

[0357] In an exemplary embodiment, as shown in Fig. 32, the signal of the auxiliary signal line VX is a non-DC signal, and is electrically connected with the fourth node N4.

[0358] For example, in some embodiments, as shown in Fig. 32, the signal value of the initial signal line INIT is adjustable to reduce the influence of temperature change on the size of the driving current. For the adjustment mode of the signal value of the initial signal line INIT, please refer to the adjustment mode of the value of the reset signal in the above-mentioned embodiments, which will not be repeated here.

[0359] In an exemplary embodiment, as shown in Fig. 32, through the part of time period in which the signal of the third reset signal line Reset3 is an effective level signal, and the signal of the second emission signal line EM2 is an effective level signal, the present disclosure can reset the third node N3 and the fourth node N4 before the write time period, and can ensure the display uniformity of the pixel driving circuit. Through making the signal of the first reset signal line Reset1 and the second emission signal line EM2 be an effective level signal in at least part of the time period after the write time period, the present disclosure can make the voltage value of the signals at both ends of the second capacitor C2 be the same in the emission stage, avoid the influence of the second capacitor C2 on the third node N3 in the emission stage, avoid introducing noise at the third node N3, can maintain the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0360] Fig. 33 is a second equivalent circuit diagram of the third control sub-circuit shown in Fig. 31. As shown in Fig. 33, in an exemplary embodiment, the third control sub-circuit, which can also be electrically connected to the second reset signal line Reset2, is configured to provide the signal of the fifth node N5 to the third node N3 under the control of the signal of the second reset signal line Reset2. Exemplarily, the third control sub-circuit can include a sixth transistor T6, a seventh transistor T7, and a second capacitor C2. The first electrode of the sixth transistor T6 is electrically connected to the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset3, the first electrode of the seventh transistor T7 is electrically connected to the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3. The first end of the second capacitor C2 is electrically connected to the fifth node N5, and the second end of the second capacitor C2 is electrically connected to the third node N3.

[0361] In an exemplary embodiment, as shown in Fig. 33, the signal of the auxiliary signal line VX can be a direct current signal, and can be the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD.

[0362] For example, in some embodiments, as shown in Fig. 33, the signal value of the auxiliary signal line VX is adjustable to reduce the influence of temperature change on the size of the driving current. For the adjustment mode of the signal value of the auxiliary signal line VX, please refer to the adjustment mode of the value of the reset signal in the above-mentioned embodiments, which will not be repeated here.

[0363] In an exemplary embodiment, as shown in Fig. 33, by making the signals of the second reset signal line Reset2 and the second emission signal line EM2 be valid level signals during the part of the time period in which the signal of the first reset signal line Reset1 is a valid level signal, the present disclosure can reset the third node N3 and the fourth node N4 before the write-in time period, and can ensure the display uniformity of the pixel driving circuit. By making the second reset signal line Reset2 be a valid level signal during at least part of the time period after the write-in time period, the present disclosure can make the voltage values of the signals at both ends of the second capacitor C2 be the same during the emission stage, avoid the influence of the second capacitor C2 on the third node N3 during the emission stage, avoid introducing noise during the display stage, maintain the stability of the driving current output by the pixel driving circuit, and improve the reliability of the pixel driving circuit.

[0364] Fig. 34 is an equivalent circuit diagram three including the third control sub-circuit shown in Fig. 31, and Fig. 35 is an equivalent circuit diagram four including the third control sub-circuit shown in Fig. 31. In an exemplary embodiment, as shown in Fig. 34 and Fig. 35, the third control sub-circuit can also be electrically connected with a third reset signal line Reset3 and an initial signal line INIT respectively, and configured to provide the signal of the initial signal line to the fourth node N4 under the control of the signal of the third reset signal line Reset3. Exemplarily, the third control sub-circuit can further include an eighth transistor T8, the control electrode of the eighth transistor T8 is electrically connected with the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected with the initial signal line, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4.

[0365] In an exemplary embodiment, the signal of the auxiliary signal line VX is a direct current signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF and the first power supply line VDD; or the signal of the auxiliary signal line VX is an alternating current signal, and the signal of the auxiliary signal line VX is electrically connected with the fourth node N4. Fig. 34 is an example in which the signal of the auxiliary signal line VX is a direct current signal, and Fig. 35 is an example in which the signal of the auxiliary signal line VX is an alternating current signal.

[0366] For example, in some embodiments, as shown in Fig. 34, the signal value of the auxiliary signal line VX is the same as the signal value of the initial signal line VINI, and the signal value of the initial signal line VINI is adjustable to reduce the influence of temperature change on the size of the driving current. For the adjustment mode of the signal value of the initial signal line VINI, please refer to the adjustment mode of the value of the reset signal in the above-mentioned embodiments, which will not be repeated here.

[0367] For example, in some embodiments, as shown in Fig. 35, the signal value of the initial signal line VINI is adjustable to reduce the influence of temperature change on the size of the driving current. For the adjustment mode of the signal value of the initial signal line VINI, please refer to the adjustment mode of the value of the reset signal in the above-mentioned embodiments, which will not be repeated here.

[0368] In the example embodiment, as shown in FIGS. 34 and 35, when the signal of the first reset signal line Reset1 is a valid level signal, the signal of the third reset signal line is a valid level signal, and the signal of the second reset signal line is an invalid level signal, and when the signal of the second reset signal line is a valid level signal, the signal of the first reset signal line is an invalid level signal, the signal of the third reset signal line Reset3 is a valid level signal in part of the time period, and the signal of the second emission signal line EM2 is a valid level signal, the third node N3 and the fourth node N4 can be reset before the write time period, and the display uniformity of the pixel driving circuit can be ensured. The signal of the second reset signal line Reset2 is a valid level signal in at least part of the time period after the write time period, the voltage value of the signal at both ends of the second capacitor C2 in the light emitting stage is the same, the influence of the second capacitor C2 on the third node N3 in the light emitting stage is avoided, noise is not introduced in the display stage, the stability of the driving current output by the pixel driving circuit can be maintained, and the reliability of the pixel driving circuit is improved.

[0369] FIG. 36 is an equivalent circuit diagram five including the third control sub-circuit shown in FIG. 31, and FIG. 37 is an equivalent circuit diagram six including the third control sub-circuit shown in FIG. 31. In the example embodiment, as shown in FIGS. 36 and 37, the third control sub-circuit can also be electrically connected with the third reset signal line Reset3 and the initial signal line INIT respectively, and configured to provide the signal of the initial signal line to the fourth node N4 under the control of the signal of the third reset signal line Reset3. For example, the third control sub-circuit can further include a sixth transistor T6, an eighth transistor T8, and a second capacitor C2. The control electrode of the sixth transistor T6 is electrically connected with the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected with the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected with the third node N3. The control electrode of the eighth transistor T8 is electrically connected with the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected with the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4. The first end of the second capacitor C2 is electrically connected with the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected with the fifth node N5.

[0370] In the example embodiment, the signal of the auxiliary signal line VX is a direct current signal, and the signal of the auxiliary signal line VX is the same as the signal of any one of the initial signal line, the reference signal line REF, and the first power supply line VDD. Alternatively, the signal of the auxiliary signal line VX is an alternating current signal, and the signal of the auxiliary signal line VX is electrically connected with the fourth node N4. FIG. 36 is an example in which the signal of the auxiliary signal line VX is a direct current signal, and FIG. 37 is an example in which the signal of the auxiliary signal line VX is an alternating current signal.

[0371] For example, in some embodiments, as shown in FIG. 36, the signal value of the auxiliary signal line VX is the same as the signal value of the initial signal line VINI, and the signal value of the initial signal line VINI is adjustable to reduce the influence of temperature change on the size of the driving current. For the adjustment manner of the signal value of the initial signal line VINI, please refer to the adjustment manner of the value of the reset signal in the above-mentioned embodiments, which will not be repeated here.

[0372] For example, in some embodiments, as shown in FIG. 37, the signal value of the initial signal line VINI is adjustable to reduce the influence of temperature change on the size of the driving current. For the adjustment manner of the signal value of the initial signal line VINI, please refer to the adjustment manner of the value of the reset signal in the above-mentioned embodiments, which will not be repeated here.

[0373] In the exemplary embodiments, as shown in FIG. 36 and FIG. 37, the display uniformity of the pixel driving circuit can be ensured by resetting the third node N3 and the fourth node N4 before the write time period through the part of time period in which the signal of the third reset signal line Reset3 is the active level signal and the signal of the second emission signal line EM2 is the active level signal. The stability of the driving current output by the pixel driving circuit can be maintained, and the reliability of the pixel driving circuit can be improved by avoiding the introduction of noise in the display stage through the part of time period in which the first reset signal line Reset1 is the inactive level signal after the write time period, so that the second capacitor C2 will not cause the influence on the third node N3.

[0374] In the exemplary embodiments, the initial signal line INIT continuously provides the low level signal, and the signal of the initial signal line INIT is the direct current signal.

[0375] In the exemplary embodiments, the voltage value of the signal of the initial signal line INIT can be less than the voltage value of the signal of the second power supply line VSS, the mis-emission of the light emitting device L can be avoided, and the reliability of the pixel driving circuit can be improved.

[0376] Only six exemplary structures of the third control sub-circuit are shown in FIG. 32 to FIG. 37, and those skilled in the art can easily understand that the implementation manner of the third control sub-circuit is not limited thereto.

[0377] FIG. 38 is a partial equivalent circuit diagram of another pixel driving circuit provided by the embodiments of the present disclosure. As shown in FIG. 38, in an exemplary implementation, the first control sub-circuit can include a first transistor T1 and a second transistor T2, the driving sub-circuit can include a third transistor T3, the second control sub-circuit can include a fourth transistor T4 and a fifth transistor T5, and the storage sub-circuit can include a first capacitor C1. Wherein, the control electrode of the first transistor T1 is electrically connected with the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected with the data signal line Data, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected with the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first emission signal line EM1, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the second emission signal line EM2, the first electrode of the fifth transistor T5 is electrically connected with the third node N3, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the third node N3.

[0378] Only one exemplary structure of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit is shown in FIG. 38, and those skilled in the art can easily understand that the implementation mode of the driving sub-circuit, the first control sub-circuit, the second control sub-circuit and the storage sub-circuit is not limited thereto.

[0379] In the example embodiment, FIG. 39 is an equivalent circuit diagram one of the pixel driving circuit shown in FIG. 38, FIG. 40 is an equivalent circuit diagram two of the pixel driving circuit shown in FIG. 38, FIG. 41 is an equivalent circuit diagram three of the pixel driving circuit shown in FIG. 38, and FIG. 42 is an equivalent circuit diagram four of the pixel driving circuit shown in FIG. 38. As shown in FIGS. 39 to 42, in the example embodiment, the first control sub-circuit in the pixel driving circuit includes the first transistor T1 and the second transistor T2, the driving sub-circuit includes the third transistor T3, the second control sub-circuit includes the fourth transistor T4 and the fifth transistor T5, the storage sub-circuit includes the first capacitor C1, the third control sub-circuit includes the second capacitor C2 and the sixth transistor T6, and the third control sub-circuit further includes at least one of the seventh transistor T7 and the eighth transistor T8. Wherein, the control electrode of the first transistor T1 is electrically connected with the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected with the data signal line Data, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected with the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first emission signal line EM1, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the second emission signal line EM2, the first electrode of the fifth transistor T5 is electrically connected with the third node N3, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected with the auxiliary signal line VX, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected with the fifth node N5, and the second electrode of the seventh transistor T7 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected with the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the third node N3; the first end of the second capacitor C2 is electrically connected with the fifth node N5, and the second end of the second capacitor C2 is electrically connected with the third node N3.FIGS. 39 and 40 are diagrams illustrating the third control sub-circuit further including the seventh transistor T7 and the eighth transistor T8, FIG. 41 is a diagram illustrating the third control sub-circuit further including the seventh transistor T7, and FIG. 42 is a diagram illustrating the third control sub-circuit further including the eighth transistor T8.

[0380] In the exemplary embodiments, as shown in FIGS. 39 and 40, the third control sub-circuit further includes the seventh transistor T7 and the eighth transistor T8. The signal of the auxiliary signal line VX in the pixel driving circuit can be a direct current signal, or can be a non-direct current signal. FIG. 39 is a diagram illustrating that the signal of the auxiliary signal line VX in the pixel driving circuit is a direct current signal, and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD. FIG. 40 is a diagram illustrating that the signal of the auxiliary signal line VX in the pixel driving circuit is a non-direct current signal, and is electrically connected to the fourth node N4.

[0381] In the exemplary embodiments, as shown in FIG. 41, the third control sub-circuit further includes the seventh transistor T7. The signal of the auxiliary signal line VX in the pixel driving circuit is a direct current signal, and is the same as the signal of any one of the initial signal line, the reference signal line, and the first power supply line.

[0382] In the exemplary embodiments, as shown in FIG. 42, the third control sub-circuit further includes the eighth transistor T8. The signal of the auxiliary signal line VX in the pixel driving circuit is a non-direct current signal, and is electrically connected to the fourth node N4.

[0383] In the exemplary embodiments, any one of the first transistor T1 to the eighth transistor T8 can be an oxide thin film transistor. The active layer of the oxide thin film transistor uses an oxide semiconductor (Oxide). The oxide thin film transistor has the advantage of low leakage current.

[0384] In the exemplary embodiments, any one of the first transistor T1 to the eighth transistor T8 is an N-type transistor.

[0385] In the example embodiment, FIG. 43 is an equivalent circuit diagram five of the pixel driving circuit shown in FIG. 38, and FIG. 44 is an equivalent circuit diagram six of the pixel driving circuit shown in FIG. 38. As shown in FIG. 43 and FIG. 44, the first control sub-circuit in the pixel driving circuit can include the first transistor T1 and the second transistor T2, the driving sub-circuit can include the third transistor T3, the second control sub-circuit can include the fourth transistor T4 and the fifth transistor T5, the storage sub-circuit can include the first capacitor C1, and the third control sub-circuit can include the second capacitor C2, the sixth transistor T6 and the eighth transistor T8. Wherein, the control electrode of the first transistor T1 is electrically connected with the first scan signal line G1, the first electrode of the first transistor T1 is electrically connected with the data signal line Data, and the second electrode of the first transistor T1 is electrically connected with the first node N1; the control electrode of the second transistor T2 is electrically connected with the second scan signal line G2, the first electrode of the second transistor T2 is electrically connected with the reference signal line REF, and the second electrode of the second transistor T2 is electrically connected with the first node N1; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first emission signal line EM1, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VDD, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the second emission signal line EM2, the first electrode of the fifth transistor T5 is electrically connected with the third node N3, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the first reset signal line Reset1, the first electrode of the sixth transistor T6 is electrically connected with the fifth node N5, and the second electrode of the sixth transistor T6 is electrically connected with the third node N3; the control electrode of the eighth transistor T8 is electrically connected with the third reset signal line Reset3, the first electrode of the eighth transistor T8 is electrically connected with the initial signal line INIT, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the third node N3; the first end of the second capacitor C2 is electrically connected with the auxiliary signal line VX, and the second end of the second capacitor C2 is electrically connected with the fifth node N5.

[0386] In the exemplary embodiments, as shown in FIGS. 43 and 44, the third control sub-circuit includes the sixth transistor T6, the eighth transistor T8, and the auxiliary signal line VX in the pixel driving circuit of the second capacitor C2. The signal of the auxiliary signal line VX in the pixel driving circuit can be a direct current signal or a non-direct current signal. FIG. 43 illustrates an example in which the signal of the auxiliary signal line VX in the pixel driving circuit is a direct current signal and is the same as the signal of any one of the initial signal line INIT, the reference signal line REF, and the first power supply line VDD. FIG. 44 illustrates an example in which the signal of the auxiliary signal line VX in the pixel driving circuit is a non-direct current signal and is electrically connected to the fourth node N4.

[0387] In the exemplary embodiments, any one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 can be an oxide thin film transistor. The active layer of the oxide thin film transistor is an oxide semiconductor. The oxide thin film transistor has the advantage of low leakage current.

[0388] In the exemplary embodiments, any one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 is an N-type transistor.

[0389] In the exemplary embodiments, the number of the first transistor T1, the second transistor T2, and the fourth transistor T4 in the pixel driving circuit provided in FIGS. 39 to 44 can be at least one.

[0390] In the exemplary embodiments, when the number of the first transistor T1 can be at least two, the control electrodes of all the first transistors are electrically connected to the first scan signal line, at least two first transistors are connected in series, the first electrode of the first first transistor is electrically connected to the data signal line, and the second electrode of the last first transistor is electrically connected to the first node N1.

[0391] In the exemplary embodiments, when the number of the second transistor T2 can be at least two, the control electrodes of all the second transistors T2 are electrically connected to the second scan signal line, at least two second transistors are connected in series, the first electrode of the first second transistor is electrically connected to the reference signal line, and the second electrode of the last second transistor is electrically connected to the second node N2.

[0392] FIG. 45 is a timing diagram of the pixel driving circuit provided in FIGS. 39 and 40. The working process of the pixel driving circuit illustrated in FIGS. 39 and 40 is described below. The pixel driving circuit in FIGS. 39 and 40 includes eight transistors (the first transistor T1 to the eighth transistor T8) and two capacitors (the first capacitor C1 and the second capacitor C2), and the eight transistors are N-type transistors.

[0393] In the example embodiment, the working process of the pixel driving circuit provided in FIGS. 39 and 40 can include:

[0394] In the first stage P1, referred to as the first reset stage, the signals of the second scan signal line G2, the second emission signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high level signals, and the signals of the first scan signal line G1, the first emission signal line EM1 and the second reset signal line Reset2 are low level signals. The signal of the second scan signal line G2 is a high level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is written to the second node N2, the signal of the second node N2 is initialized (reset), and the original charge in the second node N2 is cleared. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is written to the fifth node N5, the signal of the fifth node N5 is initialized (reset), and the original charge in the fifth node N5 is cleared. The signals of the second emission signal line EM2 and the third reset signal line Reset3 are high level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, and the signal of the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively. Since the voltage value of the signal of the first node N1 and the voltage value of the signal of the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on at this time, and the signal of the initial signal line INIT is written to the second node N2, the signals of the second node N2, the third node N3 and the fourth node N4 are initialized (reset), and the original charge in the second node N2, the third node N3 and the fourth node N4 is cleared. The signals of the first scan signal line G1, the first emission signal line EM1 and the second reset signal line Reset2 are low level signals, and the first transistor T1, the fourth transistor T4 and the seventh transistor T7 are disconnected. In this stage, the light emitting device L does not emit light.

[0395] In the second stage P2, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first emitting signal line EM1 are high level signals, and the signals of the second reset signal line Reset2, the first scan signal line G1 and the second emitting signal line EM2 are low level signals. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written into the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the second scan signal line G2 is a high level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is continuously provided to the second node N2, the signal of the first emitting signal line EM1 is a high level signal, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written into the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3, until the voltage V3 of the signal of the third node N3 is Vref-Vth, Vref is the voltage value of the signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth of the signals of the first node N1 and the third node N3. The signals of the second reset signal line Reset2, the first scan signal line G1 and the second emitting signal line EM2 are low level signals, and the first transistor T1, the fifth transistor T5 and the seventh transistor are disconnected. In this stage, the light emitting device L does not emit light.

[0396] In the third stage P3, a data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3 and the first scan signal line G1 are high level signals, the signals of the second reset signal line Reset2, the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the data signal line Data outputs a data voltage. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is continuously written to the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written to the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the first scan signal line G1 is a high level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 is Vdata, Vdata is the data voltage of the data signal line, the signal of the first node N1 jumps from the voltage value in the present stage to the voltage value in the previous stage, and therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal of the third node N3 also jumps. At this time, the voltage value V3 of the signal of the third node N3 is Vref-Vth+(Vdata-Vref)*C1 / (C1+C2), wherein C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor. The signals of the second reset signal line Reset2, the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off. In the present stage, the light emitting device L does not emit light.

[0397] In the fourth stage P4, called the second reset stage, the second reset signal line Reset2, the third reset signal line Reset3 and the second emitting signal line EM2 are high level signals, and the first reset signal line Reset1, the first emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, the signal of the initial signal line INIT is continuously written to the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the second emitting signal line EM2 is a high level signal, the fifth transistor T5 is turned on, the voltage V3 of the signal of the third node N3 is Vinit, Vinit is the voltage value of the signal of the initial signal line, at this time, the first node N1 is pulled low under the action of the first capacitor C1, so that the voltage V1 of the signal of the first node N1 is Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit, the signal of the second reset signal line Reset2 is a high level signal, the seventh transistor T7 is turned on, and the voltages of the signals of the third node N3 and the fifth node N5 remain the same. The signal of the first reset signal line Reset1, the first emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are disconnected. In this stage, the light emitting device L does not emit light.

[0398] In the fifth stage P5, called the emitting stage, the signals of the second reset signal line Reset2, the first emitting signal line EM1 and the second emitting signal line EM2 are high level signals, and the signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signals of the first emitting signal line EM1 and the second emitting signal line Reset2 are high level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fourth transistor T4, the third transistor T3 and the fifth transistor T5, and drives the light emitting device L to emit light. The signal of the second reset signal line Reset2 is a high level signal, the seventh transistor T7 is turned on, and the voltages of the signals of the third node N3 and the fifth node N5 remain the same. The signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are disconnected. In this stage, the light emitting device L emits light.

[0399] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Since the voltage value of the signal of the first node is V1 = Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] + Vinit, the voltage value of the signal of the third node N3 is V3 = Vinit, and thus the driving current of the third transistor T3 is: I = K * (Vgs - Vth) 2 = K * [Vdata - [Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)] - Vth] 2 = K * [(C2 / (C1 + C2)) * (Vdata - Vref)] 2 .

[0400] wherein I is the driving current flowing through the third transistor T3, that is, the driving current of the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0401] As can be seen from the derivation of the above current formula, in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0402] FIG. 46 is a timing diagram of the pixel driving circuit provided in FIG. 41. The working process of the pixel driving circuit exemplified by FIG. 41 is described below, and the pixel driving circuit in FIG. 41 includes seven transistors (the first transistor T1 to the seventh transistor T7) and two capacitors (the first capacitor C1 and the second capacitor C2), and the seven transistors are all N-type transistors.

[0403] In the exemplary implementation, the working process of the pixel driving circuit provided in FIG. 41 can include:

[0404] In the first stage P1, referred to as the first reset stage, the signals of the second scan signal line G2, the second emission signal line EM2, the first reset signal line Reset1 and the second reset signal line Reset2 are high level signals, and the signals of the first scan signal line G1 and the first emission signal line EM1 are low level signals. The signal of the second scan signal line G2 is a high level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is written to the second node N2, the signal of the second node N2 is initialized (reset), and the original charge in the second node N2 is cleared. The signals of the first reset signal line Reset1, the second reset signal line Reset2 and the second emission signal line EM2 are high level signals, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned on, and the signal of the auxiliary signal line VX is sequentially written to the fifth node N5, the third node N3 and the fourth node N4, the signals of the third node N3, the fourth node N4 and the fifth node N5 are initialized (reset), and the original charge in the third node N3, the fourth node N4 and the fifth node N5 is cleared. The signals of the first scan signal line G1 and the first emission signal line EM1 are low level signals, and the first transistor T1 and the fourth transistor T4 are disconnected. In this stage, the light emitting device L does not emit light.

[0405] In the second stage P2, referred to as the threshold compensation stage, the signals of the first reset signal line Reset1, the second scan signal line G2 and the first emission signal line EM1 are high level signals, and the signals of the second reset signal line Reset2, the first scan signal line G1 and the second emission signal line EM2 are low level signals. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, and the signal of the auxiliary signal line VX is continuously written to the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the second scan signal line G2 is a high level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is continuously provided to the second node N2, the signal of the first emission signal line EM1 is a high level signal, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written to the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3, until the voltage V3 of the signal of the third node N3 is Vref-Vth, Vref is the voltage value of the signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth of the signals of the first node N1 and the third node N3. The signals of the second reset signal line Reset2, the first scan signal line G1 and the second emission signal line EM2 are low level signals, the first transistor T1, the fifth transistor T5 and the seventh transistor are disconnected. In this stage, the light emitting device L does not emit light.

[0406] In the third stage P3, a data writing stage, the signals of the first reset signal line Reset1 and the first scan signal line G1 are high level signals, the signals of the second reset signal line Reset2, the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the data signal line Data outputs a data voltage. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is continuously written to the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the first scan signal line G1 is a high level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 is Vdata, Vdata is the data voltage of the data signal line, the signal of the first node N1 jumps from the voltage value in the present stage to the voltage value in the previous stage, and thus the signal of the third node N3 also jumps under the action of the first capacitor C1 and the second capacitor C2. At this time, the voltage value V3 of the signal of the third node N3 is Vref-Vth+(Vdata-Vref)*C1 / (C1+C2), wherein C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor. The signals of the second reset signal line Reset2, the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 are turned off. In the present stage, the light emitting device L does not emit light.

[0407] In the fourth stage P4, a second reset stage, the signals of the second reset signal line Reset2 and the second emitting signal line EM2 are high level signals, and the signals of the first reset signal line Reset1, the first emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signal of the second emitting signal line EM2 is a high level signal, the fifth transistor T5 is turned on, the voltage V3 of the signal of the third node N3 is Vinit, Vinit is the voltage value of the signal of the initial signal line, at this time, the first node N1 is pulled down under the action of the first capacitor C1, the voltage V1 of the signal of the first node N1 is Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit, the signal of the second reset signal line Reset2 is a high level signal, the seventh transistor T7 is turned on, and the voltages of the signals of the third node N3 and the fifth node N5 are consistent. The signals of the first reset signal line Reset1, the first emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In the present stage, the light emitting device L does not emit light.

[0408] In the fifth stage P5, the signals of the second reset signal line Reset2, the first emission signal line EM1 and the second emission signal line EM2 are high level signals, and the signals of the first reset signal line Reset1, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signals of the first emission signal line EM1 and the second emission signal line Reset2 are high level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, the driving voltage output by the first power supply line VDD is provided to the first electrode of the light emitting device L through the turned-on fourth transistor T4, the third transistor T3 and the fifth transistor T5, the light emitting device L is driven to emit light, the signal of the second reset signal line Reset2 is a high level signal, the seventh transistor T7 is turned on, and the signals of the third node N3 and the fifth node N5 are consistent in voltage. The signals of the first reset signal line Reset1, the first scan signal line G1 and the second scan signal line G2 are low level signals, the first transistor T1, the second transistor T2 and the sixth transistor T6 are turned off, and in this stage, the light emitting device L emits light.

[0409] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Since the voltage value of the signal of the first node is V1=Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit, and the voltage value of the signal of the third node N3 is V3=Vinit, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]- Vth] 2 =K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0410] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0411] As can be seen from the derivation of the above current formula, in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0412] FIG. 47 is a timing diagram of the operation of the pixel driving circuit provided in FIG. 42. The operation of the pixel driving circuit provided in FIG. 42 is described below as an example of the operation of the pixel driving circuit provided in FIG. 42, which includes seven transistors (first transistor T1 to sixth transistor T6, eighth transistor T8) and two capacitors (first capacitor C1 and second capacitor C2), and all of the seven transistors are N-type transistors.

[0413] In the example implementation, the operation of the pixel driving circuit provided in FIG. 42 can include:

[0414] In the first stage P1, referred to as the first reset stage, the signals of the second scan signal line G2, the second emission signal line EM2, the first reset signal line Reset1, and the third reset signal line Reset3 are high-level signals, and the signals of the first scan signal line G1 and the first emission signal line EM1 are low-level signals. The signal of the second scan signal line G2 is a high-level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is written to the second node N2, the signal of the second node N2 is initialized (reset), and the original charge in the second node N2 is cleared. The signal of the first reset signal line Reset1 is a high-level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is written to the fifth node N5, the signal of the fifth node N5 is initialized (reset), and the original charge in the fifth node N5 is cleared. The signals of the second emission signal line EM2 and the third reset signal line Reset3 are high-level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, the signal of the initial signal line INIT is written to the third node N3 and the fourth node N4, respectively, and since the voltage value of the signal of the first node N1 and the voltage value of the signal of the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on at this time, the signal of the initial signal line INIT is written to the second node N2, the signals of the second node N2, the third node N3, and the fourth node N4 are initialized (reset), and the original charges in the second node N2, the third node N3, and the fourth node N4 are cleared. The signals of the first scan signal line G1 and the first emission signal line EM1 are low-level signals, the first transistor T1 and the fourth transistor T4 are disconnected. In this stage, the light emitting device L does not emit light.

[0415] In the second stage P2, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first emitting signal line EM1 are high level signals, and the signals of the first scan signal line G1 and the second emitting signal line EM2 are low level signals. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written into the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the second scan signal line G2 is a high level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is continuously provided to the second node N2, the signal of the first emitting signal line EM1 is a high level signal, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written into the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3, until the voltage V3 of the signal of the third node N3 is Vref-Vth, Vref is the voltage value of the signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth of the signals of the first node N1 and the third node N3. The signals of the first scan signal line G1 and the second emitting signal line EM2 are low level signals, and the first transistor T1 and the fifth transistor T5 are disconnected. In this stage, the light emitting device L does not emit light.

[0416] In the third stage P3, a data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3 and the first scan signal line G1 are high level signals, the signals of the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the data signal line Data outputs a data voltage. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is continuously written to the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written to the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the first scan signal line G1 is a high level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 is Vdata, Vdata is the data voltage of the data signal line, the signal of the first node N1 jumps from the voltage value in the present stage to the voltage value in the previous stage, and therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal of the third node N3 also jumps. At this time, the voltage value V3 of the signal of the third node N3 is Vref-Vth+(Vdata-Vref)*C1 / (C1+C2), wherein C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor. The signals of the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are disconnected. In the present stage, the light emitting device L does not emit light.

[0417] In the fourth stage P4, referred to as the second reset stage, the first reset signal line Reset1, the third reset signal line Reset3 and the second emitting signal line EM2 are high level signals, and the first emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, the signal of the initial signal line INIT is continuously written to the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the second emitting signal line EM2 is a high level signal, the fifth transistor T5 is turned on, the voltage V3 of the signal of the third node N3 is Vinit, Vinit is the voltage value of the signal of the initial signal line, at this time, the first node N1 is pulled low under the action of the first capacitor C1, so that the voltage V1 of the signal of the first node N1 is Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit, the signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, and the voltages of the signals of the third node N3 and the fifth node N5 remain the same. The signals of the first reset signal line Reset1, the first emitting signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals, and the first transistor T1, the second transistor T2 and the fourth transistor T4 are disconnected. In this stage, the light emitting device L does not emit light.

[0418] In the fifth stage P5, referred to as the emitting stage, the signals of the first reset signal line Reset1, the first emitting signal line EM1 and the second emitting signal line EM2 are high level signals, and the signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signals of the first emitting signal line EM1 and the second emitting signal line Reset2 are high level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fourth transistor T4, the third transistor T3 and the fifth transistor T5, and drives the light emitting device L to emit light. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, and the voltages of the signals of the third node N3 and the fifth node N5 remain the same. The signals of the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low level signals, the first transistor T1, the second transistor T2 and the eighth transistor T8 are disconnected, and in this stage, the light emitting device L emits light.

[0419] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Since the voltage value of the signal of the first node is V1=Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit, and the voltage value of the signal of the third node N3 is V3=Vinit, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 = K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0420] wherein I is the driving current flowing through the third transistor T3, that is, the driving current of the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0421] As can be seen from the derivation of the above current formula, in the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0422] For the pixel driving circuit provided in FIGS. 39-42, in the fourth stage and the fifth stage, the signals of the third node N3 and the fifth node N5 at both ends of the second capacitor C2 remain consistent, so that the third node of the pixel driving circuit is not affected by the coupling effect of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0423] FIG. 48 is a timing diagram of the pixel driving circuit provided in FIGS. 43 and 44. The working process of the pixel driving circuit illustrated in FIGS. 43 and 44 is described below as an example of the present disclosure. The pixel driving circuit in FIGS. 43 and 44 includes seven transistors (the first transistor T1 to the sixth transistor T6 and the eighth transistor T8) and two capacitors (the first capacitor C1 and the second capacitor C2), and the seven transistors are all N-type transistors.

[0424] In the example embodiment, the working process of the pixel driving circuit provided in FIGS. 43 and 44 can include:

[0425] In the first stage P1, referred to as the first reset stage, the signals of the second scan signal line G2, the second emission signal line EM2, the first reset signal line Reset1 and the third reset signal line Reset3 are high level signals, and the signals of the first scan signal line G1 and the first emission signal line EM1 are low level signals. The signal of the second scan signal line G2 is a high level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is written to the second node N2, the signal of the second node N2 is initialized (reset), and the original charge in the second node N2 is cleared. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is written to the fifth node N5, the signal of the fifth node N5 is initialized (reset), and the original charge in the fifth node N5 is cleared. The signals of the second emission signal line EM2 and the third reset signal line Reset3 are high level signals, the fifth transistor T5 and the eighth transistor T8 are turned on, the signal of the initial signal line INIT is written to the third node N3 and the fourth node N4 respectively, and since the voltage value of the signal of the first node N1 and the voltage value of the signal of the third node N3 are greater than the threshold voltage of the third transistor T3, at this time, the third transistor T3 is turned on, the signal of the initial signal line INIT is written to the second node N2, the signals of the second node N2, the third node N3 and the fourth node N4 are initialized (reset), and the original charge in the second node N2, the third node N3 and the fourth node N4 is cleared. The signals of the first scan signal line G1 and the first emission signal line EM1 are low level signals, the first transistor T1 and the fourth transistor T4 are disconnected. In this stage, the light emitting device L does not emit light.

[0426] In the second stage P2, the signals of the first reset signal line Reset1, the third reset signal line Reset3, the second scan signal line G2 and the first emitting signal line EM1 are high level signals, and the signals of the first scan signal line G1 and the second emitting signal line EM2 are low level signals. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is continuously written into the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written into the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the second scan signal line G2 is a high level signal, the second transistor T2 is turned on, the signal of the reference signal line REF is continuously provided to the second node N2, the signal of the first emitting signal line EM1 is a high level signal, the fourth transistor T4 is turned on, and the signal of the first power supply line VDD is written into the third node N3 through the turned-on fourth transistor T4, the second node N2 and the turned-on third transistor T3, until the voltage V3 of the signal of the third node N3 is Vref-Vth, Vref is the voltage value of the signal of the initial signal line REF, and Vth is the threshold voltage of the third transistor T3. At this time, the first capacitor C1 stores the voltage difference Vth of the signals of the first node N1 and the third node N3. The signals of the first scan signal line G1 and the second emitting signal line EM2 are low level signals, and the first transistor T1 and the fifth transistor T5 are disconnected. In this stage, the light emitting device L does not emit light.

[0427] In the third stage P3, a data writing stage, the signals of the first reset signal line Reset1, the third reset signal line Reset3 and the first scan signal line G1 are high level signals, the signals of the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the data signal line Data outputs a data voltage. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, the signal of the auxiliary signal line VX is continuously written to the fifth node N5, and the signal of the fifth node N5 is continuously initialized (reset). The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, and the signal of the initial signal line INIT is continuously written to the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the first scan signal line G1 is a high level signal, the first transistor T1 is turned on, and the data voltage of the data signal line Data is written to the first node N1. At this time, the voltage value V1 of the first node N1 is Vdata, Vdata is the data voltage of the data signal line, the signal of the first node N1 jumps from the voltage value in the present stage to the voltage value in the previous stage, and therefore, under the action of the first capacitor C1 and the second capacitor C2, the signal of the third node N3 also jumps. At this time, the voltage value V3 of the signal of the third node N3 is Vref-Vth+(Vdata-Vref)*C1 / (C1+C2), wherein C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor. The signals of the second scan signal line G2, the first emitting signal line EM1 and the second emitting signal line EM2 are low level signals, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are disconnected. In the present stage, the light emitting device L does not emit light.

[0428] In the fourth stage P4, called the second reset stage, the third reset signal line Reset3 and the second emission signal line EM2 are high level signals, and the signals of the first reset signal line Reset1, the first emission signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signal of the third reset signal line Reset3 is a high level signal, the eighth transistor T8 is turned on, the signal of the initial signal line INIT is continuously written to the fourth node N4, and the signal of the fourth node N4 is continuously initialized (reset). The signal of the second emission signal line EM2 is a high level signal, the fifth transistor T5 is turned on, the voltage V3 of the signal of the third node N3 is Vinit, Vinit is the voltage value of the signal of the initial signal line, at this time, the first node N1 is pulled low under the action of the first capacitor C1, so that the voltage V1 of the signal of the first node N1 is Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit. The signals of the first reset signal line Reset1, the first emission signal line EM1, the first scan signal line G1 and the second scan signal line G2 are low level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are turned off. In this stage, the light emitting device L does not emit light.

[0429] In the fifth stage P5, called the light emitting stage, the signals of the first emission signal line EM1 and the second emission signal line EM2 are high level signals, and the signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low level signals. The signals of the first emission signal line EM1 and the second emission signal line Reset2 are high level signals, the fourth transistor T4 and the fifth transistor T5 are turned on, the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fourth transistor T4, the third transistor T3 and the fifth transistor T5, and drives the light emitting device L to emit light. The signal of the first reset signal line Reset1 is a high level signal, the sixth transistor T6 is turned on, and the voltages of the signals of the third node N3 and the fifth node N5 remain consistent. The signals of the first reset signal line Reset1, the third reset signal line Reset3, the first scan signal line G1 and the second scan signal line G2 are low level signals, the first transistor T1, the second transistor T2, the sixth transistor T6 and the eighth transistor T8 are turned off, and in this stage, the light emitting device L emits light.

[0430] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode (also the first node N1) and the second electrode (also the third node N3) of the third transistor T3. Since the voltage value of the signal of the first node is V1=Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]+Vinit, and the voltage value of the signal of the third node N3 is V3=Vinit, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[Vdata-[Vref-Vth+(Vdata-Vref)*C1 / (C1+C2)]-Vth] 2 = K*[(C2 / (C1+C2))*(Vdata-Vref)] 2 .

[0431] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the control electrode and the second electrode of the third transistor T3.

[0432] As can be seen from the derivation of the above current formula, in the light emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, and ensuring the uniformity of the display brightness of the display product and improving the display effect of the entire display product.

[0433] For the pixel driving circuit provided in FIGS. 43 and 44, in the fourth stage and the fifth stage, the second capacitor C2 is disconnected from the third node N3 by the sixth transistor T6, so that the third node of the pixel driving circuit is not affected by the coupling effect of the second capacitor C2 in the fifth stage, which can improve the stability of the driving current of the pixel driving circuit and improve the reliability of the pixel driving circuit.

[0434] The pixel driving circuit provided in the embodiments of the present disclosure also provides a driving method of the pixel driving circuit configured to drive the pixel driving circuit. The driving method of the pixel driving circuit can include:

[0435] Step 100, the driving sub-circuit provides a driving current to the third node under the control of the signals of the first node and the second node.

[0436] Step 200, the first control sub-circuit provides the signal of the data signal line or the reference signal line to the first node N1 under the control of the signals of the first scan signal line and the second scan signal line.

[0437] Step 300, the second control sub-circuit provides the signal of the first power supply line to the second node and the signal of the third node to the fourth node under the control of the signals of the first light-emitting signal line and the second light-emitting signal line.

[0438] Step 400, the third control sub-circuit controls the signal of the third node under the control of the signal of the first reset signal line and the driving of the signal of the auxiliary signal line.

[0439] Step 500, the storage sub-circuit stores the voltage difference of the signals between the first node and the third node.

[0440] The pixel driving circuit provided by the embodiment of the present disclosure further provides a driving method of the pixel driving circuit, which is configured to drive the pixel driving circuit provided by FIG. 41. The working process of the pixel driving circuit includes the following steps:

[0441] Step 110, in the first stage, the effective level signal is provided to the signals of the second scanning signal line, the second light-emitting signal line, the first reset signal line and the second reset signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node and the signal of the fifth node to the third node, and the second control sub-circuit provides the signal of the fourth node to the third node.

[0442] Step 120, in the second stage, the effective level signal is provided to the first reset signal line, the second scanning signal line and the first light-emitting signal line, the first control sub-circuit provides the signal of the reference signal line to the first node, the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node, the second control sub-circuit provides the signal of the first power supply line to the second node to charge the first node, and the storage sub-circuit stores the voltage difference of the signals between the first node and the third node.

[0443] Step 130, in the third stage, the signals of the first reset signal line and the first scanning signal line are high level signals, the first control sub-circuit provides the signal of the data signal line to the first node, and the third control sub-circuit provides the signal of the auxiliary signal line to the fifth node.

[0444] Step 140, in the fourth stage, the effective level signal is provided to the second reset signal line and the second light-emitting signal line, the third control sub-circuit provides the signal of the third node to the fifth node, and the second control sub-circuit provides the signal of the fourth node to the third node.

[0445] Step 150, in the fifth stage, the second reset signal line, the first light-emitting signal line and the second light-emitting signal line are provided with an effective level signal, the second control sub-circuit provides the second node with a signal of the first power supply line, provides the fourth node with a signal of the third node, and the driving sub-circuit provides the third node with a driving current under the control of the signals of the first node and the second node, and the third control sub-circuit provides the fifth node with a signal of the third node.

[0446] The pixel driving circuit provided by the embodiment of the present disclosure further provides a driving method of the pixel driving circuit, which is configured to drive the pixel driving circuit provided by FIG. 42. The working process of the pixel driving circuit includes the following steps:

[0447] Step 210, in the first stage, the second scanning signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line are provided with an effective level signal, the first control sub-circuit provides the first node with a signal of the reference signal line, the third control sub-circuit provides the fifth node with a signal of the auxiliary signal line and the fourth node with a signal of the initial signal line, and the second control sub-circuit provides the third node with a signal of the fourth node.

[0448] Step 220, in the second stage, the first reset signal line, the third reset signal line, the second scanning signal line and the first light-emitting signal line are provided with an effective level signal, the first control sub-circuit provides the first node with a signal of the reference signal line, the third control sub-circuit provides the fifth node with a signal of the auxiliary signal line and the fourth node with a signal of the initial signal line, and the second control sub-circuit provides the second node with a signal of the first power supply line to charge the first node, and the storage sub-circuit stores the voltage difference of the signals between the first node and the third node.

[0449] Step 230, in the third stage, the first reset signal line, the third reset signal line and the first scanning signal line are provided with a high level signal, the first control sub-circuit provides the first node with a signal of the data signal line, the third control sub-circuit provides the fifth node with a signal of the auxiliary signal line and the fourth node with a signal of the initial signal line.

[0450] Step 240, in the fourth stage, the first reset signal line, the third reset signal line and the second light-emitting signal line are provided with an effective level signal, the third control sub-circuit provides the fourth node with a signal of the initial signal line and the fifth node with a signal of the auxiliary signal line, and the second control sub-circuit provides the third node with a signal of the fourth node.

[0451] Step 250, in the fifth stage, the first reset signal line, the first light-emitting signal line and the second light-emitting signal line are provided with the active level signal, the second control sub-circuit provides the first power supply line signal to the second node, provides the third node signal to the fourth node, and the driving sub-circuit provides the driving current to the third node under the control of the signals of the first node and the second node, and the third control sub-circuit provides the auxiliary signal line signal to the fifth node.

[0452] The pixel driving circuit provided by the embodiment of the present disclosure further provides a driving method of the pixel driving circuit. The pixel driving circuit is configured to drive the pixel driving circuit provided in FIG. 39 and FIG. 40. The working process of the pixel driving circuit includes: the first stage to the fifth stage. The driving method of the pixel driving circuit provided in FIG. 39 and FIG. 40 can include:

[0453] Step 310, in the first stage, the second scan signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line are provided with the active level signal, the first control sub-circuit provides the reference signal line signal to the first node, the third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node, and the second control sub-circuit provides the fourth node signal to the third node.

[0454] Step 320, in the second stage, the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line are provided with the active level signal, the first control sub-circuit provides the reference signal line signal to the first node, the third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node, and the second control sub-circuit provides the first power supply line signal to the first node to charge the first node, and the storage sub-circuit stores the voltage difference of the signals between the first node and the third node.

[0455] Step 330, in the third stage, the first reset signal line, the third reset signal line and the first scan signal line are provided with the high level signal, the first control sub-circuit provides the data signal line signal to the first node, the third control sub-circuit provides the auxiliary signal line signal to the fifth node and the initial signal line signal to the fourth node.

[0456] Step 340, in the fourth stage, the second reset signal line, the third reset signal line and the second light-emitting signal line are provided with the active level signal, the third control sub-circuit provides the initial signal line signal to the fourth node and the third node signal to the fifth node, and the second control sub-circuit provides the fourth node signal to the third node.

[0457] Step 350, in the fifth stage, the second reset signal line, the first light-emitting signal line and the second light-emitting signal line are provided with the active level signal, the second control sub-circuit provides the first node with the signal of the first power supply line, provides the fourth node with the signal of the third node, and the driving sub-circuit provides the third node with the driving current under the control of the signals of the first node and the second node, and the third control sub-circuit provides the fifth node with the signal of the third node.

[0458] The pixel driving circuit provided by the embodiment of the present disclosure further provides a driving method of the pixel driving circuit. The pixel driving circuit is configured to drive the pixel driving circuit provided in FIG. 43 and FIG. 44. The working process of the pixel driving circuit includes the following steps.

[0459] Step 410, in the first stage, the second scan signal line, the second light-emitting signal line, the first reset signal line and the third reset signal line are provided with the active level signal, the first control sub-circuit provides the first node with the signal of the reference signal line, the third control sub-circuit provides the fifth node with the signal of the third node, and provides the fourth node with the signal of the initial signal line, and the second control sub-circuit provides the third node with the signal of the fourth node.

[0460] Step 420, in the second stage, the first reset signal line, the third reset signal line, the second scan signal line and the first light-emitting signal line are provided with the active level signal, the first control sub-circuit provides the first node with the signal of the reference signal line, the third control sub-circuit provides the fifth node with the signal of the third node, and provides the fourth node with the signal of the initial signal line, and the second control sub-circuit provides the first node with the signal of the first power supply line to charge the first node, and the storage sub-circuit stores the voltage difference of the signals between the first node and the third node.

[0461] Step 430, in the third stage, the first reset signal line, the third reset signal line and the first scan signal line are provided with the high level signal, the first control sub-circuit provides the first node with the signal of the data signal line, the third control sub-circuit provides the fourth node with the signal of the initial signal line, and provides the fifth node with the signal of the third node.

[0462] Step 440, in the fourth stage, the third reset signal line and the second light-emitting signal line are provided with the active level signal, the third control sub-circuit provides the fourth node with the signal of the initial signal line, and the second control sub-circuit provides the third node with the signal of the fourth node.

[0463] Step 450, in the fifth stage, an effective level signal is provided to the first light-emitting signal line and the second light-emitting signal line, the second control sub-circuit provides a signal of the first power supply line to the second node, provides a signal of the third node to the fourth node, and the driving sub-circuit provides a driving current to the third node under the control of the signals of the first node and the second node.

[0464] At least one embodiment of the present disclosure further provides a display device including the pixel circuit provided by any of the embodiments of the present disclosure. The display device may, for example, be an organic light-emitting diode display device, a quantum dot light-emitting diode display device, or other types of devices having a display function. Embodiments of the present disclosure do not limit the display device.

[0465] Other structures and functions of the display device provided by the embodiments of the present disclosure can be implemented by conventional technologies, and the embodiments of the present disclosure do not limit this. The technical effects of the display device provided by the embodiments of the present disclosure can refer to the description of the technical effects of the pixel circuit provided by the embodiments of the present disclosure, which will not be repeated here.

[0466] For example, the display device provided by at least one embodiment of the present disclosure can be a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function, and the embodiments of the present disclosure do not limit this.

[0467] For example, the display device provided by the embodiments of the present disclosure has a display area, and the display area is provided with a plurality of pixel driving circuits.

[0468] In the exemplary embodiment, the display device can include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines, respectively. The scan driver is connected to a plurality of scan signal lines, respectively. The light-emitting driver is connected to a plurality of light-emitting signal lines, respectively. The pixel array can include a plurality of sub-pixels. At least one sub-pixel can include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit can include a pixel driving circuit. The pixel driving circuit can be connected to the scan signal line, the light-emitting signal line, and the data signal line, respectively.

[0469] The scan signal line includes a first scan signal line, a second scan signal line, a first reset signal line, a second reset signal line, and a third reset signal line. The light-emitting signal line includes a first light-emitting signal line and a second light-emitting signal line.

[0470] In an exemplary embodiment, the timing controller can provide grayscale values and control signals suitable for the specifications of the data driver to the data driver, can provide clock signals, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver, and can provide clock signals, an emission stop signal, and the like suitable for the specifications of the light emitting driver to the light emitting driver.

[0471] In an exemplary embodiment, the data driver can generate data voltages to be provided to the data signal lines using the grayscale values and the control signals received from the timing controller. For example, the data driver can sample the grayscale values using the clock signals and apply data voltages corresponding to the grayscale values to the data signal lines in units of pixels.

[0472] In an exemplary embodiment, the scan driver can generate scan signals to be provided to the scan signal lines by receiving the clock signals, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide scan signals having on-pulse levels to the scan signal lines. For example, the scan driver can be configured in the form of a shift register and can generate the scan signals in a manner that sequentially transfers the scan start signals provided in the form of on-pulse levels to next stage circuits under the control of the clock signals.

[0473] In an exemplary embodiment, the light emitting driver can generate emission signals to be provided to the light emitting signal lines by receiving the clock signals, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide emission signals having off-pulse levels to the light emitting signal lines. For example, the light emitting driver can be configured in the form of a shift register and can generate the emission signals in a manner that sequentially transfers the emission stop signals provided in the form of off-pulse levels to next stage circuits under the control of the clock signals.

[0474] In an exemplary embodiment, a display substrate can include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P including a first sub-pixel emitting first color light, a second sub-pixel emitting second color light, and a third sub-pixel emitting third color light, the first sub-pixel, the second sub-pixel, and the third sub-pixel each including a pixel driving circuit and a light emitting device. The pixel driving circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected to scan signal lines, data signal lines, and light emitting signal lines, respectively, and are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and the light emitting signal lines and output corresponding currents to the light emitting devices. The light emitting devices in the first sub-pixel, the second sub-pixel, and the third sub-pixel are connected to the pixel driving circuits of the sub-pixels in which the light emitting devices are located, respectively, and are configured to emit light of corresponding brightness in response to the currents output by the pixel driving circuits of the sub-pixels in which the light emitting devices are located.

[0475] In an example embodiment, the first sub-pixel can be a red sub-pixel (R) emitting red light, the second sub-pixel can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel can be a green sub-pixel (G) emitting green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal.

[0476] In an example embodiment, the pixel unit can include three sub-pixels, which can be arranged in a horizontal parallel, vertical parallel, or triangular manner, without limitation in the present disclosure.

[0477] In an example embodiment, the pixel unit can include four sub-pixels, which can be arranged in a horizontal parallel, vertical parallel, or square manner, without limitation in the present disclosure.

[0478] In a plane perpendicular to the display substrate, the display substrate can include a driving structure layer disposed on the base, a light-emitting structure layer disposed on the driving structure layer away from the base, and an encapsulation structure layer disposed on the light-emitting structure layer away from the base. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, without limitation in the present disclosure.

[0479] In an example embodiment, the base can be a rigid base or a flexible base, wherein the rigid base can be, but is not limited to, one or more of glass, conductive foil; the flexible base can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0480] In an example embodiment, the driving structure layer can include a plurality of transistors and a storage capacitor constituting a pixel driving circuit, the light-emitting structure layer can include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode, the anode is connected to the drain electrode of the transistor through a via, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0481] In an example embodiment, the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can prevent external water vapor from entering the light-emitting structure layer.

[0482] In an example embodiment, the touch structure layer can include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protection layer covering the second touch metal layer, the first touch metal layer can include a plurality of bridge electrodes, the second touch metal layer can include a plurality of first touch electrodes and second touch electrodes, and the first touch electrodes or the second touch electrodes can be connected with the bridge electrodes through vias.

[0483] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0484] For the sake of clarity, in the drawings used to describe embodiments of the present disclosure, the thickness and size of layers or microstructures are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intervening element.

[0485] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0486] The ordinal numbers "first", "second", "third", and the like in the present specification are provided for the purpose of avoiding confusion of constituent elements, and are not intended to be limiting in terms of number.

[0487] In the present specification, for the sake of convenience, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the constituent elements with reference to the drawings, and are only for the purpose of facilitating the description of the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0488] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0489] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0490] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as it can transmit and receive an electrical signal between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having a variety of functions.

[0491] In this specification, "disposed in the same layer" refers to structures formed by patterning two (or more) kinds of structures by one patterning process, and the materials thereof can be the same or different. For example, the materials of precursors for forming the plurality of structures disposed in the same layer are the same, and the materials finally formed can be the same or different.

[0492] Although the embodiments disclosed in the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

[0493] The following points need to be explained:

[0494] (1) In the drawings of the embodiments of the present disclosure, only structures related to the embodiments of the present disclosure are involved, and other structures can be referred to general design.

[0495] (2) In the case of no conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

[0496] The above-described exemplary embodiments of the present disclosure are merely for the purpose of illustration and not intended to limit the scope of the present disclosure, which is defined by the appended claims.

Claims

1. A pixel circuit comprising: a drive circuit comprising a control terminal, a first terminal and a second terminal, and configured to control a magnitude of a drive current flowing through the first terminal and the second terminal; a first compensation circuit configured to apply a reference signal to the control terminal of the drive circuit in response to a first compensation control signal, the first compensation circuit comprising a first storage capacitor, a first pole of the first storage capacitor being electrically connected to the control terminal of the drive circuit, a second pole of the first storage capacitor being electrically connected to the first terminal of the drive circuit; a light emitting element configured to emit light under the drive of the drive current, a second pole of the light emitting element being electrically connected to a second voltage terminal to receive a second power voltage; a second light emitting control circuit, a control terminal of the second light emitting control circuit being configured to receive a second light emitting control signal, a first terminal of the second light emitting control circuit being electrically connected to the first terminal of the drive circuit, a second terminal of the second light emitting control circuit being electrically connected to a first pole of the light emitting element, the second light emitting control circuit being configured to apply the drive current to the light emitting element and allow the reset signal to be applied to the first terminal of the drive circuit in response to the second light emitting control signal; and a reset control circuit, wherein a control terminal of the reset control circuit is configured to receive a reset control signal, a first terminal of the reset control circuit is electrically connected to the first terminal of the drive circuit, a second terminal of the reset control circuit is electrically connected to a reset signal terminal to receive a reset signal, a third terminal of the reset control circuit is electrically connected to the first pole of the light emitting element, the reset control circuit being configured to apply the reset signal to the first pole of the light emitting element and / or the first terminal of the drive circuit in response to the reset control signal. The reset control circuit comprises:

2. The pixel circuit of claim 1, wherein, a second compensation circuit comprising a second storage capacitor, wherein the second compensation capacitor is electrically connected between the first terminal of the drive circuit and the reset signal terminal; and a reset circuit, a control terminal of the reset circuit being the control terminal of the reset control circuit and configured to receive the reset control signal, a first terminal of the reset circuit being the third terminal of the reset control circuit and electrically connected to the first pole of the light emitting element, a second terminal of the reset circuit being the second terminal of the reset control circuit and electrically connected to the reset signal terminal to receive the reset signal. The value of the reset signal is adjustable. The reset signal comprises at least a first reset signal and a second reset signal, the first reset signal corresponding to a first display temperature, the second reset signal corresponding to a second display temperature, the first display temperature being lower than the second display temperature, the value of the first reset signal being smaller than the value of the second reset signal.

3. The pixel circuit according to claim 1 or 2, wherein The first reset signal is adjusted to the second reset signal during a reset signal adjustment period, the pixel circuit corresponding to a plurality of display frame periods, 4. The pixel circuit of claim 3, wherein, The reset signal adjustment period is located between two adjacent display frame periods; or 5. The pixel circuit of claim 4, wherein, The reset signal adjustment period is located between two adjacent display frame periods; or ​ The reset signal adjusting period is located in a display frame period, and the display frame period at least includes a reset stage, a compensation stage, a data writing stage and a light emitting stage. The reset signal adjusting period at least partially overlaps with any one of the reset stage, the compensation stage, the data writing stage and the light emitting stage, or does not overlap with any one of the reset stage, the compensation stage, the data writing stage and the light emitting stage.

6. The pixel circuit of any of claims 1-5, wherein, The value of the reference signal is adjustable.

7. The pixel circuit of claim 2, wherein, The first pole of the second storage capacitor is electrically connected to the first end of the reset control circuit and the first end of the driving circuit, and the second pole of the second storage capacitor is electrically connected to the first end of the reset circuit.

8. The pixel circuit of claim 7, further comprising a first light emitting control circuit, a control end of the first light emitting control circuit being configured to receive a first light emitting control signal, a first end of the first light emitting control circuit being electrically connected to a second end of the driving circuit, and a second end of the first light emitting control circuit being electrically connected to a first voltage end to receive a first power voltage, the first light emitting control circuit being configured to apply the first power voltage to the second end of the driving circuit in response to the first light emitting control signal.

9. The pixel circuit of claim 8, wherein, The first light emitting control circuit comprises a first light emitting control transistor, a gate of the first light emitting control transistor being electrically connected to the first light emitting control end to receive the first light emitting control signal, a first pole of the first light emitting control transistor being electrically connected to the second end of the driving circuit, and a second pole of the first light emitting control transistor being electrically connected to the first voltage end to receive the first power voltage.

10. The pixel circuit of any of claims 2-7, wherein, The second end of the driving circuit is directly electrically connected to the first voltage end to receive the first power voltage.

11. The pixel circuit of any of claims 7-10, wherein, The reset circuit comprises a reset transistor, a gate of the reset transistor being electrically connected to the reset control end to receive the reset control signal, a first pole of the reset transistor being electrically connected to the second pole of the second storage capacitor and the first end of the driving circuit, and a second pole of the reset transistor being electrically connected to the reset signal end to receive the reset signal.

12. The pixel circuit of any of claims 7-10, wherein, The second light emitting control circuit comprises a second light emitting control transistor, a gate of the second light emitting control transistor being electrically connected to the second light emitting control end to receive the second light emitting control signal, a first pole of the second light emitting control transistor being electrically connected to the first end of the driving circuit, and a second pole of the second light emitting control transistor being electrically connected to the first electrode of the light emitting element.

13. The pixel circuit of claim 12, wherein, The pixel circuit further comprises an auxiliary compensation circuit, a control end of the auxiliary compensation circuit being configured to receive an auxiliary compensation signal, a first end of the auxiliary compensation circuit being electrically connected to the second pole of the second storage capacitor, and a second end of the auxiliary compensation circuit being electrically connected to the first electrode of the light emitting element.

14. The pixel circuit of claim 13, wherein, The first end of the auxiliary compensation circuit is also electrically connected to the second end of the second light emitting control circuit and the first end of the reset circuit.

15. The pixel circuit of claim 14, wherein, The auxiliary compensation circuit includes an auxiliary compensation transistor, a gate of the auxiliary compensation transistor is taken as a control terminal of the auxiliary compensation circuit to receive the auxiliary compensation control signal, a first pole of the auxiliary compensation transistor is electrically connected with a second pole of the second compensation capacitor and a second pole of the second light-emitting control transistor, and a second pole of the auxiliary compensation transistor is electrically connected with the first electrode of the light-emitting element.

16. The pixel circuit of claim 13, wherein, The first terminal of the auxiliary compensation circuit is also electrically connected with the first terminal of the reset circuit, and the second terminal of the auxiliary compensation circuit is also electrically connected with the second terminal of the second light-emitting control circuit.

17. The pixel circuit of claim 16, wherein, The auxiliary compensation circuit includes an auxiliary compensation transistor, a gate of the auxiliary compensation transistor is electrically connected with an auxiliary compensation control terminal to receive the auxiliary compensation control signal, a first pole of the auxiliary compensation transistor is electrically connected with a second pole of the second compensation capacitor and a first pole of the reset transistor, and a second pole of the auxiliary compensation transistor is electrically connected with the first electrode of the light-emitting element.

18. The pixel circuit according to claim 15 or 17, wherein The gate of the auxiliary compensation transistor is electrically connected with the gate of the second light-emitting control transistor, the auxiliary compensation transistor shares the gate with the second light-emitting control transistor, the second light-emitting control signal is taken as the auxiliary compensation control signal, and the type of the auxiliary compensation transistor is the same as the type of the second light-emitting control transistor; or The gate of the auxiliary compensation transistor is independent of and not electrically connected with the gate of the second light-emitting control transistor.

19. The pixel circuit according to claim 17, wherein The gate of the auxiliary compensation transistor is electrically connected with the gate of the reset transistor, the auxiliary compensation transistor shares the gate with the reset transistor, the reset control signal is taken as the auxiliary compensation control signal, and the type of the auxiliary compensation transistor is the same as the type of the reset transistor; or The gate of the auxiliary compensation transistor is independent of and not electrically connected with the gate of the reset transistor.

20. The pixel circuit of any of claims 2-19, wherein, The driving circuit includes a driving transistor, a gate of the driving transistor is taken as a control terminal of the driving circuit and is electrically connected to a first node, a first pole of the driving transistor is taken as a first terminal of the driving circuit and is electrically connected to a second node with a first pole of the second storage capacitor, and a second pole of the driving transistor is taken as a second terminal of the driving circuit and is electrically connected with a first voltage terminal to receive a first power voltage; The pixel circuit further includes a data writing circuit, a control terminal of the data writing circuit is configured to receive a data scanning signal, a first terminal of the data writing circuit is electrically connected with a data signal terminal to receive a data signal, a second terminal of the data writing circuit is electrically connected with the first node, and the data writing circuit is configured to write the data signal to the control terminal of the driving circuit in response to the data scanning signal.

21. The pixel circuit of claim 16, wherein, a control terminal of the first compensation circuit is configured to receive the first compensation control signal, a first terminal of the first compensation circuit is electrically connected with a reference signal terminal to receive the reference signal, and a second terminal of the first compensation circuit is electrically connected with the second node, wherein the first compensation circuit further comprises a first compensation transistor, a gate of the first compensation transistor serves as the control terminal of the first compensation circuit and is electrically connected with a first compensation control signal terminal to receive the first compensation control signal, a first pole of the first compensation transistor serves as the first terminal of the first compensation circuit and is electrically connected with the reference signal terminal to receive the reference signal, and a second pole of the first compensation transistor is electrically connected with the first node, the data write circuit comprises a data write transistor, a gate of the data write transistor is electrically connected with a data scan signal terminal to receive the data scan signal, a first pole of the data write transistor is electrically connected with the data signal terminal to receive the data signal, and a second pole of the data write transistor is electrically connected with the first node.

22. The pixel circuit according to claim 21, wherein the data write transistor and the first compensation transistor are respectively transistors independently controlled by each other, the data scan signal terminal and the first compensation control signal terminal are respectively different signal terminals independently from each other, and the data signal terminal and the reference signal terminal are respectively different signal terminals independently from each other; or the data write transistor is multiplexed as the first compensation transistor, the data scan signal is multiplexed as the first compensation control signal, the first pole of the data write transistor is further electrically connected with the reference signal terminal to receive the reference signal, the data signal terminal is multiplexed as the reference signal terminal, and is configured to provide the data signal or the reference signal in different time periods respectively.

23. A display device comprising the pixel circuit according to any one of claims 1-22.

24. A driving method of a pixel circuit, applicable to the pixel circuit according to any one of claims 1-22, the driving method comprising: making the reset control signal an on signal to make the reset signal pass through the reset control circuit and be applied to the first electrode of the light emitting element and / or the first terminal of the driving circuit.

25. The driving method of the pixel circuit according to claim 24, wherein the reset control circuit comprises a second compensation circuit and a reset circuit, the second compensation circuit comprises a second storage capacitor, wherein a first pole of the second storage capacitor serves as the first terminal of the reset control circuit and is electrically connected with the first terminal of the driving circuit, a second pole of the second storage capacitor is electrically connected with a first terminal of the reset circuit; a control terminal of the reset circuit serves as the control terminal of the reset control circuit and is configured to receive the reset control signal, a first terminal of the reset circuit serves as the third terminal of the reset control circuit and is electrically connected with the first electrode of the light emitting element, and a second terminal of the reset circuit serves as the second terminal of the reset control circuit and is electrically connected with the reset signal terminal to receive the reset signal, The driving method comprises a reset stage, a compensation stage, a data writing stage and a light emitting stage. In the reset stage, the reset control signal is an open signal in at least part of the time period to make the first end and the second end of the reset circuit conductive, and the reset signal is sequentially applied to the second pole of the second storage capacitor, the first end of the driving circuit and the first electrode of the light emitting element through the second end and the first end of the reset circuit. In the compensation stage and the data writing stage, the reset control signal is an open signal, and the reset signal is sequentially applied to the second pole of the second storage capacitor and the first electrode of the light emitting element through the second end and the first end of the reset circuit. In the light emitting stage, the reset control signal is a closed signal in at least part of the time period to disconnect the second pole of the second storage capacitor from the reset signal end.

26. The driving method of the pixel circuit according to claim 25, wherein The pixel circuit further comprises a data writing circuit and a first light emitting control circuit; the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected with a data signal end to receive a data signal, and the second end of the data writing circuit is electrically connected with the control end of the driving circuit; the control end of the first light emitting control circuit is configured to receive a first light emitting control signal, the first end of the first light emitting control circuit is electrically connected with the second end of the driving circuit, and the second end of the first light emitting control circuit is electrically connected with a first voltage end to make the second end of the driving circuit receive a first power voltage; In the light emitting stage, the driving method comprises sequentially performing the following steps S101-S104: Step S101: making the data scanning signal a closed signal to turn off the data writing circuit; Step S102: making the second light emitting control signal an open signal to turn on the second light emitting control circuit, and making the first light emitting control signal remain a closed signal to turn off the first light emitting control circuit; Step S104: making the first light emitting control signal an open signal to turn on the first light emitting control circuit, so that the second end of the driving circuit receives the first power voltage from the first voltage end through the first light emitting control circuit.

27. The driving method of the pixel circuit according to any one of claims 25-26, wherein The pixel circuit further comprises a data writing circuit and a first light emitting control circuit; the control end of the data writing circuit is configured to receive a data scanning signal, the first end of the data writing circuit is electrically connected with a data signal end to receive a data signal, and the second end of the data writing circuit is electrically connected with the control end of the driving circuit; the control end of the first light emitting control circuit is configured to receive a first light emitting control signal, the first end of the first light emitting control circuit is electrically connected with the second end of the driving circuit, and the second end of the first light emitting control circuit is electrically connected with a first voltage end to make the second end of the driving circuit receive a first power voltage; In the reset stage, the driving method comprises sequentially performing the following steps S1010-S1030: Step S1010: disconnecting the second end of the driving circuit from the first voltage terminal; Step S1020: setting the reset control signal as an open signal to turn on the reset circuit; Step S1030: setting the first compensation control signal as an open signal to turn on the first compensation circuit In the reset stage, the data scanning signal remains as a closed signal to turn off the data writing circuit, and the second light-emitting control signal remains as an open signal to turn on the second light-emitting control circuit. In the compensation stage, the driving method comprises sequentially performing the following steps S2010-S2020: Step S2010: setting the second light-emitting control signal as a closed signal to turn off the second light-emitting control circuit, and keeping the first light-emitting control signal as a closed signal to turn off the first light-emitting control circuit; 28. The driving method of the pixel circuit according to any one of claims 26-27, wherein, Step S2020: setting the first light-emitting control signal as an open signal to turn on the first light-emitting control circuit, and keeping the second light-emitting control signal as a closed signal; In the compensation stage, the data scanning signal remains as a closed signal to keep the data writing circuit turned off, and the first compensation control signal remains as an open signal to keep the first compensation circuit turned on. The pixel circuit further comprises a data writing circuit, a control end of the data writing circuit is configured to receive a data scanning signal, a first end of the data writing circuit is electrically connected to a data signal terminal to receive a data signal, and a second end of the data writing circuit is electrically connected to the control end of the driving circuit, In the data writing stage, the driving method comprises sequentially performing the following steps S3010-S3030: Step S3010: setting the first compensation control signal as a closed signal to turn off the first compensation circuit, and keeping the second end of the driving circuit to receive the first power voltage; and 29. The driving method of the pixel circuit according to any one of claims 25 to 28, wherein Step S3030: setting the data scanning signal as an open signal to turn on the data writing circuit, In the data writing stage, the second light-emitting control signal remains as a closed signal to keep the second light-emitting control circuit turned off. The pixel circuit further comprises a first light-emitting control circuit, a control end of the first light-emitting control circuit is configured to receive a first light-emitting control signal, a first end of the first light-emitting control circuit is electrically connected to the second end of the driving circuit, and a second end of the first light-emitting control circuit is electrically connected to the first voltage terminal to enable the second end of the driving circuit to receive the first power voltage; The step S3030 further comprises: setting the first light-emitting control signal as an open signal to turn on the first light-emitting control circuit, so that the second end of the driving circuit receives the first power voltage. ​ 30. The driving method of the pixel circuit according to claim 29, wherein ​ ​

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