Scanning driving circuit, scanning signal output method, and display panel

Abstract

A scanning driving circuit (10), a scanning signal output method, and a display panel (120). The scanning driving circuit (10) comprises: an input module (11) used for generating a first control signal at a first node; a level transmission module (12) used for generating a second control signal at a third node; an output module (13) comprising a first control end (131) and a second control end (132), wherein the first control end (131) and the second control end (132) are respectively electrically connected to the input module (11) and the level transmission module (12), so as to generate corresponding scanning output signals in response to the first control signal and the second control signal; and a first isolation module (14) located between the second control end (132) of the output module (13) and the third node.

Description

Scanning drive circuit, scanning signal output method and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the priority of Chinese patent application No. 2023110401303 filed on August 17, 2023, and all its contents are incorporated herein by reference.

Technical field

[0003] The present application relates to the technical field of display panels, and in particular to a scan driving circuit, a method for outputting a scan signal, and a display panel. [Background Technology]

[0004] Gate Driver on Array (GOA) technology integrates a gate drive circuit, also known as a scan drive circuit, on the array substrate of a display panel to generate a scan signal that is input to the pixel unit to achieve a row-by-row scanning drive mode for the pixel unit.

[0005] However, existing scan driving circuits have poor reliability.

[0006] [Summary of the invention]

[0007] The main technical problem solved by this application is to provide a scanning driving circuit, a scanning signal output method and a display panel, which can solve the problems of poor reliability of the scanning driving circuit after long-term use and large signal glitches in the output signal.

[0008] The first technical solution provided in the present application is: providing a scan driving circuit, wherein the scan driving circuit includes: an input module, used to generate a first control signal at a first node; a level transmission module, used to generate a second control signal at a third node; an output module, including a first control end and a second control end, wherein the first control end and the second control end are respectively used to electrically connect the input module and the level transmission module to generate corresponding scan output signals in response to the first control signal and the second control signal; and a first isolation module, located between the second control end of the output module and the third node.

[0009] The input module samples the scan input signal in response to at least the third clock signal to generate a first control signal at the first node; the level transfer module samples the first level signal in response to the first clock signal and the second clock signal to generate a second control signal at the third node; the periods of the first clock signal, the second clock signal and the third clock signal are the same, the phase difference between the second clock signal and the first clock signal is half a period, and the rising edge of the third clock signal is no earlier than the falling edge of the second clock signal.

[0010] The method further includes an inverting module, which samples the second level signal in response to the first control signal and the second clock signal on the first node and transmits the sample to the third node.

[0011] Among them, the inverting module includes: an inverting unit, connected to the first node, sampling the second level signal in response to the first control signal on the first node; a phase delay unit, connected to the inverting unit and the third node, and the phase delay unit phase-delays the second level signal output by the inverting unit in response to the second clock signal and transmits it to the third node.

[0012] Among them, the inverting unit includes a sixth transistor, the phase delay unit includes a fifteenth transistor, the first end of the sixth transistor is connected to the supply end of the second level signal, the control end of the sixth transistor is connected to the first node, the second end of the sixth transistor is connected to the first end of the fifteenth transistor, the control end of the fifteenth transistor is connected to the supply end of the second clock signal, and the second end of the fifteenth transistor is connected to the third node.

[0013] In which, the output module includes: a first output unit, the control end of the first output unit serves as the first control end of the output module, the first end of the first output unit receives a first level signal, the second end of the first output unit is connected to the output end of the output module, and the first output unit responds to the first control signal to transmit the first level signal as a scan output signal to the output end of the output module; a second output unit, the control end of the second output unit serves as the second control end of the output module, the first end of the second output unit receives a third clock signal, the second end of the second output unit is connected to the output end of the output module, and the second output unit responds to the second control signal to transmit the third clock signal as a scan output signal to the output end of the output module; a coupling unit, the first end of the coupling unit is connected to the control end of the second output unit, and the second end of the coupling unit is connected to the second end of the second output unit.

[0014] Among them, the first output unit includes a tenth transistor, the second output unit includes a ninth transistor, the coupling unit includes a third capacitor, the first end of the tenth transistor is connected to the supply end of the first level signal, the control end of the tenth transistor is connected to the first control end, the second end of the tenth transistor is connected to the output end of the output module, the first end of the ninth transistor is connected to the supply end of the third clock signal, the control end of the ninth transistor is connected to the first end and the second control end of the third capacitor, and the second end of the ninth transistor is connected to the second end of the third capacitor and the output end of the output module.

[0015] The method further includes: a second isolation module, which is arranged between the first control terminal of the output module and the first node.

[0016] The input module includes: a first input unit, and the first input unit samples the scan input signal in response to a third clock signal.

[0017] The input module further includes a second input unit, which is connected in series between the first input unit and the first node. The second input unit transmits the scan input signal output by the first input unit as a first control signal to the first node in response to the first clock signal.

[0018] The first input unit includes a fourteenth transistor, a first end of the fourteenth transistor is connected to the supply end of the scan input signal, a control end of the fourteenth transistor is connected to the supply end of the third clock signal, and a second end of the fourteenth transistor is connected to the first node.

[0019] The second input unit includes a first transistor, a first end of the first transistor is connected to the second end of the fourteenth transistor, a control end of the first transistor is connected to the supply end of the first clock signal, and a second end of the first transistor is connected to the first node.

[0020] Among them, the input module includes: a first input unit and a second input unit, the second input unit is connected in series between the first input unit and the first node, the first input unit samples the scan input signal in response to the first clock signal, and the second input unit transmits the scan input signal output by the first input unit as a first control signal to the first node in response to the third clock signal.

[0021] Among them, the first input unit includes a fourteenth transistor, the second input unit includes a first transistor, the first end of the fourteenth transistor is connected to the supply end of the scan input signal, the control end of the fourteenth transistor is connected to the supply end of the first clock signal, the second end of the fourteenth transistor is connected to the first end of the first transistor, the control end of the first transistor is connected to the supply end of the third clock signal, and the second end of the first transistor is connected to the first node.

[0022] The method further includes: a first control module, which samples the first clock signal in response to the potential of the first node and transmits the sample to the level transmission module.

[0023] Among them, it further includes: a second control module, the second control module is connected to the first control end and the output end of the first control module, so as to sample the second clock signal and the second level signal in response to the potential of the output end of the first control module and the potential of the first node, and transmit them to the first control end.

[0024] The scan input signal is a scan output signal output by the previous scan driving circuit.

[0025] The scan input signal is a scan start signal of the scan driving circuit.

[0026] The second technical solution provided by the present application is: to provide a method for outputting a scan signal, which is applied to the scan driving circuit as above, wherein the method for outputting a scan signal includes: in a first stage, the scan input signal is provided as a first level state, and the second clock signal and the third clock signal are in a first level state to generate a first control signal at a first node, and the output module generates a first scan output signal in response to the first control signal; in a second stage, the scan input signal is provided as a second level state, the first clock signal and the third clock signal are provided as a first level state, and the output module continuously generates the first scan output signal; in a third stage, the second clock signal is provided as a first level state to generate a second control signal at a third node, and the output module generates a second scan output signal in response to the second control signal; in a fourth stage, the scan input signal is provided as a first level state, the second clock signal is provided as a second level state, the first clock signal and the third clock signal are provided as a first level state to generate a first control signal at the first node, and the output module generates a first scan output signal in response to the first control signal; in a fifth stage, the second clock signal is provided as a first level state, and the output module continuously generates the first scan output signal.

[0027] The third technical solution provided in the present application is: providing a display panel, wherein the display panel includes a scan driving circuit and a pixel unit coupled to each other; wherein the scan driving circuit is the scan driving circuit as described in any one of the above items.

[0028] The beneficial effects of the present application are as follows: the input module in the scan driving circuit provided by the present application is used to generate a first control signal at a first node, the level transmission module is used to generate a second control signal at a third node, and the output module includes a first control end and a second control end, and the first control end and the second control end are respectively used to electrically connect the input module and the level transmission module, so as to generate corresponding scan output signals in response to the first control signal and the second control signal, respectively, and a first isolation module is also provided between the second control end and the third node of the output module, so as to reduce the cross-voltage between the level transmission module and the output module as much as possible, so as to stably output the scan output signal, thereby effectively improving the reliability of the scan driving circuit.

Brief Description of the Drawings

[0029] FIG1 is a schematic structural diagram of a first embodiment of a scan driving circuit of the present application;

[0030] FIG2 is a schematic structural diagram of a second embodiment of a scan driving circuit of the present application;

[0031] 3 is a schematic structural diagram of a third embodiment of a scan driving circuit of the present application;

[0032] FIG4 is a schematic structural diagram of a fourth embodiment of a scan driving circuit of the present application;

[0033] 5 is a schematic structural diagram of a fifth embodiment of a scan driving circuit of the present application;

[0034] FIG6 is a schematic structural diagram of a sixth embodiment of a scan driving circuit of the present application;

[0035] 7 is a schematic structural diagram of a seventh embodiment of the scan driving circuit of the present application;

[0036] FIG8 is a schematic structural diagram of an eighth embodiment of a scan driving circuit of the present application;

[0037] FIG9 is a schematic structural diagram of a ninth embodiment of a scan driving circuit according to the present invention;

[0038] 10 is a schematic structural diagram of a tenth embodiment of a scan driving circuit of the present application;

[0039] FIG11 is a schematic structural diagram of an eleventh embodiment of a scan driving circuit of the present application;

[0040] FIG12 is a schematic structural diagram of a specific embodiment of the scan driving circuit in FIG11;

[0041] FIG13 is a timing diagram of an embodiment of the input signals corresponding to the scan driving circuit in FIG12;

[0042] FIG14 is a schematic structural diagram of an embodiment of the scan driving circuit cascaded in FIG12;

[0043] FIG15 is a schematic structural diagram of another specific embodiment of the scan driving circuit in FIG11;

[0044] FIG16 is a schematic structural diagram of another specific embodiment of the scan driving circuit in FIG11;

[0045] FIG17 is a flow chart of an embodiment of a method for outputting a scanning signal according to the present invention;

[0046] FIG18 is a schematic structural diagram of an embodiment of a display panel of the present application. [Specific implementation method]

[0047] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0048] 1 is a schematic diagram of a first embodiment of a scan driving circuit according to the present invention. In this embodiment, the scan driving circuit 10 includes an input module 11 , a level transmission module 12 , an output module 13 , and a first isolation module 14 .

[0049] It should be noted that in the field of display technology, a display panel generally includes a display area and a non-display area disposed outside the display area; the display area is further provided with a plurality of scan lines S1, S2…Sn (n is an integer greater than 1) and data lines D1, D2…Dm (m is an integer greater than 1) intersecting the plurality of scan lines to define a plurality of pixel units; and the non-display area is further provided with a scan drive circuit 10, a data drive circuit, an enable signal control circuit, and a timing control circuit. The scan drive circuit 10 is connected to the scan lines to generate a scan output signal input to the pixel units for controlling the writing operation of the data signal; the data drive circuit is connected to the data lines to provide a data signal to the pixel units to drive the pixel units to display the corresponding image; the enable signal control circuit is connected to the emission control lines EM1, EM2…EMn to provide an enable signal to the pixel units; and the timing control circuit is used to provide a clock signal to the pixel units. The scan driving circuit 10 includes a plurality of stages of circuits connected to pixel rows through a plurality of scan lines, ie, a multi-stage scan circuit; each scan circuit provides a scan signal to its corresponding scan line.

[0050] Specifically, the input module 11 is used to generate a first control signal at a first node, and the level transmission module 12 is used to generate a second control signal at a third node.

[0051] The first node and the third node specifically refer to two specific connection endpoints between modules in the scan driving circuit 10 that can respectively generate a first control signal and a second control signal.

[0052] The output module 13 further includes a first control terminal 131 and a second control terminal 132, wherein the first control terminal 131 is used to electrically connect to the input module 11 to receive a first control signal sent by the input module 11; and the second control terminal 132 is used to electrically connect to the level transmission module 12 to receive a second control signal sent by the level transmission module 12, so that the output module 13 triggers an action in response to the level state of the first control signal and the second control signal to generate a corresponding scan output signal.

[0053] Furthermore, the first isolation module 14 is correspondingly arranged between the second control end 132 of the output module 13 and the third node, so that the level transmission module 12 specifically sends the second control signal generated by the third node to the output module 13 via the first isolation module 14, thereby avoiding the impact damage to the level transmission module 12 caused by the large cross-voltage caused by the change of the conductive state of the output module 13, and in turn affecting the stable output of the scan output signal.

[0054] It is worth noting that the term "coupled" as used herein encompasses both direct and indirect connection methods. Therefore, if a first element is described as being coupled to a second element, this means that the first element may be directly connected to the second element via an electrical connection, a communication connection, wireless transmission, optical transmission, or other signal connection method, or may be indirectly connected to the second element electrically or by signal connection via other elements or connection methods.

[0055] The above scheme provides a new scan driving circuit 10, and by setting a first isolation module 14 between the second control terminal 132 of the output module 13 and the third node, the cross-voltage between the level transmission module 12 and the output module 13 is reduced as much as possible, thereby being able to stably output the scan output signal, thereby effectively improving the reliability of the circuit.

[0056] In one embodiment, the input module 11 is specifically used to receive a third clock signal provided by an external timing control circuit, as well as an external input start signal or an output signal of the upper-level scan driving circuit 10, as a scan input signal, and trigger an action in response to the level state of the third clock signal to sample the scan input signal, thereby generating a first control signal at the first node in the scan driving circuit 10.

[0057] The level transmission module 12 is used to receive the first clock signal and the second clock signal provided by the timing control circuit, and trigger an action in response to the level state of the first clock signal and the second clock signal to sample the first level signal, thereby generating a second control signal at the third node in the scan driving circuit 10.

[0058] The input module 11 is specifically coupled to a specific node of the timing control circuit, and the start signal providing end of the system processing circuit or the output end of the upper scan driving circuit 10, so as to receive the third clock signal sent by the timing control circuit, and the scan input signal sent by the system processing circuit or the upper scan driving circuit 10; similarly, the level transmission module 12 is specifically coupled to two other specific nodes of the timing control circuit, so as to receive the first clock signal and the second clock signal sent by the timing control circuit.

[0059] The periods of the first clock signal, the second clock signal and the third clock signal are the same, the phase difference between the second clock signal and the first clock signal is half a period, and the rising edge of the third clock signal is no earlier than the falling edge of the second clock signal.

[0060] Optionally, the first clock signal, the second clock signal and the third clock signal are square wave periodic signals, and in one period, the pulse width at a high level is twice the pulse width at a low level.

[0061] It is worth noting that the input module 11 and the level transmission module 12 specifically use the first clock signal, the second clock signal, the third clock signal and the first level signal to perform triggering actions to generate a first control signal at the first node and a second control signal at the third node, respectively, and then use the first control signal and the second control signal to trigger the output module 13 to turn on or off, so as to be able to output a scanning output signal of a high level or a low level accordingly, and send the scanning output signal to the corresponding scanning line to output it to the corresponding pixel unit.

[0062] Please refer to FIG2 , which is a schematic structural diagram of a second embodiment of the scan driving circuit of the present application. This embodiment is based on the first embodiment of the scan driving circuit provided in the present application, and the scan driving circuit 20 further includes an inverting module 25 .

[0063] Specifically, the inverting module 25 is used to receive the first control signal sent by the first node and the second clock signal sent by the timing control circuit, to sample the second level signal in response to the first control signal and the second clock signal on the first node, and to transmit the second level signal to the third node.

[0064] The first level signal can be a low level signal, and the second level signal can be a high level signal; or the first level signal can be a high level signal, and the second level signal can be a low level signal. The inversion module 25 can transmit the high level second level signal to the third node using the low level first control signal and the second clock signal; or transmit the low level second level signal to the third node using the high level first control signal and the second clock signal.

[0065] In this embodiment, the input module 21, the level transmission module 22, the output module 23, the first control terminal 231, the second control terminal 232 and the first isolation module 24 are respectively the same as the input module 11, the level transmission module 12, the output module 13, the first control terminal 131, the second control terminal 132 and the first isolation module 14. For details, please refer to Figure 1 and related text content, and no further details are given here.

[0066] Please refer to Figure 3, which is a schematic diagram of the structure of the third embodiment of the scan driving circuit of the present application. This embodiment is based on the second embodiment of the scan driving circuit provided in the present application. Specifically, the inverting module 35 in the scan driving circuit 30 further includes an inverting unit 351 and a phase delay unit 352.

[0067] Specifically, the inverting unit 351 is connected to the first node, and the phase delay unit 352 is connected to the inverting unit 351 and the third node; wherein, the inverting unit 351 is used to receive the first control signal sent by the first node, to sample the second level signal in response to the first control signal on the first node, and transmit the second level signal to the phase delay unit 352, and the phase delay unit 352 is also used to receive the second clock signal sent by the timing control circuit, to trigger an action in response to the level state of the second clock signal, so as to phase-delay the second level signal and transmit it to the third node.

[0068] Since the rising edge of the third clock signal is no earlier than the falling edge of the second clock signal, when the third clock signal is used to generate the first control signal at the first node and then the first control signal is used to sample the second level signal, the phase delay unit 352 specifically responds to the second clock signal triggering action whose falling edge is no later than the rising edge of the third clock signal, so that after phase delay, the second level signal output by the inverting unit 351 is transmitted to the third node, thereby effectively reducing the signal glitches of the corresponding scan output signal output by the output module 33.

[0069] In one embodiment, the inverting unit 351 specifically includes a sixth transistor, and the phase delay unit includes a fifteenth transistor, the first end of the sixth transistor is connected to the supply end of the second level signal, the control end of the sixth transistor is connected to the first node, the second end of the sixth transistor is connected to the first end of the fifteenth transistor, the control end of the fifteenth transistor is connected to the supply end of the second clock signal, and the second end of the fifteenth transistor is connected to the third node.

[0070] The control end of the sixth transistor can specifically respond to the first control signal trigger action on the first node to turn on the first end and the second end of the sixth transistor to transmit the second level signal to the first end of the fifteenth transistor; and the control end of the fifteenth transistor can respond to the second clock signal trigger action to turn on the first end and the second end of the fifteenth transistor, and then transmit the second level signal to the third node; and by adjusting the level state of the first control signal and the second clock signal to adjust the triggering time of the sixth transistor and the fifteenth transistor, the phase delay of the second level signal can be effectively realized, and the signal glitches of the scan output signal corresponding to the output module 33 can be effectively reduced.

[0071] Optionally, each of the above-mentioned transistors can be specifically a P-type thin film transistor, an N-type thin film transistor or a field effect transistor, and the control end of each transistor can be specifically a gate, and the first end of the transistor is the drain, and the second end is the source; or, the control end of each transistor is the gate, and the first end of the transistor is the source, and the second end is the drain; the same below, no further details will be given.

[0072] Optionally, each of the above transistors may be a composite transistor or a single transistor, which is not limited in this application.

[0073] In other embodiments, the transistor can be specifically replaced by a triode, and the control end of each triode is the base, the first end is the collector, and the second end is the emitter; or, the control end of each triode is the base, the first end is the emitter, and the second end is the collector. This application does not limit this.

[0074] In this embodiment, the input module 31, the level transmission module 32, the output module 33, the first control terminal 331, the second control terminal 332 and the first isolation module 34 are respectively the same as the input module 21, the level transmission module 22, the output module 23, the first control terminal 231, the second control terminal 232 and the first isolation module 24. For details, please refer to Figure 2 and related text content, and no further details are given here.

[0075] Please refer to Figure 4, which is a schematic diagram of the structure of the fourth embodiment of the scan driving circuit of the present application. This embodiment is based on the first embodiment of the scan driving circuit provided in the present application. Specifically, the output module 43 in the scan driving circuit 40 further includes a first output unit 433 and a second output unit 434.

[0076] Specifically, the control end of the first output unit 433 serves as the first control end of the output module 43, and the control end of the second output unit 434 serves as the second control end of the output module 43, so that the first end of the first output unit 433 receives the first level signal, the second end of the first output unit 433 is connected to the output end of the output module 43, and the first end of the second output unit 434 receives the third clock signal, and the second end of the second output unit 434 is connected to the output end of the output module 43.

[0077] Among them, the first output unit 433 can trigger an action in response to the first control signal to transmit the first level signal as a scan output signal to the output end of the output module 43, and the second output unit 434 can trigger an action in response to the second control signal to transmit the third clock signal as a scan output signal to the output end of the output module 43, so that part of the third clock signal can be copied to output it to the lower-level scanning drive circuit 40 and the scanning line to be used as the scanning input signal of the lower-level scanning drive circuit 40 and the driving signal of the pixel unit.

[0078] Furthermore, the output module 43 specifically also includes a coupling unit 46, the first end of the coupling unit 46 is specifically connected to the control end of the second output unit 434, and the second end of the coupling unit 435 is connected to the second end of the second output unit 434, so as to effectively reduce the coupling effect of the output module 43, thereby reducing the fluctuation of the scan output signal and ensuring the stable output of the scan output signal.

[0079] In one embodiment, the first output unit 433 includes a tenth transistor, the second output unit 434 includes a ninth transistor, the coupling unit 435 includes a third capacitor, and the first end of the tenth transistor is connected to the supply end of the first level signal, the control end of the tenth transistor is connected to the first control end, the second end of the tenth transistor is connected to the output end of the output module 43, the first end of the ninth transistor is connected to the supply end of the third clock signal, the control end of the ninth transistor is connected to the first end and the second control end of the third capacitor, and the second end of the ninth transistor is connected to the second end of the third capacitor and the output end of the output module 43.

[0080] The control end of the tenth transistor can specifically respond to the first control signal trigger action on the first control end to turn on the first end and the second end of the tenth crystal to transmit the first level signal to the output end of the output module 43; and the control end of the ninth transistor can respond to the second control signal trigger action on the second control end to turn on the first end and the second end of the ninth crystal to transmit the third clock signal to the output end of the output module 43, and copy part of the third clock signal; the third capacitor is used to stabilize the output end of the output module 43.

[0081] In this embodiment, the input module 41 , the level transmission module 42 and the first isolation module 44 are respectively the same as the input module 11 , the level transmission module 12 and the first isolation module 14 . For details, please refer to FIG. 1 and related text content, which will not be repeated here.

[0082] Please refer to FIG5 , which is a schematic structural diagram of a fifth embodiment of the scan driving circuit of the present application. This embodiment is based on the first embodiment of the scan driving circuit provided in the present application, and the scan driving circuit 50 further includes a second isolation module 56 .

[0083] Specifically, the second isolation module 56 is specifically arranged between the first control end and the first node of the output module 53 to isolate the large cross-voltage caused by the change of the conduction state of the output module 53, that is, the extremely low level, so as to avoid causing impact damage to the input module 51 and in turn affecting the stable output of the scan output signal.

[0084] In this embodiment, the input module 51, the level transmission module 52, the output module 53, the first control terminal 531, the second control terminal 532 and the first isolation module 54 are respectively the same as the input module 11, the level transmission module 12, the output module 13, the first control terminal 131, the second control terminal 132 and the first isolation module 14. Please refer to Figure 1 and related text content for details, and no further details will be given here.

[0085] Please refer to Figure 6, which is a schematic diagram of the structure of the sixth embodiment of the scan driving circuit of the present application. This embodiment is based on the first embodiment of the scan driving circuit provided in the present application, and the input module 61 in the scan driving circuit 60 further includes a first input unit 611.

[0086] Among them, the input module 61 specifically uses the first input unit 611 to receive the third clock signal provided by the timing control circuit, as well as the external input start signal or the output signal of the upper scan drive circuit 60, to sample the scan input signal in response to the third clock signal.

[0087] In this embodiment, the input module 61, the level transmission module 62, the output module 63, the first control terminal 631, the second control terminal 632 and the first isolation module 64 are respectively the same as the input module 11, the level transmission module 12, the output module 13, the first control terminal 131, the second control terminal 132 and the first isolation module 14. For details, please refer to Figure 1 and related text content, and no further details are given here.

[0088] Please refer to FIG7 , which is a schematic diagram of the structure of the seventh embodiment of the scan driving circuit of the present application. This embodiment is based on the sixth embodiment of the scan driving circuit provided in the present application, and the input module 71 in the scan driving circuit 70 specifically further includes a second input unit 712 .

[0089] Specifically, the second input unit 712 is connected in series between the first input unit 711 and the first node, so that the first input unit 711 is used to sample the scan input signal in response to the third clock signal, and the second input unit 712 is used to receive the first clock signal provided by the timing control circuit, so as to trigger the action in response to the level state of the first clock signal, and transmit the scan input signal output by the first input unit 711 to the first node as the first control signal, so that the transmission of the first control signal can be achieved more stably.

[0090] In one embodiment, the first input unit 711 includes a fourteenth transistor, a first end of the fourteenth transistor is connected to the supply end of the scan input signal, a control end of the fourteenth transistor is connected to the supply end of the third clock signal, and a second end of the fourteenth transistor is connected to the first node.

[0091] In one embodiment, the second input unit 712 includes a first transistor, a first terminal of the first transistor connected to the second terminal of the fourteenth transistor, a control terminal of the first transistor connected to the supply terminal of the first clock signal, and a second terminal of the first transistor connected to the first node.

[0092] The control end of the fourteenth transistor can specifically trigger an action in response to the third clock signal to turn on the first end and the second end of the fourteenth transistor to transmit the scan input signal to the first node or the first end of the first transistor; and the control end of the first transistor can trigger an action in response to the first clock signal to turn on the first end and the second end of the first transistor to transmit the scan input signal to the first node.

[0093] In this embodiment, the level transmission module 72, the output module 73, the first control terminal 731, the second control terminal 732 and the first isolation module 74 are respectively the same as the level transmission module 62, the output module 63, the first control terminal 631, the second control terminal 632 and the first isolation module 64. For details, please refer to Figure 6 and related text content, and no further details are given here.

[0094] Please refer to Figure 8, which is a schematic diagram of the structure of the eighth embodiment of the scan driving circuit of the present application. This embodiment is based on the sixth embodiment of the scan driving circuit provided in the present application, and the input module 81 in the scan driving circuit 80 specifically further includes a second input unit 812.

[0095] Specifically, the second input unit 812 is connected in series between the first input unit 811 and the first node, the first input unit 811 samples the scan input signal in response to the first clock signal, and the second input unit 812 transmits the scan input signal output by the first input unit 811 as a first control signal to the first node in response to the third clock signal.

[0096] In one embodiment, the first input unit 811 includes a fourteenth transistor, the second input unit 812 includes a first transistor, the first end of the fourteenth transistor is connected to the supply end of the scan input signal, the control end of the fourteenth transistor is connected to the supply end of the first clock signal, the second end of the fourteenth transistor is connected to the first end of the first transistor, the control end of the first transistor is connected to the supply end of the third clock signal, and the second end of the first transistor is connected to the first node.

[0097] It can be seen from this that the third clock signal and the first clock signal received by the control ends of the fourteenth transistor and the first transistor respectively can be interchanged, and only the fourteenth transistor or the first transistor corresponding to receiving the third clock signal can be retained. This application does not limit this.

[0098] In this embodiment, the level transmission module 82, the output module 83, the first control terminal 831, the second control terminal 832 and the first isolation module 84 are respectively the same as the level transmission module 62, the output module 63, the first control terminal 631, the second control terminal 632 and the first isolation module 64. For details, please refer to Figure 6 and related text content, and no further details are given here.

[0099] Please refer to FIG9 , which is a schematic diagram of the structure of a ninth embodiment of the scan driving circuit of the present application. This embodiment is based on the first embodiment of the scan driving circuit provided in the present application, and the scan driving circuit 90 further includes a first control module 97 .

[0100] Specifically, the first control module 97 is connected to the first node so as to trigger an action in response to the potential of the first node, so as to sample the first clock signal and transmit the first clock signal to the level transmission module 92 .

[0101] In this embodiment, the input module 91, the level transmission module 92, the output module 93, the first control terminal 931, the second control terminal 932 and the first isolation module 94 are respectively the same as the input module 11, the level transmission module 12, the output module 13, the first control terminal 131, the second control terminal 132 and the first isolation module 14. Please refer to Figure 1 and related text content for details, and no further details will be given here.

[0102] Please refer to FIG10 , FIG9 is a schematic structural diagram of the tenth embodiment of the scan driving circuit of the present application. This embodiment is based on the ninth embodiment of the scan driving circuit provided in the present application, and the scan driving circuit 100 further includes a second control module 108 .

[0103] Specifically, the second control module 108 is connected to the first control end, the first node, the output end of the first control module 107 and the second level signal providing end, so as to receive the second level signal and the second clock signal provided by the timing control circuit, and trigger an action in response to the potential of the output end of the first control module 107 and the potential of the first node to sample the second clock signal and the second level signal, and transmit them to the first control end.

[0104] In this embodiment, the input module 101, the level transmission module 102, the output module 103, the first control end 1031, the second control end 1032, the first isolation module 104 and the first control module 107 are respectively the same as the input module 91, the level transmission module 92, the output module 93, the first control end 931, the second control end 932, the first isolation module 94 and the first control module 97. Please refer to Figure 9 and related text content for details, and no further details will be given here.

[0105] 11 to 13 , FIG11 is a schematic structural diagram of the eleventh embodiment of the scan driving circuit of the present application, FIG12 is a schematic structural diagram of a specific embodiment of the scan driving circuit in FIG11 , and FIG13 is a timing diagram of an embodiment of each input signal corresponding to the scan driving circuit in FIG12 .

[0106] In this embodiment, the scan driving circuit 110 specifically includes: an input module 111, a level transmission module 112, an output module 113, a first isolation module 114, an inverting module 115, a second isolation module 116, a first control module 117 and a second control module 118; and the input module 111 includes a first input unit 1111 and a second input unit 1112, the inverting module 115 includes an inverting unit 1151 and a phase delay unit 1152, and the output module 113 includes a first output unit 1133, a second output unit 1134 and a coupling unit 1135.

[0107] It is worth noting that, in this embodiment, the modules and units in the scan driving circuit are respectively the same as the modules and units with the same names in Figures 1 to 10 and the corresponding connection relationships and functions. Please refer to Figures 1 to 10 and related text content for details, and no further details will be given here.

[0108] Furthermore, in one embodiment, the first input unit 1111 includes a fourteenth transistor T14, the second input unit 1112 includes a first transistor T1, the inverting unit 1151 includes a sixth transistor T6, the phase delay unit 1152 includes a fifteenth transistor T15, the first output unit 1133 includes a tenth transistor T10, the second output unit 1134 includes a ninth transistor T9, the coupling unit 1135 includes a third capacitor C3, the level transmission module 112 includes a third transistor T3, an eleventh transistor T11, an eighth transistor T8, a seventh transistor T7 and a first capacitor C1, the first isolation module 114 includes a thirteenth transistor T13, the second isolation module 116 includes a twelfth transistor T12, the first control module 117 includes a second transistor T2, and the second transistor T2 is a composite transistor, that is, the second transistor T2 further includes a first single transistor T2-1 and The second single transistor T2-2, the second control module 118 includes a fourth transistor T4, a fifth transistor T5 and a second capacitor C2; and the connection relationship between the above-mentioned transistors and capacitors is specifically shown in Figure 12, and is correspondingly connected to the external timing control circuit, the supply end of the first level signal VGL, the supply end of the second level signal VGH, and the start signal supply end of the system processing circuit or the output end Vout of the upper scan driving circuit 110, so as to receive the first level signal VGL, the second level signal VGH, the first clock signal ECK1, the second clock signal ECK2, the third clock signal ECK3 provided by the timing control circuit, and the scan input signal EIN provided by the start signal supply end of the system processing circuit or the upper scan driving circuit 110. The level status of each clock signal is specifically shown in Figure 4. Please refer to Figures 12 and 13 for details, and will not be repeated here.

[0109] In which, taking the first level signal VGL as a low level signal, the second level signal VGH as a high level signal, and the above-mentioned transistors being specifically P-type transistors, that is, triggering the first end and the second end to be turned on when the gate voltage thereof is at a low level as an example, it can be seen that in the first stage, the scan input signal EIN is provided to the first level state, also the low level state, and the second clock signal ECK2 and the third clock signal ECK3 are in the first level state, so as to trigger the fourteenth transistor T14, the first transistor T1, the sixth transistor T6, the fifteenth transistor T15, the thirteenth transistor T13 and the tenth transistor T10 to be triggered and turned on, thereby making the first node N1 and the second node N2 correspondingly low level, and the third node N3 and the fourth node N4 correspondingly high level, so as to trigger the ninth transistor T9 to be turned off, so that the output terminal Vout outputs a low level signal accordingly.

[0110] In the second stage, the scan input signal EIN is provided to the second level state, that is, the high level state, the first clock signal ECK1 and the third clock signal ECK3 are provided to the first level state to trigger the fourteenth transistor T14, the first transistor T1, the third transistor T3, and the eleventh transistor T11 to turn on, the fifth node N5 and the sixth node N6 are correspondingly low level, and the first node N1 and the second node N2 are correspondingly high level, to trigger the eighth transistor T8 to turn on, and the second transistor T2, the sixth transistor T6 and the tenth transistor T10 to turn off, and the fourth node N4 is still high level to trigger the ninth transistor T9 to turn off, and the output terminal Vout continues to output a low level signal.

[0111] In the third stage, the second clock signal ECK2 is provided to the first level state to trigger the seventh transistor T7 to turn on, and the first level signal VGL on the sixth node N6 is transmitted to the third node N3 and the fourth node N4 through the eighth transistor T8 and the seventh transistor T7 to trigger the ninth transistor T9 to turn on, so that the output terminal Vout copies and outputs the third clock signal ECK3, that is, the third clock signal ECK3 which is currently in the high level state, to be output to the corresponding scan line, thereby outputting to the corresponding pixel unit through the scan line.

[0112] In the fourth phase, the scan input signal EIN is provided to the first level state, the second clock signal ECK2 is provided to the second level state, and the first clock signal ECK1 and the third clock signal ECK3 are provided to the first level state, thereby triggering the fourteenth transistor T14 and the first transistor T1 to turn on, and the fifteenth transistor T15 to be triggered to turn off, so that the first node N1 and the second node N2 are correspondingly at a low level, thereby triggering the tenth transistor T10 to turn on. At this time, because the third node N3 and the fourth node N4 are correspondingly at a low level in the third phase, the fourth node N4 will be coupled to a very low level by the falling edge of the third clock signal ECK3 through the coupling effect of the third capacitor C3, thereby triggering the ninth transistor T9 to turn on and fully open, and fully transmitting the low level of the third clock signal ECK3 to the output terminal Vout, so that the output terminal Vout outputs a low level signal.

[0113] Since the third node N3 is also at a low level at this time, the voltage difference (cross-voltage) between the fourth node N4, that is, the ninth transistor T9 and the seventh transistor T7 and the fifteenth transistor T15 can be effectively reduced with the help of the thirteenth transistor T13, so as to avoid the extremely low level from causing impact damage to the seventh transistor T7 and the fifteenth transistor T15, and in turn affecting the stable output of the scan output signal at the output terminal Vout.

[0114] In the fifth phase, the second clock signal ECK2 is provided to the first level state, thereby triggering the fifteenth transistor T15 to turn on, causing the second level signal VGH to be transmitted to the third node N3 and the fourth node N4 via the sixth transistor T6 and the fifteenth transistor T15, thereby triggering the ninth transistor T9 to turn off. At the same time, the second node N2 is coupled to an extremely low level by the falling edge of the second clock signal ECK2 through the coupling effect of the second capacitor C2, thereby triggering the tenth transistor T10 to turn on and fully open, so as to fully transmit the first level signal VGL to the output terminal Vout, causing the output terminal Vout to output a low level signal accordingly.

[0115] Similarly, since the first node N1 is also at a low level at this time, the voltage difference (cross-voltage) between the second node N2, that is, the tenth transistor T10 and the first transistor T1, can be effectively reduced with the help of the twelfth transistor T12, so as to avoid the extremely low level from causing impact damage to the first transistor T1, and in turn affecting the stable output of the scan output signal at the output terminal Vout.

[0116] Please continue to refer to FIG. 14 , which is a schematic structural diagram of an embodiment of the scan driving circuits in FIG. 12 being cascaded.

[0117] In this embodiment, the number of the scan driving circuits 110 can be specifically multiple, and they are cascaded with each other to be respectively connected to an external timing control circuit, a start signal providing end of a system processing circuit and a plurality of scan lines, and receive the first initial clock signal SCK1, the second initial clock signal SCK2, the third initial clock signal SCK3, the fourth initial clock signal SCK4 provided by the timing control circuit, and the scan start signal SIN sent by the start signal providing end, and after being adjusted by the multiple scan driving circuits 20, output corresponding scan output signals to the multiple scan lines, for example, the first scan output signal SCN1, the second scan output signal SCN2, the third scan output signal SCN3, and the fourth scan output signal SCN4, and provide them to the corresponding pixel units through the multiple scan lines.

[0118] The scan input signal EIN of each scan driving circuit 110 is specifically a scan output signal output by the previous scan driving circuit 110 , or a scan start signal SIN of the scan driving circuit 110 .

[0119] Optionally, the number of the scan driving circuits 110 can be any reasonable number such as 4, 6 or 8, and this application does not impose any limitation on this.

[0120] Optionally, the first initial clock signal SCK1 has the same waveform and phase as the third initial clock signal SCK3, and the second initial clock signal SCK2 has the same waveform and phase as the fourth initial clock signal SCK4; the third initial clock signal SCK3 has the same waveform as the fourth initial clock signal SCK4, and the period is 2h, and the phase difference between the third initial clock signal SCK3 and the fourth initial clock signal SCK4 is 1h.

[0121] Please continue to refer to FIG. 15 , which is a schematic structural diagram of another specific embodiment of the scan driving circuit in FIG. 11 .

[0122] The difference between the scan driving circuit 110 in this embodiment and the scan driving circuit 110 in FIG. 12 is that the clock signals connected to the control terminals of the first transistor T1 and the fourteenth transistor T14 are interchanged.

[0123] Please continue to refer to FIG. 16 , which is a schematic structural diagram of another specific embodiment of the scan driving circuit in FIG. 11 .

[0124] The difference between the scan driving circuit 110 in this embodiment and the scan driving circuit 110 in FIG. 12 is that the fourteenth transistor T14 is removed.

[0125] The present application also provides a method for outputting a scanning signal. Please refer to FIG17 , which is a flow chart of an embodiment of the method for outputting a scanning signal of the present application. Specifically, the method may include the following steps:

[0126] S31: In the first stage, the scan input signal is provided to the first level state, and the second clock signal and the third clock signal are in the first level state to generate a first control signal at the first node, and the output module generates a first scan output signal in response to the first control signal.

[0127] The scanning signal output method in this embodiment is specifically a method in which the scanning driving circuit in the display panel outputs the scanning signal to the scanning driving circuit shown in FIG4 . Please refer to FIG4 and related text content for details, which will not be repeated here.

[0128] As shown in Figure 13, in the first stage, the scan input signal is provided as a first level state, and the second clock signal and the third clock signal are in the first level state to trigger the input module, the inverting unit and the phase delay unit to turn on, and generate a first control signal at the first node, so that the output module generates a first scan output signal in response to the first control signal.

[0129] S32: In the second stage, the scan input signal is provided as a second level state, the first clock signal and the third clock signal are provided as a first level state, and the output module continuously generates the first scan output signal.

[0130] Furthermore, in the second stage, the scan input signal is provided as a second level state, and the first clock signal and the third clock signal are provided as a first level state to trigger the input module to turn on, so that the first node and the third node are set high, and trigger the inverting unit to turn off, so that the output module continues to generate the first scan output signal.

[0131] S33: In the third phase, the second clock signal is provided as a first level state to generate a second control signal at the third node, and the output module generates a second scan output signal in response to the second control signal.

[0132] Furthermore, in the third stage, the second clock signal is provided as a first level state to trigger the level transmission module to turn on, and the first level signal is provided to the output module through the level transmission module to generate a second control signal at the third node, so that the output module responds to the second control signal to generate a second scan output signal.

[0133] S34: In the fourth stage, the scan input signal is provided to a first level state, the second clock signal is provided to a second level state, the first clock signal and the third clock signal are provided to a first level state to generate a first control signal at the first node, and the output module generates a first scan output signal in response to the first control signal.

[0134] In the fourth stage, the scan input signal is provided to a first level state, the second clock signal is provided to a second level state, and the first clock signal and the third clock signal are provided to a first level state to trigger the input module, the inverting unit, and the phase delay unit to turn on, so as to generate a first control signal at the first node, and enable the output module to generate a first scan output signal in response to the first control signal.

[0135] S35: In the fifth stage, the second clock signal is provided as the first level state, and the output module continues to generate the first scan output signal.

[0136] In the fifth phase, the second clock signal is provided as a first level state, so that the output module continuously generates the first scan output signal.

[0137] In some other embodiments, the scan driving circuit specifically includes some other more specific features to enable corresponding implementation of some other more specific scan signal output methods. Please refer to Figures 1-16 and related text content for details, which will not be repeated here.

[0138] The present application also provides a display panel, as shown in Figure 18 , which is a schematic structural diagram of an embodiment of the display panel of the present application. In this embodiment, the display panel 120 includes a scan driving circuit 121 and a pixel unit 122 coupled to each other.

[0139] The scan driving circuit 121 described in this embodiment is the scan driving circuit 10, scan driving circuit 20, scan driving circuit 30, scan driving circuit 40, scan driving circuit 50, scan driving circuit 60, scan driving circuit 70, scan driving circuit 80, scan driving circuit 90, scan driving circuit 100 or scan driving circuit 110 described in any one of the above embodiments. Please refer to Figures 1 to 16 and related text content for details, and will not be repeated here.

[0140] The beneficial effects of the present application are as follows: the input module in the scan driving circuit provided by the present application is used to generate a first control signal at a first node, the level transmission module is used to generate a second control signal at a third node, and the output module includes a first control end and a second control end, and the first control end and the second control end are respectively used to electrically connect the input module and the level transmission module, so as to generate corresponding scan output signals in response to the first control signal and the second control signal, respectively, and a first isolation module is also provided between the second control end and the third node of the output module, so as to reduce the cross-voltage between the level transmission module and the output module as much as possible, so as to stably output the scan output signal, thereby effectively improving the reliability of the scan driving circuit.

Claims

1. A scanning driving circuit, wherein: include: An input module, used for generating a first control signal at a first node; A level transmission module, used for generating a second control signal at a third node; an output module, comprising a first control terminal and a second control terminal, wherein the first control terminal and the second control terminal are respectively used to electrically connect the input module and the level transmission module to generate a corresponding scan output signal in response to the first control signal and the second control signal; The first isolation module is located between the second control terminal of the output module and the third node.

2. The scan driving circuit according to claim 1, wherein: The input module samples the scan input signal in response to at least a third clock signal to generate the first control signal at the first node; The level transmission module samples the first level signal in response to the first clock signal and the second clock signal to generate the second control signal at the third node; wherein the periods of the first clock signal, the second clock signal and the third clock signal are the same, the phase difference between the second clock signal and the first clock signal is half a period, and the rising edge of the third clock signal is not earlier than the falling edge of the second clock signal.

3. The scan driving circuit according to claim 1, wherein: Further including: An inversion module, wherein the inversion module samples the second level signal in response to the first control signal and the second clock signal on the first node, and transmits the sample to the third node.

4. The scan driving circuit according to claim 3, wherein: The inverting module comprises: an inverting unit, connected to the first node, and sampling the second level signal in response to the first control signal on the first node; A phase delay unit is connected to the inverting unit and the third node. The phase delay unit performs phase delay on the second level signal output by the inverting unit in response to the second clock signal and transmits the phase delay to the third node.

5. The scan driving circuit according to claim 4, wherein: The inverting unit includes a sixth transistor, the phase delay unit includes a fifteenth transistor, the first end of the sixth transistor is connected to the supply end of the second level signal, the control end of the sixth transistor is connected to the first node, the second end of the sixth transistor is connected to the first end of the fifteenth transistor, the control end of the fifteenth transistor is connected to the supply end of the second clock signal, and the second end of the fifteenth transistor is connected to the third node.

6. The scan driving circuit according to claim 1, wherein: The output module comprises: a first output unit, wherein a control end of the first output unit serves as a first control end of the output module, a first end of the first output unit receives a first level signal, a second end of the first output unit is connected to an output end of the output module, and the first output unit transmits the first level signal as the scan output signal to the output end of the output module in response to the first control signal; a second output unit, wherein the control end of the second output unit serves as the second control end of the output module, the first end of the second output unit receives a third clock signal, the second end of the second output unit is connected to the output end of the output module, and the second output unit transmits the third clock signal as the scan output signal to the output end of the output module in response to the second control signal; A coupling unit, wherein a first end of the coupling unit is connected to the control end of the second output unit, and a second end of the coupling unit is connected to the second end of the second output unit.

7. The scan driving circuit according to claim 6, wherein: The first output unit includes a tenth transistor, the second output unit includes a ninth transistor, the coupling unit includes a third capacitor, the first end of the tenth transistor is connected to the supply end of the first level signal, the control end of the tenth transistor is connected to the first control end, the second end of the tenth transistor is connected to the output end of the output module, the first end of the ninth transistor is connected to the supply end of the third clock signal, the control end of the ninth transistor is connected to the first end of the third capacitor and the second control end, and the second end of the ninth transistor is connected to the second end of the third capacitor and the Output terminal of the output module.

8. The scan driving circuit according to claim 1, wherein: Further including: The second isolation module is arranged between the first control terminal of the output module and the first node.

9. The scan driving circuit according to claim 1, wherein: The input module comprises: A first input unit samples a scan input signal in response to a third clock signal.

10. The scan driving circuit according to claim 9, wherein: The input module also includes a second input unit, which is connected in series between the first input unit and the first node. The second input unit transmits the scan input signal output by the first input unit as the first control signal to the first node in response to a first clock signal.

11. The scan driving circuit according to claim 10, wherein: The first input unit includes a fourteenth transistor, a first end of the fourteenth transistor is connected to a supply end of the scan input signal, a control end of the fourteenth transistor is connected to a supply end of the third clock signal, and a second end of the fourteenth transistor is connected to the first node.

12. The scan driving circuit according to claim 11, wherein: The second input unit includes a first transistor, a first end of the first transistor is connected to the second end of the fourteenth transistor, a control end of the first transistor is connected to a supply end of the first clock signal, and a second end of the first transistor is connected to the first node.

13. The scan driving circuit according to claim 1, wherein: The input module comprises: A first input unit and a second input unit, wherein the second input unit is connected in series between the first input unit and the first node, the first input unit samples a scan input signal in response to a first clock signal, and the second input unit transmits the scan input signal output by the first input unit as the first control signal to the first node in response to a third clock signal.

14. The scan driving circuit according to claim 13, wherein: The first input unit includes a fourteenth transistor, and the second input unit includes a first transistor, the first end of the fourteenth transistor is connected to the supply end of the scan input signal, the control end of the fourteenth transistor is connected to the supply end of the first clock signal, the second end of the fourteenth transistor is connected to the first end of the first transistor, the control end of the first transistor is connected to the supply end of the third clock signal, and the second end of the first transistor is connected to the first node.

15. The scan driving circuit according to claim 1, wherein: Further including: A first control module, wherein the first control module samples the first clock signal in response to the potential of the first node and transmits the sample to the level transmission module.

16. The scan driving circuit according to claim 15, wherein: Further including: A second control module, wherein the second control module is connected to the first control end and the output end of the first control module, so as to sample a second clock signal and a second level signal in response to the potential of the output end of the first control module and the potential of the first node, and transmit the samples to the first control end.

17. The scan driving circuit according to any one of claims 1 to 16, wherein: The scan input signal is a scan output signal output by the scan driving circuit at the previous stage.

18. The scan driving circuit according to any one of claims 1 to 16, wherein: The scan input signal is a scan start signal of the scan driving circuit.

19. A method for outputting a scanning signal, wherein: The scanning driving circuit as claimed in claim 4 comprises: In the first stage, the scan input signal is provided as a first level state, and the second clock signal and the third clock signal are in the first level state, so as to generate a first control signal at the first node, and the output module generates a first scan output signal in response to the first control signal; In the second stage, the scan input signal is provided as a second level state, the first clock signal and the third clock signal are provided as the first level state, and the output module continuously generates the first scan output signal; In the third stage, the second clock signal is provided as the first level state to generate a second control signal at the third node, and the output module generates a second scan output signal in response to the second control signal; In the fourth stage, the scan input signal is provided as the first level state, the second clock signal is provided as the second level state, the first clock signal and the third clock signal are provided as the first level state, so as to generate a first control signal at the first node, and the output module generates the first scan output signal in response to the first control signal; In the fifth stage, the second clock signal is provided as the first level state, and the output module continues to generate the first scan output signal.

20. A display panel, wherein: The display panel includes a scan driving circuit and a pixel unit coupled to each other; Wherein, the scan driving circuit is the scan driving circuit according to any one of claims 1-18.

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