Peltier cooler manufacturing process and peltier cooler

Abstract

A Peltier cooler manufacturing process, for use in solving the problem of generation of an error code caused by interference on signal transmission of an optical communication module in a conventional Peltier cooler manufacturing method. The Peltier cooler manufacturing process comprises the steps of: S1: preparing semiconductor particles; S2: preparing a substrate on which solder paste is printed; S3: connecting the semiconductor particles prepared in step S1 to said substrate prepared in step S2 by means of solder tin to prepare a Peltier cooler device; and step S4: applying a first pressure to the Peltier cooler device prepared in step S3 and to be heated, and at the same time performing heating soldering, wherein a high temperature is maintained for a first duration. The soldering layer of the prepared Peltier cooler contains 10% or less of an eutectic structure, thereby effectively eliminating the contribution of the Peltier cooler to the error code problem of the optical communication module.

Description

Semiconductor refrigeration chip manufacturing process and semiconductor refrigeration chip Technical Field

[0001] The present invention relates to the technical field of thermoelectric refrigeration device manufacturing, and in particular to a semiconductor refrigeration chip manufacturing process and a semiconductor refrigeration chip. Background Art

[0002] Thermoelectric coolers, represented by semiconductor cooling chips, have unique advantages such as small size, vibration-free operation, high reliability, and environmental friendliness. They are widely used in medical temperature control, laser transmitters, and optical receivers in the optical communications industry. In particular, the optical communications application scenario requires small size and high reliability of temperature control devices, making semiconductor cooling chips an irreplaceable core component. It should be noted that during the communication process, errors often occur between the received codewords after filtering, sampling, judgment, and regeneration at the receiving end and the transmitted codewords at the transmitting end, known as bit errors.

[0003] In practice, due to the specific application areas, the semiconductor cooling chip manufacturing process uses Au-Sn alloy solder to solder the semiconductor particles to the upper and lower ceramic substrates with electrodes. After soldering using traditional reflow or vacuum soldering methods, eutectic structures may form within the solder layer. Extensive data testing and verification has shown that when the proportion of eutectic structure within the solder layer exceeds 10%, it can interfere with the signal transmission of the optical communication module, resulting in bit errors.

[0004] Semiconductor cooler bit errors directly affect speech intelligibility, image clarity, and data signal reliability. More and more optical communication modules are demanding that semiconductor cooler manufacturing be designed to eliminate these errors in the final module.

[0005] Summary of the Invention

[0006] The present invention is mainly intended to solve the problem that the traditional semiconductor refrigeration film manufacturing method may interfere with the signal transmission of the optical communication module and cause bit errors. It provides a semiconductor refrigeration film manufacturing process. The eutectic structure content of the prepared semiconductor refrigeration film welding layer is less than 10%, which can effectively eliminate the contribution of the semiconductor refrigeration film itself to the bit error problem of the optical communication module.

[0007] In order to achieve the above objectives, the present invention adopts the following technical solutions.

[0008] A semiconductor refrigeration chip manufacturing process includes the following steps:

[0009] Step S1: preparing semiconductor particles;

[0010] Step S2: preparing a substrate for printing solder paste;

[0011] Step S3: connecting the semiconductor particles prepared in step S1 and the substrate printed with solder paste prepared in step S2 by soldering to prepare a semiconductor refrigeration device;

[0012] Step S4: Applying a first pressure to the semiconductor refrigeration device to be heated prepared in step S3 by a jig while performing heating welding, wherein the high temperature stage is maintained for a first period of time. The heating welding is performed in a vacuum welding furnace.

[0013] The present invention provides a semiconductor refrigeration chip manufacturing process, which controls the printing thickness of Au-Sn solder and applies a certain pressure to the semiconductor refrigeration chip during welding, thereby reducing the thickness of the Au-Sn welding layer after welding, and prolongs the high-temperature holding time of heating welding on the basis of 30 to 60 seconds of the traditional heating welding recommended curve. According to experimental data, as the time is prolonged, the proportion of eutectic structure in the Au-Sn welding layer is reduced. At the same time, the substrate electrode surface connected to the welding layer has an Au layer and a Ni layer, and the coating welding surface of the semiconductor particle element also has an Au layer and a Ni layer. By prolonging the heating time, the Au-Sn When the temperature is above the melting point of the solder, the elements Au and Ni on the electrode side of the substrate and the elements Au and Ni in the plating layer on the semiconductor side will diffuse into the soldering layer. The present invention changes the composition ratio and organizational structure of the soldering layer through the above-mentioned technical means, effectively controlling the proportion of eutectic structure in the Au-Sn soldering layer to below 10%, effectively eliminating the contribution of the semiconductor refrigeration plate itself to the bit error problem of the optical communication module, solving the problem that the traditional semiconductor refrigeration plate manufacturing method will interfere with the signal transmission of the optical communication module and generate bit errors, and improving the intelligibility of language, clarity of images and reliability of data signals in the process of using semiconductor refrigeration plates.

[0014] Preferably, the specific process of step S1 includes the following steps:

[0015] Step S11: Slicing the Bi2Te3-based material ingot by wire cutting or internal circular cutting;

[0016] Step S12: preparing a Ni layer and an Au layer on the bare chip cut in step S11 to form a wafer;

[0017] Step S13: cutting the wafer prepared in step S12 into semiconductor particles of a certain size;

[0018] The coating welding surface of the semiconductor particle element of the present invention has an Au layer and a Ni layer. By prolonging the time above the melting point of the Au-Sn solder during heating, the elements Au and Ni in the semiconductor side coating will diffuse into the welding layer, thereby changing the component ratio and organizational structure of the welding layer.

[0019] Preferably, the specific process of step S2 includes the following steps:

[0020] Step S21: sputtering a copper-metal composite layer on an insulating material plate as a device substrate, wherein the insulating material is a high thermal conductivity ceramic, including aluminum nitride or aluminum oxide; and the electrode material is a high electrical conductivity and high thermal conductivity metal material such as Cu and Al;

[0021] Step S22: preparing a Ni layer and an Au layer on one side of the substrate prepared in step S21;

[0022] Step S23: etching the substrate metal layer prepared in step S22 to form the required circuit diagram according to the shape of the design drawing;

[0023] Step S24: placing solder at the soldering position on the substrate prepared in step S23;

[0024] The substrate electrode surface connected to the soldering layer of the present invention has an Au layer and a Ni layer. By extending the time above the melting point of the Au-Sn solder during heating, the elements Au and Ni on the substrate electrode side will diffuse into the soldering layer, thereby changing the component ratio and organizational structure of the soldering layer.

[0025] Preferably, in steps S12 and S22, the method for preparing the Ni layer and the Au layer is electroplating or chemical plating.

[0026] Preferably, in step S24, the solder is Au-Sn solder paste or solder sheet, and the solder is printed, with a screen thickness of less than or equal to 0.06 mm. The present invention reduces the thickness of the Au-Sn solder layer after soldering by controlling the printing thickness of the Au-Sn solder.

[0027] Preferably, in step S4, a first pressure is applied to the semiconductor refrigeration device by a fixture, specifically comprising: applying a first pressure relative to the cross section of the welding layer by the fixture, the first pressure being 30 to 60 g / mm 2 The present invention reduces the thickness of the Au-Sn welding layer after welding by applying a certain pressure to the semiconductor refrigeration plate during welding.

[0028] Preferably, after cooling, the thickness of the Au-Sn solder layer is less than 20 μm and greater than or equal to 10 μm. In step S4, the first duration of the high temperature stage is at least 220 seconds, and the high temperature stage is a stage where the temperature is above the melting point of the solder layer. After cooling, the thickness of the solder layer is less than 20 μm and greater than or equal to 10 μm. To control this thickness, the thickness of the screen used for printing is selected to be less than 0.06 mm. Before heating, the pressure applied to the semiconductor cooling sheet is 30 to 60 g / mm relative to the cross-sectional area of ​​the solder layer. 2For the above solder layer thickness, the high temperature holding time above the melting point during heating is at least 220 seconds. Compared with the high temperature holding time of traditional heating welding, the high temperature holding time is extended. The high temperature is the temperature above the melting point of the solder layer. The high temperature holding time, that is, the first time, is 220 seconds or more.

[0029] Preferably, after cooling, the thickness of the weld layer is less than 10 μm. In step S4, the first duration of the high temperature stage is at least 60 seconds. The high temperature stage is a stage where the temperature is above the melting point of the weld layer. The thinner the weld layer, the shorter the high temperature duration required during heating and welding. In this embodiment, when the weld layer thickness is less than 10 μm, the first duration of the high temperature above the melting point during heating is shortened to at least 60 seconds.

[0030] A semiconductor refrigeration plate adopts the above-mentioned semiconductor refrigeration plate manufacturing process, comprising semiconductor particles and a substrate with printed solder paste, wherein the upper side of the semiconductor particles is provided with an upper semiconductor particle Ni-plated layer and an upper semiconductor particle Au-plated layer in sequence from the inside to the outside, and the lower side of the semiconductor particles is provided with a lower semiconductor particle Ni-plated layer and a lower semiconductor particle Au-plated layer in sequence from the inside to the outside; the substrate comprises an upper substrate and a lower substrate; an upper Au-Sn soldering layer is provided between the upper substrate and the upper semiconductor particle Au-plated layer, and a lower Au-Sn soldering layer is provided between the lower substrate and the lower semiconductor particle Au-plated layer. The present invention provides a semiconductor refrigeration chip, which is made by connecting semiconductor particles and a substrate with printed solder paste through solder, and then pressing them with a special jig and heating and welding them at the same time. Compared with the existing technology, the component ratio and organizational structure of the welding layer are changed, and the proportion of eutectic structure in the Au-Sn welding layer is effectively controlled to be below 10%. The contribution of the semiconductor refrigeration chip itself to the bit error problem of the optical communication module is effectively eliminated, and the problem that the traditional semiconductor refrigeration chip manufacturing method will interfere with the signal transmission of the optical communication module and generate bit errors is solved, thereby improving the intelligibility of language, the clarity of images and the reliability of data signals in the process of using semiconductor refrigeration chips.

[0031] Preferably, the upper substrate includes an upper substrate ceramic base material, an upper substrate electrode Cu layer, an upper substrate electrode Ni layer and an upper substrate electrode Au layer arranged in sequence from top to bottom; the lower substrate includes a lower substrate ceramic base material, a lower substrate electrode Cu layer, a lower substrate electrode Ni layer and a lower substrate electrode Au layer arranged in sequence from bottom to top.

[0032] Therefore, the advantages of the present invention are: by controlling the printing thickness of the Au-Sn solder and applying a certain pressure to the semiconductor refrigeration plate during welding, the thickness of the Au-Sn welding layer after welding is reduced, and the high temperature holding time of the heating welding is extended on the basis of 30 to 60 seconds of the traditional heating welding recommended curve, so that the elements Au and Ni on the substrate electrode side and the elements Au and Ni in the semiconductor side coating are diffused into the welding layer, thereby changing the composition ratio and organizational structure of the welding layer, effectively controlling the proportion of eutectic structure in the Au-Sn welding layer to below 10%, effectively eliminating the contribution of the semiconductor refrigeration plate itself to the optical communication module bit error problem, solving the problem that the traditional semiconductor refrigeration plate manufacturing method will interfere with the signal transmission of the optical communication module and generate bit errors, and improving the intelligibility of language, image clarity and reliability of data signals in the process of using semiconductor refrigeration plates. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a flow chart of a process for manufacturing a semiconductor refrigeration plate in a first embodiment of the present invention.

[0034] FIG2 is a schematic diagram of a heating curve of a product produced using a conventional semiconductor refrigeration process in a third embodiment of the present invention.

[0035] FIG3 is a schematic diagram of a heating curve of a product using an improved semiconductor refrigeration chip manufacturing process in the third embodiment of the present invention.

[0036] FIG4 is a schematic diagram of product pressurization using an improved semiconductor refrigeration plate manufacturing process in Example 3 of the present invention.

[0037] FIG5 is a schematic structural diagram of a semiconductor refrigeration plate in a fourth embodiment of the present invention.

[0038] FIG6 a is a first cross-sectional view of a device manufactured using a conventional semiconductor refrigeration process in the third embodiment of the present invention.

[0039] FIG6 b is a second cross-sectional view of a device manufactured using a conventional semiconductor refrigeration process in the third embodiment of the present invention.

[0040] FIG6 c is a third cross-sectional view of a device manufactured using a conventional semiconductor refrigeration process in the third embodiment of the present invention.

[0041] FIG7 a is a first cross-sectional view of a device manufactured using the improved semiconductor refrigeration chip manufacturing process in the third embodiment of the present invention.

[0042] FIG7 b is a second cross-sectional view of a device manufactured using the improved semiconductor refrigeration chip manufacturing process in the third embodiment of the present invention.

[0043] 1. Upper substrate ceramic substrate 2, upper substrate electrode Cu layer 3, upper substrate electrode Ni layer 4, upper substrate electrode Au layer 5, upper Au-Sn soldering layer 6, upper semiconductor particle Au-plated layer 7, upper semiconductor particle Ni-plated layer 8, semiconductor particles 9, lower semiconductor particle Ni-plated layer 10, lower semiconductor particle Au-plated layer 11, lower Au-Sn soldering layer 12, lower substrate electrode Au layer 13, lower substrate electrode Ni layer 14, lower substrate electrode Cu layer 15, lower substrate ceramic substrate 16, semiconductor refrigeration sheet 17, and pressurizing jig. DETAILED DESCRIPTION

[0044] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0045] Example 1.

[0046] A semiconductor refrigeration chip manufacturing process, as shown in Figure 1, includes the following steps:

[0047] Step S1: preparing semiconductor particles;

[0048] Step S2: preparing a substrate for printing solder paste;

[0049] Step S3: connecting the semiconductor particles prepared in step S1 and the substrate printed with solder paste prepared in step S2 by soldering to prepare a semiconductor refrigeration device;

[0050] Step S4: Apply a first pressure to the semiconductor refrigeration device to be heated prepared in step S3 through a special fixture, and heat and weld it at the same time, wherein the high temperature stage is maintained for a first time, and a vacuum welding furnace is used for heating and welding.

[0051] This embodiment provides a semiconductor refrigeration chip manufacturing process, which controls the printing thickness of Au-Sn solder and applies a certain pressure to the semiconductor refrigeration chip during welding, thereby reducing the thickness of the Au-Sn welding layer after welding, and the high temperature holding time of heating welding is extended on the basis of 30 to 60 seconds of the traditional heating welding recommended curve. According to experimental data, as the time is extended, the proportion of eutectic structure in the Au-Sn welding layer is reduced. At the same time, the substrate electrode surface connected to the welding layer has an Au layer and a Ni layer, and the coating welding surface of the semiconductor particle element also has an Au layer and a Ni layer. By extending the heating time, the Au-Sn When the temperature is above the melting point of the solder, the elements Au and Ni on the electrode side of the substrate and the elements Au and Ni in the plating layer on the semiconductor side will diffuse into the soldering layer. This embodiment changes the composition ratio and organizational structure of the soldering layer through the above-mentioned technical means, effectively controlling the proportion of eutectic structure in the Au-Sn soldering layer to below 10%, effectively eliminating the contribution of the semiconductor refrigeration plate itself to the bit error problem of the optical communication module, and solving the problem that the traditional semiconductor refrigeration plate manufacturing method will interfere with the signal transmission of the optical communication module and generate bit errors, thereby improving the intelligibility of language, the clarity of images and the reliability of data signals in the process of using semiconductor refrigeration plates.

[0052] The specific process of step S1 includes the following steps:

[0053] Step S11: Slicing the Bi2Te3-based material ingot by wire cutting or internal circular cutting;

[0054] Step S12: preparing a Ni layer and an Au layer on the bare chip cut in step S11 to form a wafer;

[0055] Step S13: cutting the wafer prepared in step S12 into semiconductor particles of a certain size;

[0056] The plated soldering surfaces of the semiconductor particle elements in this embodiment have both Au and Ni layers. By extending the heating time above the melting point of the Au-Sn solder, the elements Au and Ni in the semiconductor side plated layer will diffuse into the soldering layer, thereby changing the composition ratio and organizational structure of the soldering layer.

[0057] The specific process of step S2 includes the following steps:

[0058] Step S21: sputtering a copper-metal composite layer on an insulating material plate as a device substrate, wherein the insulating material is a high thermal conductivity ceramic, including aluminum nitride or aluminum oxide; and the electrode material is a high electrical conductivity and high thermal conductivity metal material such as Cu and Al;

[0059] Step S22: preparing a Ni layer and an Au layer on one side of the substrate prepared in step S21;

[0060] Step S23: etching the substrate metal layer prepared in step S22 to form the required circuit diagram according to the shape of the design drawing;

[0061] Step S34: placing solder at the soldering position on the substrate prepared in step S23;

[0062] In this embodiment, the substrate electrode surface connected to the soldering layer has an Au layer and a Ni layer. By extending the time above the melting point of the Au-Sn solder during heating, the elements Au and Ni on the substrate electrode side will diffuse into the soldering layer, thereby changing the composition ratio and organizational structure of the soldering layer.

[0063] In steps S12 and S22 , the Ni layer and the Au layer are prepared by electroplating or chemical plating.

[0064] In step S34, the solder is Au-Sn solder paste or solder sheet, and the solder is printed, with a screen thickness of less than or equal to 0.06 mm. This embodiment reduces the thickness of the Au-Sn solder layer after soldering by controlling the printing thickness of the Au-Sn solder.

[0065] In step S4, after cooling, the thickness of the Au-Sn solder layer is less than 20 μm and greater than or equal to 10 μm. To control the thickness, the thickness of the screen used for printing is selected to be less than 0.06 mm, and the pressure applied to the semiconductor cooling sheet before heating is 30 to 60 g / mm relative to the cross-sectional area of ​​the solder layer. 2 ; Corresponding to the above welding layer thickness, the high temperature above the melting point during heating should be maintained for at least 220 seconds.

[0066] In step S4, the pressure applied to the semiconductor cooling sheet before heating is 30 to 60 g / mm relative to the cross-sectional area of ​​the welding layer. 2 In this embodiment, a certain pressure is applied to the semiconductor cooling plate during welding, thereby reducing the thickness of the Au-Sn welding layer after welding.

[0067] In step S4, if the thickness of the weld layer after cooling is less than 20 μm and greater than or equal to 10 μm, the high temperature holding time above the melting point during heating is at least 220 seconds. Furthermore, the thinner the weld layer, the shorter the high temperature holding time required during heating and welding. If the thickness of the weld layer after cooling is less than 10 μm, the high temperature holding time above the melting point during heating is at least 60 seconds.

[0068] Example 2.

[0069] This embodiment provides a semiconductor cooling chip manufacturing process, including the following steps:

[0070] (1) Slicing the Bi2Te3-based material ingot; the cutting method is wire cutting, inner circle cutting, etc.;

[0071] (2) preparing a Ni layer and an Au layer on the bare chip cut in step (1) to form a wafer; the metal layer is prepared by electroplating, chemical plating, etc.;

[0072] (3) cutting the wafer prepared in step (2) into semiconductor particles of a certain size;

[0073] (4) Sputtering a copper-metal composite layer on an insulating material plate as a device substrate; the insulating material is a high thermal conductivity ceramic, including aluminum nitride, aluminum oxide, etc.; the electrode material is a high electrical conductivity and high thermal conductivity metal material such as Cu and Al;

[0074] (5) sputtering one side of the substrate prepared in step (4) to prepare a Ni layer and an Au layer; the coating preparation method is electroplating, chemical plating, etc.;

[0075] (6) etching the substrate metal layer prepared in step (5) to form the required circuit diagram according to the shape of the design drawing;

[0076] (7) Arranging solder at the welding position on the substrate prepared in step (6); the solder is Au-Sn solder paste, solder sheet, etc.; the solder is completed by printing, and the screen thickness is less than 0.06 mm;

[0077] (8) connecting the semiconductor particles prepared in step (3) and the substrate printed with solder paste prepared in step (7) by soldering to prepare a semiconductor refrigeration device;

[0078] (9) The semiconductor refrigeration sheet to be heated prepared in step (8) is pressed by a special jig, and the thickness of the solder layer is reduced by pressure, while heating and welding are performed at the same time, and a vacuum welding furnace is used for heating and welding.

[0079] After cooling, the thickness of the solder layer is less than 20μm and greater than or equal to 10μm. To control the thickness, the thickness of the printing screen is selected to be less than 0.06mm. Before heating, the pressure applied to the semiconductor cooling sheet is 30-60g / mm relative to the cross-sectional area of ​​the solder layer. 2 For the above solder layer thickness, the high temperature holding time above the melting point during heating is at least 220 seconds. In addition, the thinner the solder layer thickness, the shorter the high temperature holding time required during heating and welding. When the solder layer thickness after cooling is less than 10μm, the high temperature holding time above the melting point during heating is at least 60 seconds.

[0080] Example 3.

[0081] The traditional semiconductor refrigeration chip manufacturing process includes the following steps:

[0082] (1) Slice the Bi2Te3-based material crystal rod into slices according to the required thickness using an inner circle cutting method;

[0083] (2) preparing a Ni layer with a thickness of 3 to 9 μm on the bare chip in step (1) by electroplating; and preparing an Au layer with a thickness of 0.2 to 0.5 μm on the Ni layer;

[0084] (3) cutting the wafer prepared in step (2) into semiconductor particles of 0.35×0.35 mm;

[0085] (4) sputtering a Cu metal composite layer on the insulating aluminum nitride plate;

[0086] (5) electroplating a Cu layer on the surface of the Cu metal layer of the substrate prepared in step (4) with a thickness of 15 to 25 μm; electroplating a Ni layer on the Cu layer with a thickness of 3 to 9 μm; and electroplating an Au layer on the Ni layer with a thickness of 0.2 to 0.5 μm;

[0087] (6) etching the required circuit diagram on the substrate metal layer prepared in step (5) according to the shape of the drawing;

[0088] (7) Print Au-Sn solder paste on the soldering area of ​​the substrate using a 0.08 mm thick steel mesh;

[0089] (8) The semiconductor particles prepared in step (3) and the substrate after printing the solder paste prepared in step (7) are connected by Au-Sn solder paste and welded in a vacuum furnace. The thickness of the welding layer is about 30 μm, the welding peak temperature is 310°C, and the high temperature holding time is 45 seconds. The temperature curve is shown in Figure 2.

[0090] For devices made with traditional manufacturing processes, the eutectic structure in the soldering layer accounts for more than 20%, and the bit error impact on the terminal optical communication module is 100%.

[0091] This embodiment improves upon the conventional manufacturing process and provides an improved semiconductor cooling plate manufacturing process, including the following steps:

[0092] (1) Follow the above-mentioned traditional production process to complete step (6);

[0093] (2) Printing Au-Sn solder paste on the soldering area of ​​the substrate using a 0.06 mm thick steel mesh;

[0094] (3) Assembling the semiconductor particles prepared in step (3) of the conventional manufacturing process and the substrate printed in step (2) of this embodiment by a machine;

[0095] (4) The semiconductor refrigeration sheet 16 to be heated, which is assembled in step (3), is given a relative welding layer cross-sectional area of ​​35g / mm by a special pressurizing fixture 17. 2The pressurization process is shown in Figure 4. The semiconductor cooling sheet 16 and the pressurization fixture 17 are heated and welded in a vacuum furnace. During the heating process, the peak welding temperature is 310°C, and the high temperature above the melting point of the welding layer is maintained for 303 seconds. The temperature curve is shown in Figure 3. After cooling, the thickness of the welding layer is tested to be less than 20μm.

[0096] In the device prepared in this embodiment, the eutectic structure occupancy rate in the soldering layer is less than 10%. After multiple rounds of testing, the terminal optical communication module did not generate any bit errors.

[0097] The following examples are used to compare and analyze the refrigeration fins manufactured by the manufacturing process of this embodiment with those manufactured by the traditional manufacturing process.

[0098] As shown in Figures 6a, 6b, and 6c, they are cross-sectional views of devices prepared using a traditional semiconductor refrigeration process, respectively. The area marked between the two horizontal lines is the soldering layer area after cooling, and their thicknesses are 21.59μm, 24.56μm, and 33.12μm, respectively. The thickness of the soldering layer using the traditional manufacturing process is all above 20μm, and many lines can be seen in the soldering layer area, which are eutectic structures. The eutectic structure occupancy rate in the soldering layer is above 20%, and as the thickness of the soldering layer increases, the eutectic structure occupancy rate is higher. As shown in Figure 6c, when the soldering layer thickness reaches more than 30μm, the eutectic structure occupancy rate reaches 70%-80%, which has a 100% impact on the bit error of the terminal optical communication module.

[0099] As shown in Figures 7a and 7b, they are cross-sectional views of devices prepared using the manufacturing process of this embodiment, respectively. The thickness of the welding layer area is 13.40 μm and 19.72 μm, respectively. It can be seen from the figures that the welding layer has almost no lines, the eutectic structure occupancy rate in the welding layer is less than 10%, and the smaller the thickness of the welding layer, the lower the eutectic structure occupancy rate.

[0100] Example 4.

[0101] A semiconductor refrigeration plate adopts the above-mentioned semiconductor refrigeration plate manufacturing process, as shown in Figure 5, comprising semiconductor particles 8 and a substrate with printed solder paste, wherein the upper side of the semiconductor particles 8 is provided with an upper semiconductor particle Ni-plated layer 7 and an upper semiconductor particle Au-plated layer 6 in sequence from the inside to the outside, and the lower side of the semiconductor particles 8 is provided with a lower semiconductor particle Ni-plated layer 9 and a lower semiconductor particle Au-plated layer 10 in sequence from the inside to the outside; the substrate comprises an upper substrate and a lower substrate; an upper Au-Sn soldering layer 5 is provided between the upper substrate and the upper semiconductor particle Au-plated layer 6, and a lower Au-Sn soldering layer 11 is provided between the lower substrate and the lower semiconductor particle Au-plated layer 10. This embodiment provides a semiconductor refrigeration plate, which is made by connecting semiconductor particles and a substrate with printed solder paste through solder, and then pressing them with a special jig and heating and welding them at the same time. Compared with the existing technology, the component ratio and organizational structure of the welding layer are changed, and the proportion of eutectic structure in the Au-Sn welding layer is effectively controlled to be below 10%, which effectively eliminates the contribution of the semiconductor refrigeration plate itself to the bit error problem of the optical communication module, solves the problem that the traditional semiconductor refrigeration plate manufacturing method will interfere with the signal transmission of the optical communication module and generate bit errors, and improves the intelligibility of language, clarity of image and reliability of data signals in the process of using semiconductor refrigeration plates.

[0102] The upper substrate includes an upper substrate ceramic substrate 1, an upper substrate electrode Cu layer 2, an upper substrate electrode Ni layer 3 and an upper substrate electrode Au layer 4 arranged in sequence from top to bottom; the lower substrate includes a lower substrate ceramic substrate 15, a lower substrate electrode Cu layer 14, a lower substrate electrode Ni layer 13 and a lower substrate electrode Au layer 12 arranged in sequence from bottom to top.

[0103] As shown in Figure 5, it is a schematic diagram of the metal layers and welding layers of each component of the semiconductor refrigeration plate. The semiconductor refrigeration plate includes, from top to bottom, an upper substrate ceramic base material 1, an upper substrate electrode Cu layer 2, an upper substrate electrode Ni layer 3, an upper substrate electrode Au layer 4, an upper Au-Sn welding layer 5, an upper semiconductor particle Au-plated layer 6, an upper semiconductor particle Ni-plated layer 7, semiconductor particles 8, a lower semiconductor particle Ni-plated layer 9, a lower semiconductor particle Au-plated layer 10, a lower Au-Sn welding layer 11, a lower substrate electrode Au layer 12, a lower substrate electrode Ni layer 13, a lower substrate electrode Cu layer 14, and a lower substrate ceramic base material 15.

[0104] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor refrigeration chip manufacturing process, characterized in that: The following steps are involved: Step S1: preparing semiconductor particles; Step S2: preparing a substrate for printing solder paste; Step S3: connecting the semiconductor particles prepared in step S1 and the substrate printed with solder paste prepared in step S2 by soldering to prepare a semiconductor cooling chip device; Step S4: applying a first pressure to the semiconductor refrigeration chip device to be heated by a jig through the step S3, and performing heating welding at the same time, wherein the high temperature stage is maintained for a first time period.

2. A semiconductor cooling sheet manufacturing process according to claim 1, characterized in that: The specific process of step S1 includes the following steps: Step S11: Slicing the Bi2Te3-based material crystal rod by wire cutting or inner circle cutting; Step S12: preparing a Ni layer and an Au layer on the bare chip cut in step S11 to form a wafer; Step S13: cutting the wafer prepared in step S12 into semiconductor particles of a certain size.

3. A semiconductor refrigeration sheet manufacturing process according to claim 2, characterized in that: The specific process of step S2 includes the following steps: Step S21: sputtering a copper-metal composite layer on an insulating material plate as a device substrate, wherein the insulating material is a high thermal conductivity ceramic, including aluminum nitride or aluminum oxide; Step S22: preparing a Ni layer and an Au layer on one side of the substrate prepared in step S21 by sputtering; Step S23: etching the substrate metal layer prepared in step S22 to form a required circuit diagram according to the shape of the design drawing; Step S24: Arrange solder at the welding position on the substrate prepared in step S23.

4. A semiconductor cooling sheet manufacturing process according to claim 3, characterized in that: In steps S12 and S22, the method for preparing the Ni layer and the Au layer is electroplating or chemical plating.

5. A semiconductor cooling sheet manufacturing process according to claim 3 or 4, characterized in that: In step S24, the solder is Au-Sn solder paste or solder sheet, and the solder is completed by printing, and the thickness of the screen used for printing is less than or equal to 0.06 mm.

6. A semiconductor cooling sheet manufacturing process according to claim 1, characterized in that: In step S4, a first pressure is applied to the semiconductor refrigeration device by a fixture, specifically comprising: applying a first pressure relative to the cross section of the welding layer by the fixture, the first pressure being 30 to 60 g / mm 2 .

7. A semiconductor cooling sheet manufacturing process according to claim 6, characterized in that: After cooling, the thickness of the welding layer is less than 20 μm and greater than or equal to 10 μm. In step S4, the first duration of the high temperature stage is at least 220 seconds, and the high temperature stage is a temperature stage above the melting point of the welding layer.

8. A semiconductor cooling sheet manufacturing process according to claim 6, characterized in that: After cooling, the thickness of the welding layer is less than 10 μm. In step S4, the first duration of the high temperature stage is at least 60 seconds, and the high temperature stage is a stage where the temperature is above the melting point of the welding layer.

9. A semiconductor refrigeration sheet, using a semiconductor refrigeration sheet manufacturing process as claimed in any one of claims 1 to 8, characterized in that: A substrate comprising semiconductor particles and printed solder paste, wherein an upper semiconductor particle Ni-plated layer and an upper semiconductor particle Au-plated layer are sequentially arranged on the upper side of the semiconductor particles from the inside to the outside, and a lower semiconductor particle Ni-plated layer and a lower semiconductor particle Au-plated layer are sequentially arranged on the lower side of the semiconductor particles from the inside to the outside; the substrate comprises an upper substrate and a lower substrate; an upper Au-Sn soldering layer is arranged between the upper substrate and the upper semiconductor particle Au-plated layer, and a lower Au-Sn soldering layer is arranged between the lower substrate and the lower semiconductor particle Au-plated layer.

10. The semiconductor cooling sheet according to claim 9, characterized in that: The upper substrate includes an upper substrate ceramic substrate, an upper substrate electrode Cu layer, an upper substrate electrode Ni layer and an upper substrate electrode Au layer which are arranged in sequence from top to bottom; the lower substrate includes a lower substrate ceramic substrate, a lower substrate electrode Cu layer, a lower substrate electrode Ni layer and a lower substrate electrode Au layer which are arranged in sequence from bottom to top.

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