Gate drive circuit, power conversion device, and motor unit

Abstract

One embodiment of the gate drive circuit according to the present invention drives a switching element and comprises: a charging circuit that charges the input capacitance of a switching element by applying a gate voltage to the gate terminal of the switching element; and a discharging circuit that discharges the input capacitance. The charging circuit has: a first charging path having a series circuit in which a first switch and an inductor are connected in series between a first terminal and a first node; and a second charging path in which a second switch is connected between the first terminal and the first node. When the switching element is turned on, charging is performed through the first charging path after charging through the second charging path. The discharging circuit has a configuration in which a path through which the discharge current flows from the gate terminal is switched between a first discharging path and a second discharging path having a resistance value higher than that of the first discharging path.

Description

Gate drive circuit, power conversion device, and motor unit

[0001] The present invention relates to a gate drive circuit, a power conversion device, and a motor unit.

[0002] In recent years, silicon carbide (SiC) switching elements have been attracting attention as power semiconductor switching elements that are capable of high voltage resistance, high heat resistance, and high-speed switching. However, because the transconductance of SiC switching elements is low, the conduction resistance does not decrease until a sufficiently high voltage is applied to the gate terminal, resulting in conduction loss.

[0003] High-speed switching of the switching element reduces losses, but increases noise and surges. When the switching element is turned on, a reverse recovery current generated by the body diode parasitic to the switching element is superimposed on the current waveform of the switching element. When the switching element is switched at high speed, the reverse recovery current becomes steep, which increases noise and surges. When the switching element is turned off, a surge voltage is generated due to the parasitic inductance component of the current path of the switching element.

[0004] For example, Japanese Patent Laid-Open Publication No. 2005-039988 discloses a gate drive circuit for driving a switching element, which has a circuit configuration that reduces switching loss and noise.

[0005] Japanese Patent Publication No. 2005-039988

[0006] As described above, there has been a demand for the development of a gate drive circuit that can simultaneously reduce the switching loss of the switching element to be driven and suppress noise and surges that occur during switching.

[0007] The present invention has been proposed in view of the above circumstances, and aims to provide a gate drive circuit that can reduce switching loss in the switching element to be driven and suppress noise and surges that occur during switching, as well as a power conversion device and a motor unit that include the gate drive circuit.

[0008] One aspect of the gate drive circuit of the present invention is a gate drive circuit that drives a switching element, comprising: a charging circuit that charges an input capacitance of the switching element by applying a gate voltage to a gate terminal of the switching element; and a discharging circuit that discharges the input capacitance, wherein the charging circuit has a first charging path having a series circuit in which a first switch and an inductor are connected in series between a first terminal and a first node, and a second charging path in which a second switch is connected between the first terminal and the first node, and when the switching element is turned on, charging is performed via the second charging path, and then charging is performed via the first charging path, and the discharging circuit is configured to switch a path through which a discharge current flows from the gate terminal between the first discharging path and a second discharging path that has a higher resistance than the first discharging path.

[0009] One aspect of the power conversion device of the present invention includes a bridge circuit having a plurality of switching elements, a plurality of gate drive circuits provided corresponding to each of the plurality of switching elements and driving the corresponding switching elements, and a control unit controlling the plurality of gate drive circuits, wherein each of the plurality of gate drive circuits includes a charging circuit that charges an input capacitance of the corresponding switching element by applying a gate voltage to a gate terminal of the corresponding switching element, and a discharging circuit that discharges the input capacitance, wherein the charging circuit has a first charging path including a series circuit in which a first switch and an inductor are connected in series between a first terminal and a first node, and a second charging path in which a second switch is connected between the first terminal and the first node, wherein when the switching element is turned on, charging is performed via the second charging path and then via the first charging path, and the discharging circuit is configured to switch a path through which a discharge current flows from the gate terminal between a first discharging path and a second discharging path having a higher resistance than the first discharging path.

[0010] One aspect of the motor unit of the present invention includes a motor and the power conversion device of the above aspect that supplies power to the motor.

[0011] According to the above aspects of the present invention, it is possible to provide a gate drive circuit that can reduce the switching loss of the switching element to be driven and suppress the noise and surges that occur during switching, as well as a power conversion device and a motor unit that include the gate drive circuit.

[0012] FIG. 1 is a diagram schematically illustrating the configuration of a motor unit 1 according to a first embodiment. FIG. 2 is a circuit diagram of a gate drive circuit GDA according to the first embodiment. FIG. 3 is a first diagram illustrating the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. FIG. 4 is a second diagram illustrating the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. FIG. 5 is a third diagram illustrating the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. FIG. 6 is a fourth diagram illustrating the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned on. FIG. 7 is a diagram illustrating an example of the waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned on. FIG. 8 is a first diagram illustrating the path of a current flowing through the gate drive circuit GDA when the switching element TR is turned off. FIG. 9 is a second diagram showing the path of current flowing through the gate drive circuit GDA when the switching element TR is turned off. FIG. 10 is a diagram showing an example of the waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned off. FIG. 11 is a diagram showing a specific example of the gate drive circuit GDA. FIG. 12 is a circuit configuration diagram of the gate drive circuit GDB in the second embodiment. FIG. 13 is a first diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. FIG. 14 is a second diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. FIG. 15 is a third diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. FIG. 16 is a fourth diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. Fig. 17 is a first diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned off. Fig. 18 is a second diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned off. Fig. 19 is a diagram showing a specific example of the gate drive circuit GDB. Fig. 20 is a circuit configuration diagram showing a first modified example of the gate drive circuit GDA.Fig. 21 is a circuit diagram showing a second modified example of the gate drive circuit GDA. Fig. 22 is a circuit diagram showing a third modified example of the gate drive circuit GDA. Fig. 23 is a circuit diagram showing a fourth modified example of the gate drive circuit GDA. Fig. 24 is a circuit diagram showing a fifth modified example of the gate drive circuit GDA. Fig. 25 is a circuit diagram showing a first modified example of the gate drive circuit GDB. Fig. 26 is a circuit diagram showing a second modified example of the gate drive circuit GDB. Fig. 27 is a circuit diagram showing a sixth modified example of the gate drive circuit GDA.

[0013] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0014] First Embodiment First, a first embodiment of the present invention will be described. FIG. 1 is a diagram schematically illustrating the configuration of a motor unit 1 in the first embodiment. As shown in FIG. 1, the motor unit 1 includes a motor 10 and a power conversion device 20. For example, the motor unit 1 is a drive motor unit mounted on an electric vehicle. Electric vehicles include electric vehicles, hybrid vehicles, plug-in hybrid vehicles, and fuel cell vehicles. For example, the motor 10 is a three-phase AC motor. The power conversion device 20 supplies power to the motor 10.

[0015] The power conversion device 20 is connected to the motor 10 and the first DC power source 2, and performs mutual conversion between DC power and three-phase AC power. For example, when the power conversion device 20 functions as an inverter, the power conversion device 20 converts DC power supplied from the first DC power source 2 into three-phase AC power and outputs it to the motor 10. For example, the first DC power source 2 is a drive battery that outputs a relatively high DC voltage among multiple batteries mounted on the electric vehicle.

[0016] The power conversion device 20 includes a bridge circuit 21, six gate drive circuits GD1 to GD6, a control unit 22, a smoothing capacitor 23, and a power supply circuit 24. In this embodiment, the bridge circuit 21 is a three-phase full-bridge circuit having six switching elements TR1 to TR6. In this embodiment, the switching elements TR1 to TR6 included in the bridge circuit 21 are, for example, N-channel MOS-FETs (Metal-Oxide-Semiconductor Field-Effect Transistors). The switching elements TR1 to TR6 may also be IGBTs (Insulated-Gate Bipolar Transistors). Furthermore, the switching elements TR1 to TR6 may be SiC switching elements or Si switching elements.

[0017] The switching elements TR1, TR3, and TR5 are high-side switches of the bridge circuit 21. The drain terminals of the switching elements TR1, TR3, and TR5 are connected to the positive terminal of the first DC power supply 2. The switching elements TR2, TR4, and TR6 are low-side switches of the bridge circuit 21. The source terminals of the switching elements TR2, TR4, and TR6 are connected to the negative terminal of the first DC power supply 2.

[0018] The source terminal of switching element TR1 is connected to the drain terminal of switching element TR2 and the U-phase terminal of motor 10. The source terminal of switching element TR3 is connected to the drain terminal of switching element TR4 and the V-phase terminal of motor 10. The source terminal of switching element TR5 is connected to the drain terminal of switching element TR6 and the W-phase terminal of motor 10.

[0019] The switching element TR1 has a parasitic body diode BD1 between the drain and source of the switching element TR1. In an equivalent circuit, the anode terminal of the body diode BD1 is connected to the source terminal of the switching element TR1, and the cathode terminal of the body diode BD1 is connected to the drain terminal of the switching element TR1.

[0020] Like the switching element TR1, the switching element TR2 has a body diode BD2. The switching element TR3 has a body diode BD3. The switching element TR4 has a body diode BD4. The switching element TR5 has a body diode BD5. The switching element TR6 has a body diode BD6.

[0021] The six gate drive circuits GD1 to GD6 are provided corresponding to the six switching elements TR1 to TR6, respectively, and drive the corresponding switching elements. Note that "driving a switching element" includes turning on the switching element by charging the input capacitance of the switching element, and turning off the switching element by discharging the input capacitance of the switching element.

[0022] The gate drive circuit GD1 is provided corresponding to the switching element TR1, and drives the switching element TR1 in accordance with a control signal input from the control unit 22. The gate drive circuit GD1 is connected to the gate terminal and source terminal of the switching element TR1. The gate drive circuit GD2 is provided corresponding to the switching element TR2, and drives the switching element TR2 in accordance with a control signal input from the control unit 22. The gate drive circuit GD2 is connected to the gate terminal and source terminal of the switching element TR2.

[0023] The gate drive circuit GD3 is provided corresponding to the switching element TR3, and drives the switching element TR3 in accordance with a control signal input from the control unit 22. The gate drive circuit GD3 is connected to the gate terminal and source terminal of the switching element TR3. The gate drive circuit GD4 is provided corresponding to the switching element TR4, and drives the switching element TR4 in accordance with a control signal input from the control unit 22. The gate drive circuit GD4 is connected to the gate terminal and source terminal of the switching element TR4.

[0024] The gate drive circuit GD5 is provided corresponding to the switching element TR5, and drives the switching element TR5 in accordance with a control signal input from the control unit 22. The gate drive circuit GD5 is connected to the gate terminal and source terminal of the switching element TR5. The gate drive circuit GD6 is provided corresponding to the switching element TR6, and drives the switching element TR6 in accordance with a control signal input from the control unit 22. The gate drive circuit GD6 is connected to the gate terminal and source terminal of the switching element TR6.

[0025] As will be described in detail later, the six gate drive circuits GD1 to GD6 each have the same circuit configuration. In the following description, when there is no need to distinguish between the gate drive circuits GD1 to GD6, the gate drive circuits GD1 to GD6 will be collectively referred to as gate drive circuit GDA. In the following description, the switching elements TR1 to TR6 will sometimes be collectively referred to as switching elements TR, and the body diodes BD1 to BD6 will sometimes be collectively referred to as body diodes BD.

[0026] The control unit 22 controls each of the gate drive circuits GD1 to GD6 by outputting a control signal to each of the gate drive circuits GD1 to GD6. As will be described in detail later, the control signal output from the control unit 22 controls the on and off timings of the first switch SW1, second switch SW2, third switch SW3, fourth switch SW4, and fifth switch SW5 included in each of the gate drive circuits GD1 to GD6.

[0027] For example, the control unit 22 has a function of communicating with an ECU (Electronic Control Unit) mounted on the electric vehicle. The control unit 22 receives a rotation speed command signal from the ECU, which is a higher-level control device, and outputs a control signal to each of the gate drive circuits GD1 to GD6 to rotate the motor 10 at a target rotation speed indicated by the rotation speed command signal. For example, the control unit 22 is a processor with a built-in memory (not shown). As an example, the control unit 22 is an MCU (Microcontroller Unit). The control unit 22 controls the gate drive circuits GD1 to GD6 in accordance with a program pre-stored in the memory.

[0028] The smoothing capacitor 23 is a capacitor connected in parallel with the first DC power supply 2. Note that the smoothing capacitor 23 does not necessarily have to be disposed inside the power conversion device 20, and may be disposed outside the power conversion device 20.

[0029] The power supply circuit 24 is connected to the second DC power supply 3. For example, the second DC power supply 3 is one of multiple batteries mounted on the electric vehicle that outputs a relatively low DC voltage. From the DC voltage supplied from the second DC power supply 3, the power supply circuit 24 generates a first power supply voltage Vdd used as a power supply voltage for each of the gate drive circuits GD1 to GD6 and a second power supply voltage Vc used as a power supply voltage for the control unit 22.

[0030] The power supply circuit 24 outputs a first power supply voltage Vdd to each of the gate drive circuits GD1 to GD6, and outputs a second power supply voltage Vc to the control unit 22. For example, the power supply circuit 24 is a regulator or a DC-DC converter. Note that the DC voltage output from the first DC power supply 2 may be used as the first power supply voltage Vdd supplied to each of the gate drive circuits GD1 to GD6.

[0031] The configuration of the gate drive circuit GDA in the first embodiment will be described in detail below with reference to Fig. 2. Fig. 2 is a circuit configuration diagram of the gate drive circuit GDA. As shown in Fig. 2, the gate drive circuit GDA includes a first terminal P1, a second terminal P2, a third terminal P3, a fourth terminal P4, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, an inductor L1, a first diode D1, and a resistor Rg.

[0032] The first terminal P1 is a terminal to which a first potential V1 is applied. The second terminal P2 is a terminal to which a second potential V2 lower than the first potential V1 is applied. The potential difference between the first potential V1 and the second potential V2 is equal to the first power supply voltage Vdd output from the power supply circuit 24. In other words, the first power supply voltage Vdd output from the power supply circuit 24 is input to the gate drive circuit GDA via the first terminal P1 and the second terminal P2.

[0033] The third terminal P3 is connected to the gate terminal of the switching element TR corresponding to the gate drive circuit GDA. The fourth terminal P4 is connected to the source terminal of the switching element TR. For example, if the switching element TR is an IGBT, the fourth terminal P4 is connected to the emitter terminal of the switching element TR. The fourth terminal P4 is also directly connected to the second terminal P2.

[0034] The first switch SW1 is connected in series with the inductor L1. A series circuit in which the first switch SW1 and the inductor L1 are connected in series is connected between the first terminal P1 and the second node N2. The first switch SW1 is connected between the first terminal P1 and the inductor L1. Note that the positions of the first switch SW1 and the inductor L1 may be reversed. In other words, the inductor L1 may be connected between the first terminal P1 and the first switch SW1.

[0035] The second switch SW2 is connected between the first terminal P1 and the first node N1. The third switch SW3 is connected between the second terminal P2 and the second node N2. The fourth switch SW4 is connected between the second terminal P2 and the first node N1. The fifth switch SW5 is connected between the first node N1 and the second node N2. The first diode D1 has an anode terminal connected to the second node N2 and a cathode terminal connected to the first node N1.

[0036] The resistor element Rg is connected between the first node N1 and the third terminal P3. That is, the third terminal P3 is indirectly connected to the first node N1 via the resistor element Rg. The resistor element Rg serves as a gate resistor that limits the current flowing to the gate terminal of the switching element TR. The resistor element Rg may be connected between the gate terminal of the switching element TR and the third terminal P3. In this case, the third terminal P3 is directly connected to the first node N1. In this way, the third terminal P3 is directly or indirectly connected to the first node N1.

[0037] In this embodiment, the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 may be configured with a single switching element such as a MOS-FET, or may be configured with a series-connected switching element and a resistive element. When each switch is configured with a single switching element, the switching element itself may have a conductive resistance.

[0038] The gate drive circuit GDA includes a charging circuit that charges the input capacitance of the switching element TR by applying a gate voltage to the gate terminal of the switching element TR, and a discharging circuit that discharges the input capacitance of the switching element TR. The charging circuit includes the first switch SW1, the second switch SW2, the third switch SW3, the inductor L1, and the first diode D1 from among the above components. The discharging circuit includes the third switch SW3, the fourth switch SW4, and the fifth switch SW5 from among the above components.

[0039] The charging circuit has a first charging path having a series circuit in which a first switch SW1 and an inductor L1 are connected in series between a first terminal P1 and a first node N1, and a second charging path in which a second switch SW2 is connected between the first terminal P1 and the first node N1. In this embodiment, the first charging path not only has the first switch SW1 and inductor L1 connected in series between the first terminal P1 and a second node N2, but also a first diode D1 connected between the first node N1 and the second node N2. As will be described in detail later, when the switching element TR is turned on, the charging circuit first charges via the second charging path and then via the first charging path.

[0040] The discharge circuit has a configuration that switches the path through which a discharge current flows from the gate terminal of the switching element TR between a first discharge path and a second discharge path having a higher resistance value than the first discharge path. When the switching element TR is turned off, the discharge circuit discharges through the first discharge path and then through the second discharge path. The configuration and operation of such a discharge circuit will be described later.

[0041] Hereinafter, the operation of the gate drive circuit GDA when the switching element TR is turned on will be described with reference to FIGS.

[0042] 3 is a first diagram showing the path of current flowing through the gate drive circuit GDA when the switching element TR is turned on. As shown in FIG. 3, when the control unit 22 turns on the switching element TR, at a first timing, the control unit 22 turns on the first switch SW1 and the third switch SW3 and turns off the second switch SW2 and the fifth switch SW5. As a result, after the first timing, current flows through the path indicated by the dotted arrow in FIG. 3.

[0043] That is, after the first timing, current flows in the order of the first terminal P1, the first switch SW1, the inductor L1, the second node N2, the third switch SW3, and the second terminal P2. As a result, energy is stored in the inductor L1 after the first timing. Note that, as shown in FIG. 3 , the fourth switch SW4 may be turned off at the first timing, but it is desirable that the fourth switch SW4 be on at the first timing to prevent the gate voltage of the switching element TR from becoming unstable.

[0044] 4 is a second diagram showing the path of current flowing through the gate drive circuit GDA when the switching element TR is turned on. As shown in FIG. 4, the control unit 22 turns on the second switch SW2 and turns off the fourth switch SW4 at a second timing after the first timing. As a result, from the second timing onwards, current flows through the path indicated by the dotted arrow in FIG. 4.

[0045] That is, after the second timing, in addition to the current flowing in the order of the first terminal P1, the first switch SW1, the inductor L1, the second node N2, the third switch SW3, and the second terminal P2, the current also flows in the order of the first terminal P1, the second switch SW2, the first node N1, and the resistor Rg, and the current flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the second timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and at the same time, energy is stored in the inductor L1.

[0046] 7 is a diagram showing an example of the waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned on. In FIG. 7, time t1 corresponds to the second timing. As shown in FIG. 7, after time t1, which corresponds to the second timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and the conductive resistance of the switching element TR decreases over time, so that the drain current Id increases over time.

[0047] In the above description, an example has been shown in which the control unit 22 turns on the second switch SW2 and turns off the fourth switch SW4 at the second timing, but the present invention is not limited to this. The control unit 22 may turn on the first switch SW1, the second switch SW2, and the third switch SW3 and turn off the fourth switch SW4 and the fifth switch SW5 at the first timing. In this case, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and energy is stored in the inductor L1.

[0048] Alternatively, the control unit 22 may turn on the second switch SW2 and turn off the first switch SW1, the third switch SW3, the fourth switch SW4, and the fifth switch SW5 before the first timing, and then turn on the first switch SW1 and the third switch SW3 at the first timing. In this case, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd before the first timing, and after the first timing, energy is stored in the inductor L1 at the same time that the input capacitance of the switching element TR is charged with the first power supply voltage Vdd.

[0049] 5 is a third diagram showing the path of current flowing through the gate drive circuit GDA when the switching element TR is turned on. As shown in FIG. 5, the control unit 22 turns off the second switch SW2 and the third switch SW3 at a third timing after the second timing. As a result, from the third timing onwards, current flows through the path indicated by the dotted arrow in FIG. 5.

[0050] That is, after the third timing, current flows in the order of the first terminal P1, the first switch SW1, the inductor L1, the second node N2, the first diode D1, the first node N1, and the resistor Rg, and then flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the third timing, the energy stored in the inductor L1 is released as current, causing the potential of the first node N1 to become higher than the first power supply voltage Vdd and increasing the current flowing into the gate terminal of the switching element TR. As a result, after the third timing, the input capacitance of the switching element TR is charged with a voltage higher than the first power supply voltage Vdd, and the charging speed of the input capacitance of the switching element TR increases.

[0051] In Figure 7, time t2 corresponds to the third timing. As shown in Figure 7, the third timing (time t2) is a time point after the time point at which the peak of the reverse recovery current appears in the drain current Id. In other words, the third timing is set in advance as a time point after the time point at which the peak of the reverse recovery current appears in the drain current Id, and the control unit 22 turns off the second switch SW2 and the third switch SW3 at this preset third timing. Note that the third timing is set as appropriate depending on the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0052] 6 is a fourth diagram showing the path of current flowing through the gate drive circuit GDA when the switching element TR is turned on. As shown in FIG. 6, the control unit 22 turns on the second switch SW2 after the third timing, at a timing just before or after all of the energy stored in the inductor L1 is released as current. As a result, after all of the energy stored in the inductor L1 is released as current, current flows through the path indicated by the dotted arrow in FIG. 6.

[0053] That is, after all the energy stored in inductor L1 is released as current, current flows in the order of first terminal P1, second switch SW2, first node N1, and resistor Rg, and then flows into the gate terminal of switching element TR via third terminal P3. As a result, after all the energy stored in inductor L1 is released as current, the input capacitance of switching element TR is again charged with the first power supply voltage Vdd. Note that, although the first switch SW1 is turned off in FIG. 6, the first switch SW1 may also be turned on when the second switch SW2 is turned on.

[0054] 7, time t3 corresponds to the point in time before and after all the energy stored in inductor L1 is released as current. As shown in Fig. 7, for example, when switching element TR is fully turned on at time t3, drain-source voltage Vds becomes approximately 0 V at time t3, and drain current Id is maintained at a constant value after time t3.

[0055] As described above, when the switching element TR is turned on, the gate drive circuit GDA is controlled so that the charging rate of the input capacitance of the switching element TR increases from the third timing, which is a time point after the time point at which the reverse recovery current peaks in the drain current Id. This makes it possible to reduce switching loss during turn-on while suppressing noise and surges caused by the reverse recovery current. In particular, because the charging rate increases in the latter half of the turn-on operation, an overdrive voltage can be quickly applied to the gate terminal of the switching element TR. As a result, conduction loss during the latter half of the turn-on operation can be suppressed.

[0056] As can be understood from the above description, the charging circuit provided in the gate drive circuit GDA has a first charging path having a series circuit in which a first switch SW1 and an inductor L1 are connected in series between a first terminal P1 and a first node N1, and a second charging path in which a second switch SW2 is connected between the first terminal P1 and the first node N1. It can also be understood from the above description that when the switching element TR is turned on, the charging circuit performs charging via the second charging path and then via the first charging path.

[0057] Next, the operation of the gate drive circuit GDA when the switching element TR is turned off will be described with reference to FIGS.

[0058] 8 is a first diagram showing the path of current flowing through the gate drive circuit GDA when the switching element TR is turned off. When the control unit 22 turns off the first switch SW1 and the second switch SW2 and turns on the third switch SW3, the fourth switch SW4, and the fifth switch SW5 at a fourth timing, the control unit 22 turns off the first switch SW1 and the second switch SW2 and turns on the third switch SW3, the fourth switch SW4, and the fifth switch SW5. As a result, from the fourth timing onwards, the current flows through the path indicated by the dotted arrow in FIG. 8.

[0059] That is, after the fourth timing, current flows in the order of the third terminal P3, the resistive element Rg, the first node N1, and the fourth switch SW4, and at the same time, current flows in the order of the first node N1, the fifth switch SW5, the second node N2, and the third switch SW3, and the current is released to the wiring connected to the source terminal of the switching element TR via the fourth terminal P4.

[0060] 10 is a diagram showing an example of the waveforms of the drain-source voltage Vds and the drain current Id of the switching element TR when the switching element TR is turned off. In Fig. 10, time t4 corresponds to the fourth timing. As shown in Fig. 10, after time t4, which corresponds to the fourth timing, a discharge current flows through the path shown in Fig. 8, and the conduction resistance of the switching element TR increases over time, so that the drain-source voltage Vds increases over time.

[0061] 9 is a second diagram showing the path of current flowing through the gate drive circuit GDA when the switching element TR is turned off. At a fifth timing after the fourth timing, the control unit 22 turns off at least one of the third switch SW3 and the fifth switch SW5. As a result, from the fifth timing onwards, current flows through the path indicated by the dotted arrow in FIG. 9. Note that FIG. 9 shows an example in which only the fifth switch SW5 is turned off.

[0062] That is, from the fifth timing onwards, current flows in the order of the third terminal P3, the resistive element Rg, the first node N1 and the fourth switch SW4, and the current is released via the fourth terminal P4 to the wiring connected to the source terminal of the switching element TR.

[0063] 10 , time t5 corresponds to the fifth timing. As shown in FIG. 10 , the fifth timing (time t5) is a time point before the peak of the surge voltage appears in the drain-source voltage Vds. In other words, the fifth timing is preset as a time point before the peak of the surge voltage appears in the drain-source voltage Vds, and the control unit 22 turns off at least one of the third switch SW3 and the fifth switch SW5 at this preset fifth timing. The fifth timing is set as appropriate depending on the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0064] As described above, when the switching element TR is turned off, the input capacitance of the switching element TR is discharged through two discharge paths at the beginning of the turn-off operation: one including the third switch SW3 and the fifth switch SW5, and the other including the fourth switch SW4. This increases the discharge rate of the input capacitance of the switching element TR, thereby reducing switching loss during turn-off. Furthermore, from the fifth timing, which is a point in time before the peak of the surge voltage appears in the drain-source voltage Vds, the input capacitance of the switching element TR is discharged only through the discharge path including the fourth switch SW4. This reduces the discharge rate before the peak of the surge voltage appears in the drain-source voltage Vds, thereby reducing the height of the surge voltage peak. As a result, noise and surges generated during turn-off can be suppressed.

[0065] As can be understood from the above description, the discharge circuit included in the gate drive circuit GDA is configured to switch the path through which a discharge current flows from the gate terminal of the switching element TR between a first discharge path and a second discharge path having a higher resistance value than the first discharge path. The first discharge path includes two discharge paths: one including the third switch SW3 and the fifth switch SW5, and the other including the fourth switch SW4. The second discharge path is a discharge path including the fourth switch SW4. It can also be understood from the above description that, when the switching element TR is turned off, the discharge circuit discharges along the first discharge path and then along the second discharge path.

[0066] As described above, the gate drive circuit GDA of the first embodiment can reduce the switching loss of the switching element TR to be driven, while suppressing noise and surges that occur during switching.

[0067] 11 is a diagram showing a specific example of the gate drive circuit GDA. As shown in Fig. 11, in the gate drive circuit GDA, the first switch SW1 and the second switch SW2 are preferably P-channel MOS-FETs, and the third switch SW3, the fourth switch SW4, and the fifth switch SW5 are preferably N-channel MOS-FETs.

[0068] The first switch SW1 has a first body diode SD1 parasitic between the drain and source of the first switch SW1, i.e., a P-channel MOS-FET. In an equivalent circuit, the anode terminal of the first body diode SD1 is connected to the drain terminal of the first switch SW1, and the cathode terminal of the first body diode SD1 is connected to the source terminal of the first switch SW1.

[0069] The source terminal of the first switch SW1 is connected to the first terminal P1. The drain terminal of the first switch SW1 is connected to the inductor L1 and is also connected to the second node N2 via the inductor L1. The gate terminal of the first switch SW1 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the first switch SW1.

[0070] The second switch SW2 has a second body diode SD2 parasitic between the drain and source of the second switch SW2, i.e., a P-channel MOS-FET. In an equivalent circuit, the anode terminal of the second body diode SD2 is connected to the drain terminal of the second switch SW2, and the cathode terminal of the second body diode SD2 is connected to the source terminal of the second switch SW2.

[0071] The source terminal of the second switch SW2 is connected to the first terminal P1. The drain terminal of the second switch SW2 is connected to the first node N1. The gate terminal of the second switch SW2 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the second switch SW2.

[0072] The third switch SW3 has a third body diode SD3 parasitic between the drain and source of the third switch SW3, i.e., an N-channel MOS-FET. In an equivalent circuit, the anode terminal of the third body diode SD3 is connected to the source terminal of the third switch SW3, and the cathode terminal of the third body diode SD3 is connected to the drain terminal of the third switch SW3.

[0073] The source terminal of the third switch SW3 is connected to the second terminal P2. The drain terminal of the third switch SW3 is connected to the second node N2. The gate terminal of the third switch SW3 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the third switch SW3.

[0074] The fourth switch SW4 has a fourth body diode SD4 parasitic between the drain and source of the fourth switch SW4, i.e., an N-channel MOS-FET. In an equivalent circuit, the anode terminal of the fourth body diode SD4 is connected to the source terminal of the fourth switch SW4, and the cathode terminal of the fourth body diode SD4 is connected to the drain terminal of the fourth switch SW4.

[0075] The source terminal of the fourth switch SW4 is connected to the second terminal P2. The drain terminal of the fourth switch SW4 is connected to the first node N1. The gate terminal of the fourth switch SW4 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the fourth switch SW4.

[0076] The fifth switch SW5 has a fifth body diode SD5 parasitic between the drain and source of the fifth switch SW5, i.e., an N-channel MOS-FET. In an equivalent circuit, the anode terminal of the fifth body diode SD5 is connected to the source terminal of the fifth switch SW5, and the cathode terminal of the fifth body diode SD5 is connected to the drain terminal of the fifth switch SW5.

[0077] The source terminal of the fifth switch SW5 is connected to the second node N2. The drain terminal of the fifth switch SW5 is connected to the first node N1. The gate terminal of the fifth switch SW5 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the fifth switch SW5. As can be understood by comparing FIGS. 2 and 11 , a fifth body diode SD5 parasitic on the fifth switch SW5 can be used as the first diode D1.

[0078] When the fifth switch SW5 is turned on at the fourth timing, the third switch SW3 is also on, so the source potential of the fifth switch SW5 is equal to the negative potential of the first power supply voltage Vdd, i.e., the second potential V2. Therefore, when the fifth switch SW5 is turned on at the fourth timing, the first power supply voltage Vdd or a voltage obtained by dividing the first power supply voltage Vdd is applied to the gate terminal of the fifth switch SW5.

[0079] To turn on the first switch SW1 and the second switch SW2, the second potential V2 or a potential between the first potential V1 and the second potential V2 may be applied to the respective gate terminals. To turn on the third switch SW3 and the fourth switch SW4, the first potential V1 or a potential between the first potential V1 and the second potential V2 may be applied to the respective gate terminals. In other words, the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 can be driven within a voltage range between the first potential V1 and the second potential V2.

[0080] Second Embodiment Next, a second embodiment of the present invention will be described. The second embodiment differs from the first embodiment in that the power conversion device 20 includes a gate drive circuit GDB having a different configuration from the gate drive circuit GDA. In other words, in the second embodiment, the configuration of the power conversion device 20 other than the gate drive circuit GDB and the configuration of the motor unit 1 are the same as in the first embodiment, so below only the configuration and operation of the gate drive circuit GDB will be described.

[0081] Fig. 12 is a circuit configuration diagram of the gate drive circuit GDB in the second embodiment. As can be understood by comparing Fig. 12 with Fig. 2, the gate drive circuit GDB in the second embodiment differs from the gate drive circuit GDA in the first embodiment in that it includes a sixth switch SW6 instead of the fifth switch SW5.

[0082] In the gate drive circuit GDB, only the first diode D1 is connected between the first node N1 and the second node N2. The sixth switch SW6 is connected between the second terminal P2 and the first node N1. In other words, the sixth switch SW6 is connected in parallel with the fourth switch SW4. More specifically, one end of the sixth switch SW6 is connected to the second terminal P2, and the other end of the sixth switch SW6 is connected to the first node N1.

[0083] The charging circuit of the gate drive circuit GDB includes a first switch SW1, a second switch SW2, a third switch SW3, an inductor L1, and a first diode D1, and the discharging circuit of the gate drive circuit GDB includes a fourth switch SW4 and a sixth switch SW6.

[0084] Hereinafter, the operation of the gate drive circuit GDB when the switching element TR is turned on will be described with reference to FIGS.

[0085] 13 is a first diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. As shown in FIG. 13, when the control unit 22 turns on the switching element TR, at a first timing, the control unit 22 turns on the first switch SW1 and the third switch SW3 and turns off the second switch SW2. As a result, after the first timing, current flows through the path indicated by the dotted arrow in FIG. 13.

[0086] That is, after the first timing, current flows in the order of the first terminal P1, the first switch SW1, the inductor L1, the second node N2, the third switch SW3, and the second terminal P2. As a result, energy is stored in the inductor L1 after the first timing. As shown in FIG. 13 , the fourth switch SW4 and the sixth switch SW6 may be turned off at the first timing, but it is desirable that at least one of the fourth switch SW4 and the sixth switch SW6 be on at the first timing to prevent the gate voltage of the switching element TR from becoming unstable.

[0087] 14 is a second diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. As shown in FIG. 14, at a second timing after the first timing, the control unit 22 turns on the second switch SW2 and turns off the fourth switch SW4 and the sixth switch SW6. As a result, from the second timing onwards, current flows through the path indicated by the dotted arrow in FIG. 14.

[0088] That is, after the second timing, in addition to the current flowing in the order of the first terminal P1, the first switch SW1, the inductor L1, the second node N2, the third switch SW3, and the second terminal P2, the current also flows in the order of the first terminal P1, the second switch SW2, the first node N1, and the resistor Rg, and the current flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the second timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and at the same time, energy is stored in the inductor L1.

[0089] In the above description, an example has been shown in which the control unit 22 turns on the second switch SW2 and turns off the fourth switch SW4 and the sixth switch SW6 at the second timing, but the present invention is not limited to this. The control unit 22 may turn on the first switch SW1, the second switch SW2, and the third switch SW3 and turn off the fourth switch SW4 and the sixth switch SW6 at the first timing. In this case, after the first timing, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd, and energy is stored in the inductor L1.

[0090] Alternatively, the control unit 22 may turn on the second switch SW2 and turn off the first switch SW1, the third switch SW3, the fourth switch SW4, and the sixth switch SW6 before the first timing, and then turn on the first switch SW1 and the third switch SW3 at the first timing. In this case, the input capacitance of the switching element TR is charged with the first power supply voltage Vdd before the first timing, and after the first timing, energy is stored in the inductor L1 at the same time that the input capacitance of the switching element TR is charged with the first power supply voltage Vdd.

[0091] 15 is a third diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. As shown in FIG. 15, the control unit 22 turns off the second switch SW2 and the third switch SW3 at a third timing after the second timing. As a result, from the third timing onwards, current flows through the path indicated by the dotted arrow in FIG. 15.

[0092] That is, after the third timing, current flows in the order of the first terminal P1, the first switch SW1, the inductor L1, the second node N2, the first diode D1, the first node N1, and the resistor Rg, and then flows into the gate terminal of the switching element TR via the third terminal P3. As a result, after the third timing, the energy stored in the inductor L1 is released as current, causing the potential of the first node N1 to become higher than the first power supply voltage Vdd and increasing the current flowing into the gate terminal of the switching element TR. As a result, after the third timing, the input capacitance of the switching element TR is charged with a voltage higher than the first power supply voltage Vdd, and the charging speed of the input capacitance of the switching element TR increases.

[0093] As in the first embodiment, in the second embodiment, the third timing is preset as a time point after the time point at which the reverse recovery current peak appears in the drain current Id, and the control unit 22 turns off the second switch SW2 and the third switch SW3 at the preset third timing. Note that the third timing is set as appropriate depending on the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0094] 16 is a fourth diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned on. As shown in FIG. 16, the control unit 22 turns on the second switch SW2 after the third timing, at a timing just before or after all of the energy stored in the inductor L1 is released as current. As a result, after all of the energy stored in the inductor L1 is released as current, current flows through the path indicated by the dotted arrow in FIG. 16.

[0095] That is, after all the energy stored in inductor L1 is released as current, current flows in the order of first terminal P1, second switch SW2, first node N1, and resistor Rg, and then flows into the gate terminal of switching element TR via third terminal P3. As a result, after all the energy stored in inductor L1 is released as current, the input capacitance of switching element TR is charged again with the first power supply voltage Vdd. Note that, although the first switch SW1 is turned off in FIG. 16 , the first switch SW1 may also be turned on when the second switch SW2 is turned on.

[0096] As described above, when the switching element TR is turned on, the gate drive circuit GDB is controlled so that the charging rate of the input capacitance of the switching element TR increases from the third timing, which is a time point after the time point at which the reverse recovery current peaks in the drain current Id. This makes it possible to reduce switching loss during turn-on while suppressing the generation of noise and surges caused by the reverse recovery current. In particular, because the charging rate increases in the latter half of the turn-on operation, an overdrive voltage can be quickly applied to the gate terminal of the switching element TR. As a result, conduction loss during the latter half of the turn-on operation can be suppressed.

[0097] As can be understood from the above description, the charging circuit provided in the gate drive circuit GDB has a first charging path having a series circuit in which a first switch SW1 and an inductor L1 are connected in series between a first terminal P1 and a first node N1, and a second charging path in which a second switch SW2 is connected between the first terminal P1 and the first node N1. It can also be understood from the above description that when the switching element TR is turned on, the charging circuit performs charging via the second charging path and then via the first charging path.

[0098] Next, the operation of the gate drive circuit GDB when the switching element TR is turned off will be described with reference to FIGS.

[0099] 17 is a first diagram showing the path of a current flowing through the gate drive circuit GDB when the switching element TR is turned off. When the control unit 22 turns off the first switch SW1 and the second switch SW2 and turns on the fourth switch SW4 and the sixth switch SW6 at a fourth timing, the control unit 22 turns off the first switch SW1 and the second switch SW2 and turns on the fourth switch SW4 and the sixth switch SW6. As a result, from the fourth timing onwards, a current flows through the path indicated by the dotted arrow in FIG. 17 .

[0100] That is, after the fourth timing, a current flows in the order of the third terminal P3, the resistor element Rg, the first node N1, and the fourth switch SW4, and at the same time, a current flows in the order of the third terminal P3, the resistor element Rg, and the sixth switch SW6, and is discharged to the wiring connected to the source terminal of the switching element TR via the fourth terminal P4. Note that although the third switch SW3 is turned off in Fig. 17, the third switch SW3 may be turned on at the fourth timing.

[0101] 18 is a second diagram showing the path of current flowing through the gate drive circuit GDB when the switching element TR is turned off. The control unit 22 turns off the sixth switch SW6 at a fifth timing after the fourth timing. As a result, from the fifth timing onwards, current flows through the path indicated by the dotted arrow in FIG. 18.

[0102] That is, from the fifth timing onwards, current flows in the order of the third terminal P3, the resistive element Rg, the first node N1 and the fourth switch SW4, and the current is released via the fourth terminal P4 to the wiring connected to the source terminal of the switching element TR.

[0103] As in the first embodiment, in the second embodiment, the fifth timing is preset as a time point before the peak of the surge voltage appears in the drain-source voltage Vds, and the control unit 22 turns off the sixth switch SW6 at this preset fifth timing. Note that the fifth timing is set as appropriate depending on the drain current value when the switching element TR is in the on state and the drain-source voltage when the switching element TR is in the off state.

[0104] As described above, when the switching element TR is turned off, the input capacitance of the switching element TR is discharged through two discharge paths, one including the fourth switch SW4 and the other including the sixth switch SW6, at the beginning of the turn-off operation. This increases the discharge rate of the input capacitance of the switching element TR, thereby reducing switching loss during turn-off. Furthermore, from the fifth timing, which is a point in time before the peak of the surge voltage appears in the drain-source voltage Vds, the input capacitance of the switching element TR is discharged only through the discharge path including the fourth switch SW4. This reduces the discharge rate before the peak of the surge voltage appears in the drain-source voltage Vds, thereby reducing the height of the surge voltage peak. As a result, noise and surges generated during turn-off can be suppressed.

[0105] As can be understood from the above description, the discharge circuit included in the gate drive circuit GDB is configured to switch the path through which a discharge current flows from the gate terminal of the switching element TR between a first discharge path and a second discharge path having a higher resistance value than the first discharge path. The first discharge path includes two discharge paths: a discharge path including the fourth switch SW4 and a discharge path including the sixth switch SW6. The second discharge path is a discharge path including the fourth switch SW4. It can also be understood from the above description that, when the switching element TR is turned off, the discharge circuit discharges along the first discharge path and then along the second discharge path.

[0106] As described above, the gate drive circuit GDB of the second embodiment, like the gate drive circuit GDA of the first embodiment, can achieve both a reduction in switching loss of the switching element TR to be driven and suppression of noise and surges generated during switching.

[0107] 19 is a diagram showing a specific example of the gate drive circuit GDB. As shown in Fig. 19, in the gate drive circuit GDB, the first switch SW1 and the second switch SW2 are preferably P-channel MOS-FETs, and the third switch SW3, the fourth switch SW4, and the sixth switch SW6 are preferably N-channel MOS-FETs.

[0108] The sixth switch SW6 has a sixth body diode SD6 parasitic between the drain and source of the sixth switch SW6, i.e., an N-channel MOS-FET. In an equivalent circuit, the anode terminal of the sixth body diode SD6 is connected to the source terminal of the sixth switch SW6, and the cathode terminal of the sixth body diode SD6 is connected to the drain terminal of the sixth switch SW6.

[0109] The source terminal of the sixth switch SW6 is connected to the second terminal P2. The drain terminal of the sixth switch SW6 is connected to the first node N1. The gate terminal of the sixth switch SW6 is connected to the control unit 22. One of the control signals output from the control unit 22 is input to the gate terminal of the sixth switch SW6.

[0110] The configurations of the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 in the specific example of the gate drive circuit GDB are the same as those in the specific example of the gate drive circuit GDA shown in FIG. 11, and therefore will not be described.

[0111] In the specific example of the gate drive circuit GDB, the first switch SW1 and the second switch SW2 can be turned on by applying the second potential V2 or a potential between the first potential V1 and the second potential V2 to their respective gate terminals. The third switch SW3, the fourth switch SW4, and the sixth switch SW6 can be turned on by applying the first potential V1 or a potential between the first potential V1 and the second potential V2 to their respective gate terminals. That is, the first switch SW1, the second switch SW2, the third switch SW3, the fourth switch SW4, and the sixth switch SW6 can be driven within a voltage range between the first potential V1 and the second potential V2.

[0112] [Modifications] The present invention is not limited to the above-described embodiment, and the configurations described in this specification can be combined as appropriate within a range that does not contradict each other. For example, the following modifications can be made.

[0113] (1) Figure 20 is a circuit diagram showing a first modified example of the gate drive circuit GDA. As shown in Figure 20, the gate drive circuit GDA may further include a second diode D2. The anode terminal of the second diode D2 is connected to the second terminal P2. The first switch SW1 is connected between the first terminal P1 and the inductor L1, and the cathode terminal of the second diode D2 is connected to the connection point between the first switch SW1 and the inductor L1.

[0114] According to the first modification, the excess energy stored in the inductor L1 is regenerated to the power supply circuit 24 via the second diode D2, the inductor L1, the first diode D1 (or the fifth body diode SD5 of the fifth switch SW5), the second switch SW2 (or the second body diode SD2 of the second switch SW2), and the first terminal P1, thereby enabling highly efficient driving and suppressing the occurrence of a surge at the drain terminal of the first switch SW1. When the first terminal P1 is connected to the first DC power supply 2, the excess energy stored in the inductor L1 is regenerated to the first DC power supply 2. The configuration shown in FIG. 20 may be applied to the gate drive circuit GDB of the second embodiment.

[0115] (2) Figure 21 is a circuit diagram showing a second modified example of the gate drive circuit GDA. As shown in Figure 21, the gate drive circuit GDA may further include a third diode D3. The anode terminal of the third diode D3 is connected to the third terminal P3. The cathode terminal of the third diode D3 is connected to the first terminal P1.

[0116] If the energy stored in the inductor L1 is excessive, the gate voltage of the switching element TR will rise significantly, which may result in destruction of the switching element TR. By providing the third diode D3 as described above, the gate voltage of the switching element TR is clamped to the first power supply voltage Vdd, thereby preventing destruction of the switching element TR. The configuration shown in FIG. 21 may also be applied to the gate drive circuit GDB of the second embodiment. Furthermore, the third diode D3 may be used in combination with the second diode D2 described in the first modification.

[0117] (3) Figure 22 is a circuit diagram showing a third modified example of the gate drive circuit GDA. As shown in Figure 22, the resistive element Rg may be connected between the first node N1 and the fifth switch SW5. In this case, the resistive element Rg may be substituted by the resistance value of the fifth switch SW5. In this case, the first node N1 is directly connected to the third terminal P3.

[0118] According to the third modification, the second switch SW2 plays the role of the third diode D3 described in the second modification, so there is no need to add a third diode D3 to prevent breakdown of the switching element TR. The configuration shown in FIG. 22 may also be applied to the gate drive circuit GDB of the second embodiment. The configuration shown in FIG. 22 may also be used in combination with the second diode D2 described in the first modification.

[0119] (4) Fig. 23 is a circuit diagram showing a fourth modification of the gate drive circuit GDA. As described with reference to Fig. 5, the second switch SW2 may be turned off at the third timing, but as shown in Fig. 23, the second switch SW2 may be turned on at the third timing. In this case, it is preferable that the resistance value of the second switch SW2 is higher than the resistance value of the resistive element Rg.

[0120] 23 , when the second switch SW2 is turned on at the third timing, the current of the inductor L1 flows to the first terminal P1 via the second switch SW2. However, because the resistance value of the second switch SW2 is relatively high, the potential of the first node N1 becomes higher than the positive potential of the first power supply voltage Vdd, i.e., the first potential V1. As a result, compared to before the third timing, after the third timing, the input capacitance of the switching element TR is charged with a voltage higher than the first power supply voltage Vdd, and the charging speed of the input capacitance of the switching element TR increases. Note that the second switch SW2 may also be turned on at the third timing in the gate drive circuit GDB of the second embodiment.

[0121] (5) Figure 24 is a circuit diagram showing a fifth modified example of the gate drive circuit GDA. As shown in Figure 24, the gate drive circuit GDA may further include a fourth diode D4 connected between the first node N1 and the second switch SW2. The anode terminal of the fourth diode D4 is connected to the second switch SW2, and the cathode terminal of the fourth diode D4 is connected to the first node N1.

[0122] According to the fifth modification, as shown in Fig. 24, even if the second switch SW2 is turned on at the third timing, it is possible to prevent current from flowing from the first node N1 toward the first terminal P1 via the second switch SW2. As a result, all of the current in the inductor L1 flows into the gate terminal of the switching element TR via the resistor element Rg and the third terminal P3, which makes it possible to increase the charging speed of the input capacitance of the switching element TR compared to the fourth modification. The configuration shown in Fig. 24 may also be applied to the gate drive circuit GDB of the second embodiment.

[0123] 11 is employed, the second switch SW2 has the second body diode SD2, and therefore, regardless of whether the second switch SW2 is turned on or off at the third timing, a current flows from the first node N1 to the first terminal P1 via the second body diode SD2. Therefore, in this case as well, it is preferable to make the resistance value of the second switch SW2 higher than the resistance value of the resistive element Rg, or to connect a fourth diode D4 between the first node N1 and the second switch SW2. The same applies when the specific example of the gate drive circuit GDB shown in FIG. 19 is employed.

[0124] (6) Figure 25 is a circuit diagram showing a first modified example of the gate drive circuit GDB. In the gate drive circuit GDB of the second embodiment, if the conductive resistance value of the sixth switch SW6 is smaller than the conductive resistance value of the fourth switch SW4, the control unit 22 may control the gate drive circuit GDB as follows. That is, when turning off the switching element TR, the control unit 22 turns off the first switch SW1, the second switch SW2, and the fourth switch SW4 at a fourth timing, and turns on the sixth switch SW6. As a result, from the fourth timing onwards, a current flows through the path indicated by the dotted arrow in Figure 25.

[0125] In this case, after the fourth timing, current flows through the third terminal P3, the resistor Rg, and the sixth switch SW6 in that order, and is then discharged to the wiring connected to the source terminal of the switching element TR via the fourth terminal P4. Note that although the third switch SW3 is turned off in Fig. 25, the third switch SW3 may be turned on at the fourth timing.

[0126] The control unit 22 turns off the sixth switch SW6 at a fifth timing after the fourth timing. As a result, after the fifth timing, a current flows through the path indicated by the dotted arrow in Fig. 18. That is, after the fifth timing, a current flows in the order of the third terminal P3, the resistive element Rg, the first node N1, and the fourth switch SW4, and is discharged to the wiring connected to the source terminal of the switching element TR via the fourth terminal P4.

[0127] As described above, when the switching element TR is turned off, the input capacitance of the switching element TR is discharged only through the discharge path including the sixth switch SW6 at the beginning of the turn-off operation. This increases the discharge rate of the input capacitance of the switching element TR, thereby reducing switching loss during turn-off. Furthermore, from the fifth timing, which is a point in time before the peak of the surge voltage appears in the drain-source voltage Vds, the input capacitance of the switching element TR is discharged only through the discharge path including the fourth switch SW4. This reduces the discharge rate before the peak of the surge voltage appears in the drain-source voltage Vds, thereby reducing the height of the peak of the surge voltage. As a result, noise and surges generated during turn-off can be suppressed.

[0128] As can be understood from the above description, the discharge circuit included in the first modified example of the gate drive circuit GDB has a configuration that switches the path through which a discharge current flows from the gate terminal of the switching element TR between a first discharge path and a second discharge path having a higher resistance value than the first discharge path. The first discharge path is a discharge path that includes the sixth switch SW6. The second discharge path is a discharge path that includes the fourth switch SW4. It can also be understood from the above description that, when the switching element TR is turned off, the discharge circuit discharges through the first discharge path and then through the second discharge path.

[0129] (7) Fig. 26 is a circuit diagram showing a second modified example of the gate drive circuit GDB. As shown in Fig. 26, the sixth switch SW6 may be connected between the second terminal P2 and the third terminal P3. More specifically, one end of the sixth switch SW6 is connected to the second terminal P2, and the other end of the sixth switch SW6 is connected to the wiring that connects the resistor element Rg and the third terminal P3.

[0130] According to the second modified example of the gate drive circuit GDB, the resistance value of the path passing through the third terminal P3, the sixth switch SW6, and the fourth terminal P4 is smaller than the resistance value of the path passing through the third terminal P3, the resistive element Rg, the fourth switch SW4, and the fourth terminal P4. Therefore, as described in the first modified example of the gate drive circuit GDB, when turning off the switching element TR, the control unit 22 may turn off the first switch SW1, the second switch SW2, and the fourth switch SW4 and turn on the sixth switch SW6 at the fourth timing. Note that even in this case, the control unit 22 may turn on the fourth switch SW4 and the sixth switch SW6 simultaneously at the fourth timing.

[0131] (8) Fig. 27 is a circuit diagram showing a sixth modified example of the gate drive circuit GDA. As shown in Fig. 27, the gate drive circuit GDA may have a fifth terminal P5 to which a third potential V3 lower than the first potential V1 and higher than the second potential V2 is applied. In this case, the fourth terminal P4 is directly connected to the fifth terminal P5.

[0132] The sum of the potential difference Vdd1 between the first potential V1 and the third potential V3 and the potential difference Vdd2 between the third potential V3 and the second potential V2 is equal to the first power supply voltage Vdd. When the third modification of the gate drive circuit GDA is adopted, the power supply circuit 24 generates a DC voltage corresponding to the potential difference Vdd1 and a DC voltage corresponding to the potential difference Vdd2 and outputs them to the gate drive circuit GDA.

[0133] As described above, by adopting a configuration in which the second terminal P2, to which the third switch SW3 and the fourth switch SW4 are connected, is at a negative voltage relative to the source terminal of the switching element TR, the turn-off operation of the switching element TR can be accelerated, thereby further reducing switching loss during turn-off. Furthermore, when a configuration using a high-side switching element TR and a low-side switching element TR is adopted, as in the bridge circuit 21, the occurrence of false firing can be suppressed. The configuration shown in FIG. 27 may also be applied to the gate drive circuit GDB of the second embodiment.

[0134] The sixth modified example of the gate drive circuit GDA may be combined with at least one of the first, second, third, fourth, and fifth modified examples of the gate drive circuit GDA. When the sixth modified example of the gate drive circuit GDA is combined with the first modified example of the gate drive circuit GDA, the anode terminal of the second diode D2 is connected to the fifth terminal P5 instead of the second terminal P2.

[0135] The present technology may be configured as follows: (1) A gate drive circuit for driving a switching element, comprising: a charging circuit for charging an input capacitance of the switching element by applying a gate voltage to a gate terminal of the switching element; and a discharging circuit for discharging the input capacitance, wherein the charging circuit has a first charging path including a series circuit in which a first switch and an inductor are connected in series between a first terminal and a first node; and a second charging path in which a second switch is connected between the first terminal and the first node, wherein, when the switching element is turned on, charging is performed through the second charging path and then charging is performed through the first charging path, and the discharging circuit is configured to switch a path through which a discharge current flows from the gate terminal between the first discharging path and a second discharging path having a higher resistance than the first discharging path. (2) The gate drive circuit according to (1), wherein, when the switching element is turned off, the discharging circuit discharges through the first discharging path and then discharging through the second discharging path. (3) The gate drive circuit according to (1) or (2), further comprising: a first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, and a third terminal connected to the gate terminal of the switching element and connected directly or indirectly to the first node, wherein the charging circuit includes the first switch and the inductor connected in series between the first terminal and the second node, the second switch connected between the first terminal and the first node, a third switch connected between the second terminal and the second node, and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node, and the discharging circuit includes the third switch, a fourth switch connected between the second terminal and the first node, and a fifth switch connected between the first node and the second node. (4) The gate drive circuit according to (3), wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch, and the fifth switch are N-channel MOS-FETs.(5) The gate drive circuit according to (1) or (2), further comprising: a first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, and a third terminal connected to the gate terminal of the switching element and connected directly or indirectly to the first node, wherein the charging circuit includes the first switch and the inductor connected in series between the first terminal and the second node, the second switch connected between the first terminal and the first node, a third switch connected between the second terminal and the second node, and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node, and the discharging circuit includes a fourth switch connected between the second terminal and the first node and a sixth switch connected between the second terminal and the first node. (6) The gate drive circuit according to (5), wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch, and the sixth switch are N-channel MOS-FETs. (7) The gate drive circuit according to any one of (3) to (6), further comprising a resistive element connected between the first node and the third terminal. (8) The gate drive circuit according to any one of (3) to (7), further comprising a fourth terminal connected to a source terminal or an emitter terminal of the switching element, the fourth terminal being directly connected to the second terminal. (9) The gate drive circuit according to (8), further comprising a second diode, the first switch being connected between the first terminal and the inductor, an anode terminal of the second diode being connected to the second terminal, and a cathode terminal of the second diode being connected to a connection point between the first switch and the inductor. (10) The gate drive circuit according to any one of (3) to (7), further comprising a fourth terminal connected to a source terminal or an emitter terminal of the switching element, and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, the fourth terminal being directly connected to the fifth terminal.(11) The gate drive circuit according to (10), further comprising a second diode, the first switch being connected between the first terminal and the inductor, an anode terminal of the second diode being connected to the fifth terminal, and a cathode terminal of the second diode being connected to a connection point between the first switch and the inductor. (12) The gate drive circuit according to any one of (3) to (11), further comprising a third diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal. (13) A power conversion device comprising: a bridge circuit having a plurality of switching elements; a plurality of gate drive circuits provided corresponding to the plurality of switching elements and driving the corresponding switching elements; and a control unit controlling the plurality of gate drive circuits, wherein each of the plurality of gate drive circuits comprises: a charging circuit that charges an input capacitance of the corresponding switching element by applying a gate voltage to a gate terminal of the corresponding switching element; and a discharging circuit that discharges the input capacitance, wherein the charging circuit has a first charging path including a series circuit in which a first switch and an inductor are connected in series between a first terminal and a first node; and a second charging path in which a second switch is connected between the first terminal and the first node, wherein, when the switching element is turned on, charging is performed via the second charging path and then via the first charging path, and the discharging circuit is configured to switch a path through which a discharge current flows from the gate terminal between a first discharging path and a second discharging path having a higher resistance than the first discharging path. (14) The power conversion device according to (13), wherein the discharge circuit discharges through the first discharge path and then through the second discharge path when the switching element is turned off.(15) The power conversion device according to (13) or (14), wherein the gate drive circuit further includes the first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, and a third terminal connected to the gate terminal of the corresponding switching element and connected directly or indirectly to the first node; the charging circuit includes the first switch and the inductor connected in series between the first terminal and the second node, the second switch connected between the first terminal and the first node, a third switch connected between the second terminal and the second node, and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node; and the discharging circuit includes the third switch, a fourth switch connected between the second terminal and the first node, and a fifth switch connected between the first node and the second node. (16) The power conversion device according to (15), wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch, and the fifth switch are N-channel MOS-FETs. (17) The power conversion device according to (15) or (16), wherein, when turning on the switching elements, the control unit turns on the first switch and the third switch and turns off the fifth switch at a first timing, turns on the second switch and turns off the fourth switch at a second timing before the first timing, the first timing, or after the first timing, and turns off the third switch at a third timing after the second timing. (18) The power conversion device according to (15) or (16), wherein, when turning off the switching elements, the control unit turns off the first switch and the second switch and turns on the third switch, the fourth switch, and the fifth switch at a fourth timing, and turns off at least one of the third switch and the fifth switch at a fifth timing after the fourth timing.(19) The power conversion device according to (13) or (14), wherein the gate drive circuit further includes the first terminal to which a first potential is applied, a second terminal to which a second potential lower than the first potential is applied, and a third terminal connected to the gate terminal of the switching element and connected directly or indirectly to the first node, the charging circuit includes the first switch and the inductor connected in series between the first terminal and the second node, the second switch connected between the first terminal and the first node, a third switch connected between the second terminal and the second node, and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node, and the discharging circuit includes a fourth switch connected between the second terminal and the first node and a sixth switch connected between the second terminal and the first node. (20) The power conversion device according to (19), wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch, and the sixth switch are N-channel MOS-FETs. (21) The power conversion device according to (19) or (20), wherein, when turning on the switching elements, the control unit turns on the first switch and the third switch at a first timing, turns on the second switch and turns off the fourth switch and the sixth switch at a second timing before the first timing, the first timing, or a second timing after the first timing, and turns off the third switch at a third timing after the second timing. (22) The power conversion device according to (19) or (20), wherein, when turning off the switching elements, the control unit turns off the first switch and the second switch and turns on the fourth switch and the sixth switch at a fourth timing, and turns off the sixth switch at a fifth timing after the fourth timing. (23) The power conversion device according to any one of (15) to (22), wherein the gate drive circuit further includes a resistive element connected between the first node and the third terminal.(24) The power conversion device according to any one of (15) to (23), wherein the gate drive circuit further includes a fourth terminal connected to a source terminal or an emitter terminal of the switching element, and the fourth terminal is directly connected to the second terminal. (25) The power conversion device according to (24), wherein the gate drive circuit further includes a second diode, the first switch is connected between the first terminal and the inductor, an anode terminal of the second diode is connected to the second terminal, and a cathode terminal of the second diode is connected to a connection point between the first switch and the inductor. (26) The power conversion device according to any one of (15) to (23), wherein the gate drive circuit further includes a fourth terminal connected to a source terminal or an emitter terminal of the switching element, and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, and the fourth terminal is directly connected to the fifth terminal. (27) The power conversion device according to (26), wherein the gate drive circuit further includes a second diode, the first switch is connected between the first terminal and the inductor, an anode terminal of the second diode is connected to the fifth terminal, and a cathode terminal of the second diode is connected to a connection point between the first switch and the inductor. (28) The power conversion device according to any one of (15) to (27), wherein the gate drive circuit further includes a third diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal. (29) A motor unit comprising: a motor; and the power conversion device according to any one of (13) to (28), which supplies power to the motor.

[0136] REFERENCE SIGNS LIST 1...motor unit, 2...first DC power supply, 3...second DC power supply, 10...motor, 20...power conversion device, 21...bridge circuit, 22...control unit, 23...smoothing capacitor, 24...power supply circuit, GD1 to GD6, GDA, GDB...gate drive circuit, TR1 to TR6, TR...switching element, P1...first terminal, P2...second terminal, P3...third terminal, P4...fourth terminal, P5...fifth terminal, SW1...first switch, SW2...second switch, SW3...third switch, SW4...fourth switch, SW5...fifth switch, SW6...sixth switch, L1...inductor, D1...first diode, Rg...resistance element, N1...first node, N2...second node

Claims

1. A gate drive circuit for driving a switching element, comprising: a charging circuit for charging an input capacitance of the switching element by applying a gate voltage to a gate terminal of the switching element; and a discharging circuit for discharging the input capacitance, wherein the charging circuit has a first charging path having a series circuit in which a first switch and an inductor are connected in series between a first terminal and a first node, and a second charging path in which a second switch is connected between the first terminal and the first node, and when the switching element is turned on, charging is performed via the second charging path, and then charging is performed via the first charging path, and the discharging circuit is configured to switch the path through which a discharge current flows from the gate terminal between the first discharging path and a second discharging path having a higher resistance than the first discharging path.

2. The gate drive circuit according to claim 1, wherein the discharge circuit discharges through the first discharge path and then through the second discharge path when the switching element is turned off.

3. The gate drive circuit according to claim 2, further comprising: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; and a third terminal connected to the gate terminal of the switching element and connected directly or indirectly to the first node, wherein the charging circuit includes: the first switch and the inductor connected in series between the first terminal and the second node, the second switch connected between the first terminal and the first node, a third switch connected between the second terminal and the second node, and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node, and wherein the discharging circuit includes: the third switch, a fourth switch connected between the second terminal and the first node, and a fifth switch connected between the first node and the second node.

4. The gate drive circuit according to claim 3, wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch and the fifth switch are N-channel MOS-FETs.

5. The gate drive circuit according to claim 2, further comprising: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; and a third terminal connected to the gate terminal of the switching element and connected directly or indirectly to the first node, wherein the charging circuit includes: the first switch and the inductor connected in series between the first terminal and the second node, the second switch connected between the first terminal and the first node, a third switch connected between the second terminal and the second node, and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node, and wherein the discharging circuit includes: a fourth switch connected between the second terminal and the first node, and a sixth switch connected between the second terminal and the first node.

6. The gate drive circuit according to claim 5, wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch and the sixth switch are N-channel MOS-FETs.

7. The gate drive circuit according to claim 3, further comprising a resistive element connected between the first node and the third terminal.

8. The gate drive circuit according to any one of claims 3 to 6, further comprising a fourth terminal connected to a source terminal or an emitter terminal of the switching element, the fourth terminal being directly connected to the second terminal.

9. The gate drive circuit according to claim 8, further comprising a second diode, the first switch being connected between the first terminal and the inductor, an anode terminal of the second diode being connected to the second terminal, and a cathode terminal of the second diode being connected to a connection point between the first switch and the inductor.

10. The gate drive circuit according to any one of claims 3 to 6, further comprising: a fourth terminal connected to a source terminal or an emitter terminal of the switching element; and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, wherein the fourth terminal is directly connected to the fifth terminal.

11. The gate drive circuit according to claim 10, further comprising a second diode, the first switch being connected between the first terminal and the inductor, an anode terminal of the second diode being connected to the fifth terminal, and a cathode terminal of the second diode being connected to a connection point between the first switch and the inductor.

12. The gate drive circuit of claim 3, further comprising a third diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal.

13. A power conversion device comprising: a bridge circuit having a plurality of switching elements; a plurality of gate drive circuits provided corresponding to each of the plurality of switching elements and driving the corresponding switching elements; and a control unit controlling the plurality of gate drive circuits, each of the plurality of gate drive circuits comprising: a charging circuit for charging an input capacitance of the corresponding switching element by applying a gate voltage to a gate terminal of the corresponding switching element; and a discharging circuit for discharging the input capacitance, wherein the charging circuit has a first charging path having a series circuit in which a first switch and an inductor are connected in series between a first terminal and a first node, and a second charging path in which a second switch is connected between the first terminal and the first node, wherein when the switching element is turned on, charging is performed via the second charging path and then charging is performed via the first charging path, and the discharging circuit is configured to switch a path through which a discharge current flows from the gate terminal between a first discharging path and a second discharging path having a higher resistance than the first discharging path.

14. The power conversion device according to claim 13, wherein the discharge circuit discharges through the first discharge path and then through the second discharge path when the switching element is turned off.

15. The power conversion device according to claim 14, wherein the gate drive circuit further comprises: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; and a third terminal connected to the gate terminal of the corresponding switching element and connected directly or indirectly to the first node; the charging circuit includes: the first switch and the inductor connected in series between the first terminal and the second node; the second switch connected between the first terminal and the first node; a third switch connected between the second terminal and the second node; and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node; and the discharging circuit includes: the third switch; a fourth switch connected between the second terminal and the first node; and a fifth switch connected between the first node and the second node.

16. The power conversion device according to claim 15, wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch and the fifth switch are N-channel MOS-FETs.

17. The power conversion device of claim 15, wherein, when the control unit turns on the switching element, it: turns on the first switch and the third switch and turns off the fifth switch at a first timing; turns on the second switch and turns off the fourth switch at a second timing before the first timing, at the first timing, or after the first timing; and turns off the third switch at a third timing after the second timing.

18. The power conversion device of claim 15, wherein, when the control unit turns off the switching element, at a fourth timing, it turns off the first switch and the second switch and turns on the third switch, the fourth switch and the fifth switch, and at a fifth timing after the fourth timing, it turns off at least one of the third switch and the fifth switch.

19. The power conversion device according to claim 14, wherein the gate drive circuit further comprises: a first terminal to which a first potential is applied; a second terminal to which a second potential lower than the first potential is applied; and a third terminal connected to the gate terminal of the switching element and directly or indirectly connected to the first node; the charging circuit includes: the first switch and the inductor connected in series between the first terminal and the second node; the second switch connected between the first terminal and the first node; a third switch connected between the second terminal and the second node; and a first diode having an anode terminal connected to the second node and a cathode terminal connected to the first node; and the discharging circuit includes: a fourth switch connected between the second terminal and the first node; and a sixth switch connected between the second terminal and the first node.

20. The power conversion device according to claim 19, wherein the first switch and the second switch are P-channel MOS-FETs, and the third switch, the fourth switch and the sixth switch are N-channel MOS-FETs.

21. The power conversion device of claim 19, wherein, when the control unit turns on the switching element, it turns on the first switch and the third switch at a first timing, turns on the second switch and turns off the fourth switch and the sixth switch at a second timing before the first timing, at the first timing, or after the first timing, and turns off the third switch at a third timing after the second timing.

22. The power conversion device of claim 19, wherein, when the control unit turns off the switching element, it turns off the first switch and the second switch and turns on the fourth switch and the sixth switch at a fourth timing, and turns off the sixth switch at a fifth timing after the fourth timing.

23. The power conversion device according to any one of claims 15 to 22, wherein the gate drive circuit further comprises a resistive element connected between the first node and the third terminal.

24. The power conversion device according to any one of claims 15 to 22, wherein the gate drive circuit further comprises a fourth terminal connected to a source terminal or an emitter terminal of the switching element, and the fourth terminal is directly connected to the second terminal.

25. The power conversion device according to claim 24, wherein the gate drive circuit further comprises a second diode, the first switch is connected between the first terminal and the inductor, an anode terminal of the second diode is connected to the second terminal, and a cathode terminal of the second diode is connected to a connection point between the first switch and the inductor.

26. A power conversion device according to any one of claims 15 to 22, wherein the gate drive circuit further comprises: a fourth terminal connected to a source terminal or an emitter terminal of the switching element; and a fifth terminal to which a third potential lower than the first potential and higher than the second potential is applied, the fourth terminal being directly connected to the fifth terminal.

27. The power conversion device according to claim 26, wherein the gate drive circuit further comprises a second diode, the first switch is connected between the first terminal and the inductor, an anode terminal of the second diode is connected to the fifth terminal, and a cathode terminal of the second diode is connected to a connection point between the first switch and the inductor.

28. A power conversion device according to any one of claims 15 to 22, wherein the gate drive circuit further includes a third diode having an anode terminal connected to the third terminal and a cathode terminal connected to the first terminal.

29. A motor unit comprising: a motor; and a power conversion device according to any one of claims 13 to 22 that supplies power to the motor.

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