Accelerator, data processing system, and data processing method

Abstract

This accelerator (20) comprises: a data reception unit (25) configured to receive input data; a data processing unit (26) configured to perform processing based on the input data that was received by the data reception unit (25), and to output the result of the processing; and a clock control unit (27) configured to control the clock frequency of the data processing unit (26). The data reception unit (25) monitors the data quantity of the input data. The clock control unit (26) decreases the clock frequency when the data quantity monitored by the data reception unit (25) decreases.

Description

Accelerator, data processing system, and data processing method

[0001] The present invention relates to an accelerator, a data processing system, and a data processing method.

[0002] There is known a data processing system that includes a processor (e.g., a central processing unit (CPU)) that executes a program such as an operating system (OS) or a user application, and an accelerator that is provided separately from the processor. Types of such data processing systems include a look-aside system (e.g., Non-Patent Document 1), in which input data to the accelerator passes through the processor, and an inline system, in which the input data does not pass through the processor.

[0003] “Open Programmable Acceleration Engine”, [online], 2017, Intel Corporation, [searched on March 1, 2020], Internet <URL: https: / / opae.github.io / latest / index.html> Karl Kurbjun, Carl Ribbing, “PLL Dynamic Reconfiguration”, [online], October 26, 2011, XILINX, [searched on March 1, 2020], Internet <URL: https: / / docs.xilinx.com / v / u / en-US / xapp879>

[0004] To reduce the dynamic power of the accelerator, it is possible to reduce the clock frequency of the accelerator when the amount of data input to the accelerator is low, such as during low load or idle periods. One method for reducing the clock frequency is to have the processor monitor the amount of data input to the accelerator and reduce the clock frequency when the amount of data becomes small. However, this method causes communication delays or monitoring process delays between the processor and the accelerator, which means that the accelerator must operate at a relatively high clock frequency even during low load or idle periods, thereby reducing the amount of reduction in the accelerator's dynamic power.

[0005] The present invention aims to increase the amount of dynamic power reduction of an accelerator.

[0006] In order to solve the above problem, an accelerator according to the present invention comprises a data receiving unit configured to receive input data, a data processing unit configured to perform processing based on the input data received by the data receiving unit and output a result of the processing, and a clock control unit configured to control a clock frequency of the data processing unit, wherein the data receiving unit is configured to monitor the amount of the input data, and the clock control unit is configured to reduce the clock frequency when the amount of data monitored by the data receiving unit decreases.

[0007] The data processing system according to the present invention is a data processing system comprising the accelerator and a processor that performs processing by executing a program, and the accelerator is provided in an inline manner in which the input data input to the accelerator is input directly without going through the processor.

[0008] Furthermore, a data processing method according to the present invention is a data processing method executed by an accelerator, comprising a first step of accepting input data, a second step of performing processing based on the input data accepted in the first step and outputting a result of the processing, and a third step of controlling a clock frequency of the processing, wherein the first step includes a step of monitoring the amount of input data, and the third step includes a step of decreasing the clock frequency when the amount of data to be monitored decreases.

[0009] According to the present invention, the dynamic power consumption of the accelerator can be significantly reduced.

[0010] FIG. 1 is a hardware configuration diagram of a data processing system according to a first embodiment of the present invention. FIG. 2 is a block diagram of the accelerator of FIG. 1. FIG. 3 is a configuration diagram of the data reception unit of FIG. 2. FIG. 4 is a flowchart of processing performed by the data reception unit. FIG. 5 is a flowchart of processing performed by the clock control unit. FIG. 6 is a diagram showing an example of the configuration of an input rate / clock table. FIG. 7 is a graph showing the relationship between time changes in input rate and clock type. FIG. 8 is a flowchart showing another example of clock frequency control. FIG. 9 is a configuration diagram of a data reception unit according to a second embodiment. FIG. 10 is a flowchart of processing performed by the clock control unit. FIG. 11 is a diagram showing an example of the configuration of a buffer usage rate / clock table. FIG. 12 is a graph showing the relationship between time changes in buffer usage rate and clock type. FIG. 13 is a flowchart showing another example of clock frequency control. FIG. 14 is a flowchart of processing performed by the clock control unit according to a modified example.

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention and its modifications will be described with reference to the accompanying drawings. In the following description, elements having similar functions are designated by the same reference numerals.

[0012] First Embodiment A data processing system 10 according to this embodiment shown in FIG. 1 includes a server computer and the like. The system 10 includes a processor 11 such as a CPU, a main storage device 12 including RAM, and an auxiliary storage device 13 that stores an OS and programs executed by the processor 11. The system 10 also includes a communication interface 14 connected to a network to communicate with devices external to the system 10. The communication interface 14 may be, for example, a network interface card. The system 10 also includes an accelerator 20 that adds specific functions to the system 10. The accelerator 20 may include an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or the like. Accordingly, each of the components described below is composed of a circuit.

[0013] The accelerator 20 processes input data input thereto and outputs the processing result to the processor 11, the main memory device 12, the communication interface 14, or another device (not shown) in the system 10. The input data is input to the accelerator 20 from the communication interface 14 or another device (not shown), such as another accelerator, without passing through the processor 11 and the main memory device 12. In other words, the accelerator 20 is used in an inline manner. As another aspect of the inline method, the input data may be input to the accelerator 20 via the main memory device 12 without passing through the processor 11.

[0014] As shown in FIG. 2, the accelerator 20 includes first to fourth clock generating units 21 to 24 , a data receiving unit 25 , a data processing unit 26 , and a clock control unit 27 .

[0015] The first to fourth clock generating units 21 to 24 generate and output clock signals CLK1 to CLK4, respectively, with the frequencies of the clock signals CLK1 to CLK4 being in the range 0<CLK1<CLK2<CLK3<CLK4.

[0016] The data receiving unit 25 receives, as input data, data to be processed that is input to the accelerator 20. Details of the data receiving unit 25 will be described later.

[0017] The data processing unit 26 performs processing based on the input data received by the data receiving unit 25, such as processing the input data and making judgments based on the input data. The data processing unit 26 outputs the results of the processing to the outside of the accelerator 20. Any of the clock signals CLK1 to CLK4 is input to the data processing unit 26. The data processing unit 26 performs processing in synchronization with any of the input clock signals CLK1 to CLK4. In other words, the clock frequency of the data processing unit 26 is the frequency of any of the input clock signals CLK1 to CLK4.

[0018] The clock control unit 27 controls the clock frequency of the data processing unit 26 by selecting a clock signal to be input to the data processing unit 26 from the clock signals CLK1 to CLK4.

[0019] 2, the accelerator 20 may include multiple combinations of units 25 to 27. At least some of the data processing units 26 in each combination may be configured to perform different processes, or may be configured to perform the same process for redundancy.

[0020] As shown in FIG. 3, the data receiving unit 25 includes a buffer 25A for holding input data, a data amount counter 25B for counting the data size of the input data held in the buffer 25A, and a reset unit 25C for supplying a reset signal to the data amount counter 25B at predetermined intervals.

[0021] Every time the data receiving unit 25 receives input data, the input data is stored in a buffer 25A. The buffer 25A is formed of a first-in, first-out (FIFO) memory or the like. Based on a read request from the data processing unit 26, the buffer 25A outputs the oldest input data stored therein to the data processing unit 26. In this way, by outputting input data in response to a read request from the data processing unit 26, an excessive amount of data is prevented from being input to the data processing unit 26.

[0022] The data amount counter 25B counts the amount of data of each input data held in the buffer 25A. The count value of the data amount is accumulated until a reset signal is input from the reset unit 25C, and is reset when the reset signal is input. The count value immediately before the reset is the input rate of the input data per the predetermined period. This count value as the input rate is supplied to the clock control unit 27.

[0023] The clock control unit 27 controls the clock frequency of the data processing unit 26 in accordance with the input rate supplied from the data amount counter 25B. For example, the clock control unit 27 receives clock signals CLK1 to CLK4 from the first to fourth clock generation units 21 to 24 (FIG. 2), respectively. The clock control unit 27 selects one of the clock signals CLK1 to CLK4 in accordance with the input rate. Only the selected clock signal is supplied to the data processing unit 26.

[0024] An example of an operation relating to the control of the clock frequency of the accelerator 20 having the above configuration will be described with reference to Fig. 4. The process of Fig. 4 is executed every first time P. In parallel with this operation, input data is stored in and read from the buffer 25A, and the data amount of the input data is counted by the data amount counter 25B.

[0025] First, the reset unit 25C measures the elapsed time from the start of the accelerator 20 or from the execution of step S14 (described later) using a timer included in the reset unit 25C, and determines whether the measured elapsed time reaches a second time Q (step S11). The first time P and the second time Q are the same time (e.g., 10 μsec), but the second time Q (e.g., 0.1 μsec) may be shorter than the first time P (e.g., 10 μsec).

[0026] If the elapsed time reaches the second time Q (step S11: Yes), the reset unit 25C supplies a reset signal to the data amount counter 25B (step S12).

[0027] When the reset signal is input, the data amount counter 25B supplies the current count value, i.e., the integrated value of the data amount of input data, as the input rate of the input data to the clock control unit 27 (step S13), and resets the count value (step S14). The process of FIG. 4 ends after step S14, but if the first time P and the second time Q are the same length, step S11 may be performed after step S14. In other words, steps S11 to S14 may be performed repeatedly. This eliminates a period when the process of FIG. 4 is not performed, thereby continuously obtaining the input rate and making it easy to refer to the previous input rate, etc.

[0028] When the input rate is supplied from the data amount counter 25B, the clock control unit 27 executes, for example, the process shown in Fig. 5. First, the clock control unit 27 refers to an input rate / clock table (Fig. 6) that indicates the correspondence between the input rate (IR) and the type of clock signal, and acquires the type of clock signal (i.e., any of CLK1 to CLK4 or no clock signal) that corresponds to the currently supplied input rate (step S21).

[0029] The clock control unit 27 holds the currently selected type of clock signal and compares the current type of clock signal with the type acquired in step S21 (step S22). If the comparison shows that the two types are different, the clock control unit 27 changes the type of clock signal to be supplied to the data processing unit 26 to the type acquired in step S21 (including the case where no clock signal is supplied to the data processing unit 26 when the input rate is 0) (step S23). This changes the type of clock signal, i.e., the clock frequency, supplied to the data processing unit 26, and changes the operating speed of the data processing unit 26. If the comparison shows that the two types are the same, the clock control unit 27 does not change the type of clock signal.

[0030] 7 shows an example of a graph of the actual change over time of the input rate (for example, the change over time of the input rate when it is assumed that the first time P is greater than the second time Q and the input rate is measured continuously with the second time Q as a period), as a solid line. In the graph, the black dots indicate the input rate notified to the clock control unit 27 at each first time P by the processes shown in FIGS. 4 and 5, which are executed at each first time P.

[0031] 7, the clock signal is CLK2 between timings t1 and t3, CLK4 between timings t3 and t4, and CLK1 from timing t5 onwards. Furthermore, no clock signal is supplied between timings t4 and t5, and the operation of the data processing unit 26 is stopped.

[0032] 7, there is a possibility that the selected clock signal will not be the truly required clock signal. For example, the period from timing t1 to t2 includes a period T during which the processing by the data processing unit 26 cannot keep up with the clock signal CLK2, i.e., a period T during which it would be better to temporarily use the clock signal CLK3. However, by storing input data in the buffer 25A of the data receiving unit 25, processing failures due to insufficient performance of the data processing unit 26 (insufficient clock frequency) can be avoided.

[0033] In this embodiment, the accelerator 20 includes a data receiving unit 25 that receives input data, a data processing unit 26 that processes the input data received by the data receiving unit 25 and outputs the processing results, and a clock control unit 27 that controls the clock frequency of the data processing unit 26. The data receiving unit 25 monitors the amount of input data, and the clock control unit 27 reduces the clock frequency when the amount of data monitored by the data receiving unit 25 decreases. With this configuration, the amount of input data for clock frequency control is monitored within the accelerator 20, eliminating communication delays or monitoring process delays that would occur if the processor 11 controlled the clock frequency of the data processing unit 26 of the accelerator 20. Therefore, the clock frequency of the accelerator 20 can be kept low (including frequency = 0) during low load or idle periods, thereby significantly reducing the dynamic power consumption of the accelerator 20. This delay is particularly likely to occur when the accelerator 20 operates inline. This is because the processor 11 does not directly manage the amount of input data input to the accelerator 20. Therefore, in the inline system, adopting the above configuration effectively increases the amount of dynamic power reduction.

[0034] Furthermore, since the clock control unit 27 increases the clock frequency when the amount of data monitored by the data receiving unit 25 increases, the operating speed of the data receiving unit 25 can be controlled appropriately.

[0035] Furthermore, in this embodiment, the data receiving unit 25 includes a buffer 25A configured to hold input data and to output the held input data in response to a request from the data processing unit 26. As a result, even if the input data becomes excessive compared to the data that the data processing unit 26 can process at the current clock frequency, the buffer 25A holds the input data, making it less likely that processing will fail due to an insufficient clock frequency of the data processing unit 26.

[0036] In this embodiment, the data receiving unit 25 counts the integrated value of the amount of input data held in the buffer 25A during a predetermined period and monitors the integrated value as the amount of data. The clock control unit 27 then reduces the clock frequency when the integrated value falls below a threshold A (e.g., the input rate "a2" when the current clock signal is CLK3), and increases the clock frequency when the integrated value exceeds a threshold B (e.g., the input rate "a3" when the current clock signal is CLK3) that is greater than threshold A. This configuration is simple in operation and enables clock frequency control to be achieved with limited computational resources.

[0037] When the first time P and the second time Q are the same, their lengths can be arbitrary. Setting both times to a short length, such as 0.1 μsec, increases the processing load, but reduces the likelihood of a period, such as the period T, in which the actual input rate and the clock frequency do not match, thereby achieving accurate clock frequency control. On the other hand, setting both times to 10 μsec reduces the processing load but reduces the accuracy of the clock frequency. Therefore, the lengths of the first time P and the second time Q should be determined by balancing the processing load and the accuracy of the clock frequency. Even when the second time Q is shorter than the first time P, the lengths of each time should be determined by balancing the processing load and the accuracy of the clock frequency.

[0038] The reset unit 25C of the data receiving unit 25 and the clock control unit 27 may cooperate to execute the process of FIG.

[0039] In the process of FIG. 8, first, the reset unit 25C measures the elapsed time from the start-up of the accelerator 20 or the execution of step S32 described below, and determines whether the measured elapsed time reaches a second time Q (step S31).

[0040] When the elapsed time reaches the second time Q (step S31: Yes), the reset unit 25C supplies a reset signal to the data amount counter 25B (step S32). Thereafter, in the same manner as described above, the data amount counter 25B supplies the current count value to the clock control unit 27 as the input rate of the input data based on the input of the reset signal, and resets the current count value.

[0041] When the input rate is supplied from the data amount counter 25B, if the input rate is equal to or greater than the upper limit (e.g., a2 for CLK2 in Figure 6) of the performance of the data processing unit 26 operating with the current clock signal, the clock control unit 27 increases the clock frequency by one step (steps S33 and S34).

[0042] On the other hand, when the input rate is supplied from the data amount counter 25B, if the input rate is less than the lower limit value (e.g., a1 for CLK2 in Figure 6) of the performance of the data processing unit 26 operating with the current clock signal, the clock control unit 27 lowers the clock frequency by one step (steps S35 and S36).

[0043] The above series of processes is repeated until a predetermined termination condition is met (step S37).

[0044] In the above process, the clock signal can be changed step by step, such as from CLK1 to CLK2. This process also allows the clock frequency to be appropriately controlled.

[0045] Second Embodiment A data processing system according to a second embodiment includes a data receiving unit 125 and a clock control unit 127 shown in Fig. 9 instead of the data receiving unit 25 and the clock control unit 27. The other configurations are the same as those of the first embodiment, so detailed description thereof will be omitted.

[0046] As shown in FIG. 9, the data receiving unit 125 includes a buffer 125A for holding input data, and a buffer management unit 125B for managing the buffer 125A.

[0047] The buffer management unit 125B stores input data input to the data reception unit 125 in the buffer 125A. The buffer 125A is composed of a FIFO (First In First Out) memory or the like. In response to a read request from the data processing unit 26, the buffer management unit 125B outputs the oldest input data held in the buffer 125A to the data processing unit 26. In this way, the buffer management unit 125B manages the input data held in the buffer 125A, and the buffer 125A is configured to output the held input data when a read request is received from the data processing unit 26.

[0048] The buffer management unit 125B periodically derives a buffer usage rate, which is the ratio of the total amount of input data held in the buffer 125A to the maximum amount of data that the buffer 125A can hold. For example, the buffer management unit 125B counts the amount of input data read from and written to the buffer 125A, and derives the buffer usage rate based on the value obtained by subtracting the amount of input data read from the buffer 125A from the amount of input data stored in the buffer 125A. In this way, the buffer management unit 125B monitors the buffer usage rate by deriving it. Each time the buffer management unit 125B derives the buffer usage rate, it supplies the buffer usage rate to the clock control unit 127.

[0049] When the buffer usage rate is supplied, the clock control unit 127 executes, for example, the process shown in Fig. 10. First, the clock control unit 127 references a buffer usage rate / clock table (Fig. 11) that shows the correspondence between the buffer usage rate (BR) and the type of clock signal, and acquires the type of clock signal (i.e., any of CLK1 to CLK4, or no clock signal) that corresponds to the currently supplied buffer usage rate (step S41).

[0050] The clock control unit 127 holds the currently selected type of clock signal and compares the current type of clock signal with the type acquired in step S21 (step S42). If the comparison shows that the two types are different, the clock control unit 127 changes the type of clock signal to be supplied to the data processing unit 26 to the type acquired in step S41 (including the case where no clock signal is supplied to the data processing unit 26 when the input rate is 0) (step S43). This changes the type of clock signal, i.e., the clock frequency, supplied to the data processing unit 26, and changes the operating speed of the data processing unit 26.

[0051] If the comparison shows that the two signals are the same, and if the change in buffer usage rate is increasing and the rate of increase is equal to or greater than threshold C, the clock control unit 127 changes the type of clock signal and increases the clock frequency (steps S44 and S45). The clock control unit 127 holds one or more previously supplied buffer usage rates and derives the rate of increase in buffer usage rate based on the held buffer usage rate and the currently supplied buffer usage rate. If the rate of increase is equal to or greater than threshold C, the clock control unit 127 selects a clock signal with a frequency one step higher than the current clock signal type. This allows the clock frequency to be increased when burst traffic occurs. Note that the clock control unit 127 may select the clock signal with the highest frequency to deal with burst traffic. If the comparison shows that the two signals are the same but the above-mentioned condition is not met, the clock control unit 127 does not change the clock frequency.

[0052] An example of a graph showing changes in buffer usage rate is shown by a solid line in Figure 12. As shown in Figure 12, the clock control unit 127 can select an appropriate clock frequency depending on changes in buffer usage rate. In Figure 12, the type of clock signal is CLK1 until timing t1, CLK2 from timing t1 to t2, CLK3 from timing t2 to t4, CLK4 from timing t4 to t5, and CLK3 from timing t5 onwards. The clock signal from timing t2 to t3 is CLK3 because the slope of the buffer usage rate has increased and the increase has exceeded threshold C.

[0053] In this embodiment as well, the data receiving unit 125 monitors the amount of input data, and the clock control unit 127 controls the clock frequency to reduce the clock frequency when the amount of data monitored by the data receiving unit 125 decreases. With this configuration, the same effects as in the first embodiment can be obtained.

[0054] The data receiving unit 125 also includes a buffer 125A configured to hold input data and to output the held input data when a read request is received from the data processing unit 26. This provides the same effect as the buffer 25A.

[0055] Furthermore, the data receiving unit 125 derives the buffer utilization rate of the buffer 125A and monitors this utilization rate as the data volume. The clock control unit 127 reduces the clock frequency when the buffer utilization rate decreases and increases the clock frequency when the buffer utilization rate increases. Because the buffer utilization rate is an instantaneous value, using the buffer utilization rate allows for precise control of the clock frequency in real time. This allows the data processing unit 26 to operate appropriately.

[0056] In particular, the data receiving unit 125 reduces the clock frequency when the buffer usage rate of the buffer 125A falls below a threshold D, and increases the clock frequency when the buffer usage rate is equal to or greater than the threshold E. This allows for more appropriate control of the clock frequency.

[0057] Furthermore, as described above, the clock control unit 127 increases the clock frequency when the rate of increase in the buffer usage rate is equal to or greater than the threshold C. This allows the clock frequency to be increased even when burst traffic is input, reducing the possibility of input data overflowing from the buffer 125A. In particular, even when the buffer usage rate of the buffer 125A is equal to or greater than the threshold D but less than the threshold E and there is no need to increase the clock frequency, the data receiving unit 125 can increase the clock frequency depending on the rate of increase, thereby allowing burst traffic to be handled appropriately.

[0058] The clock control unit 127 may perform the process shown in FIG.

[0059] In the process of Fig. 13, the clock control unit 127 first determines whether the current buffer usage rate has decreased compared to the previous buffer usage rate (step S51). If the buffer usage rate has decreased (step S51; Yes), the clock control unit 127 determines whether a clock frequency change condition is met, and if so, reduces the clock frequency by one step (steps S52 and S53). The change condition may be, for example, that the buffer usage rate is less than the lower limit of the performance of the data processing unit 26 operating with the current clock signal (e.g., b1 for CLK2 in Fig. 11). The mode of reducing the clock frequency by one step also includes a mode of setting the clock frequency to 0, i.e., a mode of stopping the supply of the clock signal.

[0060] If the buffer usage rate has not decreased (step S51; No), the clock control unit 127 determines whether the current buffer usage rate has increased compared to the previous buffer usage rate (step S54). If the buffer usage rate has increased (step S54; Yes), the clock control unit 127 calculates the difference between the previous and current buffer usage rates, i.e., the increase in buffer usage rate (step S55). The clock control unit 127 then determines whether a clock frequency change condition is met, and if so, increases the clock frequency by one step (steps S56 and S57). The change condition may be, for example, that the buffer usage rate is equal to or greater than the upper limit (e.g., b2 for CLK2 in FIG. 11 ) for the performance of the data processing unit 26 operating with the current clock signal, or that the increase in buffer usage rate is equal to or greater than threshold C. If the increase in buffer usage rate is greater than a predetermined threshold, the clock frequency may be increased by two or more steps.

[0061] The above series of processes is repeated until a predetermined termination condition is met (step S58).

[0062] In the above process, the clock signal can be changed step by step, such as from CLK1 to CLK2. This process also allows the clock frequency to be appropriately controlled.

[0063] (Variation 1) The clock generation unit 21 and the like may be arranged outside the accelerator 20. Alternatively, a single clock generation unit 21 capable of outputting multiple clock signals may be employed. The clock frequency may be controlled using a phase locked loop (PLL) control technique such as that described in Non-Patent Document 2. The accelerator 20 may be a sub-CPU, a graphics processing unit (GPU), or the like.

[0064] (Variation 2) The processor 11 (FIG. 1) may change the clock frequency generated by the clock generation unit based on a clock frequency change request from the accelerator 20 (including the accelerator according to the second embodiment; the same applies below). This change is realized, for example, by the PLL (Phase Locked Loop) control technology described in Non-Patent Document 2.

[0065] In such a case, the clock control unit 27 (or clock control unit 127; the same applies below) of FIG. 2 etc. executes, for example, the process shown in FIG. 14. In the process shown in FIG. 14, the clock control unit 27 periodically increments a count value during a period in which the clock frequency is not changed (steps S61 and S62), and when the count value exceeds a constant, requests the processor 11 to change the frequency (steps S63 and S64). When the clock frequency is changed or after the frequency change request, the clock control unit 27 resets the count value (step S65). When the count value does not exceed the constant or when a predetermined termination condition (step S66) is not satisfied, the process of step S61 is performed again.

[0066] When requesting a frequency change, the clock control unit 27 supplies necessary information such as the input rate for a certain period and buffer usage rate to the processor 11. The processor 11 derives an appropriate clock frequency range based on the received information and changes the settings of the derived clock generation unit. A known method can be used for the derivation. Alternatively, a predetermined table showing the correspondence between the input rate, buffer usage rate, and clock frequency range may be referenced.

[0067] As described above, when the period during which the clock frequency does not change reaches a predetermined period, the processor 11 derives a new clock frequency and supplies the derived clock frequency to the accelerator 20, and the clock control unit 27 controls the clock generation unit to generate a clock signal having the clock frequency from the processor 11. With this configuration, even when the clock frequency does not change, the clock frequency can be finely adjusted, the operating speed of the data processing unit 26 can be made appropriate, and dynamic power can be further reduced.

[0068] (Scope of the present invention) The present invention is not limited to the above-described embodiments and modifications. For example, the present invention includes various modifications to the above-described embodiments and modifications that can be understood by a person skilled in the art within the scope of the technical concept of the present invention. The configurations listed in the above-described embodiments and modifications can be combined as appropriate within a range that does not contradict. In addition, any of the above-described configurations can be deleted.

[0069] (Supplementary Notes) The following are exemplary configurations that are examples of the above-described embodiments and modifications. (Supplementary Note 1) An accelerator comprising: a data accepting unit configured to accept input data; a data processing unit configured to perform processing based on the input data accepted by the data accepting unit and output a result of the processing; and a clock control unit configured to control a clock frequency of the data processing unit, wherein the data accepting unit is configured to monitor an amount of the input data, and the clock control unit is configured to decrease the clock frequency when the amount of data monitored by the data accepting unit decreases. (Supplementary Note 2) The accelerator according to Supplementary Note 1, wherein the data accepting unit comprises a buffer configured to hold the input data and configured to output the held input data when a read request is received from the data processing unit. (Supplementary Note 3) The accelerator according to Supplementary Note 2, wherein the data receiving unit is configured to count an integrated value of the data amount of the input data held in the buffer during a predetermined period and monitor the integrated value as the data amount, and the clock control unit is configured to decrease the clock frequency when the integrated value falls below a first threshold and increase the clock frequency when the integrated value becomes equal to or greater than a second threshold that is greater than the first threshold. (Supplementary Note 4) The accelerator according to Supplementary Note 2, wherein the data receiving unit is configured to monitor a buffer usage rate of the buffer as the data amount, and the clock control unit is configured to decrease the clock frequency when the buffer usage rate decreases and increase the clock frequency when the buffer usage rate increases. (Supplementary Note 5) The accelerator according to Supplementary Note 4, wherein the clock control unit is configured to increase the clock frequency when an increase in the buffer usage rate is equal to or greater than a third threshold.(Supplementary Note 6) A data processing system comprising: the accelerator according to any one of Supplements 1 to 5; and a processor that performs processing by executing a program, wherein the accelerator is provided in an inline system in which the input data to be input to the accelerator is input directly without going through the processor. (Supplementary Note 7) The data processing system according to Supplementary Note 6 further comprises a clock generation unit configured to generate a clock signal having the clock frequency, wherein the processor is configured to derive a new clock frequency and supply the derived clock frequency to the accelerator when a period in which the clock frequency does not change reaches a predetermined period, and a clock control unit of the accelerator is configured to control the clock generation unit to generate a clock signal having the clock frequency from the processor. (Supplementary Note 8) A data processing method executed by an accelerator, comprising: a first step of accepting input data; a second step of performing processing based on the input data accepted in the first step and outputting a result of the processing; and a third step of controlling a clock frequency of the processing, wherein the first step includes a step of monitoring an amount of the input data, and the third step includes a step of decreasing the clock frequency when the amount of data to be monitored decreases.

[0070] 10...data processing system, 11...processor, 20...accelerator, 21-24...first to fourth clock generation units, 25, 125...data reception unit, 25A, 125A...buffer, 25B...data amount counter, 25C...reset unit, 125B...buffer management unit, 26...data processing unit, 27, 127...clock control unit.

Claims

1. An accelerator comprising: a data receiving unit configured to receive input data; a data processing unit configured to perform processing based on the input data received by the data receiving unit and output a result of the processing; and a clock control unit configured to control a clock frequency of the data processing unit, wherein the data receiving unit is configured to monitor an amount of the input data, and the clock control unit is configured to reduce the clock frequency when the amount of data monitored by the data receiving unit decreases.

2. The accelerator according to claim 1, wherein the data receiving unit comprises a buffer configured to hold the input data and configured to output the held input data when a read request is received from the data processing unit.

3. The accelerator of claim 2, wherein the data receiving unit is configured to count an integrated value of the data amount of the input data held in the buffer during a predetermined period and monitor the integrated value as the data amount, and the clock control unit is configured to decrease the clock frequency when the integrated value falls below a first threshold and to increase the clock frequency when the integrated value becomes equal to or greater than a second threshold that is greater than the first threshold.

4. The accelerator of claim 2, wherein the data receiving unit is configured to monitor the buffer usage rate of the buffer as the data amount, and the clock control unit is configured to decrease the clock frequency when the buffer usage rate decreases and to increase the clock frequency when the buffer usage rate increases.

5. The accelerator according to claim 4, wherein the clock control unit is configured to increase the clock frequency when the degree of increase in the buffer usage rate is equal to or greater than a third threshold.

6. A data processing system comprising the accelerator according to claim 1 and a processor that performs processing by executing a program, wherein the accelerator is provided in an inline manner such that the input data input to the accelerator is input directly without passing through the processor.

7. The data processing system of claim 6, further comprising a clock generating unit configured to generate a clock signal having said clock frequency, wherein said processor is configured to derive a new clock frequency when a period during which said clock frequency does not change reaches a predetermined period, and to supply the derived clock frequency to said accelerator, and wherein a clock control unit of said accelerator is configured to control the clock generating unit to generate a clock signal having said clock frequency from said processor.

8. A data processing method executed by an accelerator, comprising: a first step of accepting input data; a second step of performing processing based on the input data accepted in the first step and outputting a result of the processing; and a third step of controlling a clock frequency of the processing, wherein the first step includes a step of monitoring an amount of the input data, and the third step includes a step of decreasing the clock frequency when the amount of data to be monitored decreases.

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