Digital display control buffer circuit and digital display control buffer apparatus

Abstract

A digital display control buffer circuit and a digital display control buffer apparatus. A digital display control buffer circuit (100) at least comprises a deglitching circuit (101), a first comparison unit (102), a second comparison unit (103), and a first switching device (104); a first end of the first switching device (104) and a first input end of the second comparison unit (103) are used for inputting an upstream signal of the digital display control buffer circuit (100); a first input end of the first comparison unit (102) is used for inputting a downstream signal of the digital display control buffer circuit (100); and when a first signal outputted by an output end of the second comparison unit (103) is a falling edge, the deglitching circuit (101) is used for outputting a control signal to a control end of the first switching device (104), so as to turn off the first switching device (104). The digital display control buffer circuit (100) solves the problem of the occurrence of glitches due to long delay in turning off an upstream switching device in the process of a digital display control buffer sending a signal from an upstream position to a downstream position.

Description

Digital display control buffer circuit and digital display control buffer device

[0001] The present disclosure claims priority from a patent document filed on August 18, 2023, with application number 202311049069.9 and titled “Digital Display Control Buffer Circuit and Digital Display Control Buffer Device,” and the entire contents of the document are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of communications, and in particular to a digital display control buffer circuit and a digital display control buffer device. Background Art

[0003] A digital display control buffer (DDC buffer) is a buffer used to connect upstream and downstream circuits in repeater circuits supporting wired multimedia communication protocols. The DDC buffer monitors upstream and downstream signals and transmits the monitored signals to the downstream and upstream circuits, respectively, to facilitate communication between the upstream and downstream circuits. Furthermore, the DDC buffer isolates the load capacitance of the upstream and downstream circuits. The DDC buffer utilizes an open-drain N-type field-effect transistor and a series resistor to achieve pull-up and pull-down functions on the output signal level. This design effectively achieves 5V voltage tolerance.

[0004] However, in the operating mode where the DDC buffer monitors the upstream signal and sends it downstream, a large glitch is generated on the rising edge of the monitored upstream signal. This glitch not only affects the duty cycle of the upstream signal but also increases the risk of misconversion of the upstream signal to a digital signal.

[0005] Therefore, there is an urgent need for a de-burring circuit that can remove the burr phenomenon generated when a digital display control buffer sends a signal from upstream to downstream.

[0006] Summary of the Invention

[0007] The main purpose of the present disclosure is to provide a digital display control buffer circuit and a digital display control buffer device to at least solve the problem in the prior art that when a digital display control buffer sends a signal from upstream to downstream, the delay in closing the upstream switching device is long, resulting in glitches.

[0008] According to one aspect of the present disclosure, a digital display control buffer circuit is provided. The digital display control buffer circuit includes at least a deglitching circuit, a first comparison unit, a second comparison unit, and a first switching device. The first end of the first switching device and the first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit. The first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit. The first input end of the deglitching circuit is electrically connected to the output end of the first comparison unit, the second input end of the deglitching circuit is electrically connected to the output end of the second comparison unit, and the output end of the deglitching circuit is electrically connected to the control end of the first switching device. The deglitching circuit is configured to output a control signal to the control end of the first switching device to turn off the first switching device when the first signal output from the output end of the second comparison unit is a falling edge.

[0009] Optionally, the deburring circuit includes: a trigger unit, wherein the first input end of the trigger unit is the first input end of the deburring circuit, the second input end of the trigger unit is the second input end of the deburring circuit, the output end of the trigger unit is connected to the third input end of the trigger unit, and the trigger unit is used to trigger when the first signal is a falling edge and output a trigger signal; a filtering unit, wherein the first input end of the filtering unit is electrically connected to the first input end of the trigger unit, the second input end of the filtering unit is connected to the output end of the trigger unit, the output end of the filtering unit is the output end of the deburring circuit, and the filtering unit is used to output the control signal when the edges of the second signal output by the first comparison unit and the trigger signal are opposite.

[0010] Optionally, the trigger unit includes a first D trigger, the first D trigger is falling edge triggered, the reset pin of the first D trigger is the first input end of the trigger unit, the CLK pin of the first D trigger is the second input end of the trigger unit, the D pin of the first D trigger is the third input end of the trigger unit, and the Q pin of the first D trigger is the output end of the trigger unit.

[0011] Optionally, the trigger unit includes an inverter and a second D flip-flop, the second D flip-flop is rising edge triggered, the input end of the inverter is the second input end of the trigger unit, the output end of the inverter is electrically connected to the CLK pin of the second D flip-flop, the reset pin of the second D flip-flop is the first input end of the trigger unit, the D pin of the second D flip-flop is the third input end of the trigger unit, and the Q pin of the second D flip-flop is the output end of the trigger unit.

[0012] Optionally, the digital display control buffer circuit further includes an operational amplifier, the first comparison unit is a first comparator, the second comparison unit is a second comparator, the first switching device is a first NMOS transistor, the inverting input terminal of the first comparator is the first input terminal of the first comparison unit, the non-inverting input terminal of the first comparator is the second input terminal of the first comparison unit and is used to input a first reference signal, the output terminal of the first comparator is the output terminal of the first comparison unit, the inverting input terminal of the second comparator is the first input terminal of the second comparison unit, the non-inverting input terminal of the second comparator is the second input terminal of the second comparison unit and is used to input a second reference signal, the output terminal of the second comparator is the output terminal of the second comparison unit, the gate of the first NMOS transistor is the control terminal of the first switching device, the drain of the first NMOS transistor is the first terminal of the first switching device, the inverting input terminal of the operational amplifier is electrically connected to the output terminal of the operational amplifier and the source of the first NMOS transistor respectively, the source of the first NMOS transistor is the second terminal of the first switching device, and the non-inverting input terminal of the operational amplifier is used to input a third reference signal.

[0013] Optionally, the digital display control buffer circuit further includes: a second switching device, a control end of the second switching device is electrically connected to the output end of the second comparison unit, a first end of the second switching device is electrically connected to the first end of the first comparison unit, and a second end of the second switching device is grounded.

[0014] Optionally, the second switching device is a second NMOS tube, the gate of the second NMOS tube is the control end of the second switching device, the drain of the second NMOS is the first end of the second switching device, and the source of the second NMOS tube is the second end of the second switching device.

[0015] Optionally, the digital display control buffer circuit also includes: a third comparator, the inverting input terminal of the third comparator is used to input a fourth reference signal, the non-inverting input terminal of the third comparator is used to input an upstream signal of the digital display control buffer circuit, and the output terminal of the third comparator is used to output a digital signal corresponding to the upstream signal.

[0016] According to another aspect of the present disclosure, a digital display control buffer device is provided, comprising: any one of the digital display control buffer circuits described above.

[0017] Furthermore, the digital display control buffer device also includes: an upstream pull-down circuit, the upstream pull-down circuit including a first impedance, a second impedance, and a third switching device, one end of the first impedance is used to connect to the upstream power supply end, the other end of the first impedance is electrically connected to the first end of the third switching device and the first end of the second impedance, the other end of the first impedance is used to input an upstream signal to the digital display control buffer circuit, the other end of the second impedance and the second end of the third switching device are used for grounding; a downstream pull-down circuit, the downstream pull-down circuit including a third impedance, a fourth impedance, and a fourth switching device, one end of the third impedance is used to connect to the downstream power supply end, the other end of the third impedance is electrically connected to the first end of the fourth switching device and the first end of the fourth impedance, the other end of the third impedance is used to input a downstream signal to the digital display control buffer circuit, the other end of the fourth impedance and the second end of the fourth switching device are used for grounding.

[0018] Applying the technical solution of the present disclosure, a digital display control buffer circuit is provided. The digital display control buffer circuit includes at least a de-glitch circuit, a first comparison unit, a second comparison unit, and a first switching device. The first end of the first switching device and the first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit. The first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit. The first input end of the de-glitch circuit is electrically connected to the output end of the first comparison unit, the second input end of the de-glitch circuit is electrically connected to the output end of the second comparison unit, and the output end of the de-glitch circuit is electrically connected to the control end of the first switching device. The de-glitch circuit is configured to output a control signal to the control end of the first switching device to turn off the first switching device when the first signal output from the output end of the second comparison unit is at a low level. By introducing a de-burring circuit into the above-mentioned digital display control buffer circuit, when monitoring the high-level signal sent upstream of the digital display control buffer, a low-level output signal of the downstream second comparison unit is received, and a control signal is output to the control end of the first switching device to turn off the first switching device, thereby shortening the delay in turning off the first switching device, thereby avoiding interrupting the process of upstream voltage rising, and achieving the effect of removing circuit burrs, solving the problem of long delay in turning off the upstream switching device and generating burrs during the process of the digital display control buffer sending signals from upstream to downstream. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which constitute part of the present disclosure, are intended to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are intended to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the accompanying drawings:

[0020] FIG1 shows a structural block diagram of a digital display control buffer circuit provided in an embodiment of the present disclosure;

[0021] FIG2 shows a structural block diagram of a deburring circuit provided according to an embodiment of the present disclosure;

[0022] FIG3 shows a structural block diagram of a trigger unit provided according to an embodiment of the present disclosure;

[0023] FIG4 shows a structural block diagram of another trigger unit provided according to an embodiment of the present disclosure;

[0024] FIG5 shows a structural block diagram of another digital display control buffer circuit provided according to an embodiment of the present disclosure;

[0025] FIG6 shows a schematic diagram of upstream signal voltage changes;

[0026] 7 is a schematic diagram showing voltage changes of an output signal of a second comparison unit, an output signal of a trigger unit, an output signal of a first comparison unit, and a control signal output by a filtering unit according to an embodiment of the present disclosure;

[0027] FIG8 is a schematic diagram showing a signal voltage change according to an embodiment of the present disclosure;

[0028] FIG9 shows a structural block diagram of a digital display control buffer device provided according to an embodiment of the present disclosure.

[0029] The above drawings include the following reference numerals:

[0030] 100. Digital display control buffer circuit; 101. Deburring circuit; 102. First comparison unit; 103. Second comparison unit; 104. First switching device; 105. Trigger unit; 106. Filter unit; 107. First D flip-flop; 108. AND gate; 109. Second D flip-flop; 110. Inverter; 111. Operational amplifier; 112. Upstream pull-down circuit; 113. Downstream pull-down circuit. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0033] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatus.

[0034] As introduced in the background technology, in the prior art, when a digital display control buffer sends a signal from upstream to downstream, the delay in closing the upstream switching device is long, which will cause glitches. To solve the above problem, the embodiments of the present disclosure provide a digital display control buffer circuit and a digital display control buffer device.

[0035] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0036] FIG1 is a block diagram of a digital display control buffer circuit according to an embodiment of the present disclosure. As shown in FIG1 , the digital display control buffer circuit 100 includes at least a deglitching circuit 101, a first comparison unit 102, a second comparison unit 103, and a first switch 104. A first terminal of the first switch 104 and a first input terminal of the second comparison unit 103 are used to input an upstream signal from the digital display control buffer circuit 100. A first input terminal of the first comparison unit 102 is used to input a downstream signal from the digital display control buffer circuit 100. The first input terminal of the deglitching circuit 101 is electrically connected to an output terminal of the first comparison unit 102. A second input terminal of the deglitching circuit 101 is electrically connected to an output terminal of the second comparison unit 103. The output terminal of the deglitching circuit 101 is electrically connected to a control terminal of the first switch 104. The deglitching circuit 101 is configured to output a control signal to the control terminal of the first switch 104 to turn off the first switch 104 when the first signal output from the output terminal of the second comparison unit 103 is a falling edge.

[0037] Specifically, a digital display control buffer circuit is a buffer circuit that communicates between upstream and downstream circuits in a repeater circuit that supports a wired multimedia communication protocol. The DDC buffer can monitor upstream and downstream circuit signals and send the monitored signals to the upstream and downstream circuits, respectively, thereby enabling communication between the two. In practical applications, when the DDC buffer monitors the upstream circuit and sends a signal to the downstream circuit, a transient overvoltage, or glitch, may occur on the rising edge of the monitored upstream signal. Although this glitch does not affect the DDC buffer's ability to send signals downstream, it can affect the duty cycle of the upstream signal and increase the risk of erroneous conversion of the upstream electrical signal to a digital signal. In practice, the de-glitch circuit directly obtains the low-level control signal output by the second comparison unit, triggers it, and outputs a control signal to directly control the first switching device, significantly reducing the delay in closing the first switching device and further eliminating the aforementioned glitch.

[0038] Through this embodiment, a digital display control buffer circuit is provided. The digital display control buffer circuit includes at least a deglitching circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit. The first input terminal of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit. The first input terminal of the deglitching circuit is electrically connected to the output terminal of the first comparison unit, the second input terminal of the deglitching circuit is electrically connected to the output terminal of the second comparison unit, and the output terminal of the deglitching circuit is electrically connected to the control terminal of the first switching device. The deglitching circuit is configured to output a control signal to the control terminal of the first switching device to turn off the first switching device when the first signal outputted from the output terminal of the second comparison unit is at a low level. By introducing a de-burring circuit into the above-mentioned digital display control buffer circuit, when monitoring the high-level signal sent upstream of the digital display control buffer, a low-level output signal of the downstream second comparison unit is received, and a control signal is output to the control end of the first switching device to turn off the first switching device, thereby shortening the delay in turning off the first switching device, thereby avoiding interrupting the process of upstream voltage rising, and achieving the effect of removing circuit burrs, solving the problem of long delay in turning off the upstream switching device and generating burrs during the process of the digital display control buffer sending signals from upstream to downstream.

[0039] In a specific implementation, as shown in FIG2 , the deglitching circuit 101 includes: a trigger unit 105, wherein a first input terminal of the trigger unit 105 is the first input terminal of the deglitching circuit 101, a second input terminal of the trigger unit 105 is the second input terminal of the deglitching circuit 101, and an output terminal of the trigger unit 105 is connected to a third input terminal of the trigger unit 105. The trigger unit 105 is configured to trigger and output a trigger signal when the first signal has a falling edge; and a filter unit 106, wherein a first input terminal of the filter unit 106 is electrically connected to the first input terminal of the trigger unit 105, a second input terminal of the filter unit 106 is connected to the output terminal of the trigger unit 105, and an output terminal of the filter unit 106 is the output terminal of the deglitching circuit 101. The filter unit 106 is configured to output the control signal when the second signal output by the first comparison unit 102 and the trigger signal have opposite levels. By combining the trigger unit and the filter unit to implement the deglitching circuit, the deglitching circuit can be further simplified.

[0040] Specifically, a flip-flop is an electronic component used to store and stabilize signals, changing its output state under specific input conditions. Flip-flops are commonly used in digital circuits to store and process binary data. Various flip-flops have different input and output characteristics, enabling implementation of various logic functions and timing control. Those skilled in the art can select the appropriate flip-flop based on actual functional requirements.

[0041] To further simplify the trigger unit, as shown in FIG3 , the trigger unit 105 of the present disclosure includes a first D flip-flop 107. The first D flip-flop 107 is falling-edge triggered, a reset pin of the first D flip-flop 107 serves as a first input terminal of the trigger unit 105, a CLK pin of the first D flip-flop 107 serves as a second input terminal of the trigger unit 105, a D pin of the first D flip-flop 107 serves as a third input terminal of the trigger unit 105, and a Q pin of the first D flip-flop 107 serves as an output terminal of the trigger unit 105. Since the D flip-flop has the characteristics of strong stability, high reliability, simple operation, wide applicability, strong programmability, and high-speed performance, configuring the trigger unit as a D flip-flop in this circuit can further enhance the effectiveness of the de-glitch circuit in removing circuit glitches.

[0042] Specifically, the D flip-flop is a basic digital logic circuit element used to store and transmit a single bit of information. It has two input pins and two output pins: the D input pin, the clock input pin, the Q output pin, and the Q′ output pin. The D input pin is used to input the data to be stored. When the clock signal arrives, the D flip-flop stores the value on the D input pin in an internal memory cell. The clock input pin controls the operation of the memory cell. When the clock signal edge arrives, the D flip-flop updates the state of the memory cell based on the value on the D input pin. The Q output pin outputs the value stored in the memory cell. When the clock signal edge arrives, the value on the Q output pin is updated to the value in the memory cell. The Q′ output pin is the complement of the Q output pin, that is, the inverse of the Q output pin. When the clock signal edge arrives, the value on the Q′ output pin is updated to the inverse of the Q output pin. By controlling the value on the D input pin and the clock signal edge, the D flip-flop can implement various functions, such as storage, transmission, and timing control. The D flip-flop has high stability during operation and is resistant to noise and interference, ensuring stable data transmission and storage. The D flip-flop's storage properties ensure reliable data transmission and storage under the action of a clock signal, effectively preventing data loss and errors. Furthermore, the D flip-flop's fast response speed and transmission rate meet the requirements of high-speed sequential circuits, making it suitable for high-speed data transmission and processing.

[0043] As shown in FIG4 , the trigger unit 105 includes an inverter 110 and a second D flip-flop 109. The second D flip-flop 109 is rising-edge triggered. The input of the inverter 110 serves as the second input of the trigger unit 105. The output of the inverter 110 is electrically connected to the CLK pin of the second D flip-flop 109. The reset pin of the second D flip-flop 109 serves as the first input of the trigger unit 105. The D pin of the second D flip-flop 109 serves as the third input of the trigger unit 105. The Q pin of the second D flip-flop 109 serves as the output of the trigger unit 105. Because D flip-flops have the characteristics of strong stability, high reliability, simple operation, wide applicability, strong programmability, and high-speed performance, setting the trigger unit as a D flip-flop in this circuit can further enhance the effectiveness of the deglitching circuit in removing circuit glitch.

[0044] Specifically, high-level triggering means that when the clock signal of the D flip-flop is high, the level change of the data input terminal can be read by the flip-flop; low-level triggering means that when the clock signal of the D flip-flop is low, the level change of the data input terminal can be read by the flip-flop. In high-level triggering mode, the change of the data input terminal is only read by the flip-flop when the clock signal rises, and thus the output changes only when the clock signal rises. In low-level triggering mode, the change of the data input terminal is only read by the flip-flop when the clock signal falls.

[0045] In some embodiments, as shown in FIG5 , the digital display control buffer circuit further includes an operational amplifier 111, the first comparison unit is a first comparator, the second comparison unit is a second comparator, the first switch device is a first NMOS tube, the inverting input terminal of the first comparator is the first input terminal of the first comparison unit, the non-inverting input terminal of the first comparator is the second input terminal of the first comparison unit and is used to input a first reference signal, the output terminal of the first comparator is the output terminal of the first comparison unit, the inverting input terminal of the second comparator is the first input terminal of the second comparison unit, and the second comparator is a first comparator. The non-inverting input of the comparator serves as the second input of the second comparison unit and is used to input the second reference signal. The output of the second comparator serves as the output of the second comparison unit. The gate of the first NMOS transistor serves as the control terminal of the first switching device. The drain of the first NMOS transistor serves as the first terminal of the first switching device. The inverting input of the operational amplifier 111 is electrically connected to the output of the operational amplifier 111 and the source of the first NMOS transistor, respectively. The source of the first NMOS transistor serves as the second terminal of the first switching device. The non-inverting input of the operational amplifier 111 receives the third reference signal. The configuration of the operational amplifier 111 further ensures that the DDC buffer sends a low-voltage signal to the upstream.

[0046] Specifically, the above operational amplifier is used in the process of sending a high-level signal from the upstream circuit. At this time, the DDC buffer monitors the upstream data and transmits the data to the downstream. Since the first switch device and the second switch device are both turned on during the process of sending a low-level signal from the upstream, the operational amplifier first converts V SRC From V ss Pull to V SRC_OL As shown in FIG. 5 , the de-glitch circuit 101 is composed of an AND gate 108 , a second D flip-flop 109 , and an inverter 110 .

[0047] The digital display control buffer circuit disclosed herein further includes a second switching device, wherein a control terminal of the second switching device is electrically connected to the output terminal of the second comparison unit, a first terminal of the second switching device is electrically connected to the first terminal of the first comparison unit, and a second terminal of the second switching device is grounded. The second switching device is configured to further control a downstream circuit.

[0048] Specifically, since the third reference signal V OL_REF than the second reference signal V SNK_REFHigh, at this time the negative input voltage of the second comparator is higher than the positive input voltage, and the second switch device is turned off. There is no second switch device driven at the downstream end. At this time, the negative input of the first comparator is also higher than the positive input, so that the first switch device is turned off, V SRC With V SRC_OL That is, as shown in Figure 6, when the DDC buffer detects the high-level signal sent by the upstream end, V SRC Rising to V DD_SRC The process is divided into three stages: First, from V SS Rising to V SRC_OL , then at level V SRC_OL Lasts for a while and finally rises to V DD_SRC , where V OS Indicates V SRC is pulled to V by the op amp SRC_OL Overshoot voltage during the process. V SRC In V SRC_OL The duration of the glitch depends on the time after the second switch device is turned off, and the downstream load capacitance is large, the duration is long, and the glitch is also due to the overshoot voltage V OS The existence and V SCR At level V SRC_OL In fact, the purpose of the deburring circuit is to shorten the duration of the second stage.

[0049] In some embodiments, the second switching device is a second NMOS transistor, the gate of which serves as the control terminal of the second switching device, the drain of which serves as the first terminal of the second switching device, and the source of which serves as the second terminal of the second switching device. This circuit, by configuring the second switching device as a second NMOS transistor, can further simplify the second switching device and enable the second switching device to control downstream signals.

[0050] Specifically, when the upstream sends a high-level signal, the voltage changes as shown in Figure 7. SRC From V SS Pulled to V SRC_OL During the process, V SRC The level is first higher than the second reference signal V SNK_REF And the output signal of the second comparator V SNK_COMP A falling edge is generated, and the output signal V SRC_COMP Still high, the falling edge triggers the register, after the delay t of the trigger unit CK-Q The output signal of the trigger unit V D The output is low, and then passes through the delay t of the filter unit AND_DLYPull the gate of the first switching device low, disconnecting V SCR With V SRC_OL Since the gate of the second switching device is affected by the output signal V SNK_COMP After being pulled low, the downstream signal V SNK The level is rising slowly. When V SNK Higher than the first reference signal V SRC_REF When the output signal of the first comparator V SRC_COMP From high to low, the trigger in the trigger unit is reset, V D reset is high, but the output signal of the filter unit V DG Still low, without interrupting the upstream signal V SRC The pull-up process completes the above glitch removal process. It should be noted that the output signal V SNK_COMP Generates a falling edge to the output signal V of the first comparator SRC_COMP Time t from high to low II That is, corresponding to the duration of the second stage in FIG6, the output signal V SNK_COMP Trigger the trigger in the trigger unit to turn off the first switch device, and V SRC Rising to V SNK_REF From triggering the trigger to closing the first switch device, only the trigger unit and the filter unit need to delay (t CK-Q +t AND_DLY ) is much shorter than the second stage time length t in Figure 6 II , after the burrs are eliminated, V SRC The rising waveform is shown in Figure 8.

[0051] The digital display control buffer circuit disclosed herein further includes a third comparator, wherein the inverting input terminal of the third comparator is configured to input a fourth reference signal, the non-inverting input terminal of the third comparator is configured to input an upstream signal of the digital display control buffer circuit, and the output terminal of the third comparator is configured to output a digital signal corresponding to the upstream signal. This circuit can further generate a digital signal of the upstream signal.

[0052] Specifically, the process of generating the above-mentioned digital signal through a comparator is as follows: determine the input and output level range of the comparator. The comparator generally has one or more input terminals and one output terminal. The input terminal receives an analog signal and the output terminal outputs a digital signal. According to the needs of the application, the input and output level ranges are determined. A resistor divider network or other circuit can be used to generate a reference level. The analog signal to be converted into a digital signal is connected to the input terminal of the comparator, and the output terminal of the comparator is connected to the circuit that needs to receive the digital signal. According to actual needs, it may be necessary to adjust the threshold of the comparator so that it outputs a high level or a low level when the input signal exceeds or falls below a certain level. After connecting the circuit, the comparator is tested and verified to ensure that it can correctly convert the analog signal into a digital signal.

[0053] The embodiment of the present disclosure further provides a digital display control buffer device, which is introduced below.

[0054] The device includes any one of the aforementioned digital display control buffer circuits. The digital display control buffer circuit includes at least a deglitching circuit, a first comparison unit, a second comparison unit, and a first switching device. The first terminal of the first switching device and the first input terminal of the second comparison unit are used to input an upstream signal from the digital display control buffer circuit, and the first input terminal of the first comparison unit is used to input a downstream signal from the digital display control buffer circuit. The first input terminal of the deglitching circuit is electrically connected to the output terminal of the first comparison unit, the second input terminal of the deglitching circuit is electrically connected to the output terminal of the second comparison unit, and the output terminal of the deglitching circuit is electrically connected to the control terminal of the first switching device. The deglitching circuit is configured to output a control signal to the control terminal of the first switching device to turn off the first switching device when the first signal output from the output terminal of the second comparison unit is at a low level. The digital display control buffer circuit is a buffer circuit that connects upstream and downstream circuits in a repeater circuit supporting a wired multimedia communication protocol.

[0055] Specifically, the DDC buffer can monitor upstream circuit signals and downstream circuit signals, and send the monitored signals to the upstream circuit and downstream circuit respectively, thereby realizing the communication function between the two. In actual applications, in the working mode where the DDC buffer monitors the upstream circuit and sends the signal to the downstream circuit, the monitored upstream signal will generate transient overvoltage, i.e., glitch, on the rising edge. Although the glitch does not affect the function of the DDC buffer to send signals to the downstream, it will affect the duty cycle of the upstream signal and increase the risk of misconversion of the upstream electrical signal to the digital signal. In fact, the de-glitch circuit is triggered by directly obtaining the low-level control signal output by the above-mentioned second comparison unit, and outputs a control signal to directly control the first switching device, thereby greatly reducing the delay in closing the first switching device and further eliminating the above-mentioned glitch.

[0056] In this embodiment, a digital display control buffer device is provided, which includes a digital display control buffer circuit. The digital display control buffer circuit includes at least a deglitching circuit, a first comparison unit, a second comparison unit, and a first switching device. The first end of the first switching device and the first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit. The first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit. The first input end of the deglitching circuit is electrically connected to the output end of the first comparison unit, the second input end of the deglitching circuit is electrically connected to the output end of the second comparison unit, and the output end of the deglitching circuit is electrically connected to the control end of the first switching device. The deglitching circuit is configured to output a control signal to the control end of the first switching device to turn off the first switching device when the first signal output from the output end of the second comparison unit is at a low level. By introducing a de-burring circuit into the above-mentioned digital display control buffer circuit, when monitoring the high-level signal sent upstream of the digital display control buffer, a low-level output signal of the downstream second comparison unit is received, and a control signal is output to the control end of the first switching device to turn off the first switching device, thereby shortening the delay in turning off the first switching device, thereby avoiding interrupting the process of upstream voltage rising, and achieving the effect of removing circuit burrs, solving the problem of long delay in turning off the upstream switching device and generating burrs during the process of the digital display control buffer sending signals from upstream to downstream.

[0057] As an optional solution, as shown in FIG9 , the digital display control buffer device further includes: an upstream pull-down circuit 112, comprising a first impedance, a second impedance, and a third switch device. One end of the first impedance is connected to an upstream power supply terminal, and the other end of the first impedance is electrically connected to the first end of the third switch device and the first end of the second impedance. The other end of the first impedance is used to input an upstream signal to the digital display control buffer circuit 100. The other end of the second impedance and the second end of the third switch device are grounded. A downstream pull-down circuit 113, comprising a third impedance, a fourth impedance, and a fourth switch device. One end of the third impedance is connected to a downstream power supply terminal, and the other end of the third impedance is electrically connected to the first end of the fourth switch device and the first end of the fourth impedance. The other end of the third impedance is used to input a downstream signal to the digital display control buffer circuit 100. The other end of the fourth impedance and the second end of the fourth switch device are grounded. The upstream pull-down circuit 112 can further condition the upstream signal, and the downstream pull-down circuit 113 can further condition the downstream signal.

[0058] Specifically, in addition to the above-mentioned digital display control buffer circuit, it also includes an upstream pull-down circuit and a downstream pull-down circuit. The above-mentioned first impedance and third impedance can be pull-up resistors, the above-mentioned second impedance and fourth impedance can be load capacitors, and the third switching device and the fourth switching device can be NMOS tubes, which are used to send data to the upstream and downstream circuits respectively.

[0059] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0060] From the above description, it can be seen that the above embodiments of the present disclosure achieve the following technical effects:

[0061] 1) The digital display control buffer circuit disclosed herein includes at least a deburring circuit, a first comparison unit, a second comparison unit, and a first switching device. The first end of the first switching device and the first input end of the second comparison unit are used to input the upstream signal of the digital display control buffer circuit. The first input end of the first comparison unit is used to input the downstream signal of the digital display control buffer circuit. The first input end of the deburring circuit is electrically connected to the output end of the first comparison unit, the second input end of the deburring circuit is electrically connected to the output end of the second comparison unit, and the output end of the deburring circuit is electrically connected to the control end of the first switching device. The deburring circuit is used to output a control signal to the control end of the first switching device to turn off the first switching device when the first signal output from the output end of the second comparison unit is a falling edge. By introducing a de-burring circuit into the above-mentioned digital display control buffer circuit, when monitoring the high-level signal sent upstream of the digital display control buffer, a low-level output signal of the downstream second comparison unit is received, and a control signal is output to the control end of the first switching device to turn off the first switching device, thereby shortening the delay in turning off the first switching device, thereby avoiding interrupting the process of upstream voltage rising, and achieving the effect of removing circuit burrs, solving the problem of long delay in turning off the upstream switching device and generating burrs during the process of the digital display control buffer sending signals from upstream to downstream.

[0062] 2) The digital display control buffer device disclosed in the present invention includes a digital display control buffer circuit, which includes at least a deburring circuit, a first comparison unit, a second comparison unit and a first switching device. The first end of the first switching device and the first input end of the second comparison unit are used to input the upstream signal of the digital display control buffer circuit, and the first input end of the first comparison unit is used to input the downstream signal of the digital display control buffer circuit. The first input end of the deburring circuit is electrically connected to the output end of the first comparison unit, the second input end of the deburring circuit is electrically connected to the output end of the second comparison unit, and the output end of the deburring circuit is electrically connected to the control end of the first switching device. The deburring circuit is used to output a control signal to the control end of the first switching device when the first signal output from the output end of the second comparison unit is a falling edge, so as to turn off the first switching device. By introducing a de-burring circuit into the above-mentioned digital display control buffer circuit, when monitoring the high-level signal sent upstream of the digital display control buffer, a low-level output signal of the downstream second comparison unit is received, and a control signal is output to the control end of the first switching device to turn off the first switching device, thereby shortening the delay in turning off the first switching device, thereby avoiding interrupting the process of upstream voltage rising, and achieving the effect of removing circuit burrs, solving the problem of long delay in turning off the upstream switching device and generating burrs during the process of the digital display control buffer sending signals from upstream to downstream.

[0063] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A digital display control buffer circuit, characterized in that: The digital display control buffer circuit at least includes a deburring circuit, a first comparison unit, a second comparison unit and a first switch device. The first end of the first switch device and the first input end of the second comparison unit are used to input an upstream signal of the digital display control buffer circuit. The first input end of the first comparison unit is used to input a downstream signal of the digital display control buffer circuit. The first input end of the deburring circuit is electrically connected to the output end of the first comparison unit. The second input end of the deburring circuit is electrically connected to the output end of the second comparison unit. The output end of the deburring circuit is electrically connected to the control end of the first switch device. The deburring circuit is used to output a control signal to the control end of the first switch device when the first signal output from the output end of the second comparison unit is a falling edge, so as to turn off the first switch device.

2. The digital display control buffer circuit according to claim 1, characterized in that: The deburring circuit comprises: A trigger unit, wherein a first input end of the trigger unit is a first input end of the deburring circuit, a second input end of the trigger unit is a second input end of the deburring circuit, an output end of the trigger unit is connected to a third input end of the trigger unit, and the trigger unit is used to trigger when the first signal is a falling edge and output a trigger signal; A filter unit, wherein a first input end of the filter unit is electrically connected to a first input end of the trigger unit, a second input end of the filter unit is connected to an output end of the trigger unit, an output end of the filter unit is an output end of the deburring circuit, and the filter unit is configured to output the control signal when the edges of the second signal output by the first comparison unit and the trigger signal are opposite.

3. The digital display control buffer circuit according to claim 2, characterized in that: The trigger unit includes a first D trigger, the first D trigger is falling edge triggered, the reset pin of the first D trigger is the first input end of the trigger unit, the CLK pin of the first D trigger is the second input end of the trigger unit, the D pin of the first D trigger is the third input end of the trigger unit, and the Q pin of the first D trigger is the output end of the trigger unit.

4. The digital display control buffer circuit according to claim 2, characterized in that: The trigger unit includes an inverter and a second D flip-flop, the second D flip-flop is rising edge triggered, the input end of the inverter is the second input end of the trigger unit, the output end of the inverter is electrically connected to the CLK pin of the second D flip-flop, the reset pin of the second D flip-flop is the first input end of the trigger unit, the D pin of the second D flip-flop is the third input end of the trigger unit, and the Q pin of the second D flip-flop is the output end of the trigger unit.

5. The digital display control buffer circuit according to claim 1, characterized in that: The digital display control buffer circuit also includes an operational amplifier, the first comparison unit is a first comparator, the second comparison unit is a second comparator, the first switch device is a first NMOS tube, the inverting input end of the first comparator is the first input end of the first comparison unit, the non-inverting input end of the first comparator is the second input end of the first comparison unit and is used to input a first reference signal, the output end of the first comparator is the output end of the first comparison unit, the inverting input end of the second comparator is the first input end of the second comparison unit, the non-inverting input end of the second comparator is the second input end of the second comparison unit and is used to input a second reference signal, the output end of the second comparator is the output end of the second comparison unit, the gate of the first NMOS tube is the control end of the first switch device, the drain of the first NMOS tube is the first end of the first switch device, the inverting input end of the operational amplifier is electrically connected to the output end of the operational amplifier and the source of the first NMOS tube respectively, the source of the first NMOS tube is the second end of the first switch device, and the non-inverting input end of the operational amplifier is used to input a third reference signal.

6. The digital display control buffer circuit according to claim 1, characterized in that: The digital display control buffer circuit also includes: A second switch device, wherein a control terminal of the second switch device is electrically connected to the output terminal of the second comparison unit, a first terminal of the second switch device is electrically connected to the first terminal of the first comparison unit, and a second terminal of the second switch device is grounded.

7. The digital display control buffer circuit according to claim 6, characterized in that: The second switch device is a second NMOS tube, the gate of the second NMOS tube is the control end of the second switch device, the drain of the second NMOS tube is the first end of the second switch device, and the source of the second NMOS tube is the second end of the second switch device.

8. The digital display control buffer circuit according to claim 1, characterized in that: The digital display control buffer circuit also includes: A third comparator, wherein the inverting input terminal of the third comparator is used to input a fourth reference signal, the non-inverting input terminal of the third comparator is used to input an upstream signal of the digital display control buffer circuit, and the output terminal of the third comparator is used to output a digital signal corresponding to the upstream signal.

9. A digital display control buffer device, characterized in that: include: A digital display control buffer circuit as claimed in any one of claims 1 to 8.

10. The digital display control buffer device according to claim 9, characterized in that: The digital display control buffer device also includes: an upstream pull-down circuit, the upstream pull-down circuit comprising a first impedance, a second impedance and a third switch device, one end of the first impedance is used to connect to an upstream power supply terminal, the other end of the first impedance is electrically connected to a first end of the third switch device and a first end of the second impedance, the other end of the first impedance is used to input an upstream signal to the digital display control buffer circuit, and the other end of the second impedance and a second end of the third switch device are used to be grounded; A downstream pull-down circuit, the downstream pull-down circuit includes a third impedance, a fourth impedance and a fourth switch device, one end of the third impedance is used to connect to the downstream power supply end, the other end of the third impedance is electrically connected to the first end of the fourth switch device and the first end of the fourth impedance respectively, the other end of the third impedance is used to input the downstream signal to the digital display control buffer circuit, the other end of the fourth impedance and the second end of the fourth switch device are used for grounding.

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