Split-gate floating-gate flash memory device and manufacturing method therefor

Abstract

Disclosed in the present application are a split-gate floating-gate flash memory device and a manufacturing method therefor. The method comprises: S1: providing a flash memory device, the flash memory device comprising a substrate and gate structures grown on the substrate, select gate protection layers being formed at the tops of the gate structures, third spacer dielectric layers being formed on both sides of each gate structure, and source-drain regions being formed in the substrate located on both sides of each gate structure; S2: using the select gate protection layers and the third spacer dielectric layer as hard masks to perform self-aligned etching on the source-drain regions, so as to form shallow trench contact holes; and S3, depositing metal silicide in the shallow trench contact holes. The solution of the present application can solve the problem of interference in related technologies between adjacent units during programming processes.

Description

A split-gate floating-gate flash memory device and its manufacturing method Technical Field

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a split-gate floating-gate flash memory device and a manufacturing method thereof. Background Art

[0002] Split-gate and floating-gate flash memory technologies are widely used in various embedded electronic products, such as financial IC cards and automotive electronics. Reducing device size can increase storage density, save chip area, and reduce manufacturing costs. However, as device size shrinks, the requirements for flash memory devices' anti-interference properties continue to increase.

[0003] In the manufacturing process of the existing 2-bit / cell (two bits per storage cell) split-gate floating gate flash memory array, as shown in Figure 1, the metal silicide 116 is usually formed directly on the surface of the source and drain heavily doped ion implantation region 115 after the source and drain heavily doped ion implantation region 115 is implanted.

[0004] When a cell is selected and programmed in the aforementioned structure using existing methods, adjacent cells are severely disturbed. This is because during programming, electrons in the selected cell's channel are not fully collected by the high voltage of the bit line. The remaining electrons are accelerated into hot electrons as they pass through the depletion region. These electrons then collide with the floating gate of adjacent cells, causing interference.

[0005] Summary of the Invention

[0006] In order to solve the above problems, the present application provides a split-gate floating gate flash memory device and a manufacturing method thereof.

[0007] In a first aspect, an embodiment of the present application provides a method for manufacturing a split-gate floating-gate flash memory device, comprising:

[0008] S1: Provide a flash memory device, the flash memory device comprising a substrate and a gate structure grown on the substrate, a select gate protection layer formed on a top of the gate structure, a third spacer dielectric layer formed on both sides of the gate structure, and source and drain regions formed in the substrate on both sides of the gate structure;

[0009] S2: using the select gate protection layer and the third spacer dielectric layer as hard masks, performing self-aligned etching on the source and drain regions to form shallow trench contact holes;

[0010] S3: depositing metal silicide in the shallow trench contact hole.

[0011] In some embodiments, in S2, performing self-aligned etching on the source and drain regions to form shallow trench contact holes includes:

[0012] The silicon in the source and drain regions is isotropically etched to form shallow trench contact holes.

[0013] In some embodiments, in S2, the etching depth is 10-200 nm.

[0014] In some embodiments, before S1, a flash memory device formation process is also included, and the formation process includes:

[0015] S01: growing a floating gate oxide layer, a floating gate polysilicon layer, and a first silicon nitride layer in sequence on a substrate having a P-type well, and then performing an STI process to form shallow trench isolation;

[0016] S02: depositing an ONO layer, a control gate polysilicon layer, and a second silicon nitride layer in sequence on the floating gate polysilicon layer;

[0017] S03: defining a flash memory cell area by using a photolithography process, and etching away the second silicon nitride layer in the flash memory cell area;

[0018] S04: performing P-type ion implantation using the remaining second silicon nitride layer as a mask to form a first P-type ion implantation region on the surface of the P-type well;

[0019] S05: forming a self-aligned control gate in the flash memory cell area;

[0020] S06: forming a self-aligned floating gate in the flash memory cell region, wherein the floating gate is located under the control gate;

[0021] S07: performing P-type ion implantation to form a second P-type ion implantation region on the surface of the first P-type ion implantation region;

[0022] S08: depositing a select gate dielectric layer and a select gate polysilicon layer in sequence in the flash memory cell region, and forming a self-aligned select gate by a chemical mechanical polishing process;

[0023] S09: forming a select gate protection layer on the select gate polysilicon layer;

[0024] S010: forming a third spacer dielectric layer on both sides of the flash memory cell region, and forming source and drain regions in the substrate on both sides of the flash memory cell region.

[0025] In some embodiments, forming a self-aligned control gate in the flash memory cell region includes:

[0026] Depositing a silicon oxide layer in the flash memory cell area and forming a first spacer dielectric layer by anisotropic etching, wherein the bottom width of the first spacer dielectric layer defines the length of the control gate;

[0027] The first spacer dielectric layer and the second silicon nitride layer are used as hard masks, and the control gate polysilicon layer and the polysilicon ONO layer are anisotropically etched to form a self-aligned control gate.

[0028] In some embodiments, forming a self-aligned floating gate in the flash memory cell region includes:

[0029] Depositing an insulating dielectric layer on the surface of the floating gate polysilicon layer exposed in the flash memory cell area, and anisotropically etching the insulating dielectric layer to form a second spacer dielectric layer;

[0030] The second sidewall dielectric layer and the first sidewall dielectric layer are used as hard masks to self-align and etch the floating gate polysilicon layer and the floating gate oxide layer to form a floating gate.

[0031] In some embodiments, the S010 includes:

[0032] Using the select gate protection layer, the first spacer dielectric layer and the select gate dielectric layer as hard masks, etching and removing the second silicon nitride layer, the control gate polysilicon layer, the ONO layer and the floating gate polysilicon layer outside the flash memory cell area;

[0033] Performing LDD implantation in the substrate on both sides of the flash memory cell area to form a lightly doped drain ion implantation area;

[0034] forming a third spacer dielectric layer on both sides of the flash memory cell area;

[0035] Source and drain heavily doped ion implantation regions are formed in the substrate on both sides of the flash memory cell region, ultimately forming source and drain regions.

[0036] In a second aspect, an embodiment of the present application provides a split-gate floating gate flash memory device, comprising a substrate and a gate structure grown on the substrate, a selection gate protection layer formed on the top of the gate structure, a third sidewall dielectric layer formed on both sides of the gate structure, source and drain regions formed in the substrate on both sides of the gate structure, shallow trench contact holes formed on the surface of the source and drain regions, and metal silicide deposited in the shallow trench contact holes.

[0037] The technical solution of this application has at least the following advantages:

[0038] 1. By forming shallow trench contact holes in the source and drain regions, the depth and area of ​​the subsequently formed low-resistance metal silicide can be increased, thereby improving the bit line's ability to collect electrons and reducing the electron current density near the bit line junction of the adjacent unit. In other words, the number of electrons accelerated by the depletion region is reduced, thereby reducing the probability of electrons rushing into the floating gate of the adjacent unit, reducing the occurrence of interference, and improving the reliability of the flash memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] FIG1 is a schematic structural diagram of a split-gate floating-gate flash memory device in the prior art;

[0041] FIG2 is a flow chart of a method for manufacturing a split-gate floating-gate flash memory device provided by an exemplary embodiment of the present application;

[0042] 3-4 are schematic diagrams of a device during implementation of a method for manufacturing a split-gate floating-gate flash memory device provided by an exemplary embodiment of the present application;

[0043] 5 is a flow chart of a process for forming a flash memory device in step 1 of a method for manufacturing a split-gate floating-gate flash memory device according to an exemplary embodiment of the present application;

[0044] 6-11 are schematic diagrams of device structures during formation of a flash memory device in step 1 according to an exemplary embodiment of the present application;

[0045] FIG12 is a schematic structural diagram of a split-gate floating-gate flash memory device provided by an exemplary embodiment of the present application.

[0046] Explanation of the accompanying symbols: 1. Substrate; 101. Shallow trench contact hole; 102. Metal silicide; 103. P-type well; 104. Shallow trench isolation; 105. First P-type ion implantation region; 106. Second P-type ion implantation region; 2. Gate structure; 21. Floating gate oxide layer; 22. Floating gate polysilicon layer; 23. ONO layer; 24. Control gate polysilicon layer; 25. Select gate dielectric layer; 26. Select gate polysilicon layer; 3. Source and drain regions; 31. Lightly doped drain ion implantation region; 32. Source and drain heavily doped ion implantation region; 4. Select gate protection layer; 51. Third sidewall dielectric layer; 52. First sidewall dielectric layer; 53. Second sidewall dielectric layer; 61. First silicon nitride layer; 62. Second silicon nitride layer; 7. Flash memory cell area; 201. First split gate structure; 202. Second split gate structure. DETAILED DESCRIPTION

[0047] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0048] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0050] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0051] The present application provides a method for manufacturing a split-gate floating-gate flash memory device, referring to FIG2 , comprising the following steps:

[0052] S1: A flash memory device is provided, which includes a substrate and a gate structure grown on the substrate, a select gate protection layer is formed on the top of the gate structure, a third sidewall dielectric layer is formed on both sides of the gate structure, and source and drain regions are formed in the substrate on both sides of the gate structure.

[0053] Exemplarily, referring to Figure 3, a flash memory device is provided, which includes a substrate 1 and a gate structure 2 grown on the substrate 1, a selection gate protection layer 4 is formed on the top of the gate structure 2, a third sidewall dielectric layer 51 is formed on both sides of the gate structure 2, and a source and drain region 3 is formed in the substrate 1 located on both sides of the gate structure 2.

[0054] S2: using the select gate protection layer and the third sidewall dielectric layer as hard masks, self-aligned etching is performed on the source and drain regions to form shallow trench contact holes.

[0055] Exemplarily, referring to FIG. 4 , the gate protection layer 4 and the third spacer dielectric layer 51 are selected as hard masks to perform self-aligned etching on the source and drain regions 3 to form shallow trench contact holes 101 .

[0056] Furthermore, the silicon in the source and drain regions 3 may be isotropically etched to form shallow trench contact holes 101 .

[0057] In the process of forming the shallow trench contact hole 101, the etching depth is 10-200 nm.

[0058] S3: Depositing metal silicide in the shallow trench contact hole.

[0059] Exemplarily, referring to FIG. 4 , a metal silicide 102 is deposited in the shallow trench contact hole 101 .

[0060] The above-mentioned process method, by first forming the shallow trench contact hole 101 in the source and drain region 3, can increase the depth and area of ​​the low-resistance metal silicide 102 formed subsequently, thereby improving the bit line's ability to collect electrons and reducing the electron current density near the bit line junction of the adjacent unit, that is, reducing the number of electrons accelerated by the depletion region, thereby reducing the probability of electrons rushing into the floating gate of the adjacent unit, reducing the occurrence of interference, and improving the reliability of the flash memory array.

[0061] Furthermore, before the above S1, the process of forming the flash memory device provided in S1 is also included. Referring to FIG. 5 , the process includes the following steps:

[0062] S01: growing a floating gate oxide layer, a floating gate polysilicon layer, and a first silicon nitride layer in sequence on a substrate having a P-type well, and then performing an STI process to form shallow trench isolation.

[0063] Referring to Figure 6 , a floating gate oxide layer 21, a floating gate polysilicon layer 22, and a first silicon nitride layer 61 are sequentially grown on substrate 1 having a P-type well 103 formed thereon. Then, an STI (shallow-trench-isolation) process is performed to form shallow trench isolation 104. This step is used to define the active areas of the flash memory and peripheral logic areas. Substrate 1 can be a P-type substrate.

[0064] S02: depositing an ONO layer, a control gate polysilicon layer, and a second silicon nitride layer in sequence on the floating gate polysilicon layer.

[0065] 7 , an ONO layer 23 , a control gate polysilicon layer 24 and a second silicon nitride layer 62 are sequentially deposited on the floating gate polysilicon layer 22 , wherein the ONO layer 23 includes a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer sequentially stacked from bottom to top.

[0066] S03: defining a flash memory cell region by using a photolithography process, and etching away the second silicon nitride layer in the flash memory cell region.

[0067] 7 , the second silicon nitride layer 62 is first etched by a photolithography process, so that the second silicon nitride layer 62 has an opening. The opening defines the flash memory cell region 7 , that is, the control gate polysilicon layer 24 in the flash memory cell region 7 is exposed.

[0068] S04: performing P-type ion implantation using the remaining second silicon nitride layer as a mask to form a first P-type ion implantation region on the surface of the P-type well.

[0069] 7 , P-type ion implantation is performed using the remaining second silicon nitride layer 62 as a mask, thereby forming a first P-type ion implantation region 105 on the surface of the P-type well 103 .

[0070] S05: forming a self-aligned control gate in the flash memory cell region.

[0071] Furthermore, S05 may include the following contents:

[0072] A silicon oxide layer is deposited in the flash memory cell area, and a first spacer dielectric layer is formed by anisotropic etching. The bottom width of the first spacer dielectric layer defines the length of the control gate.

[0073] 7 , a silicon oxide layer is deposited in the flash memory cell region 7 and anisotropically etched to form a first spacer dielectric layer 52 on both sides of the second silicon nitride layer 62. The bottom width of the first spacer dielectric layer 52 defines the length of the control gate.

[0074] The first sidewall dielectric layer and the second silicon nitride layer are used as hard masks, and the control gate polysilicon layer and the polysilicon ONO layer are anisotropically etched to form a self-aligned control gate.

[0075] 8 , the first sidewall dielectric layer 52 and the second silicon nitride layer 62 are used as hard masks to anisotropically etch the control gate polysilicon layer 24 and the polysilicon ONO layer 23 in the flash memory cell area 7 to form a self-aligned control gate, wherein the control gate includes the remaining control gate polysilicon layer 24 and the polysilicon ONO layer 23.

[0076] S06: forming a self-aligned floating gate in the flash memory cell region, where the floating gate is located under the control gate.

[0077] Furthermore, S06 may include the following contents:

[0078] An insulating dielectric layer is deposited on the surface of the floating gate polysilicon layer exposed in the flash memory cell area, and the insulating dielectric layer is anisotropically etched to form a second sidewall dielectric layer.

[0079] Exemplarily, referring to FIG. 8 , an insulating dielectric layer is deposited on the surface of the floating gate polysilicon layer 22 exposed in the flash memory cell region 7 , and the insulating dielectric layer is anisotropically etched to form a second spacer dielectric layer 53 .

[0080] The second sidewall dielectric layer and the first sidewall dielectric layer are used as hard masks, and the floating gate polysilicon layer and the floating gate oxide layer are self-alignedly etched to form a floating gate.

[0081] 8 , the second sidewall dielectric layer 53 and the first sidewall dielectric layer 52 are used as hard masks to self-align and etch the floating gate polysilicon layer 22 and the floating gate oxide layer 21 in the flash memory cell area 7 to form a floating gate, wherein the floating gate includes the remaining floating gate polysilicon layer 22 and the floating gate oxide layer 21.

[0082] S07: Perform P-type ion implantation to form a second P-type ion implantation region on the surface of the first P-type ion implantation region.

[0083] 8 , P-type ion implantation is performed on the substrate 1 in the flash memory cell region 7 to form a second P-type ion implantation region 106 on the surface of the first P-type ion implantation region 105. The second P-type ion implantation region 106 is used to increase the threshold voltage of the select transistor device.

[0084] S08: depositing a select gate dielectric layer and a select gate polysilicon layer in sequence in the flash memory cell region, and forming a self-aligned select gate through a chemical mechanical polishing process.

[0085] For example, referring to FIG9 , a select gate dielectric layer 25 and a select gate polysilicon layer 26 are sequentially deposited in the flash memory cell region 7 . The bottom of the select gate dielectric layer 25 contacts the second P-type ion implantation region 106 in the substrate 1 . Subsequently, the top of the select gate polysilicon is processed by chemical mechanical polishing to form a self-aligned select gate. The select gate includes the remaining select gate polysilicon layer 26 and the select gate dielectric layer 25 .

[0086] S09: forming a select gate protection layer on the select gate polysilicon layer.

[0087] For example, referring to FIG. 10 , the select gate protection layer 4 may be formed on the select gate polysilicon layer 26 by a thermal oxidation process.

[0088] S010: forming a third spacer dielectric layer on both sides of the flash memory cell region, and forming source and drain regions in the substrate on both sides of the flash memory cell region.

[0089] Exemplarily, referring to FIG. 10 and FIG. 11 , S010 includes the following contents:

[0090] First, using the select gate protection layer 4, the first spacer and the select gate dielectric layer 25 as hard masks, the second silicon nitride layer 62, the control gate polysilicon layer 24, the ONO layer 23 and the floating gate polysilicon layer 22 outside the flash memory cell area 7 are etched away.

[0091] Afterwards, LDD implantation is performed in the substrate 1 on both sides of the flash memory cell region 7 to form lightly doped drain ion implantation regions 31 .

[0092] Afterwards, a third spacer dielectric layer 51 is formed on both sides of the flash memory cell region 7 .

[0093] Finally, source and drain heavily doped ion implantation regions 32 are formed in the substrate 1 on both sides of the flash memory cell region 7 , ultimately forming source and drain regions 3 , which include lightly doped drain ion implantation regions 31 and source and drain heavily doped ion implantation regions 32 .

[0094] The present application also discloses a split-gate floating-gate flash memory device, which is manufactured by the above-mentioned split-gate floating-gate flash memory device manufacturing method. Referring to Figure 12, the split-gate floating-gate flash memory device includes a substrate 1 and a gate structure 2 grown on the substrate 1, wherein the gate structure 2 is formed in the flash memory cell area 7, a select gate protection layer 4 is formed on the top of the gate structure 2, and a third sidewall dielectric layer 51 is formed on both sides of the gate structure 2. Source and drain regions 3 are formed in the substrate 1 on both sides of the gate structure 2, and shallow trench contact holes 101 are formed on the surface of the source and drain regions 3. Metal silicide 102 is deposited in the shallow trench contact holes 101. The source and drain regions 3 include a lightly doped drain ion implantation region 31 and a source and drain heavily doped ion implantation region 32, and the shallow trench contact holes 101 are formed in the source and drain heavily doped ion implantation region 32.

[0095] Referring to Figure 12 , the gate structure 2 includes a first split-gate structure 201 and a second split-gate structure 202 spaced apart from each other, with the first split-gate structure 201 and the second split-gate structure 202 located on opposite sides of the flash memory cell region 7. Both the first split-gate structure 201 and the second split-gate structure 202 include a floating gate and a control gate stacked sequentially from bottom to top. The floating gate comprises a floating gate oxide layer 21 and a floating gate polysilicon layer 22 stacked sequentially from bottom to top on the substrate 1 of the flash memory cell region 7; the control gate comprises an ONO layer 23 and a control gate polysilicon layer 24 stacked sequentially from bottom to top on the floating gate polysilicon layer 22.

[0096] Referring to Figure 12 , the control gates of both the first split-gate structure 201 and the second split-gate structure 202 are covered with a first dielectric spacer 52. A second dielectric spacer 53 is formed on the side of the first dielectric spacer 52 away from the covered control gate. The second dielectric spacer 53 is located on the upper surface of the floating gate that is not covered by the control gate. A select gate is separated from the first split-gate structure 201 and the second split-gate structure 202. The select gate comprises a select gate dielectric layer 25 and a select gate polysilicon layer 26 stacked sequentially from bottom to top, with a select gate protective layer 4 formed above the select gate polysilicon layer 26. The select gate dielectric layer 25 covers the exposed surfaces of the first dielectric spacer 52, the second dielectric spacer 53, and the substrate 1 within the flash memory cell region 7. The select gate dielectric layer 25 surrounds a space for the select gate polysilicon layer 26 to be filled in the space, thereby separating the first split-gate structure 201 and the second split-gate structure 202.

[0097] 12 , a first P-type ion implantation region 105 is formed in the P-type well 103 of the substrate 1 below the gate structure 2 , a second P-type ion implantation region 106 is formed on the surface of the P-type ion implantation region, and the top of the second P-type ion implantation region 106 is in contact with the select gate dielectric layer 25 .

[0098] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing a split-gate floating-gate flash memory device, characterized in that: include: S1: providing a flash memory device, the flash memory device comprising a substrate and a gate structure grown on the substrate, a select gate protection layer formed on the top of the gate structure, a third spacer dielectric layer formed on both sides of the gate structure, and source and drain regions formed in the substrate on both sides of the gate structure; S2: using the select gate protection layer and the third spacer dielectric layer as hard masks, performing self-aligned etching on the source and drain regions to form shallow trench contact holes; S3: depositing metal silicide in the shallow trench contact hole.

2. The method according to claim 1, characterized in that In S2, the self-aligned etching of the source and drain regions to form shallow trench contact holes includes: The silicon in the source and drain regions is isotropically etched to form shallow trench contact holes.

3. The method according to any one of claims 1 or 2, characterized in that: In the step S2, the etching depth is 10-200 nm.

4. The method according to claim 1, characterized in that: Before S1, a flash memory device formation process is also included, and the formation process includes: S01: growing a floating gate oxide layer, a floating gate polysilicon layer and a first silicon nitride layer in sequence on a substrate having a P-type well, and then performing an STI process to form a shallow trench isolation; S02: depositing an ONO layer, a control gate polysilicon layer and a second silicon nitride layer in sequence on the floating gate polysilicon layer; S03: defining a flash memory cell region by using a photolithography process, and etching and removing the second silicon nitride layer in the flash memory cell region; S04: performing P-type ion implantation using the remaining second silicon nitride layer as a mask to form a first P-type ion implantation region on the surface of the P-type well; S05: forming a self-aligned control gate in the flash memory cell region; S06: forming a self-aligned floating gate in the flash memory cell region, wherein the floating gate is located under the control gate; S07: performing P-type ion implantation to form a second P-type ion implantation region on the surface of the first P-type ion implantation region; S08: depositing a selection gate dielectric layer and a selection gate polysilicon layer in sequence in the flash memory cell region, and forming a self-aligned selection gate by a chemical mechanical polishing process; S09: forming a selection gate protection layer on the selection gate polysilicon layer; S010: forming a third spacer dielectric layer on both sides of the flash memory cell region, and forming source and drain regions in the substrate on both sides of the flash memory cell region.

5. The method according to claim 4, characterized in that The forming of a self-aligned control gate in the flash memory cell region comprises: Depositing a silicon oxide layer in the flash memory unit region, and forming a first spacer dielectric layer by anisotropic etching, wherein the bottom width of the first spacer dielectric layer defines the length of the control gate; The first spacer dielectric layer and the second silicon nitride layer are used as hard masks, and the control gate polysilicon layer and the polysilicon ONO layer are anisotropically etched to form a self-aligned control gate.

6. The method according to claim 4, characterized in that The method of forming a self-aligned floating gate in the flash memory cell region comprises: Depositing an insulating dielectric layer on the surface of the floating gate polysilicon layer exposed in the flash memory cell area, and anisotropically etching the insulating dielectric layer to form a second spacer dielectric layer; The second spacer dielectric layer and the first spacer dielectric layer are used as hard masks to self-align and etch the floating gate polysilicon layer and the floating gate oxide layer to form a floating gate.

7. The method according to claim 5, characterized in that The S010 includes: Using the select gate protection layer, the first spacer dielectric layer and the select gate dielectric layer as hard masks, etching and removing the second silicon nitride layer, the control gate polysilicon layer, the ONO layer and the floating gate polysilicon layer outside the flash memory cell area; Performing LDD implantation in the substrate on both sides of the flash memory cell area to form a lightly doped drain ion implantation area; Forming a third spacer dielectric layer on both sides of the flash memory unit area; A source-drain heavily doped ion implantation region is formed in the substrate at both sides of the flash memory cell region, and finally a source-drain region is formed.

8. A split-gate floating-gate flash memory device, characterized in that: The invention comprises a substrate (1) and a gate structure (2) grown on the substrate (1); a selection gate protection layer (4) is formed on the top of the gate structure (2); a third sidewall dielectric layer (51) is formed on both sides of the gate structure (2); source and drain regions (3) are formed in the substrate (1) located on both sides of the gate structure (2); shallow trench (104) contact holes (101) are formed on the surface of the source and drain regions (3); and metal silicide (102) is deposited in the shallow trench (104) contact holes (101).

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