Three-dimensional memory chip array circuit, three-dimensional memory and electronic device

Abstract

The present disclosure relates to a three-dimensional memory chip array circuit, a three-dimensional memory and an electronic device. The three-dimensional memory chip array circuit comprises at least one layer of functional circuit (1) stacked in a direction perpendicular to a substrate. The functional circuit (1) comprises a plurality of cell array circuits (2) arranged in rows and columns in a direction parallel to the substrate. Selection switches (3) of at least one cell array circuit (2) are arranged corresponding to memory cell selection lines (4), wherein each selection switch (3) is configured such that a first input end is connected to a corresponding row selection signal line (Lr), a second input end is connected to a corresponding column selection signal line (Lc), and an output end is connected to a corresponding memory cell selection line (4) to jointly control the turning-on or turning-off of the selection switch (3) via the row selection signal line (Lr) and the column selection signal line (Lc), so as to select or deselect the corresponding memory cell selection line (4).

Description

Three-dimensional memory chip array circuit, three-dimensional memory and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on August 21, 2023, with application number 202311056312.X and invention name “Three-dimensional memory chip array circuit, three-dimensional memory and electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a three-dimensional memory chip array circuit, a three-dimensional memory, and an electronic device. Background Art

[0004] With the development of communication and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and higher performance. Three-dimensional dynamic random access memory (3D-DRAM), known for its higher integration density and larger storage capacity, holds great development prospects.

[0005] 3D DRAM, a stacked structure, typically consists of a large number of rectangular three-dimensional memory arrays. When reading and writing data in a 3D DRAM, only one word line in the array can be opened at a time to read and write data to a single memory cell connected to that word line. This limits the bandwidth for reading and writing data, resulting in poor memory read and write efficiency.

[0006] Summary of the Invention

[0007] According to various embodiments of the present disclosure, a three-dimensional memory chip array circuit, a three-dimensional memory, and an electronic device are provided.

[0008] According to some embodiments, one aspect of the present disclosure provides a three-dimensional memory chip array circuit, which includes a substrate and at least one layer of functional circuits stacked in a direction perpendicular to the substrate, the functional circuit including a plurality of unit array circuits arranged in rows and columns; the unit array circuit including row selection signal lines, column selection signal lines, selection switches, and memory unit selection lines arranged in rows and columns; in at least one functional circuit, the selection switch of at least one unit array circuit is arranged corresponding to the memory unit selection line, and the selection switch is configured as follows: a first input terminal is connected to the corresponding row selection signal line, a second input terminal is connected to the corresponding column selection signal line, a third input terminal is connected to a first potential, and an output terminal is connected to the corresponding memory unit selection line, for jointly controlling the conduction or disconnection of the selection switch via the row selection signal line and the column selection signal line to select or deselect the corresponding memory unit selection line.

[0009] According to some embodiments, the third input terminal of the selection switch is connected to the first potential.

[0010] According to some embodiments, the selection switch includes two transistors, which are configured as follows: at least one of the gates of the two transistors serves as a first input terminal of the selection switch, the source of one of the transistors serves as a second input terminal of the selection switch, the source of the other transistor serves as a third input terminal of the selection switch, and the drains of the two transistors are connected to each other and to a storage cell selection line.

[0011] According to some embodiments, the selection switch includes a first transistor and a second transistor, the first transistor is configured as follows: the gate serves as the first input terminal of the selection switch and is connected to the corresponding row selection signal line, the source serves as the third input terminal of the selection switch and is connected to the first potential, and the drain serves as the output terminal of the selection switch and is connected to the corresponding memory cell selection line; the second transistor is configured as follows: the gate is connected to the gate of the first transistor, the source serves as the second input terminal of the selection switch and is connected to the corresponding column selection signal line, and the drain is connected to the drain of the first transistor; the channel types of the first transistor and the second transistor are different.

[0012] According to some embodiments, in a cell array circuit: the selection switch corresponding to the selected memory cell selection line is configured so that the row selection signal line is connected to the second potential and the column selection signal line is connected to the third potential; and the selection switch corresponding to the unselected memory cell selection line is configured so that the row selection signal line is connected to the third potential and the column selection signal line is connected to the second potential; wherein the amplitude of the third potential is greater than the amplitude of the first potential and the amplitude of the second potential.

[0013] According to some embodiments, the first transistor is an N-type transistor, and the second transistor is a P-type transistor.

[0014] According to some embodiments, the selection switch includes a third transistor and a fourth transistor, the third transistor is configured as follows: the gate is connected to the corresponding complementary row selection signal line, the source serves as the third input terminal of the selection switch and is connected to the first potential, and the drain serves as the output terminal of the selection switch and is connected to the corresponding storage unit selection line; the fourth transistor is configured as follows: the gate serves as the first input terminal of the selection switch and is connected to the corresponding row selection signal line, the source serves as the second input terminal of the selection switch and is connected to the corresponding column selection signal line, and the drain is connected to the drain of the third transistor; the complementary row selection signal line and the row selection signal line transmit signals that are inverted to each other, and the channel type of the third transistor and the fourth transistor is the same.

[0015] According to some embodiments, the third transistor and the fourth transistor are both N-type transistors; in the cell array circuit: the selection switch corresponding to the selected memory cell selection line is configured so that both the row selection signal line and the column selection signal line are connected to the third potential; and the selection switch corresponding to the unselected memory cell selection line is configured so that both the row selection signal line and the column selection signal line are connected to the second potential; wherein the amplitude of the third potential is greater than the amplitude of the first potential and the amplitude of the second potential.

[0016] According to some embodiments, in the functional circuit: adjacent cell array circuits along the row direction share a row selection signal line extending along the row direction, and adjacent cell array circuits along the column direction share a column selection signal line extending along the column direction; the functional circuit further includes multiple row selection switches and multiple column selection switches, and the same row selection switch is connected to the corresponding row selection switch via the shared row selection signal line; the same column selection switch is connected to the corresponding column selection switch via the shared column selection signal line.

[0017] According to some embodiments, a memory cell selection line is configured to electrically connect x layers of memory cells stacked in a direction perpendicular to the substrate; the functional circuit includes a cell array circuit with m rows and n columns; wherein a row selection switch and a column selection switch control a row selection signal line and a column selection signal line to jointly control the conduction of the selection switches to select the corresponding memory cell selection line and simultaneously select q memory cells, q = m × n × x; q, m, x and n are all positive integers.

[0018] According to some embodiments, the memory cell selection line includes a word line or a bit line.

[0019] According to some embodiments, the memory cell selection lines include word lines; in at least one functional circuit: word lines in the same column are all connected to a bit line extending along the column direction via corresponding selection transistors; and word lines in different columns are connected to different bit lines via corresponding selection transistors; wherein the bit lines in the same layer of functional circuits are all connected to a common bit line extending along the row direction, and the bit lines in different layers of functional circuits are connected to different common bit lines.

[0020] According to some embodiments, the functional circuit further includes a bit line control switch, which is arranged corresponding to the bit line; the bit lines in the same layer of functional circuits are all connected to a common bit line extending along the row direction via the corresponding bit line control switch.

[0021] According to some embodiments, the memory cell selection line includes a word line; in at least one functional circuit: two adjacent columns of word lines along the row direction are connected to a bit line extending along the column direction via corresponding selection transistors; wherein, the bit lines in the same layer of functional circuits are all connected to a common bit line extending along the row direction, and the bit lines in different layers of functional circuits are connected to different common bit lines.

[0022] According to some embodiments, in the functional circuit of the same layer, the functional circuit further includes a bit line control line connected to a bit line control switch, and the bit lines are all connected to a common bit line extending along the row direction via the bit line control switch, and the bit line control switch is connected to the corresponding column selection signal line via the bit line control line.

[0023] According to some embodiments, the functional circuit further includes a bit line control line and a bit line connection line connected to the bit line control switch. In at least one functional circuit: two adjacent columns of word lines are connected to a bit line extending in the column direction via corresponding selection transistors, the bit line is connected to a common bit line extending in the row direction via the bit line control switch, and the bit line control switch is connected to an external decoder circuit via the bit line control line and the bit line connection line to realize control of the timing of opening the bit line and the word line.

[0024] According to some embodiments, another aspect of the present disclosure provides a three-dimensional memory, which includes the three-dimensional memory chip array circuit of any of the above embodiments; and a plurality of functional layers stacked along a direction perpendicular to the substrate, the functional layers including a plurality of memory cells arranged in rows and columns; in a functional layer, the memory cell selection lines corresponding to adjacent memory cells along a column direction parallel to the substrate are insulated from each other and extend along a direction perpendicular to the substrate; the memory cells adjacent along the direction perpendicular to the substrate share a memory cell selection line extending along the direction perpendicular to the substrate.

[0025] According to some embodiments, the three-dimensional memory further includes a first three-dimensional memory chip array circuit, a second three-dimensional memory chip array circuit, and a readout amplifier arranged along the row direction; the first three-dimensional memory chip array circuit and the second three-dimensional memory chip array circuit both include a three-dimensional memory chip array circuit; the first three-dimensional memory chip array circuit and the second three-dimensional memory chip array circuit are located on opposite sides of the readout amplifier along the column direction; the first three-dimensional memory chip array circuit is connected to the first input terminal of the readout amplifier, and the second three-dimensional memory chip array circuit is connected to the second input terminal of the readout amplifier.

[0026] According to some embodiments, another aspect of the present disclosure provides an electronic device, comprising the three-dimensional memory in any of the above embodiments.

[0027] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] FIG1 is a schematic diagram of a three-dimensional memory array circuit provided in one embodiment;

[0030] FIG2 is a schematic diagram of a principle diagram of a selection switch provided in one embodiment;

[0031] FIG3 is a schematic diagram of a principle diagram of a selection switch array provided in one embodiment;

[0032] FIG4 is a schematic diagram of a principle diagram of a selection switch provided in another embodiment;

[0033] FIG5 is a schematic diagram of a principle diagram of a selection switch array provided in another embodiment;

[0034] FIG6 is a schematic structural diagram of a selection switch provided in another embodiment;

[0035] FIG7 is a schematic diagram of a functional circuit provided in one embodiment;

[0036] FIG8 is a schematic diagram of a functional circuit provided in another embodiment;

[0037] FIG9 is a schematic diagram of a principle of a three-dimensional memory provided in one embodiment;

[0038] FIG10 is a schematic structural diagram of a three-dimensional memory provided in one embodiment;

[0039] FIG11 is a schematic diagram of a principle of a three-dimensional memory provided in yet another embodiment;

[0040] FIG12 is a schematic structural diagram of a three-dimensional memory provided in yet another embodiment;

[0041] FIG13 is a schematic structural diagram of a memory array circuit provided in one embodiment. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0044] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0045] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.

[0048] In the related art, 3D DRAM with a stacked structure is usually composed of a large number of rectangular three-dimensional memory arrays. Each memory cell in the memory array contains a horizontally placed capacitor and a selection transistor (access transistor) with a drain connected to the capacitor. The gate of the selection transistor is connected to the word line, which is perpendicular to the top surface of the wafer substrate; the source of the selection transistor is connected to the bit line, which is parallel to the top surface of the wafer substrate. A bit line connects multiple memory cells, and each layer has multiple parallel bit lines, stacked in multiple layers. When using a 3D DRAM with the above-mentioned three-dimensional memory array for reading and writing, only one word line can be opened in a memory array at a time, and the memory cells of each layer on this word line are read and written simultaneously, resulting in poor read and write efficiency of the memory. In addition, since the size of the three-dimensional memory array is usually small, the area occupied by the peripheral control circuit is relatively large, which hinders the further miniaturization of memory products.

[0049] Based on this, a three-dimensional memory chip array circuit, a three-dimensional memory and an electronic device are provided, which can at least improve the reading and writing efficiency.

[0050] Referring to FIG1 , according to some embodiments, a three-dimensional memory chip array circuit is provided. The three-dimensional memory chip array circuit includes a substrate and at least one layer of functional circuit 1 stacked in a direction perpendicular to the substrate. The functional circuit 1 includes a plurality of unit array circuits 2 arranged in rows and columns. The unit array circuits 2 can be arranged in rows and columns parallel to the substrate, or in a direction not parallel to the substrate. The unit array circuit 2 includes row selection signal lines Lr, column selection signal lines Lc, selection switches 3, and memory cell selection lines 4 arranged in rows and columns. The memory cell selection lines can be extended in a direction perpendicular to the substrate. The select switch 3 of at least one unit array circuit 2 in at least one functional circuit 1 is provided corresponding to a memory cell select line 4 and is configured such that: a first input terminal is connected to the corresponding row select signal line Lr, a second input terminal is connected to the corresponding column select signal line Lc, and an output terminal is connected to the corresponding memory cell select line 4, for controlling the conduction or disconnection of the select switch 3 via the row select signal line Lr and the column select signal line Lc to select or deselect the corresponding memory cell select line 4. It will be understood that selection refers to causing the memory cell select line 4 to have a high or low level, thereby turning on the transistor of the connected memory cell.

[0051] In the three-dimensional memory chip array circuit of the above embodiment, the unit array circuit 2 includes a row selection signal line Lr, a column selection signal line Lc, a selection switch 3, and a memory cell selection line 4. In at least one functional circuit 1, the selection switch 3 of at least one unit array circuit 2 is arranged corresponding to the memory cell selection line 4, the first input end of the selection switch 3 is connected to the corresponding row selection signal line Lr, the second input end of the selection switch 3 is connected to the corresponding column selection signal line Lc, and the output end of the selection switch 3 is connected to the corresponding memory cell selection line 4, which is used to jointly control the conduction or disconnection of the selection switch 3 via the row selection signal line Lr and the column selection signal line Lc to select or deselect the corresponding memory cell selection line 4, thereby realizing simultaneous reading operations of multiple unit array circuits 2 and improving the reading efficiency of the device.

[0052] 1 , in some embodiments, the third input terminal of the selection switch 3 is connected to the first potential Vlow. For example, the first potential can be a low level, so that the third input terminal of the selection switch 3 is always at a low level.

[0053] 1 , in some embodiments, in the functional circuit 1 , adjacent unit array circuits 2 along the row direction share a row selection signal line Lr extending along the row direction, and adjacent unit array circuits 2 along the column direction share a column selection signal line Lc extending along the column direction; the functional circuit 1 further includes a plurality of row selection switches 5 and a plurality of column selection switches 6 , wherein the same row selection switch 3 is connected to the corresponding row selection switch 5 via the shared row selection signal line Lr; and the same column selection switch 3 is connected to the corresponding column selection switch 6 via the shared column selection signal line Lc.

[0054] In some embodiments, the memory cell selection line 4 is configured to electrically connect x layers of memory cells stacked along a direction perpendicular to the substrate; the functional circuit 1 includes a cell array circuit 2 with m rows and n columns; wherein, a row selection signal line Lr and a column selection signal line Lc are controlled by a row selection switch 5 and a column selection switch 6 to jointly control the conduction of the selection switch 3 to select the corresponding memory cell selection line 4 and q memory cells can be selected at the same time, q = m×n×x; q, m, x and n are all positive integers.

[0055] In the three-dimensional memory chip array circuit of the above embodiment, the functional circuit 1 further includes row selection switches 5 and column selection switches 6. The row selection switches 5 are arranged in a corresponding number of rows as the selection switches 3 of the functional circuit 1. The same row selection switch 3 is connected to the corresponding row selection switch 5 via a common row selection signal line Lr, thereby controlling the potential of the row selection signal line Lr via the row selection switch 5; the column selection switches 6 are arranged in a corresponding number of columns as the selection switches 3 of the functional circuit 1. The same column selection switch 3 is connected to the corresponding column selection switch 6 via a common column selection signal line Lc, thereby controlling the potential of the column selection signal line via the column selection switch 6 to select the memory cell selection line 4. This saves the area occupied by peripheral circuits, reduces device size, and facilitates further product miniaturization.

[0056] Please refer to Figure 2. In some embodiments, the selection switch 3 includes two transistors and is configured as follows: the gates G of the two transistors are connected to the row selection signal line Lr, the source S of one transistor is connected to the column selection signal line Lc, the source S of the other transistor is connected to the first potential Vlow, and the drains D of the two transistors are connected and both connected to the storage cell selection line 4.

[0057] Continuing with FIG. 2 , in some embodiments, the selection switch 3 includes a first transistor T1 and a second transistor T2 . The first transistor T1 is configured such that: a gate G serves as a first input terminal of the selection switch 3 and is connected to a corresponding row selection signal line Lr; a source S serves as a third input terminal of the selection switch 3 and is connected to a first potential Vlow; and a drain D serves as an output terminal of the selection switch 3 and is connected to a corresponding memory cell selection line 4 . The second transistor T2 is configured such that: a gate G is connected to the gate of the first transistor T1 ; a source S serves as a second input terminal of the selection switch 3 and is connected to a corresponding column selection signal line Lc; and a drain D is connected to the drain of the first transistor T1 . The first transistor T1 and the second transistor T2 have different channel types. For example, the first transistor T1 has an N-type channel and the second transistor T2 has a P-type channel, or the first transistor T1 has a P-type channel and the second transistor T2 has an N-type channel.

[0058] In some embodiments, the first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor; the second potential is used to turn on the second transistor T2; and the third potential is used to turn on the first transistor T1.

[0059] For example, when the corresponding memory cell selection line 4 needs to be selected, the row selection signal line Lr to which the gate G of the first transistor T1 and the gate G of the second transistor T2 are commonly connected is connected to a low level. In the selection switches 3 corresponding to the remaining unselected memory cell selection lines 4, the row selection signal line Lr corresponding to the gate G of the first transistor T1 and the gate G of the second transistor T2 is connected to a high level, the column selection signal line Lc corresponding to the source S of the second transistor T2 is connected to a high level, and the column selection signal line Lc corresponding to the source S of the second transistor T2 of the selection switches 3 corresponding to the remaining unselected memory cell selection lines 4 is connected to a low level. At this time, the selection switch 3 corresponding to the selected memory cell selection line 4 is turned on, and the selection switches 3 corresponding to the remaining unselected memory cell selection lines 4 are turned off, so as to achieve the selection of the memory cell selection line 4.

[0060] Referring to FIG. 3 , in some embodiments, in the cell array circuit 2 , the select switch 3 corresponding to the selected memory cell select line 4 is configured such that the row select signal line Lr is connected to the second potential and the column select signal line Lc is connected to the third potential; and the select switch 3 corresponding to the unselected memory cell select line 4 is configured such that the row select signal line Lr is connected to the third potential and the column select signal line Lc is connected to the second potential. The amplitude of the third potential is greater than the amplitude of the first potential Vlow and the amplitude of the second potential. For example, the third potential is a high level and the second potential is a low level. That is, in the selection switch 3 corresponding to the selected storage cell selection line 4, the row selection signal line Lr is connected to the second potential of the low level, the column selection signal line Lc is connected to the third potential of the high level, and the source of the first transistor T1 is connected to the first potential of the low level Vlow. At this time, the selection switch 3 corresponding to the selected storage cell selection line 4 is turned on; correspondingly, in the selection switch 3 corresponding to the unselected storage cell selection line 4, the row selection signal line Lr is connected to the third potential of the high level, and the column selection signal line Lc is connected to the second potential of the low level, then the selection switch 3 corresponding to the unselected storage cell selection line 4 is disconnected, so as to realize the selection or unselection of the storage cell selection line 4.

[0061] Referring to FIG. 4 , in some embodiments, the selection switch 3 includes a third transistor T3 and a fourth transistor T4. The third transistor T3 is configured such that: a gate G is connected to a corresponding complementary row selection signal line LrN; a source S serves as a third input terminal of the selection switch 3 and is connected to a first potential Vlow; and a drain D serves as an output terminal of the selection switch 3 and is connected to a corresponding memory cell selection line. The fourth transistor T4 is configured such that: a gate G serves as a first input terminal of the selection switch 3 and is connected to a corresponding row selection signal line Lr; a source S serves as a second input terminal of the selection switch 3 and is connected to a corresponding column selection signal line Lc; and a drain D is connected to a drain D of the third transistor T3. The complementary row selection signal line LrN and the row selection signal line Lr transmit signals of opposite phases. The third transistor T3 and the fourth transistor T4 have the same channel type. For example, the third transistor T3 and the fourth transistor T4 both have N-type channels, or the third transistor T3 and the second transistor T2 both have P-type channels. For example, when the corresponding memory cell selection line 4 needs to be selected, the row selection signal line Lr corresponding to the gate G of the fourth transistor T4 is connected to a high level, the complementary row selection signal line LrN corresponding to the gate G of the third transistor T3 is connected to a low level, and the column selection signal line Lc corresponding to the source S of the fourth transistor T4 is connected to a high level. In the selection switches 3 corresponding to the remaining unselected memory cell selection lines 4, the row selection signal line Lr corresponding to the gate G of the fourth transistor T4 is connected to a low level, the complementary row selection signal line LrN corresponding to the gate G of the third transistor T3 is connected to a high level, and the column selection signal line Lc corresponding to the source S of the fourth transistor T4 is connected to a low level. At this time, the selection switch 3 corresponding to the selected memory cell selection line 4 is turned on, and the selection switches 3 corresponding to the remaining unselected memory cell selection lines 4 are turned off, so as to achieve the selection of the memory cell selection line 4.

[0062] Referring to FIG. 5 , in some embodiments, the third transistor T3 and the fourth transistor T4 are both N-type transistors. In the cell array circuit 2 , the selection switch 3 corresponding to the selected memory cell selection line 4 is configured such that both the row selection signal line Lr and the column selection signal line Lc are connected to a third potential. Furthermore, the selection switch 3 corresponding to the unselected memory cell selection line 4 is configured such that both the row selection signal line Lr and the column selection signal line Lc are connected to a second potential. The amplitude of the third potential is greater than the amplitude of the first potential Vlow and the amplitude of the second potential. For example, the third potential is a high level, and the second potential is a low level. That is, in the selection switch 3 corresponding to the selected storage cell selection line 4, the row selection signal line Lr is connected to the third potential of the high level, the column selection signal line Lc is connected to the third potential of the high level, and the source of the third transistor T3 is connected to the first potential of the low level Vlow. At this time, the selection switch 3 corresponding to the selected storage cell selection line 4 is turned on; correspondingly, in the selection switch 3 corresponding to the unselected storage cell selection line 4, the row selection signal line Lr is connected to the second potential of the low level, and the column selection signal line Lc is connected to the second potential of the low level, then the selection switch 3 corresponding to the unselected storage cell selection line 4 is disconnected, so as to realize the selection or non-selection of the storage cell selection line 4.

[0063] Referring to FIG6 , in an embodiment where the selection switch 3 includes a third transistor T3 and a fourth transistor T4, the cell array circuit 2 includes a plurality of selection switches 3, a memory cell selection line 4 extending along a first direction, a column selection signal line Lc extending along a second direction, a row selection signal line Lr and a complementary row selection signal line LrN extending along a third direction, and a first potential line extending along the third direction. The first direction is the Z direction, the second direction is the X direction, and the third direction is the Y direction. For example, the second direction and the third direction intersect and are both perpendicular to the first direction.

[0064] Continuing with FIG6 , the selection switch 3 includes an active pillar 31, a channel layer 32 surrounding the active pillar 31, and gate oxide layers 33 located on both sides of the channel layer 32. The channel layer 32 and the corresponding gate oxide layer 33 can be used to form a third transistor T3 or a fourth transistor T4. A row selection signal line Lr is located on one side of the gate oxide layer 33 of the fourth transistor T4, and a portion of the row selection signal line Lr can be used as the gate of the fourth transistor T4. A complementary row selection signal line LrN is located on one side of the gate oxide layer 33 of the third transistor T3, and a portion of the complementary row selection signal line LrN can be used as the gate of the third transistor T3. The row selection signal line Lr and the complementary row selection signal line LrN can be located on the same side or different sides of the selection switch 3. FIG6 illustrates the example of the row selection signal line Lr and the complementary row selection signal line LrN being located on the same side of the selection switch 3. The cell array circuit 2 further includes a first contact plug 34 and a second contact plug 35. The active pillar 31 of the third transistor T3 at the end facing away from the fourth transistor T4 serves as the second input of the selection switch 3 and is connected to the column selection signal line Lc via the first contact plug 34. The active pillar 31 between the third transistor T3 and the fourth transistor T4 serves as the output of the selection switch 3 and is connected to the memory cell selection line 4 via the second contact plug 35. The active pillar 31 of the fourth transistor T4 at the end facing away from the third transistor T3 serves as the third input of the selection switch 3 and is connected to the first potential line and is used to connect to the first potential Vlow. For example, multiple selection switches 3 in the cell array circuit 2 can be symmetrically arranged, and adjacent selection switches 3 along the second direction can share the first potential line and be connected to the same column selection signal line Lc.

[0065] In some embodiments, the memory cell selection line includes a word line or a bit line.

[0066] Referring to FIG. 7 or FIG. 8 , in embodiments where the memory cell select line includes a word line WL, the select switch 3 can be located above or below the three-dimensional stacked memory array. Alternatively, one transistor in the select switch 3 can be located above the three-dimensional stacked memory array, while the other transistor can be located below the three-dimensional stacked memory array. For example, in a select switch 3 comprising a first transistor T1 and a second transistor T2, the first transistor T1 is located above the three-dimensional stacked memory array, while the second transistor T2 is located below the three-dimensional stacked memory array. FIG. 7 illustrates an example of a select switch 3 comprising a first transistor T1 and a second transistor T2 being used above a three-dimensional stacked memory array having a 1T1C structure. FIG. 8 illustrates an example of a select switch 3 comprising a third transistor T3 and a fourth transistor T4 being used above a three-dimensional stacked memory array having a 1T1C structure.

[0067] Please refer to Figure 9. In some embodiments, the memory cell selection line includes a word line WL; in at least one functional circuit: two adjacent columns of word lines WL along the row direction are connected to a bit line BL extending along the column direction through corresponding selection transistors; wherein, the bit lines BL in the same layer of functional circuits are all connected to a common bit line BLc extending along the row direction, and the bit lines BL in different layers of functional circuits are connected to different common bit lines BLc.

[0068] Referring to FIG. 11 , in some embodiments, memory cell select lines include word lines WL. In at least one functional circuit, word lines WL in the same column are all connected to a bit line BL extending along the column direction via corresponding select transistors, and word lines WL in different columns are connected to different bit lines BL via corresponding select transistors. Bit lines BL in the same functional circuit layer are all connected to a common bit line BLc extending along the row direction, while bit lines BL in different functional circuit layers are connected to different common bit lines BLc. This allows for control over the turn-on timing of the bit lines BL and word lines WL.

[0069] 11 , in some embodiments, the functional circuit further includes a bit line control switch 7 , which is disposed corresponding to the bit line BL. The bit lines BL in the functional circuits of the same layer are all connected to a common bit line BLc extending along the row direction via the corresponding bit line control switch 7 .

[0070] Referring to Figures 9 to 12, according to some embodiments, a three-dimensional memory is provided, which includes the three-dimensional memory chip array circuit of any of the above embodiments; and a plurality of functional layers stacked along a direction perpendicular to the substrate, the functional layers including a plurality of memory units SU arranged in rows and columns; in a functional layer, the memory unit selection lines corresponding to adjacent memory units SU along a column direction parallel to the substrate are insulated from each other and extend along a direction perpendicular to the substrate; the memory units SU adjacent along the direction perpendicular to the substrate share a memory unit selection line extending in the direction perpendicular to the substrate.

[0071] In the three-dimensional memory of the above embodiment, multiple functional layers are included, each of which includes a plurality of memory cells SU arranged in rows and columns. The cell array circuit 2 includes a row selection signal line Lr, a column selection signal line Lc, a selection switch 3, and memory cell selection lines arranged in rows and columns and extending in a direction perpendicular to the substrate. In at least one functional circuit, the selection switch 3 of at least one cell array circuit 2 is provided corresponding to a memory cell selection line. A first input terminal of the selection switch 3 is connected to the corresponding row selection signal line Lr, a second input terminal of the selection switch 3 is connected to the corresponding column selection signal line Lc, a third input terminal of the selection switch 3 is connected to a first potential Vlow, and an output terminal of the selection switch 3 is connected to the corresponding memory cell selection line. The selection switch 3 is used to control the conduction or disconnection of the selection switch 3 via the row selection signal line Lr and the column selection signal line Lc to select or deselect the corresponding memory cell selection line, thereby enabling simultaneous reading operations of multiple cell array circuits 2 and improving the reading efficiency of the device.

[0072] Please refer to Figures 10 and 12. In some embodiments, the functional layer has a word line WL extending in a direction perpendicular to the substrate, a common bit line BLc extending in a second direction, a bit line BL extending in a third direction, and a plurality of memory cells SU; the memory cell SU includes a selection transistor 91, the selection transistor 91 includes a first semiconductor layer 912 surrounding the word line WL and a first gate dielectric layer 911 located between the word line WL and the first semiconductor layer 912; the memory cell SU also includes a capacitor, the capacitor includes an active layer 92 located on a sidewall of the first semiconductor layer 912 away from the bit line BL along the second direction, a dielectric layer 94 covering at least the sidewall of the active layer 92, and an electrode layer 93 covering the dielectric layer 94; the functional layer also has an insulating layer 95, the insulating layer 95 fills the gaps between each memory cell SU and the bit line BL, and the common bit line BLc, and the dielectric layer 94 also covers the sidewall of the insulating layer 95 away from the bit line BL.

[0073] Continuing to refer to Figures 10 and 12, in some embodiments, the functional circuit further includes a bit line control switch 7, which is disposed corresponding to the bit line BL. The bit line control switch 7 includes a gate conductive layer 71 extending in a direction perpendicular to the substrate, a second gate dielectric layer 72 surrounding the gate conductive layer 71, and a second semiconductor layer 73 surrounding the second gate dielectric layer 72. The bit lines BL in the same layer of the functional circuit are all connected to a common bit line BLc extending in the row direction via the corresponding bit line control switch 7. For example, the row direction is parallel to the second direction. The functional circuit further includes a bit line control line 74 connected to the bit line control switch 7, and the bit line control line 74 is perpendicular to the substrate. For example, the gate conductive layers 71 of the bit line control switches 7 in different layers are vertically connected to form a single bit line control line 74.

[0074] Referring to Figures 9 and 10 , for example, in at least one functional circuit, two adjacent word lines WL along the row direction are each connected to a bit line BL extending along the column direction via corresponding select transistors 91. The bit lines BL in the same functional circuit layer are each connected to a common bit line BLc extending along the row direction via bit line control switches 7, while the bit lines BL in functional circuits on different layers are connected to different common bit lines BLc via bit line control switches 7. The bit line control switches 7 are connected to corresponding column select signal lines Lc via bit line control lines 74. For example, the column direction is parallel to the third direction.

[0075] For example, in the functional circuits of the same layer, the bit lines BL are all connected to a common bit line BLc extending along the row direction via the bit line control switch 7 , and the bit line control switch 7 is connected to the corresponding column selection signal line Lc via the bit line control line 74 .

[0076] Referring to Figures 11 and 12 , for example, in at least one functional circuit, word lines WL in the same column are all connected to a bit line BL extending along the column direction via corresponding select transistors 91; and word lines WL in different columns are connected to different bit lines BL via corresponding select transistors 91. Bit lines BL in the same layer of functional circuits are all connected to a common bit line BLc extending along the row direction via bit line control switches 7, while bit lines BL in different layers of functional circuits are connected to different common bit lines BLc. The functional circuit also includes a bit line connection line 75 connected to the bit line control switch 7. Bit line connection line 75 is connected to an external decoder circuit via a bit line control line 74, thereby controlling the turn-on timing of the bit lines BL and word lines WL.

[0077] For example, in at least one functional circuit, two adjacent columns of word lines WL are connected to a bit line BL extending along the column direction via corresponding selection transistors 91; the bit line BL is connected to a common bit line BLc extending along the row direction via a bit line control switch 7; the bit line control switch 7 is connected to an external decoder circuit via a bit line connection line 75 to implement control of the turn-on timing of the bit line BL and the word line WL.

[0078] Referring to FIG. 13 , in some embodiments, the three-dimensional memory further includes a first three-dimensional memory chip array circuit 81, a second three-dimensional memory chip array circuit 82, and a sense amplifier 83 arranged along the row direction. The first three-dimensional memory chip array circuit 81 and the second three-dimensional memory chip array circuit 82 each include the three-dimensional memory chip array circuit of any of the above embodiments. The first three-dimensional memory chip array circuit 81 and the second three-dimensional memory chip array circuit 82 are located on opposite sides of the sense amplifier 83 along the column direction. The first three-dimensional memory chip array circuit 81 is connected to a first input terminal of the sense amplifier 83, and the second three-dimensional memory chip array circuit 82 is connected to a second input terminal of the sense amplifier 83. Thus, the first three-dimensional memory chip array circuit 81 and the second three-dimensional memory chip array circuit 82 share the sense amplifier 83.

[0079] According to some embodiments, an electronic device is also provided, including the memory device described in any of the above embodiments, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include a housing, a circuit board disposed within the housing, and a memory device integrated on the circuit board. The electronic device may also include other necessary elements or components, which are not limited in the present embodiments.

[0080] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A three-dimensional memory chip array circuit, wherein: It comprises a substrate and at least one layer of functional circuits stacked in a direction perpendicular to the substrate, wherein the functional circuit comprises a plurality of unit array circuits arranged in rows and columns; The cell array circuit includes a row selection signal line, a column selection signal line, a selection switch and storage cell selection lines arranged in rows and columns; In at least one of the functional circuits, the selection switch of at least one of the unit array circuits is set corresponding to the storage unit selection line, and the selection switch is configured as follows: a first input terminal is connected to the corresponding row selection signal line, a second input terminal is connected to the corresponding column selection signal line, and an output terminal is connected to the corresponding storage unit selection line, and is used to control the conduction or disconnection of the selection switch via the row selection signal line and the column selection signal line to select or deselect the corresponding storage unit selection line.

2. The three-dimensional memory chip array circuit according to claim 1, wherein: The third input terminal of the selection switch is connected to the first potential.

3. The three-dimensional memory chip array circuit according to claim 1 or 2, wherein: The selection switch includes two transistors and is configured as follows: at least one of the gates of the two transistors serves as a first input terminal of the selection switch, a source of one of the transistors serves as a second input terminal of the selection switch, a source of the other transistor serves as a third input terminal of the selection switch, and the drains of the two transistors are connected to each other and to the storage unit selection line.

4. The three-dimensional memory chip array circuit according to claim 1 or 2, wherein: The selection switch comprises: A first transistor, configured as follows: a gate as a first input terminal of the selection switch and connected to a corresponding row selection signal line, a source as a third input terminal of the selection switch and connected to the first potential, and a drain as an output terminal of the selection switch and connected to a corresponding storage unit selection line; a second transistor, configured as follows: a gate connected to the gate of the first transistor, a source serving as a second input terminal of the selection switch and connected to a corresponding column selection signal line, and a drain connected to the drain of the first transistor; The first transistor and the second transistor have different channel types.

5. The three-dimensional memory chip array circuit according to any one of claims 1, 2 and 4, wherein: In the cell array circuit: the selection switch corresponding to the selected storage cell selection line is configured so that the row selection signal line is connected to the second potential and the column selection signal line is connected to the third potential; as well as The selection switches corresponding to the unselected memory cell selection lines are configured such that the row selection signal line is connected to the third potential and the column selection signal line is connected to the second potential; The amplitude of the third potential is greater than the amplitude of the first potential and the amplitude of the second potential.

6. The three-dimensional memory chip array circuit according to any one of claims 1, 2, 4 and 5, wherein: The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

7. The three-dimensional memory chip array circuit according to claim 1 or 2, wherein: The selection switch comprises: A third transistor is configured as follows: a gate is connected to a corresponding complementary row selection signal line, a source is used as a third input terminal of the selection switch and is connected to the first potential, and a drain is used as an output terminal of the selection switch and is connected to a corresponding storage unit selection line; a fourth transistor, configured as follows: a gate serving as a first input terminal of the selection switch and connected to a corresponding row selection signal line, a source serving as a second input terminal of the selection switch and connected to a corresponding column selection signal line, and a drain connected to a drain of the third transistor; The complementary row selection signal line and the row selection signal line transmit signals that are inverted from each other, and the third transistor and the fourth transistor have the same channel type.

8. The three-dimensional memory chip array circuit according to any one of claims 1, 2 and 7, wherein: The third transistor and the fourth transistor are both N-type transistors; In the cell array circuit: the selection switch corresponding to the selected storage cell selection line is configured so that both the row selection signal line and the column selection signal line are connected to the third potential; as well as The select switches corresponding to the unselected storage cell select lines are configured to connect both the row select signal line and the column select signal line. connected to the second potential; The amplitude of the third potential is greater than the amplitude of the first potential and the amplitude of the second potential.

9. The three-dimensional memory chip array circuit according to claim 1 or 2, wherein: In the functional circuit: the unit array circuits adjacent in the row direction share a row selection signal line extending in the row direction, and the unit array circuits adjacent in the column direction share a column selection signal line extending in the column direction; The functional circuit also includes: a plurality of row selection switches, wherein the selection switches in the same row are connected to corresponding row selection switches via a common row selection signal line; and A plurality of column selection switches, wherein the selection switches in the same column are connected to corresponding column selection switches via a common column selection signal line.

10. The three-dimensional memory chip array circuit according to any one of claims 1, 2 and 9, wherein: The memory cell selection line is configured to electrically connect x layers of memory cells stacked along the perpendicular substrate direction; The functional circuit includes a unit array circuit of m rows and n columns; The row selection signal line and the column selection signal line are controlled by the row selection switch and the column selection switch to jointly control the conduction of the selection switch to select the corresponding memory cell selection line and q memory cells can be selected at the same time, q=m×n×x; q, m, x and n are all positive integers.

11. The three-dimensional memory chip array circuit according to claim 1 or 2, wherein: The memory cell selection line includes a word line or a bit line.

12. The three-dimensional memory chip array circuit according to claim 1 or 2, wherein: The memory cell selection line includes a word line; in at least one of the functional circuits: The word lines in the same column are all connected to a bit line extending along the column direction via corresponding selection transistors; and The word lines in different columns are connected to different bit lines via corresponding selection transistors; The bit lines in the functional circuits of the same layer are all connected to a common bit line extending along the row direction, and the bit lines in the functional circuits of different layers are connected to different common bit lines.

13. The three-dimensional memory chip array circuit according to any one of claims 1, 2 and 12, wherein: The functional circuit also includes: The bit line control switch is arranged corresponding to the bit line; the bit lines in the functional circuits of the same layer are all connected to a common bit line extending along the row direction via the corresponding bit line control switch.

14. The three-dimensional memory chip array circuit according to claim 1 or 2, wherein: The memory cell selection line includes a word line; in at least one of the functional circuits: The word lines of two adjacent columns along the row direction are both connected to a bit line extending along the column direction via corresponding selection transistors; The bit lines in the functional circuits of the same layer are all connected to a common bit line extending along the row direction, and the bit lines in the functional circuits of different layers are connected to different common bit lines.

15. The three-dimensional memory chip array circuit according to any one of claims 1, 2, 12, and 13, wherein: The functional circuit also includes a bit line control line connected to the bit line control switch. In the functional circuits on the same layer, the bit lines are all connected to a common bit line extending along the row direction via the bit line control switch, and the bit line control switch is connected to the corresponding column selection signal line via the bit line control line.

16. The three-dimensional memory chip array circuit according to any one of claims 1, 2, 12, and 13, wherein: The functional circuit also includes a bit line control line and a bit line connection line connected to the bit line control switch. In at least one functional circuit: the word lines in two adjacent columns are connected to a bit line extending in the column direction via the corresponding selection transistors, the bit line is connected to a common bit line extending in the row direction via the bit line control switch, and the bit line control switch is connected to an external decoder circuit via the bit line control line and the bit line connection line, so as to realize the control of the start-up timing of the bit line and the word line.

17. A three-dimensional memory, wherein: A three-dimensional memory chip array circuit comprising any one of claims 1 to 16; and a plurality of functional layers stacked in a direction perpendicular to the substrate, wherein the functional layers comprise a plurality of memory cells arranged in rows and columns; In the functional layer, the memory cell selection lines corresponding to the memory cells adjacent to each other along the column direction parallel to the substrate are insulated from each other and extend along the direction perpendicular to the substrate; The memory cells adjacent to each other along the direction perpendicular to the substrate share a memory cell selection line extending along the direction perpendicular to the substrate.

18. The three-dimensional memory according to claim 17, wherein: It also includes a first three-dimensional memory chip array circuit, a second three-dimensional memory chip array circuit, and readout amplifiers arranged along the row direction; The first three-dimensional memory chip array circuit and the second three-dimensional memory chip array circuit both include the three-dimensional memory chip array circuit; The first three-dimensional memory chip array circuit and the second three-dimensional memory chip array circuit are located on two opposite sides of the readout amplifier along the column direction; The first three-dimensional memory chip array circuit is connected to a first input terminal of the readout amplifier, and the second three-dimensional memory chip array circuit is connected to a second input terminal of the readout amplifier.

19. An electronic device, wherein: include: The three-dimensional memory according to claim 17 or 18.

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