Semiconductor circuit and driving method

Abstract

A semiconductor circuit according to an embodiment of the present disclosure includes a first inverter capable of applying an inverted voltage of a first node voltage to a second node, a second inverter capable of applying an inverted voltage of a second node voltage to the first node, first and second bit lines, a first transistor provided in a path joining the first bit line and the first node, a second transistor provided in a path joining the second bit line and the second node, first and second control lines, a first ferroelectric capacitor provided in a path joining the first control line and the first node, a second ferroelectric capacitor provided in a path joining the second control line and the second node, a third transistor having a gate connected to the second node, a first signal line, and a fourth transistor provided in a path joining the first signal line and the third transistor.

Description

Semiconductor circuit and driving method

[0001] The present disclosure relates to a semiconductor circuit for storing data and a method for driving the same.

[0002] Data is often stored in semiconductor circuits. For example, Non-Patent Document 1 discloses a technique for improving read disturb by adding two transistors for read operations to a static random access memory (SRAM) memory cell.

[0003] Leland Chang, et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond”, p.129, 2005 Symposium on VLSI Technology

[0004] In a data storage circuit, it is desirable to store data stably by making it difficult for read disturbance and write disturbance to occur.

[0005] It is desirable to provide a semiconductor circuit capable of stably storing data and a method for driving the same.

[0006] A semiconductor circuit according to an embodiment of the present disclosure includes a first inverter, a second inverter, first and second bit lines, a first transistor, a second transistor, first and second control lines, a first ferroelectric capacitor, a second ferroelectric capacitor, a third transistor, a first signal line, and a fourth transistor. The first inverter is capable of generating an inverted voltage of a voltage at a first node and applying the inverted voltage to a second node. The second inverter is capable of generating an inverted voltage of a voltage at the second node and applying the inverted voltage to the first node. The first transistor is provided in a path connecting the first bit line and the first node. The second transistor is provided in a path connecting the second bit line and the second node. The first ferroelectric capacitor is provided in a path connecting the first control line and the first node. The second ferroelectric capacitor is provided in a path connecting the second control line and the second node, the third transistor has a gate connected to the second node, a source, and a drain, and the fourth transistor is provided in a path connecting the first signal line and one of the source and drain of the third transistor.

[0007] A driving method according to an embodiment of the present disclosure includes a first inverter capable of generating an inverted voltage of a voltage at a first node and applying the inverted voltage to a second node; a second inverter capable of generating an inverted voltage of a voltage at the second node and applying the inverted voltage to the first node; a first bit line and a second bit line, a first transistor provided in a path connecting the first bit line and the first node; a second transistor provided in a path connecting the second bit line and the second node; a first control line and a second control line, a first ferroelectric capacitor provided in a path connecting the first control line and the first node; a second ferroelectric capacitor provided in a path connecting the second control line and the second node; a third transistor having a gate connected to the second node, a source, and a drain; and a first signal line and a fourth transistor provided in a path connecting the first signal line and one of the source and drain of the third transistor. the first driving operation includes turning on the semiconductor circuit, applying one of an active voltage and a ground voltage to the first bit line and the second control line, and applying the other of the active voltage and the ground voltage to the second bit line and the first control line; the second driving operation includes turning off the first transistor and the second transistor, applying a ground voltage to the first control line and the second control line, and stopping the supply of power to the first inverter and the second inverter; and the third driving operation includes turning off the first transistor and the second transistor, applying a ground voltage to the first control line and the second control line, and supplying power to the first inverter and the second inverter.

[0008] In a semiconductor circuit according to an embodiment of the present disclosure, a first inverter applies an inverted voltage of a voltage at a first node to a second node, and a second inverter applies an inverted voltage of a voltage at the second node to the first node. A first transistor is provided in a path connecting a first bit line and the first node, and a second transistor is provided in a path connecting a second bit line and the second node. A first ferroelectric capacitor is provided in a path connecting a first control line and the first node, and a second ferroelectric capacitor is provided in a path connecting a second control line and the second node. The second node is connected to a gate of a third transistor. A fourth transistor is provided in a path connecting the first signal line and one of the source and drain of the third transistor.

[0009] In a driving method according to an embodiment of the present disclosure, the semiconductor circuit is subjected to a first driving operation, a second driving operation, and a third driving operation. In the first driving operation, the first and second transistors are turned on, one of an active voltage and a ground voltage is applied to the first bit line and the second control line, and the other of the active voltage and the ground voltage is applied to the second bit line and the first control line. In the second driving operation, the first and second transistors are turned off, a ground voltage is applied to the first and second control lines, and power supply to the first and second inverters is stopped. In the third driving operation, the first and second transistors are turned off, a ground voltage is applied to the first and second control lines, and power supply to the first and second inverters is stopped.

[0010] FIG. 1 is a block diagram showing an example configuration of a semiconductor circuit according to a first embodiment of the present disclosure. FIG. 2 is a circuit diagram showing an example configuration of a memory cell shown in FIG. 1. FIG. 3 is a characteristic diagram showing an example characteristic of a ferroelectric capacitor shown in FIG. 2. FIG. 4 is a table showing an example of a write operation of the semiconductor circuit shown in FIG. 1. FIG. 5 is an explanatory diagram showing an operation state in the write operation shown in FIG. 4. FIG. 6 is an explanatory diagram showing another operation state in the write operation shown in FIG. 4. FIG. 7 is an explanatory diagram showing another operation state in the write operation shown in FIG. 4. FIG. 8A is an explanatory diagram showing an operation state in the operation shown in FIG. 7. FIG. 8B is an explanatory diagram showing an example of an operating point of a ferroelectric capacitor in the operation shown in FIG. 8A. FIG. 9A is an explanatory diagram showing another operation state in the operation shown in FIG. 7. FIG. 9B is an explanatory diagram showing an example of an operating point of a ferroelectric capacitor in the operation shown in FIG. 9A. FIG. 10A is an explanatory diagram showing another operation state in the operation shown in FIG. 7. FIG. 10B is an explanatory diagram showing an example of an operating point of a ferroelectric capacitor in the operation shown in FIG. 10A. FIG. 11A is an explanatory diagram illustrating one operating state of a write operation in the semiconductor circuit shown in FIG. 1. FIG. 11B is an explanatory diagram illustrating another operating state of a write operation in the semiconductor circuit shown in FIG. 1. FIG. 11C is an explanatory diagram illustrating another operating state of a write operation in the semiconductor circuit shown in FIG. 1. FIG. 11D is an explanatory diagram illustrating another operating state of a write operation in the semiconductor circuit shown in FIG. 1. FIG. 12 is a table illustrating an example of a read operation and a standby operation of the semiconductor circuit shown in FIG. 1. FIG. 13 is an explanatory diagram illustrating one operating state of the read operation shown in FIG. 12. FIG. 14 is an explanatory diagram illustrating one operating state of the standby operation shown in FIG. 12. FIG. 15 is a table illustrating an example of a store operation of the semiconductor circuit shown in FIG. 1. FIG. 16A is an explanatory diagram illustrating one operating state of the store operation shown in FIG. 15. FIG. 16B is an explanatory diagram illustrating another operating state of the store operation shown in FIG. 15. FIG. 17 is a table illustrating an example of a write operation of a semiconductor circuit according to a modification of the first embodiment. Fig. 18 is an explanatory diagram showing one operation state in the write operation shown in Fig. 17. Fig. 19 is a block diagram showing one configuration example of a semiconductor circuit according to the second embodiment.Fig. 20 is a circuit diagram showing an example of the configuration of the memory cell shown in Fig. 19. Fig. 21 is a block diagram showing an example of the operation of the semiconductor circuit shown in Fig. 19. Fig. 22 is a block diagram showing an example of the operation of a semiconductor circuit according to a modification of the second embodiment. Fig. 23 is a circuit diagram showing an example of the configuration of the memory cell array shown in Fig. 22. Fig. 24 is a circuit diagram showing an example of the configuration of a memory cell according to a modification of the second embodiment. Fig. 25 is a circuit diagram showing an example of the configuration of a memory cell according to another modification of the second embodiment.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. First embodiment 2. Second embodiment

[0012] 1 shows an example of the configuration of a semiconductor circuit (semiconductor circuit 1) according to a first embodiment. The semiconductor circuit 1 is a circuit that stores data. The semiconductor circuit 1 includes a control unit 11, a memory cell array 12, drive units 13 and 14, and a sense amplifier unit 15.

[0013] The control unit 11 is configured to control the operation of the semiconductor circuit 1 by controlling the operations of the memory cell array 12, the drive units 13 and 14, and the sense amplifier unit 15. Specifically, the control unit 11 controls the operation of the semiconductor circuit 1 so that data is written to the memory cell array 12 based on a write command and write data supplied from the outside, and data is read from the memory cell array 12 based on a read command supplied from the outside. The control unit 11 also controls the power supply voltage of each circuit in the semiconductor circuit 1 according to the operation.

[0014] The memory cell array 12 has a plurality of memory cells 20, a plurality of write word lines WWL, a plurality of read word lines RWL, a plurality of write bit lines WBL, a plurality of write bit lines WBLN, a plurality of read bit lines RBL, a plurality of control lines PL, and a plurality of control lines PLN.

[0015] Each of the plurality of memory cells 20 is configured to store data. The plurality of memory cells 20 are arranged in a matrix. The memory cells 20 are connected to a write word line WWL, a read word line RWL, write bit lines WBL and WBLN, a read bit line RBL, and control lines PL and PLN.

[0016] The write word line WWL extends in the horizontal direction in FIG. 1, and one end of the write word line WWL is connected to the driver 13. The read word line RWL extends in the horizontal direction in FIG. 1, and one end of the read word line RWL is connected to the driver 13. The write bit line WBL extends in the vertical direction in FIG. 1, and one end of the write bit line WBL is connected to the driver 14. The write bit line WBLN extends in the vertical direction in FIG. 1, and one end of the write bit line WBLN is connected to the driver 14. The read bit line RBL extends in the vertical direction in FIG. 1, and one end of the read bit line RBL is connected to the sense amplifier unit 15. The control line PL extends in the vertical direction in FIG. 1, and one end of the control line PLN is connected to the driver 14.

[0017] 2 shows an example of the configuration of the memory cell 20. The memory cell 20 has transistors 21 to 28 and ferroelectric capacitors 31 and 32.

[0018] The transistors 21 and 23 are P-type MOS (Metal Oxide Semiconductor) transistors, and the transistors 22 and 24 are N-type MOS transistors. The gate of the transistor 21 is connected to the node N1, its source is connected to the power supply node PWR, and its drain is connected to the node N2. The gate of the transistor 22 is connected to the node N1, its source is grounded, and its drain is connected to the node N2. The transistors 21 and 22 form an inverter IV1. The inverter IV1 inverts the voltage at the node N1 and outputs the inverted voltage to the node N2. The gate of the transistor 23 is connected to the node N2, its source is connected to the power supply node PWR, and its drain is connected to the node N1. The gate of the transistor 24 is connected to the node N2, its source is grounded, and its drain is connected to the node N1. The transistors 23 and 24 form an inverter IV2. The inverter IV2 inverts the voltage at the node N2 and outputs the inverted voltage to the node N1.

[0019] With this configuration, the input terminal of inverter IV1 and the output terminal of inverter IV2 are connected to each other via node N1, and the input terminal of inverter IV2 and the output terminal of inverter IV1 are connected to each other via node N2. As a result, the circuit consisting of inverters IV1 and IV2 maintains one bit of data through positive feedback. In this way, the circuit consisting of inverters IV1 and IV2 functions as a hold circuit that holds one bit of data.

[0020] Transistors 25 to 28 are N-type MOS transistors. The gate of transistor 25 is connected to the write word line WWL, the source is connected to the write bit line WBL, and the drain is connected to node N1. The gate of transistor 26 is connected to the write word line WWL, the source is connected to the write bit line WBLN, and the drain is connected to node N2. The gate of transistor 27 is connected to node N2, the source is grounded, and the drain is connected to the source of transistor 28. The gate of transistor 28 is connected to the read word line RWL, the source is connected to the drain of transistor 27, and the drain is connected to the read bit line RBL.

[0021] The ferroelectric capacitors 31 and 32 are capacitors made of a ferroelectric material and are nonvolatile memory elements that store data by utilizing the polarization state of the ferroelectric. One end of the ferroelectric capacitor 31 is connected to a node N1, and the other end is connected to a control line PL. One end of the ferroelectric capacitor 32 is connected to a node N2, and the other end is connected to a control line PLN.

[0022] 3 shows an example of the operation of the ferroelectric capacitor 31. The horizontal axis represents the voltage ΔV1 across the ferroelectric capacitor 31, and the vertical axis represents the polarization charge in the ferroelectric capacitor 31. The voltage ΔV1 is the voltage of the node N1 with respect to the control line PL.

[0023] The ferroelectric capacitor 31 can be in two polarization states S1 and S2. The polarization state S1 is, for example, a state in which the polarization charge is positive (positive state). The polarization state S2 is, for example, a state in which the polarization charge is negative (negative state).

[0024] For example, when the polarization state of the ferroelectric capacitor 31 is polarization state S2, if the voltage ΔV1 is changed from "0 V" to "1.5 V," the polarization charge changes from negative to positive in response to this change in voltage ΔV1. Then, when the voltage ΔV1 reaches, for example, about "1.5 V," the polarization state changes to polarization state S1 (positive state). Thereafter, when the voltage ΔV1 is returned from "1.5 V" to "0 V," the polarization charge changes slightly but remains positive. In this way, the polarization state of the ferroelectric capacitor 31 becomes polarization state S1.

[0025] For example, when the polarization state of the ferroelectric capacitor 31 is polarization state S1, if the voltage ΔV1 is changed from "0 V" to "-1.5 V", the polarization charge changes from positive to negative in response to this change in voltage ΔV1. Then, when the voltage ΔV1 reaches, for example, about "-1.5 V", the polarization state changes to polarization state S2 (negative state). After that, when the voltage ΔV1 is returned from "-1.5 V" to "0 V", the polarization charge changes slightly but remains negative. In this way, the polarization state of the ferroelectric capacitor 31 becomes polarization state S2.

[0026] Thus, in this example, when the voltage ΔV1 of the ferroelectric capacitor 31 is set to "1.5 V," the polarization state of the ferroelectric capacitor 31 becomes polarization state S1, and when the voltage ΔV1 of the ferroelectric capacitor 31 is set to "-1.5 V," the polarization state of the ferroelectric capacitor 31 becomes polarization state S2. The ferroelectric capacitor 31 has a hysteresis characteristic, as shown in FIG. 3. While the operation of the ferroelectric capacitor 31 has been described above as an example, the same is true for the ferroelectric capacitor 32, and the polarization state of the ferroelectric capacitor 32 changes depending on the voltage ΔV2 across the ferroelectric capacitor 32. The voltage ΔV2 is the voltage of the node N2 with respect to the control line PLN. The ferroelectric capacitors 31 and 32 store data by utilizing such polarization states.

[0027] Thus, the memory cell 20 is composed of eight transistors 21 to 28 and two ferroelectric capacitors 31 and 32. With this configuration, in a write operation in the memory cell 20, data is first written to the ferroelectric capacitors 31 and 32 via the transistors 25 and 26, and then the data written to the ferroelectric capacitors 31 and 32 is written to the circuit consisting of the inverters IV1 and IV2. In addition, in a read operation in this memory cell 20, data written to the circuit consisting of the inverters IV1 and IV2 is read out via the transistor 28.

[0028] The drive unit 13 (Figure 1) is connected to a plurality of write word lines WWL and a plurality of read word lines RWL in the memory cell array 12, and is configured to apply signals to the write word lines WWL and read word lines RWL in the memory cell array 12 based on control signals supplied from the control unit 11.

[0029] The drive unit 14 is connected to the plurality of write bit lines WBL, the plurality of write bit lines WBLN, the plurality of control lines PL, and the plurality of control lines PLN in the memory cell array 12, and is configured to apply signals to the write bit lines WBL, WBLN and the control lines PL, PLN in the memory cell array 12 based on control signals supplied from the control unit 11.

[0030] The sense amplifier unit 15 is connected to a plurality of read bit lines RBL in the memory cell array 12, and is configured to read data from the memory cell array 12 via the read bit lines RBL based on a control signal supplied from the control unit 11, and supply the read data to the control unit 11.

[0031] Here, inverter IV1 corresponds to a specific example of a "first inverter" in an embodiment of the present disclosure. Inverter IV2 corresponds to a specific example of a "second inverter" in an embodiment of the present disclosure. Node N1 corresponds to a specific example of a "first node" in an embodiment of the present disclosure. Node N2 corresponds to a specific example of a "second node" in an embodiment of the present disclosure. Write bit line WBL corresponds to a specific example of a "first bit line" in an embodiment of the present disclosure. Write bit line WBLN corresponds to a specific example of a "second bit line" in an embodiment of the present disclosure. Transistor 25 corresponds to a specific example of a "first transistor" in an embodiment of the present disclosure. Transistor 26 corresponds to a specific example of a "second transistor" in an embodiment of the present disclosure. Control line PL corresponds to a specific example of a "first control line" in an embodiment of the present disclosure. Control line PLN corresponds to a specific example of a "second control line" in an embodiment of the present disclosure. The ferroelectric capacitor 31 corresponds to a specific example of a "first ferroelectric capacitor" in an embodiment of the present disclosure. The ferroelectric capacitor 32 corresponds to a specific example of a "second ferroelectric capacitor" in an embodiment of the present disclosure. The transistor 27 corresponds to a specific example of a "third transistor" in an embodiment of the present disclosure. The read bit line RBL corresponds to a specific example of a "first signal line" in an embodiment of the present disclosure. The transistor 28 corresponds to a specific example of a "fourth transistor" in an embodiment of the present disclosure. The driving units 13 and 14 correspond to a specific example of a "driving unit" in an embodiment of the present disclosure. The sense amplifier unit 15 corresponds to a specific example of a "read unit" in an embodiment of the present disclosure. The power supply node PWR corresponds to a specific example of a "power supply node" in an embodiment of the present disclosure.

[0032] [Operation and Function] Next, the operation and function of the semiconductor circuit 1 of this embodiment will be described.

[0033] (Overall Operation Overview) First, an overview of the overall operation of the semiconductor circuit 1 will be described with reference to FIGS. 1 and 2 . The control unit 11 controls the operation of the memory cell array 12, the drive units 13 and 14, and the sense amplifier unit 15, thereby controlling the operation of the semiconductor circuit 1. Each of the multiple memory cells 20 in the memory cell array 12 stores data. The drive unit 13 applies signals to the write word lines WWL and read word lines RWL in the memory cell array 12 based on control signals supplied from the control unit 11. The drive unit 14 applies signals to the write bit lines WBL and WBLN and control lines PL and PLN in the memory cell array 12 based on control signals supplied from the control unit 11. The sense amplifier unit 15 reads data from the memory cell array 12 via the read bit line RBL based on the control signals supplied from the control unit 11, and supplies the read data to the control unit 11.

[0034] (Detailed Operations) Next, the write operation OP1, read operation OP2, standby operation OP3, and store operation OP4 in the semiconductor circuit 1 will be described in detail.

[0035] 4 shows an example of a write operation OP1 of data to the memory cell 20. The write operation OP1 is an operation of writing data to the memory cell 20. The write operation OP1 includes three operations OP11 to OP13. The operation OP11 is an operation of storing data in the ferroelectric capacitors 31 and 32 in the memory cell 20, the operation OP12 is an operation of temporarily stopping the power supply to the inverters IV1 and IV2, and the operation OP13 is an operation of resuming the power supply to the inverters IV1 and IV2 and transferring the data stored in the ferroelectric capacitors 31 and 32 to a holding circuit consisting of the inverters IV1 and IV2. FIG. 4 shows the voltage VWWL of the write word line WWL, the voltage VPL of the control line PL, the voltage VPLN of the control line PLN, the voltage VWBL of the write bit line WBL, the voltage VWBLN of the write bit line WBLN, the voltage VPWR of the power supply node PWR, the voltage VRWL of the read word line RWL, the voltage VRBL of the read bit line RBL, the voltage VN1 of the node N1, and the voltage VN2 of the node N2 in each of operations OP11 to OP13.

[0036] Fig. 5 shows an example of operation OP11, Fig. 6 shows an example of operation OP12, and Fig. 7 shows an example of operation OP13. In Figs. 5 to 7, inverters IV1 and IV2 are shown using inverter symbols, and transistors 25, 26, and 28 are shown using switch symbols indicating their on / off states. In these operations OP11 to OP13, the drive unit 13 sets the voltage VRWL of the read word line RWL to "0 V," and the sense amplifier unit 15 sets the voltage VRBL of the read bit line RBL to "0 V." This causes the transistor 28 to maintain its off state.

[0037] First, the semiconductor circuit 1 performs operation OP11 to store data in the ferroelectric capacitors 31 and 32 of the memory cell 20 (FIG. 5). Specifically, the driver 13 first sets the voltage VWWL of the write word line WWL to 2V. This turns on the transistors 25 and 26. The driver 14 then sets the voltage VWBL of the write bit line WBL to 0V and the voltage VWBLN of the write bit line WBLN to 1.5V. This causes the voltage VN1 of the node N1 to 0V and the voltage VN2 of the node N2 to 1.5V. The driver 14 also sets the voltage VPL of the control line PL to 1.5V and the voltage VPLN of the control line PLN to 0V. As a result, the voltage ΔV1 of the ferroelectric capacitor 31 becomes "-1.5 V" and the voltage ΔV2 of the ferroelectric capacitor 32 becomes "1.5 V." As a result, the polarization state of the ferroelectric capacitor 31 becomes polarization state S2 (negative state), and the polarization state of the ferroelectric capacitor 32 becomes polarization state S1 (positive state).

[0038] Next, the semiconductor circuit 1 performs operation OP12 to temporarily stop the power supply to the inverters IV1 and IV2 of the memory cell 20 ( FIG. 6 ). Specifically, the drive unit 13 first sets the voltage VWWL of the write word line WWL to "0 V." This turns off the transistors 25 and 26. The drive unit 14 then sets the voltage VWBL of the write bit line WBL, the voltage VWBLN of the write bit line WBLN, the voltage VPL of the control line PL, and the voltage VPLN of the control line PLN to "0 V." The control unit 11 then sets the voltage VPWR of the power supply node PWR to "0 V." The polarization state of the ferroelectric capacitor 31 is maintained in polarization state S2, and the polarization state of the ferroelectric capacitor 32 is maintained in polarization state S1.

[0039] Next, the semiconductor circuit 1 performs operation OP13 to transfer the data stored in the ferroelectric capacitors 31 and 32 to a holding circuit consisting of inverters IV1 and IV2 (FIG. 7). Specifically, the driver 13 first sets the voltage VWWL of the write word line WWL to "0 V." This turns off the transistors 25 and 26. The driver 14 also sets the voltage VWBL of the write bit line WBL, the voltage VWBLN of the write bit line WBLN, the voltage VPL of the control line PL, and the voltage VPLN of the control line PLN to "0 V." The controller 11 then changes the voltage VPWR of the power supply node PWR from "0 V" to "1 V." This causes the voltages VN1 and VN2 of the nodes N1 and N2 to change to voltages corresponding to the polarization states of the ferroelectric capacitors 31 and 32.

[0040] 8A, 8B, 9A, 9B, 10A, and 10B show an example of detailed operations in operation OP13. In this operation OP13, the state of the memory cell 20 changes in the order of the states shown in FIGS. 8A and 8B, the states shown in FIGS. 9A and 9B, and the states shown in FIGS. 10A and 10B. In FIGS. 8B, 9B, and 10B, square symbols indicate operating points of the ferroelectric capacitor 31, and circle symbols indicate operating points of the ferroelectric capacitor 32. Note that the read word line RWL, read bit line RBL, and transistors 27 and 28 are not shown in FIGS. 8A, 8B, and 8C.

[0041] 8A, the voltage of the power supply node PWR changes from "0V" to "1V." Initially, the voltage VN1 of the node N1 and the voltage VN2 of the node N2 are "0V." Therefore, as the voltage of the power supply node PWR rises, the transistor 21 of the inverter IV1 and the transistor 23 of the inverter IV2 change from the OFF state to the ON state. As a result, a current I1 flows from the power supply node PWR to the node N2 via the transistor 21 of the inverter IV1, and a current I2 flows from the power supply node PWR to the node N1 via the transistor 23 of the inverter IV2, so that the voltage VN1 of the node N1 and the voltage VN2 of the node N2 rise. Therefore, the voltages ΔV1 and ΔV2 of the ferroelectric capacitors 31 and 32 increase, and as shown in FIG. 8B, the operating point of the ferroelectric capacitor 31 moves to the right along the characteristic line of the polarization state S2 of the ferroelectric capacitor 31, and the operating point of the ferroelectric capacitor 32 moves to the right along the characteristic line of the polarization state S1 of the ferroelectric capacitor 32.

[0042] 8B, the change in polarization charge when the operating point of ferroelectric capacitor 32 changes is smaller than the change in polarization charge when the operating point of ferroelectric capacitor 31 changes. This means that the capacitance across ferroelectric capacitor 32 is smaller than the capacitance across ferroelectric capacitor 31. Therefore, the voltage VN2 at node N2 to which ferroelectric capacitor 32 is connected rises faster than the voltage VN1 at node N1 to which ferroelectric capacitor 31 is connected.

[0043] When the voltage VN2 at node N2 rises, the transistor 23 of the inverter IV2 changes from an ON state to an OFF state, and the transistor 24 changes from an OFF state to an ON state. As a result, as shown in FIG. 9A, a current I3 flows from the node N1 to the ground node via the transistor 24 of the inverter IV2. This causes the voltage VN1 at node N1 to fall. In this manner, the voltage VN2 at node N2 rises, and the voltage VN1 at node N1 falls. As a result, the voltage ΔV1 of the ferroelectric capacitor 31 falls, and the voltage ΔV2 of the ferroelectric capacitor 32 rises. Therefore, as shown in FIG. 9B, the operating point of the ferroelectric capacitor 31 shifts leftward along the characteristic line of the polarization state S2 of the ferroelectric capacitor 31, and the operating point of the ferroelectric capacitor 32 shifts rightward along the characteristic line of the polarization state S1 of the ferroelectric capacitor 32.

[0044] In this way, the voltage VN2 at the node N2 rises, and the voltage VN1 at the node N1 falls. Finally, as shown in Fig. 10A, the voltage VN1 at the node N1 becomes "1 V," and the voltage VN2 at the node N2 becomes "0 V." As shown in Fig. 10B, the voltage ΔV1 at the ferroelectric capacitor 31 is "0 V," and the voltage ΔV2 at the ferroelectric capacitor 32 is "1 V."

[0045] In this way, the semiconductor circuit 1 performs an operation OP11 to store data in the ferroelectric capacitors 31 and 32 in the memory cell 20, an operation OP12 to temporarily stop the power supply to the inverters IV1 and IV2, and an operation OP13 to resume the power supply to the inverters IV1 and IV2 and transfer the data stored in the ferroelectric capacitors 31 and 32 to the holding circuit made up of the inverters IV1 and IV2. This makes it possible to make the semiconductor circuit 1 less susceptible to write disturbance, as will be described below.

[0046] 11A to 11D show an example of a data write operation in the memory cell array 12. These figures show two memory cells 20 (memory cells 20A and 20B). These two memory cells 20A and 20B belong to the same row and are connected to one write word line WWL and one read word line RWL. The read word line RWL, read bit line RBL, and transistors 27 and 28 are not shown in these figures.

[0047] In this example, data is written to the memory cell 20B, but not to the memory cell 20A. Therefore, the semiconductor circuit 1 performs operations OP11 to OP13 on the memory cell 20B.

[0048] 11A, immediately before the write operation, in this example, the voltage of the write word line WWL connected to the memory cells 20A and 20B is "0V." Therefore, the transistors 25 and 26 in the memory cells 20A and 20B are in the off state. Also, the voltages of the write bit lines WBL and WBLN connected to the memory cells 20A and 20B and the voltages of the control lines PL and PLN are "0V." Also, in this example, the voltage of the power supply node PWR of the memory cells 20A and 20B is "1V."

[0049] In this example, in memory cell 20A, the polarization state of ferroelectric capacitor 31 is polarization state S2, and the polarization state of ferroelectric capacitor 32 is polarization state S1. Therefore, the voltage of node N1 is "0V", and the voltage of node N2 is "1V". On the other hand, in memory cell 20B, the polarization state of ferroelectric capacitor 31 is polarization state S1, and the polarization state of ferroelectric capacitor 32 is polarization state S2. Therefore, the voltage of node N1 is "1V", and the voltage of node N2 is "0V".

[0050] Next, the semiconductor circuit 1 performs operation OP11 on the memory cell 20B. In this operation OP11, as shown in FIG. 11B, the driver 13 applies "2 V" to the write word line WWL connected to the memory cells 20A and 20B. This turns on the transistors 25 and 26 in the memory cells 20A and 20B. The driver 14 then applies "0 V" to the write bit line WBL and control line PLN connected to the memory cell 20B, and applies "1.5 V" to the write bit line WBLN and control line PL connected to the memory cell 20B. As a result, in the memory cell 20B, the voltage ΔV1 of the ferroelectric capacitor 31 is "-1.5 V," so the polarization state of the ferroelectric capacitor 31 becomes polarization state S2 (negative state), and the voltage ΔV2 of the ferroelectric capacitor 32 is "1.5 V," so the polarization state of the ferroelectric capacitor 32 becomes polarization state S1 (positive state). Thus, in memory cell 20B, this operation OP11 changes the polarization state of ferroelectric capacitor 31 from polarization state S1 (FIG. 11A) to polarization state S2 (FIG. 11B), and the polarization state of ferroelectric capacitor 32 from polarization state S2 (FIG. 11A) to polarization state S1 (FIG. 11B).

[0051] On the other hand, in this example, since no data is written to memory cell 20A, drive unit 14 floats write bit lines WBL and WBLN and control lines PL and PLN connected to memory cell 20A. At this time, the holding circuit consisting of inverters IV1 and IV2 may not be able to maintain the voltages at nodes N1 and N2. In particular, when transistors 21 to 24 of inverters IV1 and IV2 are small in size or when the so-called β ratio is small, it is difficult to maintain the voltages at nodes N1 and N2. Even in this case, in memory cell 20A, the polarization state of ferroelectric capacitor 31 is maintained in polarization state S2, and the polarization state of ferroelectric capacitor 32 is maintained in polarization state S1.

[0052] Next, the semiconductor circuit 1 performs operation OP12. In this operation OP12, as shown in FIG. 11C , the drive unit 13 applies "0 V" to the write word line WWL connected to the memory cells 20A and 20B. Therefore, the transistors 25 and 26 in the memory cells 20A and 20B are turned off. The drive unit 14 then applies "0 V" to the write bit lines WBL and WBLN and the control lines PL and PLN connected to the memory cells 20A and 20B. The control unit 11 then applies "0 V" to the power supply node PWR. As a result, in the memory cells 20A and 20B, the voltage ΔV1 of the ferroelectric capacitor 31 is "0 V," and the voltage ΔV2 of the ferroelectric capacitor 32 is "0 V." Therefore, the polarization states of the ferroelectric capacitors 31 and 32 are maintained in the memory cells 20A and 20B.

[0053] Next, the semiconductor circuit 1 performs operation OP13. In this operation OP13, as shown in FIG. 11D, the driver 13 applies "0 V" to the write word line WWL. Therefore, the transistors 25 and 26 in the memory cells 20A and 20B are turned off. The driver 14 then applies "0 V" to the write bit lines WBL and WBLN and the control lines PL and PLN connected to the memory cells 20A and 20B. The controller 11 then applies "1 V" to the power supply node PWR. This causes the memory cells 20A and 20B to perform the operations shown in FIGS. 8A, 8B, 9A, 9B, 10A, and 10B, respectively. As a result, in the memory cell 20A, the voltage of the node N1 becomes "0 V" and the voltage of the node N2 becomes "1 V" depending on the polarization states of the ferroelectric capacitors 31 and 32 of the memory cell 20A. In the memory cell 20B, the voltage at the node N1 becomes "0V" and the voltage at the node N2 becomes "1V" depending on the polarization state of the ferroelectric capacitors 31 and 32 of the memory cell 20B.

[0054] As described above, in the semiconductor circuit 1, in the memory cell 20A to which data is not written, it may be impossible to maintain the voltages of the nodes N1 and N2 when the transistors 25 and 26 are turned on, as shown in FIG. 11B. Even in such a case, the voltages of the nodes N1 and N2 can be restored to their original state, as shown in FIG. 11D, based on the data stored in the ferroelectric capacitors 31 and 32 of the memory cell 20A. As a result, the semiconductor circuit 1 can be made less susceptible to write disturbance.

[0055] (Read Operation OP2 and Standby Operation OP3) Fig. 12 shows an example of a read operation OP2 and a standby operation OP3 of data for the memory cell 20. The read operation OP2 is an operation of reading data from the memory cell 20. The standby operation OP3 is an operation of retaining data while reducing power consumption by lowering the power supply voltage supplied to the memory cell 20. Fig. 13 shows an example of the read operation OP2, and Fig. 14 shows an example of the standby operation OP3.

[0056] First, the read operation OP2 will be described in detail with reference to FIGS.

[0057] Prior to this read operation OP2, the sense amplifier unit 15 in this example performs a precharge operation on the read bit line RBL, thereby precharging the read bit line RBL to, for example, "1 V".

[0058] 12 and 13, in a read operation OP2, the drive unit 13 sets the voltage VWWL of the write word line WWL to "0 V" and the voltage VRWL of the read word line RWL to "1 V." This turns off the transistors 25 and 26 and turns on the transistor 28. The drive unit 14 sets the voltage VWBL of the write bit line WBL, the voltage VWBLN of the write bit line WBLN, the voltage VPL of the control line PL, and the voltage VPLN of the control line PLN to "0 V."

[0059] In this example, the voltage VN1 of node N1 is 0 V, and the voltage VN2 of node N2 is 1 V. Therefore, transistor 27 is on, and current flows from the precharged read bit line RBL to the ground node via transistors 28 and 27. As a result, the voltage VRBL of read bit line RBL drops from the precharged voltage (e.g., 1 V). Conversely, when the voltage VN1 of node N1 is 1 V and the voltage VN2 of node N2 is 0 V, transistor 27 is off, and the voltage VRBL of read bit line RBL is maintained at the precharged voltage (e.g., 1 V). The sense amplifier unit 15 compares the voltage VRBL of the read bit line RBL with a predetermined threshold voltage. In this manner, the semiconductor circuit 1 reads data stored in the memory cell 20.

[0060] In this example, the sense amplifier unit 15 precharges the voltage of the read bit line RBL to, for example, "1 V," but this is not limiting. For example, the voltage of the read bit line RBL may be predischarged to, for example, "0 V." In this case, the drain of transistor 27 is connected to the power supply node PWR, and the source of transistor 27 is connected to the drain of transistor 28. The drain of transistor 28 is connected to the source of transistor 27, and the source is connected to the read bit line RBL. When the voltage VN1 of node N1 is "0 V" and the voltage VN2 of node N2 is "1 V," transistor 27 is in the on state, and a current flows from the power supply node PWR to the predischarged read bit line RBL via transistors 27 and 28. As a result, the voltage VRBL of the read bit line RBL rises from the predischarged voltage (for example, "0 V"). Conversely, when the voltage VN1 of the node N1 is 1 V and the voltage VN2 of the node N2 is 0 V, the transistor 27 is in the off state, and the voltage VRBL of the read bit line RBL is maintained at a pre-discharged voltage (e.g., 0 V). The sense amplifier unit 15 compares the voltage VRBL of the read bit line RBL with a predetermined threshold voltage. In this way, the semiconductor circuit 1 can read data stored in the memory cell 20.

[0061] In this way, in the semiconductor circuit 1, the read operation OP2 is performed using the transistors 27 and 28. This makes it possible to read data from the memory cell 20 while keeping the transistors 25 and 26 in the off state. As a result, in the semiconductor circuit 1, it is possible to make read disturbance less likely to occur.

[0062] That is, for example, a semiconductor circuit may be configured so that data is read via transistors 25 and 26 without providing transistors 27 and 28. In this case, by turning on transistors 25 and 26 during a read operation, the holding circuit formed by inverters IV1 and IV2 may be unable to maintain the voltages at nodes N1 and N2. In particular, if the size of transistors 21 to 24 of inverters IV1 and IV2 is small or if the so-called β ratio is small, inverters IV1 and IV2 find it difficult to maintain the voltages at nodes N1 and N2. In this case, it becomes difficult to read the data stored in memory cell 20. As a result, read disturbance occurs in semiconductor circuit 1.

[0063] On the other hand, in semiconductor circuit 1, transistors 27 and 28 are provided and data is read via transistor 28, so transistors 25 and 26 remain off. Therefore, the holding circuit formed by inverters IV1 and IV2 can easily maintain the voltages at nodes N1 and N2. As a result, read disturbance is less likely to occur in semiconductor circuit 1.

[0064] Next, the standby operation OP3 will be described in detail with reference to FIGS.

[0065] 12 and 14, in standby operation OP3, the driver 13 sets the voltage VWWL of the write word line WWL to "0V" and the voltage VRWL of the read word line RWL to "0V." This turns off the transistors 25, 26, and 28. The driver 14 sets the voltage VWBL of the write bit line WBL, the voltage VWBLN of the write bit line WBLN, the voltage VPL of the control line PL, and the voltage VPLN of the control line PLN to "0V." The controller 11 then sets the voltage VPWR of the power supply node PWR to "0.5V." In this example, the voltage VN1 of the node N1 is "0V," and the voltage VN2 of the node N2 is "0.5V." A holding circuit consisting of inverters IV1 and IV2 maintains the voltages of the nodes N1 and N2.

[0066] In this way, in the semiconductor circuit 1, the voltage VPWR of the power supply node PWR is set to a low voltage to maintain the data in the memory cell 20. This allows the semiconductor circuit 1 to reduce power consumption when the write operation OP1 or the read operation OP2 is not performed.

[0067] (Store Operation OP4) Fig. 15 shows an example of a store operation OP4 of data to the memory cell 20. The store operation OP4 is an operation of transferring data stored in a holding circuit consisting of inverters IV1 and IV2 to the ferroelectric capacitors 31 and 32. The store operation OP4 includes two operations OP41 and OP42. Fig. 16A shows an example of the operation OP41, and Fig. 16B shows an example of the operation OP42.

[0068] First, the semiconductor circuit 1 performs operation OP41 to store data in one of the two ferroelectric capacitors 31 and 32 (FIG. 16A). Specifically, the driver 13 first sets the voltage VWWL of the write word line WWL and the voltage VWRL of the read word line RWL to "0 V." This turns off the transistors 25, 26, and 28. The driver 14 then sets the voltage VWBL of the write bit line WBL and the voltage VWBLN of the write bit line WBLN to "0 V." The driver 14 also sets the voltage VPL of the control line PL and the voltage VPLN of the control line PLN to "1.5 V." The control unit 11 then sets the voltage VPWR of the power supply node PWR to "1.5 V."

[0069] In this example, the voltage VN1 of the node N1 is "0 V", and the voltage VN2 of the node N2 is "1.5 V". Therefore, the voltage ΔV1 of the ferroelectric capacitor 31 is "-1.5 V", and the voltage ΔV2 of the ferroelectric capacitor 32 is "0 V". As a result, the polarization state of the ferroelectric capacitor 31 becomes polarization state S2 (negative state). On the other hand, the polarization state of the ferroelectric capacitor 32 is maintained in its previous state. In this way, in operation OP41, data is stored in the ferroelectric capacitor connected to the node of the two nodes N1, N2 whose voltage is "0 V".

[0070] Next, the semiconductor circuit 1 performs operation OP42 to store data in the other of the two ferroelectric capacitors 31 and 32 (FIG. 16B). Specifically, the drive unit 14 sets the voltage VPL of the control line PL and the voltage VPLN of the control line PLN to "0 V."

[0071] In this example, the voltage VN1 of the node N1 is "0 V", and the voltage VN2 of the node N2 is "1.5 V". Therefore, the voltage ΔV1 of the ferroelectric capacitor 31 is "0 V", and the voltage ΔV2 of the ferroelectric capacitor 32 is "1.5 V". As a result, the polarization state of the ferroelectric capacitor 32 becomes the polarization state S1 (positive state). On the other hand, the polarization state of the ferroelectric capacitor 31 is maintained in its previous state. In this way, in operation OP42, data is stored in the ferroelectric capacitor connected to the node of the two nodes N1, N2 whose voltage is "1.5 V".

[0072] In this example, the semiconductor circuit 1 performs the operations OP41 and OP42 in this order, but this is not limitative, and the operations may be performed in the order of operation OP42 and operation OP41.

[0073] In this way, the polarization state of the ferroelectric capacitor 31 is set to a polarization state corresponding to the voltage VN1 at the node N1, and the polarization state of the ferroelectric capacitor 32 is set to a polarization state corresponding to the voltage VN2 at the node N2. As a result, the data stored in the holding circuit consisting of the inverters IV1 and IV2 is transferred to the ferroelectric capacitors 31 and 32.

[0074] Thereafter, for example, the semiconductor circuit 1 performs so-called power gating, and the control unit 11 can set the voltage VPWR of the power supply node PWR to "0 V." At this time, no power is consumed in the memory cell 20. Then, for example, when the control unit 11 subsequently sets the voltage VPWR of the power supply node PWR to "1 V," the data stored in the ferroelectric capacitors 31 and 32 is transferred to the holding circuit consisting of the inverters IV1 and IV2, as in the case of operation OP13 (FIGS. 8A, 8B, 9A, 9B, 10A, and 10C). In the semiconductor circuit 1, power consumption can be reduced by performing such power gating.

[0075] As described above, the semiconductor circuit 1 includes a first inverter (inverter IV1) capable of generating an inverted voltage of the voltage at the first node (node ​​N1) and applying the inverted voltage to the second node (node ​​N2), a second inverter (inverter IV2) capable of generating an inverted voltage of the voltage at the second node (node ​​N2) and applying the inverted voltage to the first node (node ​​N1), a first bit line (write bit line WBL) and a second bit line (write bit line WBLN), a first transistor (transistor 25) provided on a path connecting the first bit line and the first node, and a second transistor (transistor 26) provided on a path connecting the second bit line and the second node. The semiconductor circuit 1 includes a first ferroelectric capacitor (ferroelectric capacitor 31) provided in a path connecting the first control line and the first node, a second ferroelectric capacitor (ferroelectric capacitor 32) provided in a path connecting the second control line and the second node, a third transistor (transistor 27) having a gate connected to the second node, a source, and a drain, a first signal line (read bit line RBL), and a fourth transistor (transistor 28) provided in a path connecting the first signal line (read bit line RBL) and one of the source and drain of the third transistor (transistor 27). As a result, in the semiconductor circuit 1, for example, as shown in FIGS. 11A to 11D , data can be temporarily stored in the ferroelectric capacitors 31 and 32 in the write operation OP1, making it less likely that write disturbance will occur. 13, the semiconductor circuit 1 can perform the read operation OP2 using transistors 27 and 28, making it difficult for read disturb to occur. As a result, data can be stably stored in the semiconductor circuit 1. Furthermore, the semiconductor circuit 1 can thus make it difficult for write disturb and read disturb to occur, and can make the read speed independent of the transistors 21 to 24 of the inverters IV1 and IV2, making it possible to reduce the size of the transistors 21 to 24 of the inverters IV1 and IV2 and to reduce the β ratio.In this case, the size of the semiconductor circuit 1 can be reduced.

[0076] The semiconductor circuit 1 is further provided with driving units (driving units 13, 14) that are capable of applying voltages to the first bit line (write bit line WBL), the second bit line (write bit line WBLN), the first control line (control line PL), and the second control line (control line PLN), that are capable of controlling the operations of the first transistor (transistor 25) and the second transistor (transistor 26), and that are capable of performing a first driving operation (operation OP11), a second driving operation (operation OP12), and a third driving operation (operation OP13) in this order. The first driving operation (operation OP11) includes turning on the first transistor (transistor 25) and the second transistor (transistor 26), applying one of an active voltage (e.g., 1.5 V) and a ground voltage to the first bit line (write bit line WBL) and the second control line (control line PLN), and applying the other of the active voltage (e.g., 1.5 V) and a ground voltage to the second bit line (write bit line WBLN) and the first control line (control line PL). The second driving operation (operation OP12) includes turning off the first transistor (transistor 25) and the second transistor (transistor 26), and stopping the power supply to the first inverter (inverter IV1) and the second inverter (inverter IV2). The third driving operation (operation OP13) includes turning off the first transistor (transistor 25) and the second transistor (transistor 26), applying a ground voltage to the first control line (control line PL) and the second control line (control line PLN), and supplying power to the first inverter (inverter IV1) and the second inverter (inverter IV2). As a result, in the semiconductor circuit 1, as shown in FIGS. 5 to 7 , data is stored in the ferroelectric capacitors 31 and 32, the power supply to the inverters IV1 and IV2 is temporarily stopped, and the power supply to the inverters IV1 and IV2 is resumed, and the data stored in the ferroelectric capacitors 31 and 32 is transferred to the holding circuit formed by the inverters IV1 and IV2. As a result, the semiconductor circuit 1 can be made less susceptible to write disturbance, thereby enabling stable data storage.

[0077] The semiconductor circuit 1 further includes a sense amplifier unit 15 connected to the first signal line (read bit line RBL). The drive units (drive units 13 and 14) are further capable of controlling the operation of a fourth transistor (transistor 28) to perform a fourth drive operation (read operation OP2). The fourth drive operation (read operation OP2) includes turning off the first transistor (transistor 25) and the second transistor (transistor 26) and turning on the fourth transistor (transistor 28). The sense amplifier unit 15 is operable based on a signal on the first signal line (read bit line RBL) while the drive units (drive units 13 and 14) are performing the fourth drive operation (read operation OP2). As a result, in the semiconductor circuit 1, data can be read via transistor 28 while transistors 25 and 26 are kept off, as shown in FIG. 13 . As a result, in the semiconductor circuit 1, read disturbance can be made less likely to occur, and data can be stored stably.

[0078] [effect] As described above, in this embodiment, there are provided a first inverter capable of generating an inverted voltage of the voltage at the first node and applying the inverted voltage to the second node, a second inverter capable of generating an inverted voltage of the voltage at the second node and applying the inverted voltage to the first node, a first bit line and a second bit line, a first transistor provided in a path connecting the first bit line and the first node, a second transistor provided in a path connecting the second bit line and the second node, a first control line and a second control line, a first ferroelectric capacitor provided in a path connecting the first control line and the first node, a second ferroelectric capacitor provided in a path connecting the second control line and the second node, a third transistor having a gate connected to the second node, a source, and a drain, and a first signal line, and a fourth transistor provided in a path connecting the first signal line and one of the source and drain of the third transistor, thereby enabling stable storage of data.

[0079] In this embodiment, the semiconductor memory device further includes a drive unit capable of applying voltages to the first bit line, the second bit line, the first control line, and the second control line, controlling the operation of the first transistor and the second transistor, and performing a first drive operation, a second drive operation, and a third drive operation in this order. The first drive operation includes turning on the first transistor and the second transistor, applying one of an active voltage and a ground voltage to the first bit line and the second control line, and applying the other of the active voltage and the ground voltage to the second bit line and the first control line. The second drive operation includes turning off the first transistor and the second transistor, and stopping power supply to the first inverter and the second inverter. The third drive operation includes turning off the first transistor and the second transistor, applying a ground voltage to the first control line and the second control line, and supplying power to the first inverter and the second inverter. This allows data to be stored stably.

[0080] In this embodiment, the memory cell further includes a sense amplifier unit connected to the first signal line. The drive unit is further capable of controlling the operation of the fourth transistor, enabling a fourth drive operation. The fourth drive operation includes turning off the first transistor and the second transistor and turning on the fourth transistor. The sense amplifier unit is operable based on the signal on the first signal line while the drive unit is performing the fourth drive operation. This allows stable data storage.

[0081] [Modification 1-1] In the above embodiment, as shown in FIGS. 4 and 5, power is supplied to the holding circuit consisting of inverters IV1 and IV2 in operation OP11 of write operation OP1. However, this is not limited to this. Alternatively, for example, as shown in FIGS. 17 and 18, power may not be supplied in this operation OP11. As shown in FIGS. 17 and 18, the control unit 11 sets the voltage VPWR of the power supply node PWR to "0 V" in this operation OP11. Even in this case, the voltage ΔV1 of the ferroelectric capacitor 31 becomes "-1.5 V" and the voltage ΔV2 of the ferroelectric capacitor 32 becomes "1.5 V". As a result, the polarization state of the ferroelectric capacitor 31 becomes polarization state S2, and the polarization state of the ferroelectric capacitor 32 becomes polarization state S1.

[0082] [Variation 1-2] In the above embodiment, in the read operation OP2, the sense amplifier unit 15 precharges the read bit line RBL and reads the data stored in the memory cell 20 based on the voltage of the read bit line RBL after the transistor 28 turns on. However, this is not limiting. Alternatively, for example, the sense amplifier unit 15 may read the data stored in the memory cell 20 based on the current flowing through the read bit line RBL after the transistor 28 turns on, without performing the precharge operation. For example, when the voltage VN1 of the node N1 is 0 V and the voltage VN2 of the node N2 is 1 V, the transistor 27 is on, and a current flows through the read bit line RBL. Furthermore, for example, when the voltage VN1 of the node N1 is 1 V and the voltage VN2 of the node N2 is 0 V, the transistor 27 is off, and no current flows through the read bit line RBL. The sense amplifier section 15 can read data stored in the memory cell 20 based on the current in the read bit line RBL.

[0083] [Other Modifications] Two or more of these modifications may be combined.

[0084] 2. Second Embodiment Next, a semiconductor circuit 2 according to a second embodiment will be described. Note that components that are substantially the same as those in the semiconductor circuit 1 according to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0085] 19 shows an example of the configuration of the semiconductor circuit 2. The semiconductor circuit 2 is a computing memory and a product-sum operation circuit that performs weighted addition on signals. The semiconductor circuit 2 includes a control unit 41, a memory cell array 42, drive units 43 and 44, an AD (Analog to Digital) conversion unit 45, and an input signal generation unit 46.

[0086] The control unit 41 is configured to control the operation of the memory cell array 42, the drive units 43 and 44, and the AD conversion unit 45, thereby controlling the operation of the semiconductor circuit 2. Specifically, the control unit 41 controls the operation of the semiconductor circuit 2 so that it writes data to the memory cell array 42 based on a write command and write data supplied from the outside, and performs a product-sum operation based on an operation command supplied from the outside and outputs the operation result as a signal Sout. The control unit 41 also controls the power supply voltage of each circuit in the semiconductor circuit 2 in accordance with the operation.

[0087] The memory cell array 42 has a plurality of memory cells 50, a plurality of write word lines WWL, a plurality of read word lines RWL, a plurality of write bit lines WBL, a plurality of write bit lines WBLN, a plurality of control lines PL, a plurality of control lines PLN, a plurality of signal lines SIGL, and a plurality of signal lines SUML.

[0088] Each of the plurality of memory cells 50 is configured to store data. The plurality of memory cells 50 are arranged in a matrix. The memory cells 50 are connected to a write word line WWL, a read word line RWL, write bit lines WBL and WBLN, control lines PL and PLN, a signal line SIGL, and a signal line SUML. The signal line SIGL extends in the horizontal direction in FIG. 19 , and one end of the signal line SIGL is connected to the input signal generating unit 46. The signal line SUML extends in the vertical direction in FIG. 19 , and one end of the signal line SUML is connected to the AD converting unit 45.

[0089] 20 shows an example of the configuration of a memory cell 50. The memory cell 50 has transistors 21 to 28 and ferroelectric capacitors 31 and 32. The circuit configuration of the memory cell 50 is similar to that of the memory cell 20 (FIG. 2) according to the first embodiment. The source of the transistor 27 is connected to a signal line SIGL. The drain of the transistor 28 is connected to a signal line SUML.

[0090] The drive unit 43 (Figure 19) is connected to a plurality of write word lines WWL and a plurality of read word lines RWL in the memory cell array 42, and is configured to apply signals to the write word lines WWL and read word lines RWL in the memory cell array 42 based on control signals supplied from the control unit 41.

[0091] The drive unit 44 is connected to the plurality of write bit lines WBL, the plurality of write bit lines WBLN, the plurality of control lines PL, and the plurality of control lines PLN in the memory cell array 42, and is configured to apply signals to the write bit lines WBL, WBLN and the control lines PL, PLN in the memory cell array 42 based on control signals supplied from the control unit 41.

[0092] The AD conversion unit 45 is connected to a plurality of signal lines SUML in the memory cell array 42, and is configured to convert the analog signal supplied from the memory cell array 42 via the signal line SUML into a digital code based on a control signal supplied from the control unit 41, and output the digital code as a signal Sout.

[0093] The input signal generating unit 46 is configured to generate a plurality of signals based on the signal Sin and apply the generated signals to a plurality of signal lines SIGL in the memory cell array 42. Each of the signals is, for example, a PWM (Pulse Width Modulation) signal.

[0094] Here, inverter IV1 corresponds to a specific example of a "first inverter" and a "third inverter" in an embodiment of the present disclosure. Inverter IV2 corresponds to a specific example of a "second inverter" and a "fourth inverter" in an embodiment of the present disclosure. Node N1 corresponds to a specific example of a "first node" and a "third node" in an embodiment of the present disclosure. Node N2 corresponds to a specific example of a "second node" and a "fourth node" in an embodiment of the present disclosure. Transistor 25 corresponds to a specific example of a "first transistor" and a "fifth transistor" in an embodiment of the present disclosure. Transistor 26 corresponds to a specific example of a "second transistor" and a "sixth transistor" in an embodiment of the present disclosure. Ferroelectric capacitor 31 corresponds to a specific example of a "first ferroelectric capacitor" and a "third ferroelectric capacitor" in an embodiment of the present disclosure. Ferroelectric capacitor 32 corresponds to a specific example of a "second ferroelectric capacitor" and a "fourth ferroelectric capacitor" in an embodiment of the present disclosure. The transistor 27 corresponds to a specific example of a "third transistor" and a "seventh transistor" in an embodiment of the present disclosure. The signal line SUML corresponds to a specific example of a "first signal line" in an embodiment of the present disclosure. The signal line SIGL corresponds to a specific example of a "second signal line" and a "third signal line" in an embodiment of the present disclosure. The transistor 28 corresponds to a specific example of a "fourth transistor" and an "eighth transistor" in an embodiment of the present disclosure. The driving units 43 and 44 correspond to a specific example of a "driving unit" in an embodiment of the present disclosure. The AD conversion unit 45 corresponds to a specific example of a "readout unit" in an embodiment of the present disclosure. The input signal generation unit 46 corresponds to a specific example of a "signal generation unit" in an embodiment of the present disclosure.

[0095] The semiconductor circuit 2 can perform a write operation OP1, a standby operation OP3, and a store operation OP4, similarly to the semiconductor circuit 1 according to the first embodiment.

[0096] Furthermore, the semiconductor circuit 2 performs a read operation OP2 to perform a product-sum operation on the signals generated by the input signal generating section 46 using the data stored in the memory cells 50.

[0097] 21 shows an example of the operation of a product-sum operation in the semiconductor circuit 2. This FIG. 21 illustrates 16 (=4×4) memory cells 50 out of the plurality of memory cells 50 in the memory cell array 42. In this example, the plurality of memory cells 50 have already stored data through a write operation OP1. By performing a read operation OP2 (FIGS. 12 and 13), the semiconductor circuit 2 performs a product-sum operation on the plurality of signals generated by the input signal generation unit 46 using the data stored in the plurality of memory cells 50.

[0098] For example, the input signal generating unit 46 generates a plurality of signals and applies the generated signals to a plurality of signal lines SIGL. A plurality of memory cells 50 (part W1) in one column of the memory cell array 42 performs a product-sum operation on the plurality of signals generated by the input signal generating unit 46 using the data stored in the memory cells 50.

[0099] For example, among the multiple memory cells 50 in one column, in the memory cells 50 where the voltage of node N2 is high (e.g., 1 V), the transistor 27 is turned on, and a current corresponding to the signal line SIGL flows through the signal line SUML. Also, among the multiple memory cells 50 in one column, in the memory cells 50 where the voltage of node N2 is low (e.g., 0 V), the transistor 27 is turned off, and no current flows through the signal line SUML. In this way, the memory cells 50 perform an integration of the signal on the signal line SIGL using the data stored in the memory cells 50, and then flow the integrated current through the signal line SUML. When each of the multiple memory cells 50 in one column performs this operation, the sum of the integrated currents flows through the signal line SUML. In this way, a current obtained by the product-sum operation flows through the signal line SUML.

[0100] The AD conversion unit 45 generates a digital code by performing AD conversion based on the sum-of-products current flowing through the signal line SUML.

[0101] In this way, the memory cells 50 in one column perform a product-sum operation on the signals generated by the input signal generating unit 46, causing a current to flow through the signal line SUML, and the AD converting unit 45 performs AD conversion based on the product-sum operated current flowing through the signal line SUML. The same applies to each of the other columns. The AD converting unit 45 then outputs the digital code generated by the AD conversion as the signal Sout.

[0102] As described above, the semiconductor circuit 2 includes a first inverter (inverter IV1) capable of generating an inverted voltage of the voltage at the first node (node ​​N1) and applying the inverted voltage to the second node (node ​​N2), a second inverter (inverter IV2) capable of generating an inverted voltage of the voltage at the second node (node ​​N2) and applying the inverted voltage to the first node (node ​​N1), a first bit line (write bit line WBL) and a second bit line (write bit line WBLN), a first transistor (transistor 25) provided on a path connecting the first bit line and the first node, and a second transistor (transistor 26) provided on a path connecting the second bit line and the second node. The semiconductor circuit 2 further includes a first ferroelectric capacitor (ferroelectric capacitor 31) connected to the first node, a second ferroelectric capacitor (ferroelectric capacitor 32) connected to the second node, a third transistor (transistor 27) having a gate connected to the second node, a source, and a drain, a first signal line (signal line SUML), and a fourth transistor (transistor 28) connected to the path connecting the first signal line (signal line SUML) and one of the source and drain of the third transistor (transistor 27). Even in this case, as with the semiconductor circuit 1 according to the first embodiment, the semiconductor circuit 2 can temporarily store data in the ferroelectric capacitors 31 and 32 during the write operation OP1, thereby making it less likely for write disturbance to occur. As a result, the semiconductor circuit 2 can stably store data. Furthermore, since the semiconductor circuit 2 can be made less susceptible to write disturbance in this way, the size of the transistors 21 to 24 of the inverters IV1 and IV2 can be reduced, which allows the size of the semiconductor circuit 2 to be reduced.

[0103] [effect] As described above, in this embodiment, there are provided a first inverter capable of generating an inverted voltage of the voltage at the first node and applying the inverted voltage to the second node, a second inverter capable of generating an inverted voltage of the voltage at the second node and applying the inverted voltage to the first node, a first bit line and a second bit line, a first transistor provided in a path connecting the first bit line and the first node, a second transistor provided in a path connecting the second bit line and the second node, a first control line and a second control line, a first ferroelectric capacitor provided in a path connecting the first control line and the first node, a second ferroelectric capacitor provided in a path connecting the second control line and the second node, a third transistor having a gate connected to the second node, a source, and a drain, and a first signal line, and a fourth transistor provided in a path connecting the first signal line and one of the source and drain of the third transistor, thereby enabling stable storage of data.

[0104] [Modification 2-1] In the above embodiment, a product-sum operation is performed on multiple signals generated by the input signal generation unit 46 using 1-bit data in the memory cell 50, but this is not limited to this. Instead, for example, a product-sum operation may be performed on one signal using multiple-bit data. A semiconductor circuit 2A according to this modification will be described in detail below.

[0105] 22 shows an example of the configuration of a semiconductor circuit 2A. The semiconductor circuit 2A has a control unit 41, a memory cell array 42A, drive units 43 and 44, an AD conversion unit 45, and an input signal generation unit 46A.

[0106] The memory cell array 42A includes a plurality of memory cells 50A, a plurality of write word lines WWL, a plurality of read word lines RWL, a plurality of write bit lines WBL, a plurality of write bit lines WBLN, a plurality of control lines PL, a plurality of control lines PLN, a plurality of signal lines SIGL, and a plurality of signal lines SUML. These signal lines SIGL are connected to each other.

[0107] 23 shows an example of the configuration of a main portion of a column of memory cells 50A. The write word line WWL, write bit lines WBL and WBLN, and control lines PL and PLN are not shown in FIG. The gate widths of the transistors 27 in a column of memory cells 50A (portion W2) are set to different widths, such as 1W, 2W, 4W, 8W, and so on, in this example. As a result, for example, a memory cell 50A having a transistor 27 with a gate width of 2W can pass twice as much current through signal line SUML as a memory cell 50A having a transistor 27 with a gate width of W.

[0108] The input signal generating unit 46A is configured to generate a signal based on the signal Sin and apply the generated signal to a plurality of signal lines SIGL in the memory cell array 42. This signal is, for example, a PWM signal.

[0109] A column of memory cells 50 (portion W2) in the memory cell array 42A performs a multiply-and-accumulate operation on a single signal generated by the input signal generating unit 46 using multi-bit data stored in the memory cells 50. For example, among the multiple memory cells 50 in one column, data stored in a memory cell 50 with a gate width of 1W is the least significant bit (LSB), data stored in a memory cell 50 with a gate width of 2W is the bit one place higher than that, data stored in a memory cell 50 with a gate width of 4W is the bit one place higher than that, and data stored in a memory cell 50 with a gate width of 8W is the bit one place higher than that. The multiple memory cells 50 in one column perform a multiply-and-accumulate operation using such multi-bit data. As a result, a current resulting from the multiply-and-accumulate operation flows through the signal line SUML. The AD conversion unit 45 generates a digital code by AD conversion based on the current resulting from the multiply-and-accumulate operation flowing through the signal line SUML.

[0110] In this way, the memory cells 50 in one column perform a product-sum operation on the signal generated by the input signal generating unit 46A, causing a current to flow through the signal line SUML, and the AD conversion unit 45 performs AD conversion based on the product-sum operated current flowing through the signal line SUML. The same applies to each of the other columns. The AD conversion unit 45 then outputs the digital code generated by the AD conversion as the signal Sout.

[0111] [Modification 2-2] In the above embodiment, the transistor 27 is configured using a normal FET (Field Effect Transistor). However, this is not limiting. Instead, for example, as shown in FIG. 24 , the transistor 27 may be configured using a tunnel FET. This reduces the conductance of the transistor 27. If the conductance were reduced by increasing the gate length of the transistor 27, the size of the transistor 27 would increase. By using a tunnel FET as the transistor 27 in this way, the conductance can be reduced while suppressing an increase in size.

[0112] Also, for example, as shown in FIG. 25, a transistor 27 may be configured using a tunnel FET, and a transistor 28 may also be configured using a tunnel FET.

[0113] [Other Modifications] Two or more of these modifications may be combined.

[0114] Although the present technology has been described above by giving several embodiments and modifications, the present technology is not limited to these embodiments and the like, and various modifications are possible.

[0115] For example, in each of the above embodiments, the methods of extending the write word line WWL, read word line RWL, write bit lines WBL, WBLN, read bit line RBL, control line PL, control line PLN, signal line SIGL, and signal line SUML are not limited to the examples of the above embodiments, and may be changed as appropriate.

[0116] For example, in each of the above embodiments, the memory cells 20 and 50 have transistors 21 to 28 and ferroelectric capacitors 31 and 32, but are not limited to this and may further include other elements.

[0117] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0118] The present technology can be configured as follows: According to the present technology configured as follows, data can be stored stably.

[0119] (1) A first inverter capable of generating an inverted voltage of a voltage at a first node and applying the inverted voltage to a second node; a second inverter capable of generating an inverted voltage of a voltage at the second node and applying the inverted voltage to the first node; a first bit line and a second bit line; a first transistor provided in a path connecting the first bit line and the first node; a second transistor provided in a path connecting the second bit line and the second node; a first control line and a second control line; a first ferroelectric capacitor provided in a path connecting the first control line and the first node; a second ferroelectric capacitor provided in a path connecting the second control line and the second node; a third transistor having a gate, a source, and a drain connected to the second node; a first signal line; and a fourth transistor provided in a path connecting the first signal line and one of the source and the drain of the third transistor. A semiconductor circuit comprising:(2) The semiconductor memory device further includes a drive unit capable of applying voltages to the first bit line, the second bit line, the first control line, and the second control line, capable of controlling operations of the first transistor and the second transistor, and capable of performing a first drive operation, a second drive operation, and a third drive operation in this order, wherein the first drive operation includes turning on the first transistor and the second transistor, applying one of an active voltage and a ground voltage to the first bit line and the second control line, and applying the other of the active voltage and the ground voltage to the second bit line and the first control line, and the second drive operation includes turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and stopping power supply to the first inverter and the second inverter, The semiconductor circuit according to any one of (1) to (3), wherein the third driving operation includes turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and supplying power to the first inverter and the second inverter. (3) The semiconductor circuit according to (2), further comprising a readout unit connected to the first signal line, wherein the driving unit is further capable of controlling the operation of the fourth transistor and performing a fourth driving operation, the fourth driving operation includes turning off the first transistor and the second transistor and turning on the fourth transistor, and the readout unit is operable based on a signal on the first signal line while the driving unit is performing the fourth driving operation. (4) The semiconductor circuit according to any one of (1) to (3), wherein the other of the source and the drain of the third transistor is connected to a power supply node. (5) The semiconductor circuit according to any one of (1) to (3), further comprising: a second signal line connected to the other of the source and the drain of the third transistor; and a signal generating unit capable of supplying a signal to the second signal line.(6) The semiconductor memory device further comprises: a third inverter capable of generating an inverted voltage of a voltage at a third node and applying the inverted voltage to a fourth node; a fourth inverter capable of generating an inverted voltage of a voltage at the fourth node and applying the inverted voltage to the third node; a fifth transistor provided in a path connecting the first bit line and the third node; a sixth transistor provided in a path connecting the second bit line and the fourth node; a third ferroelectric capacitor provided in a path connecting the first control line and the third node; a fourth ferroelectric capacitor provided in a path connecting the second control line and the fourth node; a seventh transistor having a gate connected to the fourth node, a source, and a drain; an eighth transistor provided in a path connecting the first signal line and one of the source and the drain of the seventh transistor; and a third signal line connected to the other of the source and the drain of the seventh transistor, The semiconductor circuit according to (5), wherein the signal generating unit is capable of supplying signals to the second signal line and the third signal line. (7) The semiconductor circuit according to (6), wherein the second signal line and the third signal line are connected to each other. (8) The semiconductor circuit according to (6) or (7), wherein the size of the third transistor and the size of the seventh transistor are different from each other. (9) The semiconductor circuit according to (8), wherein the gate width of the third transistor and the gate width of the seventh transistor are different from each other. (10) The semiconductor circuit according to any of (6) to (9), wherein the third transistor and the seventh transistor are each a tunnel field effect transistor.(11) A transistor including: a first inverter capable of generating an inverted voltage of a voltage at a first node and applying the inverted voltage to a second node; a second inverter capable of generating an inverted voltage of a voltage at the second node and applying the inverted voltage to the first node; a first bit line and a second bit line; a first transistor provided in a path connecting the first bit line and the first node; a second transistor provided in a path connecting the second bit line and the second node; a first control line and a second control line; a first ferroelectric capacitor provided in a path connecting the first control line and the first node; a semiconductor circuit including a second ferroelectric capacitor connected to the second node, a third transistor having a gate connected to the second node, a source, and a drain, a first signal line, and a fourth transistor provided in a path connecting the first signal line and one of the source and the drain of the third transistor, performing a first driving operation including turning on the first transistor and the second transistor, applying one of an active voltage and a ground voltage to the first bit line and the second control line, and applying the other of the active voltage and the ground voltage to the second bit line and the first control line; a driving method comprising: performing a second driving operation on the semiconductor circuit, the second driving operation including turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and stopping the supply of power to the first inverter and the second inverter; and performing a third driving operation on the semiconductor circuit, the third driving operation including turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and supplying power to the first inverter and the second inverter.

[0120] This application claims priority based on Japanese Patent Application No. 2023-136263, filed on August 24, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0121] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a first inverter capable of generating an inverted voltage of a voltage at a first node and applying the inverted voltage to a second node; a second inverter capable of generating an inverted voltage of a voltage at the second node and applying the inverted voltage to the first node; a first bit line and a second bit line; a first transistor provided in a path connecting the first bit line and the first node; a second transistor provided in a path connecting the second bit line and the second node; a first control line and a second control line; a first ferroelectric capacitor provided in a path connecting the first control line and the first node; a second ferroelectric capacitor provided in a path connecting the second control line and the second node; a third transistor having a gate, a source, and a drain connected to the second node; a first signal line; and a fourth transistor provided in a path connecting the first signal line and one of the source and the drain of the third transistor. A semiconductor circuit comprising:

2. The semiconductor memory device further includes a drive unit capable of applying voltages to the first bit line, the second bit line, the first control line, and the second control line, capable of controlling operations of the first transistor and the second transistor, and capable of performing a first drive operation, a second drive operation, and a third drive operation in this order, wherein the first drive operation includes turning on the first transistor and the second transistor, applying one of an active voltage and a ground voltage to the first bit line and the second control line, and applying the other of the active voltage and the ground voltage to the second bit line and the first control line, and the second drive operation includes turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and stopping the power supply to the first inverter and the second inverter, 2. The semiconductor circuit according to claim 1, wherein the third driving operation includes turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and supplying power to the first inverter and the second inverter.

3. The semiconductor circuit according to claim 2, further comprising a readout unit connected to the first signal line, wherein the drive unit is further capable of controlling the operation of the fourth transistor and capable of performing a fourth drive operation, wherein the fourth drive operation includes turning off the first transistor and the second transistor and turning on the fourth transistor, and wherein the readout unit is operable based on the signal on the first signal line during a period in which the drive unit is performing the fourth drive operation.

4. The semiconductor circuit according to claim 1, wherein the other of the source and the drain of the third transistor is connected to a power supply node.

5. The semiconductor circuit according to claim 1, further comprising: a second signal line connected to the other of the source and the drain of the third transistor; and a signal generating section capable of supplying a signal to the second signal line.

6. A third inverter capable of generating an inverted voltage of a voltage at a third node and applying the inverted voltage to a fourth node; a fourth inverter capable of generating an inverted voltage of a voltage at the fourth node and applying the inverted voltage to the third node; a fifth transistor provided in a path connecting the first bit line and the third node; a sixth transistor provided in a path connecting the second bit line and the fourth node; a third ferroelectric capacitor provided in a path connecting the first control line and the third node; a fourth ferroelectric capacitor provided in a path connecting the second control line and the fourth node; a seventh transistor having a gate, a source, and a drain connected to the fourth node; an eighth transistor provided in a path connecting the first signal line and one of the source and the drain of the seventh transistor; and a third signal line connected to the other of the source and the drain of the seventh transistor, The semiconductor circuit according to claim 5 , wherein the signal generating section is capable of supplying signals to the second signal line and the third signal line.

7. The semiconductor circuit according to claim 6, wherein the second signal line and the third signal line are connected to each other.

8. The semiconductor circuit according to claim 6, wherein the size of the third transistor and the size of the seventh transistor are different from each other.

9. The semiconductor circuit according to claim 8, wherein the gate width of the third transistor and the gate width of the seventh transistor are different from each other.

10. The semiconductor circuit according to claim 6, wherein each of the third transistor and the seventh transistor is a tunnel field effect transistor.

11. A first inverter capable of generating an inverted voltage of a voltage at a first node and applying the inverted voltage to a second node; a second inverter capable of generating an inverted voltage of a voltage at the second node and applying the inverted voltage to the first node; a first bit line and a second bit line, a first transistor provided in a path connecting the first bit line and the first node, a second transistor provided in a path connecting the second bit line and the second node, a first control line and a second control line, a first ferroelectric capacitor provided in a path connecting the first control line and the first node, and a second transistor provided in a path connecting the second control line and the second node. a semiconductor circuit including a second ferroelectric capacitor connected to the second node, a third transistor having a gate, a source, and a drain connected to the second node, a first signal line, and a fourth transistor provided in a path connecting the first signal line and one of the source and the drain of the third transistor, performing a first driving operation including turning on the first transistor and the second transistor, applying one of an active voltage and a ground voltage to the first bit line and the second control line, and applying the other of the active voltage and the ground voltage to the second bit line and the first control line; a driving method comprising: performing a second driving operation on the semiconductor circuit, the second driving operation including turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and stopping power supply to the first inverter and the second inverter; and performing a third driving operation on the semiconductor circuit, the third driving operation including turning off the first transistor and the second transistor, applying the ground voltage to the first control line and the second control line, and supplying power to the first inverter and the second inverter.

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