Balun and front end circuit

Abstract

This balun comprises a dielectric substrate (Sb1) having a first surface (Sf1) and a second surface (Sf2) opposing one other, a grounding electrode (Mk1) formed on the first surface, an unbalanced terminal (TU1) formed on the second surface, a pair of balanced terminals including a first balanced terminal (TB1) formed on the second surface, a main line (ML1) formed on the second surface and having one end (Es1) connected to the unbalanced terminal and another end (Ee1) open, a first sub-line (SL1) formed on the second surface and having one end (Ee2) connected to the first balanced terminal, and a second sub-line (SL2) formed on the second surface and having one end (Ee2) connected to the first balanced terminal, wherein: the first sub-line (SL1) has another end (Es2) connected to the grounding electrode (Mk1) via a first via (V1), and is disposed between the main line (ML1) and the second sub-line (SL2); and the first sub-line and the second sub-line each overlap the grounding electrode when the second surface is viewed in plan.

Description

Balun, front-end circuit

[0001] The present invention relates to a balun that converts a signal between an unbalanced line and a balanced line, and more particularly to a structure for improving the characteristics of a balun.

[0002] A balun is a converter used to convert between unbalanced and balanced signals. Balanced signals are a pair of signals with equal amplitude and opposite phase. They are used in differential amplifier circuits and antennas and are less susceptible to noise. On the other hand, unbalanced signals are used in transmission systems that transmit changes in potential relative to a ground electrode. Although they are less expensive than balanced signals, they are more susceptible to noise than balanced signals.

[0003] Japanese Patent Application Laid-Open Publication No. 2017-158174 (Patent Document 1) discloses a Marchand balun using coupled lines, in which a line connected to an unbalanced terminal and having a length of 1 / 2 the wavelength λ (λ / 2) is coupled to two lines connected to parallel terminals and having a length of λ / 4.

[0004] Apart from baluns, there are other types of transformers that convert unbalanced signals to balanced signals and vice versa, such as MCT (Magnetic Coupled Transformer) elements, which use magnetic coupling between a primary transformer and a secondary transformer. The sizes of MCT elements and Marchand baluns are generally determined based on the wavelength. Because MCT elements use shorter lines than those used in Marchand baluns, the size of the device can be made smaller than that of a Marchand balun. However, in the sub-terahertz band, the parasitic capacitance between the transformer wires increases, resulting in degradation of performance.

[0005] At high frequencies such as sub-terahertz, the line length is extremely short, so even if a Marchand balun is used, it is possible to reduce the size and loss of the device. Therefore, in recent years, the Marchand balun has attracted attention as a converter applicable to high frequencies such as sub-terahertz.

[0006] JP 2017-158174 A

[0007] In a dielectric substrate on which a Marchand balun is mounted in the sub-terahertz range, a through-hole is formed from the back side of the surface on which the balun is mounted to the balun itself, and a via is placed in the through-hole to electrically connect the balun to the ground electrode. In this case, parasitic capacitance may be generated at the interface between the via and the balun. The parasitic capacitance generated at the interface between the via and the balun and the inductance of the balun itself may form an unintended series resonant circuit, which may result in an attenuation pole in the passband.

[0008] The present disclosure has been made to solve such problems, and its purpose is to improve the transmission characteristics of a balun used in a communication device.

[0009] A balun according to the present disclosure includes a dielectric substrate having a first surface and a second surface facing each other, a ground electrode formed on the first surface, an unbalanced terminal formed on the second surface, a pair of balanced terminals including a first balanced terminal formed on the second surface, a main line formed on the second surface and having one end connected to the unbalanced terminal and the other end open, a first sub-line formed on the second surface and having one end connected to the first balanced terminal, and a second sub-line formed on the second surface and having one end connected to the first balanced terminal. The other end of the first sub-line is connected to the ground electrode via a first via and is disposed between the main line and the second sub-line, and each of the first sub-line and the second sub-line overlaps with the ground electrode when the second surface is viewed from above.

[0010] According to one aspect, the balun includes a dielectric substrate on which a plurality of layers including a first layer are stacked, a ground electrode formed on the first layer, an unbalanced terminal provided on the dielectric substrate, a pair of balanced terminals including the first balanced terminal provided on the dielectric substrate, a main line formed on a layer different from the first layer and having one end connected to the unbalanced terminal and the other end open, a first sub-line formed on a layer different from the first layer and having one end connected to the first balanced terminal, and a second sub-line formed on a layer different from the first layer and having one end connected to the first balanced terminal. The other end of the first sub-line is connected to the ground electrode via a first via, and the first sub-line is disposed between the main line and the second sub-line when viewed from the stacking direction of the dielectric substrate, and each of the first sub-line and the second sub-line overlaps with the ground electrode when viewed from the stacking direction of the dielectric substrate.

[0011] According to the present invention, in a balun in which a ground electrode and a first sub-line are electrically connected, in addition to a first sub-line connected to a balanced terminal, a second sub-line similarly connected to the balanced terminal is formed. The first sub-line is disposed between the main line and the second sub-line, and the second sub-line is capacitively coupled to the ground electrode via a dielectric substrate. The second sub-line, which has a lower degree of coupling with the main line than the first sub-line, is capacitively coupled with the ground electrode, thereby suppressing deterioration of the degree of coupling between the main line and the sub-line and lowering the series resonance frequency, thereby adjusting the frequency at which an attenuation pole occurs. In other words, the pass characteristics of a balun used in a communication device can be improved.

[0012] 11 is a block diagram of a communication device including a front-end circuit to which a balun according to an embodiment is applied. FIG. 12 is an example of a circuit diagram of the balun in FIG. 1. FIG. 13 is a plan view of the balun according to the first embodiment. FIG. 14 is a diagram for explaining cross sections of end portions Es2 and Es3. FIG. 15 is a diagram showing an equivalent circuit of the sub-line SL1 and the sub-line SL2 according to the first embodiment. FIG. 16 is an example of a circuit diagram of a balun according to a comparative example. FIG. 17 is a plan view of the balun according to the comparative example. FIG. 18 is an equivalent circuit diagram showing the relationship between the sub-line SL1 and the via V1 according to the comparative example. FIG. 19 is an enlarged view of insertion loss near the pass band of FIG. 9. FIG. 19 is a diagram for explaining the pass characteristics of the balun according to the first embodiment. FIG. 11 is an enlarged view of insertion loss near the pass band of FIG. 11. FIG. 19 is a diagram for explaining electric field coupling between wiring patterns in the balun according to the comparative example. FIG. 19 is a diagram for explaining electric field coupling between wiring patterns according to the first embodiment. FIG. 20 is a schematic configuration diagram of a communication device according to a second embodiment. FIG. 21 is a plan view of a balun according to a third embodiment.

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals and description thereof will not be repeated.

[0014] First Embodiment A schematic configuration of a balun 100 and a front-end circuit 10 according to a first embodiment will be described with reference to FIG.

[0015] 1 is a block diagram of a communication device 1000 including a front-end circuit 10 to which a balun 100 according to an embodiment is applied. Referring to FIG. 1, in addition to the front-end circuit 10, the communication device 1000 includes an antenna ANT and an RFIC 20 that is a signal processing circuit.

[0016] The RFIC 20 outputs a high-frequency signal to be radiated from the antenna ANT to the front-end circuit 10. The front-end circuit 10 includes a matching circuit 50 and a power amplifier PA in addition to the balun 100. The balun 100, the matching circuit 50, and the power amplifier PA are arranged within the same dielectric substrate Sb1.

[0017] The base material of the dielectric substrate Sb1 is a compound semiconductor. The compound semiconductor is manufactured by an integrated circuit process using a semiconductor material whose main component is, for example, a compound of a group III element and a group V element. The semiconductor is, for example, a semiconductor whose main component is GaAs (gallium arsenide).

[0018] The power amplifier PA amplifies the high-frequency signal transmitted from the RFIC 20 and outputs the amplified signal to the matching circuit 50. The matching circuit 50 is provided between the power amplifier PA and the balun 100, and performs impedance matching between the power amplifier PA and the balun 100. The high-frequency signal matched by the matching circuit 50 is transmitted to the balun 100.

[0019] Balun 100 is a converter that converts signals between unbalanced and balanced signals, and in the first embodiment, converts unbalanced signals to balanced signals. Balanced signals are a pair of signals with equal amplitudes and opposite phases, and unbalanced signals are signals used in a transmission system that transmits changes in potential relative to a ground electrode. The high-frequency signal converted from an unbalanced signal to a balanced signal by balun 100 is transmitted to antenna ANT. Antenna ANT is, for example, a patch antenna having feed points Fp1 and Fp2.

[0020] The balun 100 has an unbalanced terminal TU1 and two balanced terminals (balanced terminal TB1 and TB2). The balanced signal converted by the balun 100 and output from the balanced terminal TB1 is supplied to the feed point Fp1 of the antenna ANT. The balanced signal output from the balanced terminal TB2 is supplied to the feed point Fp2 of the antenna ANT. The feed points Fp1 and Fp2 are offset in opposite directions in the polarization direction from the center of the antenna ANT, which is a patch antenna. The balun 100 feeds two signals with opposite phases in the same polarization direction.

[0021] <Balun Configuration> Fig. 2 is an example circuit diagram of the balun 100 in Fig. 1. Referring to Fig. 2, the balun 100 includes an unbalanced terminal TU1, balanced terminals TB1 and TB2, as well as a main line ML1 and sub-lines SL1 to SL4. When the wavelength of the high-frequency signal to be passed is λ, the main line ML1 has an electrical length of λ / 2, and each of the sub-lines SL1, SL2, SL3, and SL4 has an electrical length of λ / 4.

[0022] In the first embodiment, an example will be described in which an unbalanced signal is converted into a balanced signal using the unbalanced terminal TU1 as an input terminal and the balanced terminals TB1 and TB2 as output terminals. Note that the balun 100 can also be used in cases in which a balanced signal input to the balanced terminals TB1 and TB2 is converted into an unbalanced signal and output from the unbalanced terminal TU1.

[0023] The pass band of balun 100 in the first embodiment is a band of 120 GHz to 140 GHz. In some aspects, the pass band of balun 100 may be another band, for example, a band of 130 GHz to 150 GHz or a band of 140 GHz to 160 GHz.

[0024] Balun 100 is a so-called Marchand balun in which two sub-lines SL1 and SL3, each having a length of λ / 4, are coupled to a main line ML1 having a length of 1 / 2 the wavelength λ (λ / 2) connected to an unbalanced terminal. In such a Marchand balun, the lengths of the main line ML1 and the sub-lines SL1 to SL4 are appropriately set according to the center frequency of the passband.

[0025] As shown in FIG. 2 , one end of the main line ML1 is connected to the unbalanced terminal TU1, and the other end is open. A sub-line SL1 is connected between the balanced terminal TB1 and a ground electrode (reference potential). The sub-line SL1 is arranged so as to be electromagnetically coupled to the main line ML1, which is an unbalanced line. Similarly, a sub-line SL3 is connected between the balanced terminal TB2 and the ground electrode. The sub-line SL3 is arranged so as to be electromagnetically coupled to the main line ML1, which is also an unbalanced line. The sub-lines SL1 and SL3 are connected to the ground electrode and the balanced terminals TB1 and TB2, respectively, so that the phase of the high-frequency signal output via the sub-line SL1 is inverted from the phase of the high-frequency signal output via the sub-line SL3.

[0026] In a Marchand balun having such a configuration, a high-frequency signal input to the unbalanced terminal TU1 (input terminal) is transmitted to two balanced lines by electromagnetic field coupling and output as a balanced signal from the balanced terminal TB1 (output terminal) and the balanced terminal TB2 (output terminal).

[0027] In the first embodiment, as shown in Fig. 2, a sub-line SL2 is connected in parallel to the sub-line SL1 between the balanced terminal TB1 and the ground electrode, and as shown in Fig. 2, a sub-line SL4 is connected in parallel to the sub-line SL3 between the balanced terminal TB2 and the ground electrode.

[0028] 2, the distance between the sub-line SL3 and the main line ML1 and the distance between the sub-line SL1 and the main line ML1 are each a distance D1, and the distance between the sub-line SL4 and the sub-line SL3 and the distance between the sub-line SL2 and the sub-line SL1 are each a distance D2.

[0029] In the balun 100 of this embodiment, the sub-lines SL2 and SL4 shown in FIG. 2 are provided, thereby making it possible to lower the frequency of the attenuation pole occurring in the pass band, thereby improving the pass band characteristics of the balun 100. Note that the main line ML1 may correspond to the "main line" in this disclosure. Also, the sub-lines SL1 to SL4 may correspond to the "first sub-line to fourth sub-line" in this disclosure, respectively. The balanced terminal TB1 may correspond to the "first balanced terminal" in this disclosure. The balanced terminal TB2 may correspond to the "second balanced terminal" in this disclosure.

[0030] Next, the shape of the balun 100 shown in FIG. 2 will be described in detail using FIGS. 3 and 4 . FIG. 3 is a plan view of the balun 100 according to the first embodiment. As shown in FIG. 3 , the balun 100 is formed on a dielectric substrate Sb1. In FIGS. 3 and 4 , the normal direction to the main surface Sf1 of the dielectric substrate Sb1 is defined as the Z axis, a direction within the plane of the main surface Sf1 is defined as the X axis, and a direction perpendicular to the X axis is defined as the Y axis. FIG. 3 shows the main surface Sf2 of the dielectric substrate Sb1, which is the surface in the positive direction of the Z axis. The dielectric substrate Sb1 according to the first embodiment is a substrate formed by stacking multiple layers. In one aspect, the dielectric substrate Sb1 may be a single-layer substrate.

[0031] The main line ML1 and sub-lines SL1 to SL4 included in the balun 100 are formed on the main surface Sf2 of the dielectric substrate Sb1. Point Cp1 is a point on the main surface Sf2. The main line ML1 and the sub-lines SL1 to SL4 are arranged with point Cp1 as their centers. The balun 100 includes wiring patterns Pt1, Pt2, and Pt3.

[0032] In the first embodiment, the main line ML1 described in FIG. 2 is realized by the wiring pattern Pt1 and the end portions Es1 and Ee1 shown in FIG. 3. The wiring pattern Pt1 is located closest to the point Cp1 among the wiring patterns Pt1 to Pt3. In other words, the wiring pattern Pt1 is located at the innermost position in the balun 100. The wiring pattern Pt1 is connected to the unbalanced terminal TU1 at the end portion Es1. As shown in FIG. 3, the main line ML1 extends from the end portion Es1 toward the positive side of the X-axis direction and is then wound clockwise around the Z-axis passing through the point Cp1 as the winding axis. In other words, the main line ML1 has a shape wound around the Z-axis passing through the point Cp1 when the dielectric substrate Sb1 is viewed in plan. The end portion Ee1 is an open end.

[0033] The wiring pattern Pt2 is disposed on the positive side of the Y-axis relative to the wiring pattern Pt1. The wiring pattern Pt3 is disposed on the negative side of the Y-axis relative to the wiring pattern Pt1. In other words, the wiring pattern Pt1 is disposed between the wiring patterns Pt2 and Pt3. The wiring patterns Pt2 and Pt3 have shapes that are symmetrical with respect to the line L1 shown in FIG. 3 as the center line. The line L1 is a line in the X-axis direction that passes through the point Cp1.

[0034] In the first embodiment, the sub-line SL1 and the sub-line SL2 described in FIG. 2 are each realized by the wiring pattern Pt2 and the end portions Es2 and Ee2 shown in FIG. 3. The wiring pattern Pt2 contacts the ground electrode on the negative side of the end portion Es2 along the Z axis. The contact point between the end portion Es2 and the ground electrode will be described later using the cross-sectional view of FIG. 4. As shown in FIG. 3, the sub-line SL1 is disposed along the main line ML1 disposed on the positive side of the line L1 along the Y axis. In other words, the sub-line SL1 has a substantially J-shape. The sub-line SL1 is electromagnetically coupled to the main line ML1 disposed on the positive side of the line L1 along the Y axis. The distance between the sub-line SL1 and the main line ML1 is a gap D1.

[0035] As an example, the distance D1 is equal to or greater than 5 μm and less than 6 μm. As shown in FIG. 3 , the distance D1 is shown as the distance between the sub-line SL1 and the main line ML1 in the Y-axis direction, but the distance between the sub-line SL1 and the main line ML1 in the X-axis direction and at the curved portion is also the distance D1. That is, the sub-line SL1 and the main line ML1 are arranged so that the distance between the sub-line SL1 and the main line ML1 in each direction is all uniformly the distance D1. In other words, the distance D1 is the shortest distance from the side edge of the sub-line SL1 to the side edge of the main line ML1.

[0036] As shown in FIG. 3 , the sub-line SL2 is arranged along the sub-line SL1. That is, the sub-line SL2 also has a substantially J-shape. The distance between the sub-line SL2 and the sub-line SL1 is a gap D2. The gap D2 is, for example, 3 μm or more and less than 5 μm. Like the gap D1 between the sub-line SL1 and the main line ML1, the gap D2 also exists between the sub-line SL2 and the sub-line SL1 in the Y-axis direction, the X-axis direction, and the curved portion. That is, the sub-line SL2 and the sub-line SL1 are arranged such that the distances between the sub-line SL2 and the sub-line SL1 in each direction are all uniformly the gap D2. In other words, the gap D2 is the shortest distance from the edge of the side surface of the sub-line SL1 to the edge of the side surface of the sub-line SL1. In this way, the sub-lines SL1 and SL2 are arranged along the shape of the main line ML1. As a result, the sub-line SL1 is arranged between the sub-line SL2 and the main line ML1.

[0037] As described above, the wiring pattern Pt2 is formed so that the interval D2 is shorter than the interval D1. The wiring pattern Pt2 is connected to the balanced terminal TB1 at the end Ee2. This allows the electrical lengths of the sub-lines SL2 and SL1 to be closer to each other. If the interval D2 and the interval D1 were the same length, the electrical length of the sub-line SL2 would be longer than the electrical length of the sub-line SL1 because the sub-line SL2 is disposed on the outer side of the sub-line SL1. As a result, the length of one of the sub-lines SL1 and SL2 deviates from the length of λ / 4. Therefore, in the first embodiment, by making the interval D2 shorter than the interval D1, the electrical lengths of the sub-lines SL1 and SL2 can be made closer to each other, thereby preventing the deviation from the length of λ / 4 from increasing.

[0038] In the first embodiment, the sub-line SL3 and the sub-line SL4 described in FIG. 2 are each realized by the wiring pattern Pt3 and the end portions Es3 and Ee3 shown in FIG. 3. The wiring pattern Pt3 contacts the ground electrode on the negative side of the end portion Es3 in the Z-axis direction. The contact point between the end portion Es3 and the ground electrode will be described later using the cross-sectional view of FIG. 4. The sub-line SL3 has a shape that follows the main line ML1 that is disposed on the negative side of the line L1 in the Y-axis direction. In other words, the sub-line SL3 has a substantially J-shape.

[0039] The distance between the sub-line SL3 and the main line ML1 is the distance D1, similar to the distance between the sub-line SL1 and the main line ML1. The sub-line SL3 is electromagnetically coupled to the main line ML1, which is located on the negative side of the Y-axis of the line L1. The distance D1 between the sub-line SL3 and the main line ML1 is also the distance D1 in the X-axis direction and at the curved portion, similar to the distance between the sub-line SL1 and the main line ML1. In other words, the sub-line SL3 and the main line ML1 are arranged so that the distance between the sub-line SL3 and the main line ML1 in all directions is the uniform distance D1. In other words, the distance D1 is the shortest distance from the side edge of the sub-line SL3 to the side edge of the main line ML1.

[0040] The sub-line SL4 has a shape that follows the sub-line SL3. That is, the sub-line SL4 also has a substantially J-shape. The distance between the sub-line SL4 and the sub-line SL1 is a distance D2. The distance D2 between the sub-line SL4 and the sub-line SL3 is the same in the X-axis direction and at the curved portion as the distance between the sub-line SL2 and the sub-line SL1. That is, the sub-line SL4 and the sub-line SL3 are arranged so that the distance between the sub-line SL4 and the sub-line SL3 in each direction is uniformly the distance D2. In other words, the distance D2 is the shortest distance from the edge of the side surface of the sub-line SL4 to the edge of the side surface of the sub-line SL3.

[0041] In this way, like the wiring pattern Pt2, the wiring pattern Pt3 is also formed so that the interval D2 is shorter than the interval D1. The wiring pattern Pt3 is connected to the balanced terminal TB2 at the end Ee3. As a result, in the first embodiment, the electrical lengths of the sub-lines SL3 and SL4 can be made closer to the same length, thereby preventing the deviation from the length of λ / 4 from increasing. Also, as described above, the main line ML1 in the first embodiment has a shape that is wound around the Z-axis. This allows the balun 100 to be made smaller than when the main line ML1 is straight and not wound.

[0042] 3, the main line ML1 has a width WM1, the sub-line SL1 has a width W1, and the sub-line SL2 has a width W2.

[0043] 4 is a diagram for explaining the cross sections of the end portion Es2 and the end portion Es3. The cross sections of the end portion Es2 and the end portion Es3 in FIG. 3 have the same shape. Therefore, for ease of explanation, the following description will be given using the end portion Es2 as an example.

[0044] The upper part of Fig. 4 shows a plan view of the end Es2 as viewed from the positive side of the Z axis shown in Fig. 3. The lower part of Fig. 4 shows a cross-sectional view of the end Es2 as viewed from the negative side of the Y axis. As shown in the lower part of Fig. 4, the dielectric substrate Sb1 has a main surface Sf2 on the positive side of the Z axis and a main surface Sf1 on the negative side of the Z axis. A through hole U1 is formed in the main surface Sf1 of the end Es2 by etching. The end Es2 is arranged at the opening of the through hole U1 on the main surface Sf2 side so as to cover the through hole U1. More specifically, the through hole U1 is a region in which the end Es2 of the wiring pattern Pt2 is arranged on the positive side of the Z axis and which has an opening on the negative side of the Z axis.

[0045] In the balun 100, after the through hole U1 is formed, the ground electrode Mk1 is disposed on the main surface Sf1. The ground electrode Mk1 is formed, for example, by plating. In the first embodiment, plating is also performed on the main surface Sf1 and the interior of the through hole U1. As a result, as shown in FIG. 4 , a via V1 is formed on the inner surface of the through hole U1. The ground electrode Mk1 and the via V1 are made of the same base material. The electrode formed on the main surface Sf1 is referred to as the "ground electrode Mk1," and the electrode formed inside the through hole U1 is referred to as the "via V1." That is, the via V1 electrically connects the end Es2, which is disposed on the main surface Sf2, to the ground electrode Mk1, which is also disposed on the main surface Sf1. Note that a via V2 and a through hole U2 are formed at the end Es3, similar to the end Es2.

[0046] The ground electrode Mk1 is disposed over the entire main surface Sf1 and is also disposed on the main surface Sf2 below the main line ML1 and the sub-lines SL1 and SL2. In other words, the main line ML1 and the sub-lines SL1 and SL2 each overlap with the ground electrode Mk1 when the main surface Sf1 is viewed in plan. That is, capacitive coupling occurs between the main line ML1 and the ground electrode Mk1, between the sub-line SL1 and the ground electrode Mk1, and between the sub-line SL2 and the ground electrode Mk1. The magnitude of these capacitive couplings increases as the width WM1 of the main line ML1, the width W1 of the sub-line SL1, and the width W2 of the sub-line SL2 shown in FIG. 3 increase. In the first embodiment, the width WM1 is the same as the width W1. The width W2 is shorter than the width W1.

[0047] The approximately elliptical shape indicated by the dashed line at the top of Figure 4 indicates the opening of the through-hole, i.e., the region where the ground electrode Mk1 and the end Es2 are in contact. The length of the approximately elliptical shape in the Y-axis direction is length D3. The length of the approximately elliptical shape in the X-axis direction is length D4. As an example, length D3 is 15 µm, and length D4 is 30 µm.

[0048] Thus, in the balun 100 of this embodiment, the end Es2 is connected to the ground electrode Mk1 through the via V1 formed on the negative side of the end Es2 along the Z axis. However, it is difficult to achieve perfect contact between the via V1 formed in the through hole U1 by plating and the end Es2, and a small capacitance component may occur between the via V1 and the end Es2. As a result, unintended parasitic capacitance occurs between the end Es2 and the via V1.

[0049] If parasitic capacitance occurs between the ground electrode Mk1 and the end Es2, an LC series resonator is formed by the capacitance component of the parasitic capacitance and the inductance components of the sub-line SL1 and the sub-line SL2. As a result, in the balun 100, at the resonant frequency of this LC series resonator, part of the unbalanced signal flows into the ground electrode Mk1. If the resonant frequency of the LC series resonator is within the passband, the pass characteristics of the balun 100 are degraded. Therefore, in the balun 100 of the first embodiment, the sub-lines SL2 and SL4 are provided to lower the resonant frequency of the LC series resonator formed by the capacitance component between the ground electrode Mk1 and the end Es2, thereby suppressing degradation of the pass characteristics of the balun 100.

[0050] FIG. 5 is a diagram showing an equivalent circuit of the sub-line SL1, the sub-line SL2, and the via V1 in the first embodiment. FIG. 5 shows the sub-line SL1, the sub-line SL2, the load RL which is the load impedance of the antenna ANT, and the via V1. As shown in FIG. 5, the unintended parasitic capacitance described above is shown as capacitance CX1 at one end of the sub-line SL1. The load RL is connected to the other end of the sub-line SL1. In FIG. 5, the capacitance component generated between the sub-line SL1 and the ground electrode Mk1, which are arranged in a position overlapping when the main surface Sf1 is viewed from above, is shown as capacitance Cs2. As described above, as the width W1 increases, the capacitance value of capacitance Cs2 increases.

[0051] The balun 100 of the first embodiment includes a sub-line SL2 in addition to the sub-line SL1. This generates a capacitance Cs3 between the sub-line SL2 and the ground electrode Mk1 applied to the main surface Sf1. Like the capacitance Cs2, the capacitance Cs3 is a capacitance component generated between the sub-line SL2 and the ground electrode Mk1. As described above, the capacitance value of the capacitance Cs3 increases as the width W2 increases. In the first embodiment, this capacitance Cs3 increases the capacitance component of the LC series resonator formed by the parasitic capacitance CX1 and the inductance components of the sub-line SL1 and the sub-line SL2. This allows the resonant frequency of the LC series resonator to be lowered in the first embodiment compared to a configuration without the sub-line SL2.

[0052] 6 is an example of a circuit diagram of a balun 100Z in a comparative example. The balun 100Z in Fig. 6 is a general Marchand balun, and has a configuration in which the sub-line SL2 and the sub-line SL4 are removed from the balun 100 in the first embodiment.

[0053] 7 is a plan view of a balun 100Z according to a comparative example. As shown in FIG. 7, the wiring patterns Pt2 and Pt3 according to the comparative example have a shape obtained by removing the sub-lines SL2 and SL4 from the wiring patterns Pt2 and Pt3 according to the first embodiment. That is, the wiring patterns Pt2 and Pt3 in the balun 100Z according to the comparative example each have only the sub-lines SL1 and SL3. As shown in FIG. 7, in the balun 100Z according to the comparative example, the width W1Z of the main line ML1 is the same as the width W1Z of the sub-line SL1.

[0054] 8 is an equivalent circuit diagram showing the relationship between the sub-line SL1 and the via V1 in the comparative example. In the comparative example, the sub-line SL2 is removed, and therefore the only capacitance component connected in parallel with the ground electrode Mk1 between the via V1 and the load RL is the capacitance Cs2 between the sub-line SL1 and the ground electrode Mk1. In the comparative example, an attenuation pole is generated by the resonant frequency of an LC series resonator formed by the capacitance CX1 of the parasitic capacitance and the inductance component of the sub-line SL1.

[0055] FIG. 9 is a diagram illustrating the pass characteristics of the balun 100Z of the comparative example. In FIG. 9, the horizontal axis represents frequency, and the vertical axis represents the insertion loss of the balun 100Z. FIG. 10 is an enlarged view of the insertion loss near the pass band of FIG. 9. In FIGS. 9 and 10, the solid line LN1Z represents the insertion loss of the balun 100Z of the comparative example. As shown in FIG. 10, the balun 100 of the first embodiment generates an attenuation pole near 119 GHz, which is on the lower side of the pass band. This attenuation pole is generated by the LC series resonator formed by the parasitic capacitance CX1 and the inductance component of the sub-line SL1, as described above. As a result, as shown in FIG. 10, the influence of this attenuation pole occurs within the pass band of the balun 100Z, degrading the pass characteristics of the balun 100Z.

[0056] <Regarding Pass Characteristics of First Embodiment> Fig. 11 is a diagram for explaining the pass characteristics of the balun 100 according to the first embodiment. In Fig. 11, similar to Fig. 6, the horizontal axis represents frequency, and the vertical axis represents the insertion loss of the balun 100. Fig. 12 is an enlarged view of the insertion loss near the pass band of Fig. 11. In Figs. 11 and 12, the solid line LN1 indicates the insertion loss in the balun 100 according to the first embodiment.

[0057] 11 , in the balun 100 of the first embodiment, an attenuation pole is generated near 102 GHz, which is on the lower side of the passband. As described above, this attenuation pole is generated by the LC series resonator formed by the parasitic capacitance CX1 and the inductance components of the sub-lines SL1 and SL2. However, in the balun 100 of the first embodiment, the provision of the sub-line SL2 generates a capacitance Cs3, and by increasing the capacitance component of the LC series resonator, the frequency of the attenuation pole is shifted to a lower frequency.

[0058] In this way, in the balun 100 of the first embodiment, the resonant frequency of the LC series resonator, which would otherwise be formed unintentionally, is lowered by providing the sub-line SL2, thereby shifting the attenuation pole to a frequency band lower than the passband. As a result, as shown in FIG. 12 , no attenuation pole is generated within the passband in the first embodiment. That is, the pass characteristics of the balun 100 used in the communication device 1000 are improved. While the above description has been made regarding the effect of providing the sub-line SL2 in the wiring pattern Pt2, the same effect can be achieved by providing the sub-line SL4 in the wiring pattern Pt3. In the example of the first embodiment, the wiring patterns Pt2 and Pt3 each have the sub-line SL2 and SL4, respectively. However, the sub-line SL2 or the sub-line SL4 may be provided in only one of the wiring patterns Pt2 and Pt3.

[0059] As shown by comparing the comparative example shown in Figures 8 to 12 with the first embodiment, in the first embodiment, the capacitance Cs3 generated by the provision of the sub-line SL2 is added to the capacitance component of the LC series resonator. In particular, by comparing Figures 5 and 8, in the first embodiment, the capacitance Cs3 shown in Figure 5 can shift the attenuation pole of the LC series resonator to a lower frequency, thereby improving the pass characteristics. Next, the advantages of the first embodiment will be described from the viewpoint of the coupling coefficient k of the electric field coupling between the wiring pattern Pt1 and the wiring pattern Pt2.

[0060] <Coupling Coefficient of Electric Field Coupling> Figure 13 is a diagram for explaining the electric field coupling between the wiring patterns Pt1 and Pt2 in the balun 100Z of the comparative example. The wiring patterns Pt1 and Pt2 described above are electric field coupled to each other. The coupling coefficient k of the electric field coupling between the wiring patterns is generally determined by the wiring capacitances Cs1 and Cs2 and the inter-wiring capacitance Cm1 between the main line ML1 and the sub-line SL1, as shown in Figure 13.

[0061] The wiring capacitance Cs1 is a capacitance component between the main line ML1 and the ground electrode Mk1. The wiring capacitance Cs2 is a capacitance component between the sub-line SL1 and the ground electrode Mk1. As described above, in the comparative example, the width of the main line ML1 and the width of the sub-line SL1 are both width W1Z. Therefore, the value of the wiring capacitance Cs1 and the value of the wiring capacitance Cs2 are the same. The inter-line capacitance Cm1 is a capacitance component between the sub-line SL1 and the main line ML1.

[0062] As shown in Figure 13, in the balun 100Z in the comparative example, the coupling coefficient k between the wiring pattern Pt1 and the wiring pattern Pt2 is the value obtained by dividing the inter-wiring capacitance Cm1 between the sub-line SL1 and the main line ML1 by the sum of the inter-wiring capacitance Cm1 and the wiring capacitances Cs1 and Cs2.

[0063] Next, electric field coupling in the first embodiment will be described. FIG. 14 is a diagram for explaining electric field coupling between wiring patterns in the first embodiment. The balun 100 of the first embodiment is provided with a sub-line SL2. The wiring capacitance Cs3 is a capacitance component between the sub-line SL2 and the ground electrode Mk1. The coupling coefficient k between the wiring patterns Pt1 and Pt2 is calculated by dividing the inter-line capacitance Cm1 between the sub-line SL1 and the main line ML1 by the sum of the inter-line capacitance Cm1 and the wiring capacitances Cs1 to Cs3.

[0064] The wiring capacitances Cs2 and Cs3 in Fig. 14 correspond to the capacitances Cs2 and Cs3 in Fig. 5. As described above, in the first embodiment, the width WM1 of the main line ML1 and the width W1 of the sub-line SL1 are the same width. Therefore, the wiring capacitances Cs1 and Cs2 in Fig. 14 are the same value. On the other hand, the width W2 of the sub-line SL2 is shorter than the width WM1 and the width W1. Therefore, the wiring capacitance Cs3 is smaller than the wiring capacitance Cs1.

[0065] In the Marchand balun described with reference to FIGS. 1 to 5, the pass characteristics of the balun 100 are improved by lowering the resonant frequency of the LC series resonator due to the unintentional capacitance CX1. On the other hand, in the Marchand balun according to the first embodiment, it is undesirable to change the coupling coefficient k from the same coupling coefficient k as that of the balun 100Z of the comparative example. If the coupling coefficient k between the wiring patterns Pt1 and Pt2 decreases, the characteristics in the pass band will deteriorate. Furthermore, if the coupling coefficient k between the wiring patterns Pt1 and Pt2 increases, the width of the main line ML1 or the sub-line SL1 will decrease, increasing the loss generated in the main line ML1 or the sub-line SL1.

[0066] Therefore, the balun 100 of the first embodiment has a configuration in which the sub-line SL1 is disposed between the sub-line SL2 and the main line ML1, as described with reference to Figures 2 and 3. As a result, the coupling coefficient k of the first embodiment varies only by the addition of the wiring capacitance Cs3 to the denominator, as compared to the coupling coefficient k of the first comparative example. Increasing the width W1Z of the sub-line SL1 in the configuration of the first comparative example can increase the capacitance component of the LC series resonator, but the width W1Z of the sub-line SL1 also affects the wiring capacitance Cm1 between the sub-line SL1 and the main line ML1, and the coupling coefficient k varies significantly from the coupling coefficient k shown in Figure 13.

[0067] Therefore, in the first embodiment, the width WM1 of the main line ML1 and the width W1 of the sub-line SL1 are set to the same value, and a sub-line SL2 different from the sub-line SL1 is added. This allows the first embodiment to lower the resonant frequency of the LC series resonator while minimizing fluctuations in the coupling coefficient k. Note that, as long as the value of the coupling coefficient k in the first embodiment varies little from the value of the coupling coefficient k in the first comparative example, the width W1 of the sub-line SL1 does not need to be the same as the width WM1 of the main line ML1. For example, the width W1 of the sub-line SL1 may be smaller than the width WM1 of the main line ML1 and larger than the width W2 of the sub-line SL3. The widths WM1, W1, and W2 can be adjusted as appropriate through simulation, experiment, or the like. In this way, in the balun 100 of the first embodiment, the sub-line SL2 is provided separately from the sub-line SL1, so that the LC series resonance frequency can be lowered and the frequency at which an attenuation pole occurs can be adjusted while suppressing deterioration of the degree of coupling between the main line ML1 and the sub-line SL1, thereby improving the pass characteristics of the balun 100.

[0068] In the above example, the wiring patterns Pt1 to Pt3 are arranged on the same layer on the dielectric substrate Sb1. However, this is not limiting. Each of the wiring patterns Pt1 to Pt3 may be provided on a different layer within the multi-layer dielectric substrate Sb1. Furthermore, each of the wiring patterns Pt1 to Pt3 may be formed as an electrode spanning multiple layers. That is, in the first embodiment, it is sufficient that the sub-lines SL1 and SL2 overlap with the ground electrode Mk1 when viewed from the stacking direction of the dielectric substrate Sb1, generating the wiring capacitances Cs2 and Cs3. The main line ML1, the sub-lines SL1 and SL2, the ground electrode Mk1, the balanced terminals TB1 and TB2, and the unbalanced terminal TU1 may be formed on different layers.

[0069] More specifically, if the dielectric substrate Sb1 is formed by stacking four layers, namely, a first layer, a second layer, a third layer, and a fourth layer, the ground electrode Mk1 may be formed on the first layer, the main line ML1 may be formed on the second layer, the sub-line SL1 may be formed on the third layer, and the sub-line SL2 may be formed on the fourth layer. Even in this case, the sub-line SL1 is formed between the main line ML1 and the sub-line SL2, and therefore the degree of coupling between the sub-line SL2 and the main line ML1 is weaker than the degree of coupling between the sub-line SL1 and the main line ML1.

[0070] [Embodiment 2] The schematic configuration of a balun 100 and a front-end circuit 10A according to embodiment 2 will be described with reference to Fig. 15. Fig. 15 is a schematic configuration diagram of a communication device 1000A according to embodiment 2. In embodiment 2, the description of the same configuration as in embodiment 1 will not be repeated.

[0071] The communication device 1000A of the second embodiment has a converter 110 configured with an MCT element or a balun between the RFIC 20 and the front-end circuit 10A. The converter 110 converts an unbalanced signal into a balanced signal and outputs the balanced signal to the front-end circuit 10A.

[0072] The front-end circuit 10A of the second embodiment includes power amplifiers PA1 and PA2 and matching circuits 50A and 50B. The power amplifiers PA1 and PA2 amplify the unbalanced signal converted by the converter 110 and output the amplified signal to the matching circuits 50A and 50B, respectively.

[0073] Matching circuit 50A is provided between power amplifier PA1 and balun 100 and performs impedance matching between power amplifier PA1 and balun 100. Matching circuit 50B is provided between power amplifier PA2 and balun 100 and performs impedance matching between power amplifier PA2 and balun 100. In the second embodiment, balun 100, unlike in the first embodiment, performs conversion from a balanced signal to an unbalanced signal. The high-frequency signal converted from a balanced signal to an unbalanced signal by balun 100 of the second embodiment is transmitted to feed point Fp1 of antenna ANT.

[0074] As described above, the balun 100 of this embodiment can also be applied to a balun 100 that converts a balanced signal to an unbalanced signal. In the second embodiment, as in the first embodiment, the sub-line SL2 is provided separately from the sub-line SL1, thereby suppressing deterioration of the degree of coupling between the main line ML1 and the sub-line SL1, lowering the LC series resonance frequency, and adjusting the frequency at which an attenuation pole occurs. In other words, the pass characteristics of the balun 100 can be improved.

[0075] [Third Embodiment] The configuration of a balun 100A according to a third embodiment will be described with reference to Fig. 16. Fig. 16 is a plan view of balun 100A according to the third embodiment. In the third embodiment, the description of the same configuration as in the first embodiment will not be repeated.

[0076] In the third embodiment, as shown in FIG. 16 , the main line ML1 has a linear shape. The sub-lines SL1 and SL2 have a shape that follows the main line ML1, and therefore have a linear shape similar to the main line ML1. Even with this shape, the balun 100A of the third embodiment can suppress deterioration of the degree of coupling between the main line ML1 and the sub-line SL1 by providing the sub-line SL2 separately from the sub-line SL1, thereby lowering the LC series resonance frequency and adjusting the frequency at which an attenuation pole occurs. In other words, the pass characteristics of the balun 100A can be improved.

[0077] Furthermore, in the third embodiment, because both the sub-lines SL1 and SL2 have a linear shape, it is not necessary to make the distance between the sub-line SL2 and the sub-line SL1 smaller than the distance between the main line ML1 and the sub-line SL1. Therefore, as shown in FIG. 16 , in the third embodiment, the distance between the sub-line SL1 and the sub-line SL2 is the same as the distance D5 between the main line ML1 and the sub-line SL1. Also, in the third embodiment, because the main line ML1 has a linear shape extending in the Y-axis direction, the length of the balun 100A as a whole in the X-axis direction is reduced. As shown in the first and third embodiments, the design flexibility of the balun 100 can be improved by changing the shapes of the main line ML1 and the sub-lines SL1 and SL2.

[0078] <Supplementary Note 1> A balun comprising: a dielectric substrate having a first surface and a second surface opposing each other; a ground electrode formed on the first surface; an unbalanced terminal formed on the second surface; a pair of balanced terminals including a first balanced terminal formed on the second surface; a main line formed on the second surface, one end connected to the unbalanced terminal and the other end open; a first sub-line formed on the second surface, one end connected to the first balanced terminal; and a second sub-line formed on the second surface, one end connected to the first balanced terminal, wherein the other end of the first sub-line is connected to the ground electrode via a first via and is disposed between the main line and the second sub-line, and each of the first sub-line and the second sub-line overlaps with the ground electrode when the second surface is viewed in plan.

[0079] <Supplementary Note 2> The balun according to Supplementary Note 1, wherein the main line has a shape wound around a winding axis when the second surface is viewed in plan.

[0080] <Supplementary Note 3> The balun according to Supplementary Note 2, wherein the shortest distance between the main line and the first sub-line is longer than the shortest distance between the first sub-line and the second sub-line.

[0081] <Supplementary Note 4> The balun according to Supplementary Note 1, wherein the main line has a linear shape when the second surface is viewed in plan.

[0082] <Supplementary Note 5> The balun according to Supplementary Note 4, wherein the shortest distance between the main line and the first sub-line is the same as the shortest distance between the first sub-line and the second sub-line.

[0083] <Supplementary Note 6> The balun according to any one of Supplementary Note 1 to Supplementary Note 5, wherein the width of the first sub-line when the second surface is viewed in plan is the same as the width of the main line.

[0084] <Supplementary Note 7> The balun according to any one of Supplementary Note 1 to Supplementary Note 6, wherein the width of the second sub-line when the second surface is viewed in plan is smaller than the width of the first sub-line.

[0085] <Supplementary Note 8> The balun according to any one of Supplementary Note 1 to Supplementary Note 7, wherein the base material of the dielectric substrate is a compound semiconductor.

[0086] <Supplementary Note 9> The balun according to any one of Supplementary Notes 1 to 8, wherein the pair of balanced terminals includes a second balanced terminal formed on the second surface, and the balun further comprises: a third sub-line formed on the second surface and having one end connected to the second balanced terminal; and a fourth sub-line formed on the second surface and having one end connected between the second balanced terminal and the ground electrode, wherein the other end of the third sub-line is connected to the ground electrode via a second via and the third sub-line is disposed between the main line and the fourth sub-line, and each of the third sub-line and the fourth sub-line overlaps with the ground electrode when the first surface is viewed in plan.

[0087] <Supplementary Note 10> A front-end circuit comprising: the balun according to Supplementary Note 9; and an amplifier connected to at least one of the first balanced terminal, the second balanced terminal, and the unbalanced terminal, wherein the amplifier is formed on a dielectric substrate.

[0088] <Supplementary Note 11> A balun comprising: a dielectric substrate on which a plurality of layers including a first layer are laminated; a ground electrode formed on the first layer; an unbalanced terminal provided on the dielectric substrate; a pair of balanced terminals including the first balanced terminal provided on the dielectric substrate; a main line formed on a layer different from the first layer, one end connected to the unbalanced terminal and the other end open; a first sub-line formed on a layer different from the first layer, one end connected to the first balanced terminal; and a second sub-line formed on a layer different from the first layer, one end connected to the first balanced terminal, wherein the other end of the first sub-line is connected to the ground electrode via a first via, and the first sub-line is disposed between the main line and the second sub-line when viewed from the lamination direction of the dielectric substrate, and each of the first sub-line and the second sub-line overlaps with the ground electrode when viewed from the lamination direction of the dielectric substrate.

[0089] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0090] 1000, 1000A communication device, ANT antenna, CX1, Cs1 to Cs3 capacitance, Cm1 inter-wiring capacitance, Cp1 point, D1, D2, D5 spacing, D3, D4 length, Ee1, Ee2, Ee3, Es1, Es2, Es3 end, Fp1, Fp2 feeding point, L1 line, LN1Z, LN1 solid line, ML1 main line, Mk1 ground electrode, PA, PA1, PA2 power amplifier, Pt1 to Pt3 wiring pattern, SL1 to SL4 sub-line, Sb1 dielectric substrate, Sf1, Sf2 main surface, TB1, TB2 balanced terminal, TU1 unbalanced terminal, U1 through hole, V1 via, W1Z, W1, W2, WM1 width, k coupling coefficient.

Claims

1. A balun comprising: a dielectric substrate having a first surface and a second surface opposing each other; a ground electrode formed on the first surface; an unbalanced terminal formed on the second surface; a pair of balanced terminals including a first balanced terminal formed on the second surface; a main line formed on the second surface and having one end connected to the unbalanced terminal and the other end open; a first sub-line formed on the second surface and having one end connected to the first balanced terminal; and a second sub-line formed on the second surface and having one end connected to the first balanced terminal, wherein the other end of the first sub-line is connected to the ground electrode via a first via and is disposed between the main line and the second sub-line, and each of the first sub-line and the second sub-line overlaps with the ground electrode when the second surface is viewed in plan.

2. The balun according to claim 1, wherein the main line has a shape wound around a winding axis when the second surface is viewed in plan.

3. The balun according to claim 2, wherein the shortest distance between the main line and the first sub-line is longer than the shortest distance between the first sub-line and the second sub-line.

4. The balun according to claim 1, wherein the main line has a linear shape when the second surface is viewed in plan.

5. The balun of claim 4, wherein the shortest distance between the main line and the first sub-line is the same as the shortest distance between the first sub-line and the second sub-line.

6. A balun according to any one of claims 1 to 5, wherein the width of the first sub-line when the second surface is viewed in a plan view is the same as the width of the main line.

7. A balun according to any one of claims 1 to 6, wherein the width of the second sub-line when the second surface is viewed in a plan view is smaller than the width of the first sub-line.

8. A balun according to any one of claims 1 to 7, wherein the base material of the dielectric substrate is a compound semiconductor.

9. The balun according to any one of claims 1 to 8, wherein the pair of balanced terminals includes a second balanced terminal formed on the second surface, and the balun further comprises: a third sub-line formed on the second surface and having one end connected to the second balanced terminal; and a fourth sub-line formed on the second surface and having one end connected between the second balanced terminal and the ground electrode, the third sub-line having the other end connected to the ground electrode via a second via and being disposed between the main line and the fourth sub-line, and each of the third sub-line and the fourth sub-line overlaps with the ground electrode when the first surface is viewed in plan.

10. A front-end circuit comprising: a balun as claimed in claim 9; and an amplifier connected to at least one of the first balanced terminal, the second balanced terminal, and the unbalanced terminal, the amplifier being formed on the dielectric substrate.

11. A balun comprising: a dielectric substrate on which a plurality of layers including a first layer are laminated; a ground electrode formed on the first layer; an unbalanced terminal provided on the dielectric substrate; a pair of balanced terminals including a first balanced terminal provided on the dielectric substrate; a main line formed on a layer different from the first layer and having one end connected to the unbalanced terminal and the other end open; a first sub-line formed on a layer different from the first layer and having one end connected to the first balanced terminal; and a second sub-line formed on a layer different from the first layer and having one end connected to the first balanced terminal, wherein the other end of the first sub-line is connected to the ground electrode via a first via, and the first sub-line is disposed between the main line and the second sub-line when viewed from the stacking direction of the dielectric substrate, and each of the first sub-line and the second sub-line overlaps with the ground electrode when viewed from the stacking direction of the dielectric substrate.

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