Display substrate and display apparatus

Abstract

Provided in the present disclosure are a display substrate and a display apparatus. The display substrate comprises first light emission control signal lines, second light emission control signal lines and a plurality of sub-pixels, wherein each sub-pixel comprises a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit comprising a driving transistor, a power supply control transistor and a light emission control transistor; a gate electrode of the power supply control transistor is coupled to a corresponding first light emission control signal line, a first electrode of the power supply control transistor is coupled to a corresponding power supply line, and a second electrode of the power supply control transistor is coupled to a first electrode of the driving transistor; a gate electrode of the light emission control transistor is coupled to a corresponding second light emission control signal line, a first electrode of the light emission control transistor is coupled to a second electrode of the driving transistor, and a second electrode of the light emission control transistor is coupled to the light-emitting element; and the orthographic projections of the first light emission control signal lines on a base substrate and the orthographic projections of the second light emission control signal lines on the base substrate are aligned in a second direction.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In recent years, with the rapid development of the display industry, rigid liquid crystal displays (LCDs) have gradually failed to meet people's pursuit of a better life. Therefore, organic light-emitting diode (OLED) displays, known for their flexibility, have emerged. Regardless of the type of display product, consumers have placed high demands on the image quality of the display products.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a power supply line, a first light emission control signal line, a second light emission control signal line, and a plurality of sub-pixels, all disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit comprising a driving transistor, a power supply control transistor, and a light emission control transistor;

[0007] The gate of the power control transistor is coupled to the corresponding first light-emitting control signal line, the first electrode of the power control transistor is coupled to the corresponding power line, and the second electrode of the power control transistor is coupled to the first electrode of the driving transistor; the gate of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is coupled to the light-emitting element;

[0008] The first light-emitting control signal line includes at least a portion extending along a first direction, the second light-emitting control signal line includes at least a portion extending along the first direction, the orthographic projection of the first light-emitting control signal line on the base substrate and the orthographic projection of the second light-emitting control signal line on the base substrate are arranged along a second direction, and the second direction intersects with the first direction.

[0009] Optionally, the power control transistor includes a power control active layer, the light emission control transistor includes a light emission control active layer, and the power control active layer and the light emission control active layer are arranged along the first direction.

[0010] Optionally, in the layout area of ​​the same sub-pixel driving circuit, at least part of the orthographic projection of the first light-emitting control signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second light-emitting control signal line on the substrate.

[0011] Optionally, at least a portion of the orthographic projection of the gate of the power control transistor on the substrate, and / or at least a portion of the orthographic projection of the gate of the light emitting control transistor on the substrate, is located between the orthographic projection of the first light emitting control signal line on the substrate and the orthographic projection of the second light emitting control signal line on the substrate.

[0012] Optionally, the display substrate further includes a first scan line and a data line; the sub-pixel driving circuit includes a data writing transistor, wherein a gate of the data writing transistor is coupled to the corresponding first scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0013] In the layout area of ​​the same sub-pixel driving circuit, at least part of the orthographic projection of the first scanning line on the base substrate is located between the orthographic projection of the first light-emitting control signal line on the base substrate and the orthographic projection of the second light-emitting control signal line on the base substrate.

[0014] Optionally, the orthographic projection of the first scan line on the substrate does not overlap with the orthographic projection of the first light-emitting control signal line on the substrate; and / or the orthographic projection of the first scan line on the substrate does not overlap with the orthographic projection of the second light-emitting control signal line on the substrate.

[0015] Optionally, the data write transistor includes a data write active layer, the power control transistor includes a power control active layer, and the drive transistor includes a drive active layer; a first end of the data write active layer, a first end of the power control active layer, and a first end of the drive active layer are coupled to form a second node portion;

[0016] At least a portion of the data writing active layer and at least a portion of the power control active layer are located on the same side of the driving active layer along the second direction.

[0017] Optionally, the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power line;

[0018] The second electrode plate includes a coupled electrode plate main body and an electrode plate extension, the orthographic projection of the electrode plate main body on the base substrate partially overlaps with the orthographic projection of the first electrode plate on the base substrate, the orthographic projection of the electrode plate extension on the base substrate does not overlap with the orthographic projection of the first electrode plate on the base substrate; the orthographic projection of the electrode plate extension on the base substrate at least partially overlaps with the orthographic projection of the second node portion on the base substrate.

[0019] Optionally, the orthographic projection of the electrode extension portion on the base substrate partially overlaps with the orthographic projection of the first light-emitting control signal line on the base substrate, and does not overlap with the orthographic projection of the second light-emitting control signal line on the base substrate.

[0020] Optionally, the sub-pixel driving circuit also includes a first conductive connection portion, which is coupled to the first pole of the power control transistor, the plate extension portion and the power line respectively; the orthographic projection of the first conductive connection portion on the substrate does not overlap with the orthographic projection of the plate main body on the substrate.

[0021] Optionally, the power line includes at least a portion extending along the second direction; an orthographic projection of the power line on the base substrate and an orthographic projection of the first light-emitting control signal line on the base substrate have a first overlapping area, and an orthographic projection of the power line on the base substrate and an orthographic projection of the second light-emitting control signal line on the base substrate have a second overlapping area;

[0022] A length of the first overlapping region along the first direction is greater than a length of the second overlapping region along the first direction.

[0023] Optionally, the first light-emitting control signal line and the gate of the power control transistor are arranged in different layers; and / or the second light-emitting control signal line and the gate of the light-emitting control transistor are arranged in different layers.

[0024] Optionally, the display substrate further includes a first source-drain metal layer, and the first light-emitting control signal line and / or the second light-emitting control signal line are provided in the same layer and with the same material as the first source-drain metal layer.

[0025] Optionally, the display substrate further includes a first initialization signal transmission layer, the first initialization signal transmission layer includes a plurality of first initialization transmission parts and a plurality of second initialization transmission parts, and an extension direction of the first initialization transmission parts intersects with an extension direction of the second initialization transmission parts;

[0026] At least part of the sub-pixel driving circuit also includes a first reset transistor and a second conductive connection part, the second conductive connection part is coupled to the first electrode of the first reset transistor, the corresponding first initialization transmission part and the corresponding second initialization transmission part respectively; the second electrode of the first reset transistor is coupled to the gate of the driving transistor.

[0027] Optionally, the display substrate further includes a second initialization signal transmission layer, the second initialization signal transmission layer includes a plurality of third initialization transmission parts and a plurality of fourth initialization transmission parts, and an extension direction of the third initialization transmission parts intersects with an extension direction of the fourth initialization transmission parts;

[0028] At least part of the sub-pixel driving circuit also includes a second reset transistor and an eighth conductive connection part, and the eighth conductive connection part is coupled to the first electrode of the second reset transistor, the corresponding third initialization transmission part and the corresponding fourth initialization transmission part respectively; the second electrode of the second reset transistor is coupled to the light-emitting element.

[0029] Optionally, the display substrate further includes a cathode layer and a plurality of first cathode compensation lines, the first cathode compensation lines include at least a portion extending along the second direction, and the plurality of first cathode compensation lines are respectively coupled to the cathode layer.

[0030] Optionally, the first initialization transmission portion and the third initialization transmission portion are alternately arranged along the second direction; and / or,

[0031] The second initialization transmission portion and the fourth initialization transmission portion are alternately arranged along the first direction; and / or,

[0032] At least a portion of the first cathode compensation line is located between the adjacent second initialization transfer portion and the fourth initialization transfer portion.

[0033] Optionally, the display substrate includes a plurality of power lines and a plurality of data lines;

[0034] The second initialization transmission portion is located between the adjacent power line and the data line; and / or the fourth initialization transmission portion is located between the adjacent power line and the data line; and / or the first cathode compensation line is located between the adjacent power line and the data line;

[0035] The adjacent power lines and data lines are coupled to the same sub-pixel driving circuit.

[0036] Optionally, the display substrate further includes a plurality of second cathode compensation lines arranged along the second direction, the second cathode compensation lines include at least a portion extending along the first direction, and the second cathode compensation lines are coupled to the first cathode compensation lines.

[0037] Optionally, the display substrate further includes a plurality of power compensation lines, each of which includes at least a portion extending along the first direction and is coupled to the power line; the power compensation line and the second cathode compensation line are alternately arranged along the second direction.

[0038] Optionally, the first reset transistor includes a first reset active layer, the first reset active layer includes two first channel portions, and first conductive portions respectively coupled to the two first channel portions; the orthographic projection of the first conductive portion on the base substrate at least partially overlaps with the orthographic projection of the third initialization transmission portion on the base substrate.

[0039] Optionally, the sub-pixel driving circuit further includes a compensation transistor, wherein a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to a gate of the driving transistor;

[0040] The compensation transistor includes a compensation active layer, which includes two second channel portions and second conductive portions respectively coupled to the two second channel portions; an orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first initialization transmission portion on the base substrate.

[0041] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0043] FIG1 is a schematic diagram of a circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0044] FIG2 is a driving timing diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0045] FIG3 is a schematic cross-sectional view of a film layer of a display substrate provided by an embodiment of the present disclosure;

[0046] FIG4 is a schematic diagram of the layout of the active layer of the display substrate provided in an embodiment of the present disclosure;

[0047] FIG5 is a schematic diagram showing the layout of the active layer and the first gate metal layer of the display substrate provided by an embodiment of the present disclosure;

[0048] FIG6 is a schematic diagram of the layout of the second gate metal layer of the display substrate provided by an embodiment of the present disclosure;

[0049] FIG7 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG5 ;

[0050] FIG8 is a schematic diagram of a via hole formed on an interlayer insulating layer of a display substrate according to an embodiment of the present disclosure;

[0051] FIG9 is a schematic diagram of a first layout of a first source / drain metal layer of a display substrate provided by an embodiment of the present disclosure;

[0052] FIG10 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG5 ;

[0053] FIG11 is a schematic diagram showing the layout of the second gate metal layer and the first source / drain metal layer of the display substrate provided by an embodiment of the present disclosure;

[0054] FIG12 is a schematic diagram showing the layout of a display substrate provided by an embodiment of the present disclosure, with a first source / drain metal layer added on the basis of FIG7 ;

[0055] FIG13 is a schematic diagram of a first layout of via holes formed on a first flat layer of a display substrate provided by an embodiment of the present disclosure;

[0056] FIG14 is a schematic diagram of a first layout of a second source / drain metal layer of a display substrate provided by an embodiment of the present disclosure;

[0057] FIG15 is a schematic diagram of the layout of via holes formed on the second flat layer of the display substrate provided by an embodiment of the present disclosure;

[0058] FIG16 is a schematic diagram of a first layout of a first source-drain metal layer and a second source-drain metal layer of a display substrate provided by an embodiment of the present disclosure;

[0059] FIG17 is a schematic diagram of a layout in which a second source / drain metal layer is added based on FIG11 ;

[0060] FIG18 is a schematic diagram of a layout in which a second source / drain metal layer is added on the basis of FIG12;

[0061] FIG19 is a schematic diagram of a second layout of the first source / drain metal layer of the display substrate provided by an embodiment of the present disclosure;

[0062] FIG20 is a schematic diagram of a second layout of via holes formed on the first flat layer of the display substrate provided by an embodiment of the present disclosure;

[0063] FIG21 is a schematic diagram of a second layout of a second source / drain metal layer of a display substrate provided by an embodiment of the present disclosure;

[0064] FIG22 is a second schematic diagram of the layout of the first source-drain metal layer and the second source-drain metal layer of the display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0066] The display image quality of a display product is related to the circuit structure and working state of the sub-pixel driving circuit included in the display product. In related technologies, the driving transistor in the sub-pixel driving circuit has hysteresis, and the frequency switching flicker problem of display products has not been well improved.

[0067] As shown in FIG1 , the present disclosure provides a display substrate comprising a plurality of sub-pixels, each of which includes a coupled sub-pixel driving circuit and a light-emitting element. The display substrate further comprises: a plurality of first light-emission control signal lines EM1, a plurality of second light-emission control signal lines EM2, a plurality of first scan lines GA1, a plurality of second scan lines GA2, a plurality of reset signal lines RST, a plurality of power lines VDD, a plurality of data lines DA, a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2, and a cathode layer.

[0068] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0069] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0070] As shown in Figures 5, 9, 10 and 11, exemplarily, the multiple first light-emitting control signal lines EM1 correspond one-to-one to the multiple rows of sub-pixel driving circuits, and the first light-emitting control signal line EM1 is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0071] Exemplarily, the plurality of second light emitting control signal lines EM2 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second light emitting control signal line EM2 is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0072] Exemplarily, the plurality of first scan lines GA1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first scan line GA1 is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0073] Exemplarily, the plurality of second scan lines GA2 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the second scan line GA2 is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0074] Exemplarily, the plurality of reset signal lines RST correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the reset signal line RST is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0075] Exemplarily, the plurality of power lines VDD correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the power line VDD is respectively coupled to each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuits.

[0076] Exemplarily, the plurality of data lines DA correspond one-to-one to the plurality of columns of sub-pixel driving circuits, and the data line DA is respectively coupled to each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuits.

[0077] As shown in FIG1 , the sub-pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. FIG1 also illustrates nodes N1, N2, N3, and N4.

[0078] Exemplarily, each transistor included in the sub-pixel driving circuit may be a low temperature polysilicon (English: Low Temperature Poly-Silicon, abbreviated: LTPS) transistor, but is not limited thereto.

[0079] The gate of the first transistor T1 is coupled to the corresponding reset signal line RST, the first electrode of the first transistor T1 is coupled to the first initialization signal transmission layer Vinit1, and the second electrode of the first transistor T1 is coupled to the gate of the third transistor T3.

[0080] A gate of the second transistor T2 is coupled to the corresponding second scan line GA2 , a first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3 , and a second electrode of the second transistor T2 is coupled to the gate of the third transistor T3 .

[0081] A gate of the fourth transistor T4 is coupled to the corresponding first scan line GA1 , a first electrode of the fourth transistor T4 is coupled to the corresponding data line DA, and a second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3 .

[0082] A gate of the fifth transistor T5 is coupled to the corresponding first light emitting control signal line EM1 , a first electrode of the fifth transistor T5 is coupled to the corresponding power line VDD, and a second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor T3 .

[0083] The gate of the sixth transistor T6 is coupled to the corresponding second light emitting control signal line EM2 , the first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3 , and the second electrode of the sixth transistor T6 is coupled to the anode of the light emitting element.

[0084] The gate of the seventh transistor T7 is coupled to the corresponding first scan line GA1, the first electrode of the seventh transistor T7 is coupled to the second initialization signal transmission layer Vinit2, and the second electrode of the seventh transistor T7 is coupled to the anode of the light-emitting element. The cathode layer serves as the cathode of the light-emitting element.

[0085] The first plate Cst1 of the storage capacitor Cst is coupled to the gate of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power line VDD. Exemplarily, the gate T3-g of the third transistor T3 is reused as the first plate Cst1.

[0086] As shown in FIG2 , the working process of the sub-pixel driving circuit is as follows:

[0087] In the P1 phase, the sixth transistor T6 is turned off, the fifth transistor T5 is kept on, and the high-level power signal transmitted by the power line VDD biases the third transistor T3 with a high voltage, thereby improving the hysteresis of the third transistor T3 (ie, the driving transistor).

[0088] In the P2 phase: the first transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal transmission layer Vinit1 initializes the gate of the third transistor T3 (ie, the N1 node).

[0089] In the P3 stage: the first transistor T1 is continuously turned on, the second transistor T2 is turned on, and the first initialization signal performs low-level initialization on the N1 node, the N2 node and the N3 node at the same time, so that before the data signal is written, the potential environment of the related nodes N1 node, the N2 node and the N3 node of the third transistor T3 is consistent, thereby improving the frequency switching flicker problem.

[0090] In the P4 phase: the second transistor T2 is continuously turned on, the fourth transistor T4 is turned on, a data signal is written into the data line DA, and the third transistor T3 performs threshold voltage Vth compensation.

[0091] In the P5 phase: the fourth transistor T4 is turned off, the second transistor T2 is continuously turned on, and the third transistor T3 continues to perform threshold voltage Vth compensation.

[0092] In the P6 phase: the sixth transistor T6 is turned on and the fifth transistor T5 is turned off. Before the light-emitting element emits light, the N2 node, the N3 node and the N4 node are turned on, so that the N2 node, the N3 node and the N4 node are connected and the voltage reaches a stable state before light emission.

[0093] In the P7 phase: the fifth transistor T5 is turned on, the sixth transistor T6 is continuously turned on, and the light-emitting element emits light.

[0094] Referring to Figures 1, 5, 9, and 10, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a power line VDD, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, and a plurality of sub-pixels, all disposed on the base substrate; the sub-pixels comprising a sub-pixel driving circuit and a light-emitting element; the sub-pixel driving circuit comprising a driving transistor (i.e., the third transistor T3), a power control transistor (i.e., the fifth transistor T5), and a light-emitting control transistor (i.e., the sixth transistor T6);

[0095] The gate T5-g of the power control transistor is coupled to the corresponding first light-emitting control signal line EM1, the first electrode of the power control transistor is coupled to the corresponding power line VDD, and the second electrode of the power control transistor is coupled to the first electrode of the driving transistor; the gate T6-g of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line EM2, the first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is coupled to the light-emitting element;

[0096] The first light-emitting control signal line EM1 includes at least a portion extending along a first direction, and the second light-emitting control signal line EM2 includes at least a portion extending along the first direction. The orthographic projection of the first light-emitting control signal line EM1 on the base substrate and the orthographic projection of the second light-emitting control signal line EM2 on the base substrate are arranged along a second direction, and the second direction intersects with the first direction.

[0097] Exemplarily, the display substrate includes a plurality of first light emitting control signal lines EM1 , the plurality of first light emitting control signal lines EM1 are arranged along the second direction, and the first light emitting control signal lines EM1 include at least a portion extending along the first direction.

[0098] Exemplarily, the display substrate includes a plurality of second light emitting control signal lines EM2 , the plurality of second light emitting control signal lines EM2 are arranged along the second direction, and the second light emitting control signal lines EM2 include at least a portion extending along the first direction.

[0099] Exemplarily, the display substrate further includes a plurality of shift register units (also called GOA units), and the first light emitting control signal line EM1 and the second light emitting control signal line EM2 coupled to the same row of sub-pixel driving circuits are driven by different GOA units respectively.

[0100] Exemplarily, an orthographic projection of the first light emitting control signal line EM1 on the base substrate does not overlap with an orthographic projection of the second light emitting control signal line EM2 on the base substrate.

[0101] As shown in FIG3 , the display substrate exemplarily includes a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarizing layer PLN1, a second source / drain metal layer SD2, a second planarizing layer PLN2, an anode layer ANO, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may further include, but is not limited to, a passivation layer PVX.

[0102] Exemplarily, the first light emitting control signal line EM1 and the gate T5-g of the power control transistor are arranged in different layers; and / or the second light emitting control signal line EM2 and the gate T6-g of the light emitting control transistor are arranged in different layers.

[0103] Exemplarily, the first emission control signal line EM1 and / or the second emission control signal line EM2 are provided in the same layer and material as the first source / drain metal layer. The gate T5-g of the power control transistor and the gate T6-g of the emission control transistor are provided in the same layer and material as the first gate metal layer. This arrangement helps reduce the layout difficulty of the display substrate and improves the resolution of the display substrate.

[0104] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, in the same sub-pixel driving circuit, the gate T5-g of the power control transistor is coupled to the corresponding first light-emitting control signal line EM1, and the gate T6-g of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line EM2. In this way, the power control transistor and the light-emitting control transistor can be independently controlled by the corresponding first light-emitting control signal line EM1 and the second light-emitting control signal line EM2, respectively. It is possible to independently control the power control transistor to turn on during the initialization phase (i.e., the above-mentioned phase P1). In this way, the power signal transmitted by the power line VDD can be transmitted to the first electrode of the driving transistor through the power control transistor, so that the driving transistor has a high voltage bias during the initialization phase, effectively improving the hysteresis of the driving transistor. At the same time, during the initialization phase (i.e., the above-mentioned phase P3), the power control transistor and the light-emitting control transistor are both controlled to be turned off, so that the gate T3-g, the first electrode, and the second electrode of the driving transistor are simultaneously initialized to a low level. Before the data signal is written, the potential environment of the gate T3-g, the first electrode, and the second electrode of the driving transistor is kept consistent, effectively improving the frequency switching flicker problem.

[0105] In a display substrate provided by an embodiment of the present disclosure, a plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array, the plurality of sub-pixel driving circuits being divided into a plurality of rows of sub-pixel driving circuits, the plurality of rows of sub-pixel driving circuits being arranged along the second direction, and each row of sub-pixel driving circuits including a plurality of sub-pixel driving circuits arranged along the first direction. A plurality of first light-emitting control signal lines EM1 are arranged along the second direction, and a plurality of second light-emitting control signal lines EM2 are arranged along the second direction. The orthographic projections of the first light-emitting control signal lines EM1 and the orthographic projections of the second light-emitting control signal lines EM2 on the substrate are alternately arranged along the second direction. The first light-emitting control signal lines EM1 include at least a portion extending along the first direction, and the second light-emitting control signal lines EM2 include at least a portion extending along the first direction.

[0106] This arrangement enables each power control transistor included in a row of sub-pixel drive circuits to be coupled to a corresponding first emission control signal line EM1, and each emission control transistor included in a row of sub-pixel drive circuits to be coupled to a corresponding second emission control signal line EM2. While enabling independent control of the power control transistors and emission control transistors, it also rationally manages the layout space of the display substrate, reducing the layout complexity of the display substrate while maintaining high resolution.

[0107] In the display substrate provided by the embodiment of the present disclosure, by setting the orthographic projection of the first light-emitting control signal line EM1 on the base substrate to not overlap with the orthographic projection of the second light-emitting control signal line EM2 on the base substrate, interference between the first light-emitting control signal transmitted by the first light-emitting control signal line EM1 and the second light-emitting control signal transmitted by the second light-emitting control signal line EM2 can be avoided, thereby ensuring stable transmission of the light-emitting control signals.

[0108] As shown in FIG4 , in some embodiments, the power control transistor includes a power control active layer 15 , and the light emission control transistor includes a light emission control active layer 16 . The power control active layer 15 and the light emission control active layer 16 are arranged along the first direction.

[0109] Exemplarily, the power control active layer 15 includes a power control channel portion, the orthographic projection of which on the substrate is covered by the orthographic projection of the gate T5-g of the power control transistor on the substrate. The light emission control active layer 16 includes a light emission control channel portion, the orthographic projection of which on the substrate is covered by the orthographic projection of the gate T6-g of the light emission control transistor on the substrate.

[0110] Exemplarily, the gate T5 - g of the power control transistor includes at least a portion extending along the first direction. The gate T6 - g of the light emission control transistor includes at least a portion extending along the first direction.

[0111] Exemplarily, at least a portion of the gate T5 - g of the power control transistor and at least a portion of the gate T6 - g of the light emission control transistor are arranged along the first direction.

[0112] Exemplarily, at least a portion of the power control channel portion and at least a portion of the light emission control channel portion are arranged along the first direction.

[0113] Exemplarily, in the layout area of ​​the same sub-pixel driving circuit, at least part of the orthographic projection of the first light-emitting control signal line EM1 on the substrate is located between the orthographic projection of the gate T3-g of the driving transistor on the substrate and the orthographic projection of the second light-emitting control signal line on the substrate.

[0114] Exemplarily, at least a portion of the orthographic projection of the gate T5-g of the power control transistor on the substrate, and / or at least a portion of the orthographic projection of the gate T6-g of the light emitting control transistor on the substrate, is located between the orthographic projection of the first light emitting control signal line EM1 on the substrate and the orthographic projection of the second light emitting control signal line on the substrate.

[0115] The above arrangement reasonably plans the layout space of the display substrate, is beneficial to improving the resolution of the display substrate, and reduces the difficulty of the layout of the display substrate.

[0116] As shown in FIG5 to FIG12, in some embodiments, the display substrate further includes a first scan line GA1 and a data line DA; the sub-pixel driving circuit includes a data writing transistor (i.e., a fourth transistor T4), wherein a gate of the data writing transistor is coupled to the corresponding first scan line GA1, a first electrode of the data writing transistor is coupled to the corresponding data line DA, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0117] In the layout area of ​​the same sub-pixel driving circuit, at least part of the orthographic projection of the first scanning line GA1 on the base substrate is located between the orthographic projection of the first light-emitting control signal line EM1 on the base substrate and the orthographic projection of the second light-emitting control signal line EM2 on the base substrate.

[0118] Exemplarily, an orthographic projection of the first scan line GA1 on the base substrate partially overlaps with an orthographic projection of the second light emitting control signal line EM2 on the base substrate.

[0119] Exemplarily, the second light-emission control signal line EM2 includes a second light-emission control main body portion and a second light-emission control protrusion coupled to each other. The second light-emission control main body portion includes at least a portion extending along the first direction, and the second light-emission control protrusion protrudes from the second light-emission control main body portion along the second direction. The second light-emission control protrusion is coupled to the gate electrode T6-g of the light-emission control transistor.

[0120] Exemplarily, the first light-emission control signal line EM1 includes a first light-emission control main portion and a first light-emission control protrusion coupled to each other. The first light-emission control main portion includes at least a portion extending along the first direction, and the first light-emission control protrusion protrudes from the first light-emission control main portion along the second direction. The first light-emission control protrusion is coupled to the gate electrode T5-g of the power control transistor.

[0121] Exemplarily, the first light emission control protrusion and the second light emission control protrusion are both located between the first light emission control body and the second light emission control body.

[0122] Exemplarily, an orthographic projection of the first scan line GA1 on the base substrate does not overlap with an orthographic projection of the first light emitting control signal line EM1 on the base substrate.

[0123] Exemplarily, the orthographic projection of the first scanning line GA1 on the base substrate does not overlap with the orthographic projection of the second light emitting control body on the base substrate.

[0124] Exemplarily, an orthographic projection of the first scan line GA1 on the base substrate partially overlaps with an orthographic projection of the second light emission control protrusion on the base substrate.

[0125] Exemplarily, the orthographic projection of the first scan line GA1 on the base substrate does not overlap with the orthographic projection of the first light-emitting control signal line EM1 on the base substrate; and / or, the orthographic projection of the first scan line GA1 on the base substrate does not overlap with the orthographic projection of the second light-emitting control signal line EM2 on the base substrate.

[0126] The above-mentioned setting method enables the orthographic projection of the first scanning line GA1 on the substrate to avoid overlapping with the orthographic projection of the first light-emitting control signal line EM1 on the substrate and the orthographic projection of the second light-emitting control signal line EM2 on the substrate as much as possible, and minimizes the overlapping area between the first scanning line GA1 and the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2. This not only reduces the loading of the first scanning line GA1, but also avoids poor display caused by crosstalk between signals, and avoids poor display split screen caused by multiple pulses of the first light-emitting control signal and the second light-emitting control signal.

[0127] As shown in FIG4 , in some embodiments, the data write transistor includes a data write active layer 14, the power control transistor includes a power control active layer 15, and the drive transistor includes a drive active layer 13; a first end of the data write active layer 14 (which may serve as the second electrode of the data write transistor, which may optionally be a drain), a first end of the power control active layer 15 (which may serve as the second electrode of the power control transistor, which may optionally be a drain), and a first end of the drive active layer 13 (which may serve as the first electrode of the drive transistor) are all coupled to form a second node portion J2 (i.e., corresponding to the second node N2);

[0128] At least a portion of the data writing active layer 14 and at least a portion of the power control active layer 15 are located on the same side of the driving active layer 13 along the second direction.

[0129] Exemplarily, the data write active layer 14 includes at least a portion extending along the second direction, and the data write active layer 14 is located on a side of the second node portion J2 away from the driving active layer 13. Exemplarily, the data write active layer 14 includes a channel portion located on a side of the second node portion J2 away from the driving active layer 13, and an orthographic projection of the channel portion on the base substrate overlaps with an orthographic projection of the first scan line GA1 on the base substrate.

[0130] Exemplarily, the orthographic projection of the data writing active layer 14 on the substrate at least partially overlaps with the orthographic projection of the second light-emitting control signal line EM2 on the substrate. This arrangement helps reduce the layout space occupied by the second light-emitting control signal line EM2 and improves the resolution of the display substrate.

[0131] Exemplarily, the sub-pixel driving circuit further includes a storage capacitor Cst, a first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-g of the driving transistor, and a second plate Cst2 of the storage capacitor Cst is coupled to the power line VDD;

[0132] As shown in Figures 5 to 7, the second electrode Cst2 includes a coupled electrode main body Cst21 and an electrode extension Cst22, the orthographic projection of the electrode main body Cst21 on the base substrate partially overlaps with the orthographic projection of the first electrode Cst1 on the base substrate, the orthographic projection of the electrode extension Cst22 on the base substrate does not overlap with the orthographic projection of the first electrode Cst1 on the base substrate; the orthographic projection of the electrode extension Cst22 on the base substrate at least partially overlaps with the orthographic projection of the second node portion J2 on the base substrate.

[0133] Illustratively, the electrode plate main portion Cst21 and the electrode plate extension portion Cst22 form an integral structure.

[0134] Exemplarily, the plate bodies Cst21 located in the same row along the first direction are coupled in sequence to form a plate structure extending along the first direction. The plate structure is connected to a power signal and can form a grid structure with the power line VDD.

[0135] The above setting method enables the second electrode of the data writing transistor and the second electrode of the power control transistor to be directly coupled to the first electrode of the driving transistor through the active layer without the need for other film layers for switching, which can effectively reduce the number of vias and optimize wiring space.

[0136] Moreover, the above-mentioned setting method makes the active layer routing corresponding to the second node portion J2 longer. In this way, by setting the positive projection of the electrode extension portion Cst22 on the base substrate to overlap with the positive projection of the second node portion J2 on the base substrate, the capacitance value between the N2 node and the second electrode plate Cst2 of the storage capacitor Cst can be optimized, so that the N2 node can be fully shielded by a stable power supply signal, which is beneficial to improving the grayscale Mura and afterimage performance of the low display substrate.

[0137] As shown in Figures 1 to 18, in some embodiments, the sub-pixel driving circuit also includes a first conductive connection portion 21, which is respectively coupled to the first electrode of the power control transistor, the plate extension portion Cst22 and the power line VDD; the orthographic projection of the first conductive connection portion 21 on the substrate does not overlap with the orthographic projection of the plate main portion Cst21 on the substrate.

[0138] Exemplarily, the first conductive connection portion 21 includes at least a portion extending along the first direction.

[0139] The above configuration enables electrical connection between the first electrode of the power control transistor, the plate extension Cst22 and the power line VDD via only one first conductive connection portion 21, which is beneficial for simplifying the circuit structure, improving the resolution of the display substrate, and reducing the resolution of the display substrate.

[0140] As shown in Figures 6 and 11, in some embodiments, the orthographic projection of the electrode extension portion Cst22 on the base substrate partially overlaps with the orthographic projection of the first light-emitting control signal line EM1 on the base substrate, and does not overlap with the orthographic projection of the second light-emitting control signal line EM2 on the base substrate.

[0141] The above configuration allows the second light-emitting control signal line EM2 to avoid overlapping with the structure transmitting the power signal as much as possible.

[0142] As shown in Figure 16, in some embodiments, the power line VDD includes at least a portion extending along the second direction; the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the first light-emitting control signal line EM1 on the base substrate have a first overlapping area, and the orthographic projection of the power line VDD on the base substrate and the orthographic projection of the second light-emitting control signal line EM2 on the base substrate have a second overlapping area; the length L1 of the first overlapping area along the first direction is greater than the length L2 of the second overlapping area along the first direction.

[0143] Exemplarily, the length of the second overlapping region along the first direction may be between 2 micrometers and 5 micrometers, including end values, but not limited thereto.

[0144] Exemplarily, the orthographic projection of the power line VDD on the base substrate has a third overlapping area with the orthographic projection of the second scan line GA2 on the base substrate, and the length of the third overlapping area along the first direction is greater than the length of the second overlapping area along the first direction.

[0145] The above configuration allows the power line VDD to be narrowed in the second overlapping region, so that the second light-emitting control signal line EM2 can minimize the overlapping area with the structure transmitting the power signal.

[0146] As shown in Figures 7, 9, 11, 12, 14 and 17, in some embodiments, the display substrate further includes a first initialization signal transmission layer Vinit1, the first initialization signal transmission layer Vinit1 includes a plurality of first initialization transmission parts Vinit11 and a plurality of second initialization transmission parts Vinit12, and an extension direction of the first initialization transmission parts Vinit11 intersects with an extension direction of the second initialization transmission parts Vinit12;

[0147] At least part of the sub-pixel driving circuit also includes a first reset transistor (i.e., a first transistor T1) and a second conductive connection part 22, wherein the second conductive connection part 22 is respectively coupled to the first electrode of the first reset transistor, the corresponding first initialization transmission part Vinit11 and the corresponding second initialization transmission part Vinit12; the second electrode of the first reset transistor is coupled to the gate T3-g of the driving transistor.

[0148] Exemplarily, the first initialization signal transmission layer Vinit1 is used to transmit a first initialization signal. The first initialization signal transmission layer Vinit1 is formed into a grid structure.

[0149] Exemplarily, the multiple first initialization transmission parts Vinit11 are arranged in sequence along the second direction, the first initialization transmission part Vinit11 includes at least a portion extending along the first direction, and the first initialization transmission part Vinit11 is set in the same layer and material as the second gate metal layer.

[0150] Exemplarily, the multiple second initialization transmission parts Vinit12 are arranged in sequence along the first direction, the second initialization transmission part Vinit12 includes at least a portion extending along the second direction, and the second initialization transmission part Vinit12 is set in the same layer and material as the second source and drain metal layer.

[0151] Exemplarily, a gate of the first reset transistor is coupled to a corresponding reset signal line RST.

[0152] The above configuration is beneficial to reducing the resistance of the first initialization signal transmission layer Vinit1, reducing the loading of the first initialization signal transmission layer Vinit1, and improving the uniformity of the first initialization signal transmitted by the first initialization signal transmission layer Vinit1.

[0153] As shown in Figures 7, 9, 11, 12, 14 and 17, in some embodiments, the display substrate further includes a second initialization signal transmission layer Vinit2, the second initialization signal transmission layer Vinit2 includes a plurality of third initialization transmission parts Vinit21 and a plurality of fourth initialization transmission parts Vinit22, and an extension direction of the third initialization transmission parts Vinit21 intersects with an extension direction of the fourth initialization transmission parts Vinit22;

[0154] At least part of the sub-pixel driving circuit also includes a second reset transistor (i.e., a seventh transistor T7) and an eighth conductive connection part, and the eighth conductive connection part is coupled to the first electrode of the second reset transistor, the corresponding third initialization transmission part Vinit21 and the corresponding fourth initialization transmission part Vinit22 respectively; the second electrode of the second reset transistor is coupled to the light-emitting element.

[0155] Exemplarily, the second initialization signal transmission layer Vinit2 is used to transmit a second initialization signal. The second initialization signal transmission layer Vinit2 is formed into a grid structure.

[0156] Exemplarily, the plurality of third initialization transmission portions Vinit21 are sequentially arranged along the second direction, the third initialization transmission portion Vinit21 includes at least a portion extending along the first direction, and the third initialization transmission portion Vinit21 is provided in the same layer and material as the second gate metal layer.

[0157] Exemplarily, the plurality of fourth initialization transmission portions Vinit22 are sequentially arranged along the first direction, the fourth initialization transmission portion Vinit22 includes at least a portion extending along the second direction, and the fourth initialization transmission portion Vinit22 is provided in the same layer and material as the second source / drain metal layer.

[0158] Exemplarily, the gate of the second reset transistor is coupled to the corresponding first scan line GA1. The second reset transistor T7 and the data write transistor T4 in the same sub-pixel driver circuit share the same first scan line GA1. This configuration helps reduce the complexity of the display substrate and improve the resolution of the display substrate.

[0159] The above configuration is beneficial to reducing the resistance of the second initialization signal transmission layer Vinit2, reducing the loading of the second initialization signal transmission layer Vinit2, and improving the uniformity of the second initialization signal transmitted by the second initialization signal transmission layer Vinit2.

[0160] As shown in Figures 9 and 11 to 18, in some embodiments, the display substrate further includes a cathode layer and a plurality of first cathode compensation lines VSS1, the first cathode compensation lines VSS1 include at least a portion extending along the second direction, and the plurality of first cathode compensation lines VSS1 are respectively coupled to the cathode layer.

[0161] Exemplarily, the plurality of first cathode compensation lines VSS1 are arranged along the first direction, the first cathode compensation line VSS1 includes at least a portion extending along the second direction, and the first cathode compensation line VSS1 and the second source / drain metal layer are provided in the same layer and material.

[0162] Exemplarily, the display substrate includes a display area and a peripheral area located around the display area, and the cathode layer can extend from the display area to the peripheral area. In the peripheral area, the first cathode compensation line VSS1 is coupled to the cathode layer through a switching pattern, and the switching pattern can be set in the same layer and material as the anode layer in the display substrate, but is not limited to this.

[0163] The above configuration is beneficial to reducing the resistance of the cathode layer, reducing the loading of the cathode layer, and improving the uniformity of the cathode signal.

[0164] As shown in Figures 7 to 18, in some embodiments, the first initialization transmission part Vinit11 and the third initialization transmission part Vinit21 are alternately arranged along the second direction; and / or, the second initialization transmission part Vinit12 and the fourth initialization transmission part Vinit22 are alternately arranged along the first direction; and / or, at least part of the first cathode compensation line VSS1 is located between the adjacent second initialization transmission part Vinit12 and the fourth initialization transmission part Vinit22.

[0165] Exemplarily, the second initialization transfer part Vinit12 , the first cathode compensation line VSS1 , the fourth initialization transfer part Vinit22 , and the first cathode compensation line VSS1 are sequentially and cyclically arranged along the first direction.

[0166] Exemplarily, the second initialization transmission part Vinit12 , the first cathode compensation line VSS1 , and the fourth initialization transmission part Vinit22 are all provided in the same layer and with the same material as the second source / drain metal layer.

[0167] Exemplarily, each column of sub-pixel driving circuits corresponds to only one of the second initialization transmission part Vinit12 , the first cathode compensation line VSS1 , and the fourth initialization transmission part Vinit22 , but is not limited thereto.

[0168] More specifically, among four adjacent columns of sub-pixel driver circuits, the layout area of ​​the first column of sub-pixel driver circuits includes the second initialization transfer portion Vinit12, the layout area of ​​the second column of sub-pixel driver circuits includes the first cathode compensation line VSS1, the layout area of ​​the third column of sub-pixel driver circuits includes the fourth initialization transfer portion Vinit22, and the layout area of ​​the fourth column of sub-pixel driver circuits includes the first cathode compensation line VSS1. In this case, the sub-pixel driver circuits in the first column of sub-pixel driver circuits include the second conductive connection portion 22, and the sub-pixel driver circuits in the third column of sub-pixel driver circuits include the eighth conductive connection portion.

[0169] It is worth noting that the wiring density of the second initialization transfer part Vinit12 , the first cathode compensation line VSS1 , and the fourth initialization transfer part Vinit22 can be flexibly adjusted.

[0170] As shown in FIG16 , in some embodiments, the display substrate includes a plurality of power lines VDD and a plurality of data lines DA;

[0171] The second initialization transmission part Vinit12 is located between the adjacent power line VDD and the data line DA; and / or the fourth initialization transmission part Vinit22 is located between the adjacent power line VDD and the data line DA; and / or the first cathode compensation line VSS1 is located between the adjacent power line VDD and the data line DA;

[0172] The adjacent power line VDD and the data line DA are coupled to the same sub-pixel driving circuit.

[0173] Exemplarily, the plurality of power lines VDD are arranged along the first direction, the plurality of data lines DA are arranged along the first direction, and the power lines VDD and the data lines DA are both provided in the same layer and material as the second source / drain metal layer. The power lines VDD and the data lines DA are alternately arranged along the first direction.

[0174] Exemplarily, in the layout area of ​​a column of sub-pixel driving circuits, the second initialization transmission part Vinit12 is located between the power line VDD and the data line DA; or, the fourth initialization transmission part Vinit22 is located between the power line VDD and the data line DA; or, the first cathode compensation line VSS1 is located between the power line VDD and the data line DA.

[0175] The above-mentioned setting method enables a second initialization transmission part Vinit12, a fourth initialization transmission part Vinit22 or a first cathode compensation line VSS1 to be provided between the data line DA and the power line VDD coupled to the same sub-pixel driving circuit, so that the data line DA and the power line VDD coupled to the same sub-pixel driving circuit can be separated by the second initialization transmission part Vinit12, the fourth initialization transmission part Vinit22 or the first cathode compensation line VSS1, thereby reducing the risk of crosstalk between the data line DA and the power line VDD.

[0176] As shown in Figure 16, in some embodiments, the display substrate further includes a plurality of second cathode compensation lines VSS2 arranged along the second direction, the second cathode compensation line VSS2 includes at least a portion extending along the first direction, and the second cathode compensation line VSS2 is coupled to the first cathode compensation line VSS1.

[0177] Exemplarily, the second cathode compensation line VSS2 is provided in the same layer and with the same material as the first source / drain metal layer.

[0178] The above configuration enables the first cathode compensation line VSS1 and the second cathode compensation line VSS2 to form a grid structure, further reducing the loading of the cathode layer, improving the uniformity of the cathode signal, and effectively improving the heating problem of the display substrate under high-brightness display.

[0179] As shown in Figure 16, in some embodiments, the display substrate further includes a plurality of power compensation lines VDD1, the power compensation line VDD1 includes at least a portion extending along the first direction, and the power compensation line VDD1 is coupled to the power line VDD; the power compensation line VDD1 and the second cathode compensation line VSS2 are alternately arranged along the second direction.

[0180] Exemplarily, the plurality of power compensation lines VDD1 are arranged along the second direction, and the power compensation lines VDD1 are provided in the same layer and with the same material as the first source / drain metal layer.

[0181] Exemplarily, one of the power compensation line VDD1 and the second cathode compensation line VSS2 is arranged in the layout area of ​​the odd-numbered row sub-pixel driving circuit, and the other one of the power compensation line VDD1 and the second cathode compensation line VSS2 is arranged in the layout area of ​​the even-numbered row sub-pixel driving circuit.

[0182] The above-mentioned setting couples the power compensation line VDD1 with the power line VDD, so that the power compensation line VDD1 and the power line VDD together form a grid structure, which is beneficial to reducing the loading of the power line VDD, improving the uniformity of the power signal, and effectively improving the heating problem of the display substrate under high-brightness display.

[0183] Moreover, the second plate Cst2 of the storage capacitor Cst in the display substrate is coupled to the power line VDD and receives the power signal. The second plates Cst2 located in the same row along the first direction are coupled in sequence. The connection method of the second plate Cst2, the power compensation line VDD1 and the power line VDD further reduces the loading of the power line VDD and improves the uniformity of the power signal.

[0184] The power compensation lines VDD1 and the second cathode compensation lines VSS2 are alternately arranged along the second direction, which reasonably utilizes the layout space of the display substrate and reduces the layout difficulty of the display substrate.

[0185] As shown in Figures 19 to 22, in some embodiments, the display substrate only includes a second cathode compensation line VSS2, and does not include a power compensation line VDD1. Each row of sub-pixel driving circuits corresponds to a second cathode compensation line VSS2, and the second cathode compensation line VSS2 is located in the layout area of ​​the corresponding row of sub-pixel driving circuits.

[0186] The above setting method can effectively reduce the cathode layer electrode, improve the cathode layer Drop, and effectively reduce the display power consumption of the display substrate displaying G255 grayscale under normal display, and can also reduce the power consumption of the display panel under high-brightness HBM display state.

[0187] As shown in Figures 4 to 7, in some embodiments, the first reset transistor (i.e., the first transistor T1) includes a first reset active layer 11, the first reset active layer 11 includes two first channel portions 110, and first conductive portions 111 respectively coupled to the two first channel portions 110; the orthographic projection of the first conductive portion 111 on the base substrate at least partially overlaps with the orthographic projection of the third initialization transmission portion Vinit21 on the base substrate.

[0188] Exemplarily, the first reset transistor includes a dual-gate transistor.

[0189] Exemplarily, the two first channel portions 110 and the first conductive portion 111 are formed together into an n-type structure, but the present invention is not limited thereto.

[0190] Illustratively, an orthographic projection of the first conductive portion 111 on the substrate at least partially overlaps an orthographic projection of the third initialization transfer portion Vinit21 on the substrate. The third initialization transfer portion Vinit21 is located in a layout area of ​​a sub-pixel driver circuit adjacent to the sub-pixel driver circuit to which the first conductive portion 111 belongs along the second direction.

[0191] The above-mentioned setting method enables the first conductive part 111 included in the first reset transistor to be covered by the third initialization transmission part Vinit21, so that the third initialization transmission part Vinit21 can shield the first conductive part 111, thereby ensuring the stability of the first conductive part 111 and thus ensuring the working stability of the first reset transistor.

[0192] As shown in FIG4 to FIG7, in some embodiments, the sub-pixel driving circuit further includes a compensation transistor (i.e., a second transistor T2), a first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate T3-g of the driving transistor;

[0193] The compensation transistor includes a compensation active layer 12, which includes two second channel portions 120 and second conductive portions 121 respectively coupled to the two second channel portions 120; the orthographic projection of the second conductive portion 121 on the substrate at least partially overlaps with the orthographic projection of the first initialization transmission portion Vinit11 on the substrate.

[0194] Exemplarily, the compensation transistor comprises a dual-gate transistor.

[0195] Exemplarily, the gate of the compensation transistor is coupled to the corresponding second scan line GA2. The compensation transistor can be independently controlled by the second scan line GA2, which is beneficial for fully compensating the threshold voltage of the driving transistor and improving the low grayscale display quality of the display substrate.

[0196] Exemplarily, the two second channel portions 120 and the second conductive portion 121 are formed together into an L-shaped structure, but the present invention is not limited thereto.

[0197] Exemplarily, the orthographic projection of the second conductive portion 121 on the substrate at least partially overlaps with the orthographic projection of the first initialization transmission portion Vinit11 on the substrate. The first initialization portion is coupled to the sub-pixel driving circuit to which the second conductive portion 121 belongs.

[0198] The above-mentioned setting method enables the second conductive part 121 included in the compensation transistor to be covered by the first initialization transmission part Vinit11, so that the first initialization transmission part Vinit11 can shield the second conductive part 121, thereby ensuring the stability of the second conductive part 121 and thus ensuring the working stability of the compensation transistor.

[0199] As shown in FIG16 , in some embodiments, the sub-pixel driving circuit further includes a fourth conductive connection portion 24, which is respectively coupled to the gate electrode T3-g of the driving transistor, the second electrode of the compensation transistor, and the second electrode of the first reset transistor. The orthographic projection of the fourth conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the power line VDD on the substrate. This arrangement effectively shields the potential of the fourth conductive connection portion (corresponding to the potential of the N1 node) from interference.

[0200] Exemplarily, an orthographic projection of the fourth conductive connection portion on the base substrate is completely covered by an orthographic projection of the power line VDD on the base substrate.

[0201] Exemplarily, the orthographic projection of the second initialization transmission portion Vinit12 on the base substrate is located between the orthographic projection of the fourth conductive connection portion on the base substrate and the orthographic projection of the data line DA on the base substrate.

[0202] Illustratively, the orthographic projection of the fourth initialization transmission portion Vinit22 on the base substrate is located between the orthographic projection of the fourth conductive connection portion on the base substrate and the orthographic projection of the data line DA on the base substrate.

[0203] Exemplarily, the orthographic projection of the first cathode compensation line VSS1 on the base substrate is located between the orthographic projection of the fourth conductive connection portion on the base substrate and the orthographic projection of the data line DA on the base substrate.

[0204] More specifically, as shown in FIG4 , the figure schematically illustrates a first reset active layer 11 included in the first reset transistor, a compensation active layer 12 included in the compensation transistor, a drive active layer 13 included in the drive transistor, a data write active layer 14 included in the data write transistor, a power control active layer 15 included in the power control transistor, a light emission control active layer 16 included in the light emission control transistor, and a second reset active layer 17 included in the second reset transistor.

[0205] As shown in FIG. 9 , the first conductive connection portion 21 to the eighth conductive connection portion 28 are illustrated.

[0206] As shown in Figures 4 to 18, the first conductive connection portion 21 is coupled to the first electrode of the power control transistor through the tenth via Via10, the first conductive connection portion 21 is coupled to the electrode extension portion Cst22 through the eleventh via Via11, and the first conductive connection portion 21 is coupled to the power line VDD through the thirteenth via Via13.

[0207] The second conductive connection part 22 is coupled to the first electrode of the first reset transistor through the fourth via Via4, the second conductive connection part 22 is coupled to the corresponding first initialization transmission part Vinit11 through the third via Via3, and the second conductive connection part 22 is coupled to the corresponding second initialization transmission part Vinit12 through the fifteenth via Via15.

[0208] The third conductive connection portion 23 is coupled to the first electrode of the second reset transistor through a first via Via1 and is coupled to the corresponding third initialization transmission portion Vinit21 through a second via Via2.

[0209] The fourth conductive connection portion 24 is coupled to the gate T3 - g of the driving transistor through a sixth via Via6 , and the fourth conductive connection portion 24 is coupled to the second electrode of the compensation transistor and the second electrode of the first reset transistor through a fifth via Via5 .

[0210] The fifth conductive connection portion 25 is coupled to the second electrode of the light emitting control transistor through the ninth via Via9, coupled to the ninth conductive connection portion 29 through the twelfth via Via12, and coupled to the anode of the light emitting element through the nineteenth via Via19.

[0211] The sixth conductive connection portion 26 is coupled to the first electrode of the data writing transistor through the twentieth via hole Via20 and is coupled to the data line DA through the fourteenth via hole Via14.

[0212] The seventh conductive connection portion 27 is coupled to the first electrode of the first reset transistor through the fourth via Via4 , and the seventh conductive connection portion 27 is coupled to the corresponding first initialization transmission portion Vinit11 through the third via Via3 .

[0213] The eighth conductive connection portion 28 is coupled to the first electrode of the second reset transistor through a first via Via1, coupled to the corresponding third initialization transmission portion Vinit21 through a second via Via2, and coupled to the corresponding fourth initialization transmission portion Vinit22 through an eighteenth via Via18.

[0214] The first light emitting control signal line EM1 is coupled to the gate of the power control transistor through the seventh via hole Via7 , and the second light emitting control signal line EM2 is coupled to the gate of the light emitting control transistor through the eighth via hole Via8 .

[0215] The first cathode compensation line VSS1 is coupled to the second cathode compensation line VSS2 through the sixteenth via hole Via16 .

[0216] The power line VDD is coupled to the power compensation line VDD1 through the seventeenth via Via17.

[0217] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0218] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, or a tablet computer, wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.

[0219] In the display substrate provided in the above embodiment, the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array, the plurality of sub-pixel driving circuits being divided into a plurality of rows of sub-pixel driving circuits, the plurality of rows of sub-pixel driving circuits being arranged along the second direction, and each row of sub-pixel driving circuits including a plurality of sub-pixel driving circuits arranged along the first direction. A plurality of first light-emitting control signal lines are arranged along the second direction, and a plurality of second light-emitting control signal lines are arranged along the second direction. The orthographic projections of the first light-emitting control signal lines on the substrate alternate with the orthographic projections of the second light-emitting control signal lines on the substrate along the second direction. The first light-emitting control signal lines include at least a portion extending along the first direction, and the second light-emitting control signal lines include at least a portion extending along the first direction.

[0220] This arrangement enables each power control transistor included in a row of sub-pixel drive circuits to be coupled to a corresponding first light-emission control signal line, and each emission control transistor included in a row of sub-pixel drive circuits to be coupled to a corresponding second light-emission control signal line. While enabling independent control of the power control transistors and emission control transistors, it also rationally manages the layout space of the display substrate, reducing the layout complexity of the display substrate while maintaining high resolution.

[0221] In the display substrate provided by the above embodiment, by setting the orthographic projection of the first light-emitting control signal line on the base substrate to not overlap with the orthographic projection of the second light-emitting control signal line on the base substrate, interference between the first light-emitting control signal transmitted by the first light-emitting control signal line and the second light-emitting control signal transmitted by the second light-emitting control signal line can be avoided, thereby ensuring stable transmission of the light-emitting control signal.

[0222] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0223] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0224] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0225] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0226] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0227] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0228] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0229] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0230] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a power line, a first light-emitting control signal line, a second light-emitting control signal line and a plurality of sub-pixels all arranged on the base substrate; The sub-pixel comprises a sub-pixel driving circuit and a light-emitting element, wherein the sub-pixel driving circuit comprises a driving transistor, a power control transistor and a light-emitting control transistor; The gate of the power control transistor is coupled to the corresponding first light-emitting control signal line, the first electrode of the power control transistor is coupled to the corresponding power line, and the second electrode of the power control transistor is coupled to the first electrode of the driving transistor; the gate of the light-emitting control transistor is coupled to the corresponding second light-emitting control signal line, the first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, and the second electrode of the light-emitting control transistor is coupled to the light-emitting element; The first light-emitting control signal line includes at least a portion extending along a first direction, the second light-emitting control signal line includes at least a portion extending along the first direction, the orthographic projection of the first light-emitting control signal line on the base substrate and the orthographic projection of the second light-emitting control signal line on the base substrate are arranged along a second direction, and the second direction intersects with the first direction.

2. The display substrate according to claim 1, wherein: The power control transistor includes a power control active layer, the light emission control transistor includes a light emission control active layer, and the power control active layer and the light emission control active layer are arranged along the first direction.

3. The display substrate according to claim 2, wherein: In the layout area of ​​the same sub-pixel driving circuit, at least part of the orthographic projection of the first light-emitting control signal line on the base substrate is located between the orthographic projection of the gate of the driving transistor on the base substrate and the orthographic projection of the second light-emitting control signal line on the base substrate.

4. The display substrate according to claim 2, wherein: At least a portion of the orthographic projection of the gate of the power control transistor on the substrate, and / or at least a portion of the orthographic projection of the gate of the light emitting control transistor on the substrate, is located between the orthographic projection of the first light emitting control signal line on the substrate and the orthographic projection of the second light emitting control signal line on the substrate.

5. The display substrate according to claim 1, wherein: The display substrate further includes a first scan line and a data line; the sub-pixel driving circuit includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding first scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; In the layout area of ​​the same sub-pixel driving circuit, at least part of the orthographic projection of the first scanning line on the substrate is located between the orthographic projection of the first light-emitting control signal line on the substrate and the orthographic projection of the second light-emitting control signal line on the substrate.

6. The display substrate according to claim 5, wherein: The orthographic projection of the first scan line on the base substrate does not overlap with the orthographic projection of the first light-emitting control signal line on the base substrate; and / or the orthographic projection of the first scan line on the base substrate does not overlap with the orthographic projection of the second light-emitting control signal line on the base substrate.

7. The display substrate according to claim 5, wherein: The data writing transistor includes a data writing active layer, the power control transistor includes a power control active layer, and the driving transistor includes a driving active layer; a first end of the data writing active layer, a first end of the power control active layer, and a first end of the driving active layer are coupled to form a second node portion; At least a portion of the data writing active layer and at least a portion of the power control active layer are located at the same side of the driving active layer along the second direction.

8. The display substrate according to claim 7, wherein: The sub-pixel driving circuit further comprises a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the power line; The second electrode plate comprises a electrode plate main body and an electrode plate extension portion coupled to each other, the orthographic projection of the electrode plate main body on the substrate overlaps with the orthographic projection of the first electrode plate on the substrate, and the orthographic projection of the electrode plate extension portion on the substrate does not overlap with the orthographic projection of the first electrode plate on the substrate; An orthographic projection of the electrode plate extension portion on the base substrate at least partially overlaps with an orthographic projection of the second node portion on the base substrate.

9. The display substrate according to claim 8, wherein: The orthographic projection of the plate extension portion on the base substrate overlaps with the orthographic projection of the first light-emitting control signal line on the base substrate, and does not overlap with the orthographic projection of the second light-emitting control signal line on the base substrate.

10. The display substrate according to claim 8, wherein: The sub-pixel driving circuit also includes a first conductive connection portion, which is respectively coupled to the first electrode of the power control transistor, the electrode plate extension portion and the power line; the orthographic projection of the first conductive connection portion on the substrate does not overlap with the orthographic projection of the electrode plate main body on the substrate.

11. The display substrate according to claim 1, wherein: The power line includes at least a portion extending along a second direction; the orthographic projection of the power line on the base substrate and the orthographic projection of the first light-emitting control signal line on the base substrate have a first overlapping area, and the orthographic projection of the power line on the base substrate and the orthographic projection of the second light-emitting control signal line on the base substrate have a second overlapping area; A length of the first overlapping region along the first direction is greater than a length of the second overlapping region along the first direction.

12. The display substrate according to claim 1, wherein: The first light emitting control signal line and the gate of the power supply control transistor are arranged in different layers; and / or the second light emitting control signal line and the gate of the light emitting control transistor are arranged in different layers.

13. The display substrate according to claim 11, wherein: The display substrate further includes a first source-drain metal layer, and the first light-emitting control signal line and / or the second light-emitting control signal line are provided in the same layer and with the same material as the first source-drain metal layer.

14. The display substrate according to claim 1, wherein: The display substrate further includes a first initialization signal transmission layer, the first initialization signal transmission layer includes a plurality of first initialization transmission parts and a plurality of second initialization transmission parts, and an extension direction of the first initialization transmission parts intersects with an extension direction of the second initialization transmission parts; At least part of the sub-pixel driving circuit also includes a first reset transistor and a second conductive connection part, the second conductive connection part is respectively coupled to the first electrode of the first reset transistor, the corresponding first initialization transmission part and the corresponding second initialization transmission part; the second electrode of the first reset transistor is coupled to the gate of the driving transistor.

15. The display substrate according to claim 14, wherein: The display substrate further includes a second initialization signal transmission layer, the second initialization signal transmission layer includes a plurality of third initialization transmission parts and a plurality of fourth initialization transmission parts, and an extension direction of the third initialization transmission parts intersects with an extension direction of the fourth initialization transmission parts; At least part of the sub-pixel driving circuit further includes a second reset transistor and an eighth conductive connection The eighth conductive connection part is respectively coupled to the first electrode of the second reset transistor, the corresponding third initialization transmission part and the corresponding fourth initialization transmission part; the second electrode of the second reset transistor is coupled to the light emitting element.

16. The display substrate according to claim 15, wherein: The display substrate further includes a cathode layer and a plurality of first cathode compensation lines, the first cathode compensation lines including at least a portion extending along a second direction, the plurality of first cathode compensation lines being respectively coupled to the cathode layer.

17. The display substrate according to claim 16, wherein: The first initialization transmission parts and the third initialization transmission parts are alternately arranged along the second direction; and / or, The second initialization transmission parts and the fourth initialization transmission parts are alternately arranged along the first direction; and / or, At least a portion of the first cathode compensation line is located between the adjacent second initialization transfer portion and the fourth initialization transfer portion.

18. The display substrate according to claim 17, wherein: The display substrate includes a plurality of power lines and a plurality of data lines; The second initialization transmission part is located between the adjacent power line and the data line; and / or, the fourth initialization transmission part is located between the adjacent power line and the data line; and / or, the first cathode compensation line is located between the adjacent power line and the data line; The adjacent power lines and data lines are coupled to the same sub-pixel driving circuit.

19. The display substrate according to claim 16, wherein: The display substrate further includes a plurality of second cathode compensation lines arranged along the second direction, the second cathode compensation lines including at least a portion extending along the first direction, and the second cathode compensation lines are coupled to the first cathode compensation lines.

20. The display substrate according to claim 19, wherein: The display substrate further comprises a plurality of power compensation lines, the power compensation lines comprising at least a portion extending along the first direction, the power compensation lines being coupled to the power lines; the power compensation lines and the second cathode compensation lines being alternately arranged along the second direction.

21. The display substrate according to claim 15, wherein: The first reset transistor includes a first reset active layer, the first reset active layer includes two first channel portions, and first conductive portions respectively coupled to the two first channel portions; An orthographic projection of the first conductive portion on the base substrate at least partially overlaps with an orthographic projection of the third initialization transfer portion on the base substrate.

22. The display substrate according to claim 14, wherein: The sub-pixel driving circuit further includes a compensation transistor, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and a second electrode of the compensation transistor is coupled to a gate of the driving transistor; The compensation transistor comprises a compensation active layer, wherein the compensation active layer comprises two second channel portions and second conductive portions respectively coupled to the two second channel portions; An orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first initialization transfer portion on the base substrate.

23. A display device comprising the display substrate according to any one of claims 1 to 22.

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