Polar code encoding method and apparatus

Abstract

A polar code encoding method and apparatus, which relate to the technical field of communications, and enable information bit sequences of different sizes to construct polar codes on the basis of the same reliability sequence and the same first matrix, thereby reducing the hardware complexity and improving the decoding performance. The method comprises: on the basis of a reliability sequence having a length of N, mapping an information bit sequence having a length of k onto k bits of a first sequence having a length of N, so as to obtain a second sequence comprising k information bits, x PC bits and N-k-x frozen bits; multiplying the second sequence by a first matrix, so as to obtain a third sequence; and performing polarization encoding, so as to obtain a fourth sequence, wherein k≤K≤N; 1≤x; K is the maximum value of the length of the information bit sequence; k, K, N and x are all positive integers; the elements below the diagonals of the first matrix are all 0; the elements on the diagonals are all 1; the column weight of a column in the first matrix which corresponds to the PC bits is greater than 1; the column weight of a column corresponding to the frozen bits or the information bits is equal to 1; and the number of columns having a column weight greater than 1 is less than or equal to N-K.

Description

Polar code encoding method and device Technical Field The embodiments of the present application relate to the field of communication technology, and in particular to a method and device for encoding a polarization code. Background Art In a communication system, in order to reduce coding complexity, a coding scheme based on parity check polar codes (PC-Polar codes) is proposed. Among them, the PC-Polar code may include information bits, frozen bits, PC bits and rate matching shortening bits. The information bits are used to carry information bits, the frozen bits are used to carry frozen bits, and the PC bits are used to carry PC bits. The PC bits are determined according to the information bits. The value of the PC bits can be determined by the PC equation according to the value of the information bit located in front of the PC bit. The rate matching shortening bits do not need to be sent to the channel. For information bit sequences with different numbers, the positions of the information bits are different, which will result in different PC bits and PC equations. That is, the corresponding PC bits and PC equations need to be stored separately for information bit sequences with different numbers, which has high hardware complexity and high hardware overhead. Summary of the invention The present application provides a polar code encoding method and device, which can enable different numbers of information bit sequences to construct polar codes based on the same reliability sequence and a first matrix, which can reduce hardware complexity, reduce hardware overhead, improve code spectrum characteristics, reduce decoding complexity, and improve decoding performance. In a first aspect, an embodiment of the present application provides a polarization code encoding method, and the execution subject of the method can be a transmitting device, or a chip, a chip system, or a system on chip of the transmitting device. The method includes: the transmitting device maps an information bit sequence of length k to k bits of a first sequence of length N according to a reliability sequence to obtain a second sequence, multiplying the second sequence by a first matrix to obtain a third sequence, and polarization encoding the third sequence to obtain a fourth sequence. Among them, the length of the reliability sequence is N, the second sequence includes k information bits, x parity check PC bits, and Nkx frozen bits, k≤K≤N, 1≤x, K is the maximum length of the information bit sequence, k, K, N, x are all positive integers; the first matrix is ​​a matrix with all 0s below the diagonal and all 1s on the diagonal, the column weight of the column corresponding to the PC bit in the first matrix is ​​greater than 1, the column weight of the column corresponding to the frozen bit or the information bit is equal to 1, and the number of columns with column weight greater than 1 in the first matrix is ​​less than or equal to NK. Based on the first aspect, the embodiment of the present application provides a polarization code encoding scheme based on nested PC, which can construct a reliability sequence of length N with nested characteristics for the information bit sequence separately, so as to reduce the number of performance bad points, improve the code spectrum characteristics, and improve the decoding performance when the holes are punched sequentially from back to front. At the same time, the information bit sequences of different numbers in the embodiment of the present application can construct polarization codes based on the same first matrix, that is, the first matrix has a nested characteristic for information bit sequences of different numbers, and the first matrix does not change with the number of information bit sequences, or it can also be described as the PC bits and PC equations corresponding to the information bit sequences of different numbers are nested. The transmitting end device can save the same first matrix for information bit sequences of different lengths, and does not need to store the corresponding PC bits and PC equations separately for information bit sequences of different lengths, thereby reducing hardware complexity, reducing hardware overhead, improving code spectrum characteristics, reducing decoding complexity, and improving decoding performance. In one possible design, the second sequence is multiplied by the first matrix to obtain a third sequence, including: determining one or more PC bits and PC bit check bits based on the first matrix; determining the value of the PC bit in the second sequence based on the value of the PC bit check bit to obtain the third sequence. Based on this possible design, when the second sequence is processed according to the first matrix, one or more PC bits of the second sequence can be determined according to the columns in the first matrix whose column weights are greater than 1, and then the values ​​of each PC bit in the second sequence can be determined according to the bits of each PC bit check. For example, the XOR result of the values ​​of the bits of the PC bit check can be used as the value of the PC bit, which provides a feasible solution for obtaining a third sequence by processing the second sequence according to the first matrix. In one possible design, the reliability sequence is determined based on one or more of the following: reliability, code spectrum, and performance optimization results. Based on this possible design, a reliability sequence with a length of N can be constructed separately for the information bit sequence based on parameters such as reliability, code spectrum, and performance optimization results. When the encoded sequence is subsequently punctured from back to front, the number of performance bad points can be reduced, the code spectrum characteristics can be improved, and the decoding performance can be improved. In one possible design, the column weight of the first matrix is ​​less than or equal to the first value. Based on this possible design, the column weight of the first matrix may be less than or equal to the first value, thereby ensuring the sparsity of the first matrix and obtaining better code spectrum characteristics. In one possible design, the first matrix is: In one possible design, the first matrix is: Based on the above two possible designs, multiple feasible solutions are provided for the design of the first matrix. In one possible design, the third sequence includes one or more PC bits, and the difference between the number of the PC bits and the number of the bits of the PC bit check is a prime number. Based on this possible design, by limiting the difference between the number of the PC bit and the number of the bit of the PC bit check to a prime number, the search space can be greatly reduced, and while improving the code spectrum characteristics, the optimality can be lost as little as possible. In one possible design, the PC bits of the third sequence are one or more of the following bit positions of the third sequence: 16, 18, 21, or 25. In one possible design, when the PC bit is the 16th bit in the third sequence, the bit checked by the PC bit is the 13th bit in the third sequence; or, when the PC bit is the 18th bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 11, 13, 15; or, when the PC bit is the 21st bit in the third sequence, the bit checked by the PC bit is the 14th bit in the third sequence; or, when the PC bit is the 25th bit in the third sequence, the bit checked by the PC bit is the 22nd bit in the third sequence. Based on the above two possible designs, a better example is provided for the PC bit and the bit of the PC bit check, which can greatly reduce the search space, obtain better code spectrum characteristics, and at the same time lose as little optimality as possible, reduce decoding complexity, and improve decoding performance. In one possible design, the PC bits of the third sequence are one or more of the following bit positions of the third sequence: 19, 21, 25, or 26. In one possible design, when the PC bit is the 19th bit in the third sequence, the bit checked by the PC bit is the 14th bit in the third sequence; or, when the PC bit is the 21st bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 11, 14; or, when the PC bit is the 25th bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 14, 22; or, when the PC bit is the 26th bit in the third sequence, the bit checked by the PC bit is the 13th bit in the third sequence. Based on the above two possible designs, another better example is provided for the PC bit and the bit of the PC bit check, which can greatly reduce the search space, obtain better code spectrum characteristics, and at the same time lose as little optimality as possible, reduce decoding complexity, and improve decoding performance. In one possible design, the method further includes: interleaving the fourth sequence according to the first interleaving pattern to obtain a fifth sequence; and rate matching the fifth sequence to obtain a first rate matching sequence. Based on this possible design, the first interleaving pattern can be an interleaving pattern determined according to sequence performance and nesting characteristics, so that there is no need to store interleaving patterns separately for different numbers of information bit sequences, which can reduce hardware complexity and hardware overhead. At the same time, since the first interleaving pattern is determined according to sequence performance, it can ensure that the rate matching performance has no bad points (such as 1-bit fine-grained rate matching performance has no bad points), thereby improving decoding performance. In one possible design, the first interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the fifth sequence; wherein the mapping relationship between A and B is: (5, 31), (26, 30), (11, 29), (9, 28), (28, 27), (7, 26), (30, 25), (16, 24), (31, 23), (21, 22), (10, 21), (24, 20), (27, 19), (6, 18), (3, 17), (12, 16), (17, 15), (8, 14), (13, 13), (0, 12), (2, 11), (1, 10), (4, 9), (14, 8), (25, 7), (23, 6), (22, 5), (19, 4). In one possible design, the first interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the fifth sequence; wherein the mapping relationship between A and B is: (4, 31), (22, 30), (27, 29), (17, 28), (8, 27), (2, 26), (15, 25), (21, 24), (29, 23), (23, 22), (6, 21), (26, 20), (20, 19), (7, 18), (0, 17), (13, 16), (19, 15), (11, 14), (14, 13), (16, 12), (25, 11), (3, 10), (10, 9), (5, 8), (12, 7), (1, 6), (18, 5), (24, 4). Based on the above two possible designs, two better examples are provided for the first interleaving pattern, which can ensure the rate matching performance without bad points while having the nesting characteristics, thereby improving the decoding performance. In one possible design, the method further includes: interleaving the fourth sequence according to a second interleaving pattern to obtain a sixth sequence; and rate matching the sixth sequence to obtain a second rate matching sequence. Based on this possible design, different from the first interleaving pattern with nested characteristics in the first possible design mentioned above, corresponding second interleaving patterns can also be designed separately for different numbers of information bit sequences, that is, different numbers of information bit sequences can correspond to different second interleaving patterns, so as to better fit different numbers of information bit sequences, ensure rate matching performance without bad points, and improve decoding performance. In a possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (12, 31), (9, 30), (19, 29), (18, 28), (1, 27), (15, 26), (14, 25), (29, 24), (16, 23), (10, 22), (28, 21), (23, 20), (20, 19), (6, 18), (21, 17), (7, 16), (2, 15), (25, 14), (0, 13), (3, 12), (5, 11), (31, 10), (30, 9), (4, 8), (22, 7), (13, 6), (27, 5), (8, 4). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (18, 31), (29, 30), (9, 29), (12, 28), (27, 27), (22, 26), (23, 25), (26, 24), (4, 23), (0, 22), (7, 21), (14, 20), (8, 19), (19, 18), (1, 17), (21, 16), (13, 15), (11, 14), (17, 13), (20, 12), (16, 11), (15, 10), (6, 9), (10, 8), (28, 7), (25, 6), (24, 5). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (2, 31), (20, 30), (12, 29), (25, 28), (8, 27), (22, 26), (16, 25), (5, 24), (29, 23), (14, 22), (23, 21), (15, 20), (3, 19), (11, 18), (10, 17), (17, 16), (0, 15), (30, 14), (18, 13), (27, 12), (4, 11), (19, 10), (21, 9), (6, 8), (26, 7), (9, 6). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (19, 31), (23, 30), (16, 29), (18, 28), (29, 27), (0, 26), (21, 25), (8, 24), (11, 23), (4, 22), (13, 21), (2, 20), (20, 19), (24, 18), (25, 17), (6, 16), (28, 15), (14, 14), (10, 13), (9, 12), (31, 11), (26, 10), (7, 9), (17, 8), (1, 7). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (7, 31), (9, 30), (19, 29), (26, 28), (31, 27), (21, 26), (27, 25), (2, 24), (23, 23), (17, 22), (10, 21), (30, 20), (25, 19), (24, 18), (0, 17), (16, 16), (4, 15), (11, 14), (20, 13), (12, 12), (29, 11), (18, 10), (13, 9), (3, 8). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (15, 31), (16, 30), (9, 29), (14, 28), (17, 27), (24, 26), (21, 25), (20, 24), (5, 23), (1, 22), (7, 21), (30, 20), (11, 19), (6, 18), (2, 17), (3, 16), (8, 15), (22, 14), (12, 13), (23, 12), (19, 11), (10, 10), (29, 9). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (17, 31), (21, 30), (15, 29), (14, 28), (4, 27), (24, 26), (8, 25), (29, 24), (19, 23), (16, 22), (7, 21), (2, 20), (9, 19), (25, 18), (26, 17), (23, 16), (28, 15), (30, 14), (13, 13), (6, 12), (22, 11), (0, 10). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (28, 31), (29, 30), (14, 29), (26, 28), (8, 27), (23, 26), (24, 25), (30, 24), (0, 23), (31, 22), (10, 21), (5, 20), (20, 19), (4, 18), (16, 17), (12, 16), (9, 15), (21, 14), (1, 13), (11, 12), (22, 11). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (22, 31), (19, 30), (28, 29), (9, 28), (4, 27), (6, 26), (14, 25), (11, 24), (3, 23), (13, 22), (0, 21), (15, 20), (26, 19), (24, 18), (27, 17), (18, 16), (21, 15), (17, 14), (20, 13), (12, 12). Based on the above nine possible designs, a possible second interleaving pattern is provided for k equal to 3 to 11, that is, corresponding second interleaving patterns are designed separately for information bit sequences with different numbers, so as to ensure that the rate matching performance has no bad points and improve the decoding performance. In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (5, 31), (11, 30), (24, 29), (30, 28), (13, 27), (20, 26), (22, 25), (3, 24), (4, 23), (25, 22), (31, 21), (6, 20), (10, 19), (8, 18), (21, 17), (15, 16), (9, 15), (2, 14), (0, 13), (27, 12), (14, 11), (16, 10), (17, 9), (23, 8), (28, 7), (26, 6), (1, 5), (7, 4). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (16, 31), (28, 30), (10, 29), (30, 28), (19, 27), (7, 26), (13, 25), (9, 24), (11, 23), (6, 22), (8, 21), (26, 20), (21, 19), (20, 18), (23, 17), (25, 16), (0, 15), (17, 14), (27, 13), (22, 12), (18, 11), (15, 10), (5, 9), (12, 8), (2, 7), (29, 6), (24, 5). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (9, 31), (19, 30), (11, 29), (12, 28), (21, 27), (0, 26), (29, 25), (2, 24), (4, 23), (31, 22), (10, 21), (1, 20), (22, 19), (7, 18), (24, 17), (30, 16), (20, 15), (3, 14), (28, 13), (13, 12), (14, 11), (8, 10), (6, 9), (5, 8), (17, 7), (18, 6). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (11, 31), (25, 30), (31, 29), (27, 28), (14, 27), (0, 26), (22, 25), (19, 24), (18, 23), (3, 22), (20, 21), (2, 20), (4, 19), (17, 18), (23, 17), (24, 16), (12, 15), (1, 14), (7, 13), (10, 12), (28, 11), (26, 10), (6, 9), (5, 8), (8, 7). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (7, 31), (12, 30), (2, 29), (5, 28), (26, 27), (6, 26), (27, 25), (24, 24), (4, 23), (19, 22), (1, 21), (29, 20), (9, 19), (8, 18), (13, 17), (11, 16), (28, 15), (10, 14), (25, 13), (16, 12), (30, 11), (0, 10), (21, 9), (3, 8). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (7, 31), (30, 30), (17, 29), (16, 28), (19, 27), (6, 26), (29, 25), (18, 24), (10, 23), (3, 22), (24, 21), (9, 20), (21, 19), (28, 18), (31, 17), (12, 16), (23, 15), (2, 14), (15, 13), (4, 12), (27, 11), (20, 10), (25, 9). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (28, 31), (25, 30), (17, 29), (6, 28), (11, 27), (21, 26), (27, 25), (30, 24), (3, 23), (1, 22), (4, 21), (8, 20), (15, 19), (26, 18), (29, 17), (18, 16), (9, 15), (19, 14), (2, 13), (20, 12), (23, 11), (10, 10). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (23, 31), (30, 30), (3, 29), (28, 28), (14, 27), (19, 26), (9, 25), (16, 24), (29, 23), (13, 22), (26, 21), (12, 20), (18, 19), (0, 18), (15, 17), (4, 16), (20, 15), (1, 14), (25, 13), (31, 12), (21, 11). In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (1, 31), (24, 30), (14, 29), (15, 28), (25, 27), (12, 26), (26, 25), (13, 24), (27, 23), (31, 22), (8, 21), (5, 20), (20, 19), (21, 18), (3, 17), (28, 16), (17, 15), (6, 14), (19, 13), (11, 12). Based on the above nine possible designs, another possible second interleaving pattern is provided for k equal to 3 to 11, that is, corresponding second interleaving patterns are designed separately for information bit sequences with different numbers, so as to ensure the rate matching performance without bad points and improve the decoding performance. In the second aspect, the embodiment of the present application provides a communication device, which can be applied to the transmitting device of the first aspect to implement the functions performed by the transmitting device. The communication device can be a transmitting device, or a chip or chip system or system on chip of the transmitting device, etc. The communication device can perform the functions performed by the transmitting device through hardware, or can perform the corresponding software implementation through hardware. The hardware or software includes one or more modules corresponding to the above functions. For example, a transceiver module and a processing module. The transceiver module can independently complete the following transceiver operations, or cooperate with the processing module to complete the following transceiver operations; accordingly, the processing module can also independently complete the following processing operations, or cooperate with the transceiver module to complete the following processing operations, without limitation. The processing module is used to map the information bit sequence of length k to k bits of the first sequence of length N according to the reliability sequence to obtain a second sequence, and is also used to multiply the second sequence by the first matrix to obtain a third sequence, and polarization encode the third sequence to obtain a fourth sequence. The length of the reliability sequence is N, the second sequence includes k information bits, x parity check PC bits and Nkx frozen bits, k≤K≤N, 1≤x, K is the maximum length of the information bit sequence, k, K, N, x are all positive integers; the first matrix is ​​a matrix with all 0s below the diagonal and all 1s on the diagonal, the column weight of the column corresponding to the PC bit in the first matrix is ​​greater than 1, the column weight of the column corresponding to the frozen bit or the information bit is equal to 1, and the number of columns with column weight greater than 1 in the first matrix is ​​less than or equal to NK. In one possible design, the processing module is specifically used to determine one or more PC bits and PC bit check bits according to the first matrix, and determine the value of the PC bit in the second sequence according to the value of the PC bit check bit to obtain a third sequence. In one possible design, the reliability sequence is determined based on one or more of the following: reliability, code spectrum, and performance optimization results. In one possible design, the column weight of the first matrix is ​​less than or equal to the first value. In one possible design, the third sequence includes one or more PC bits, and the difference between the number of the PC bits and the number of the bits of the PC bit check is a prime number. In one possible design, the PC bits of the third sequence are one or more of the following bit positions of the third sequence: 16, 18, 21, or 25. In one possible design, when the PC bit is the 16th bit in the third sequence, the bit checked by the PC bit is the 13th bit in the third sequence; or, when the PC bit is the 18th bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 11, 13, 15; or, when the PC bit is the 21st bit in the third sequence, the bit checked by the PC bit is the 14th bit in the third sequence; or, when the PC bit is the 25th bit in the third sequence, the bit checked by the PC bit is the 22nd bit in the third sequence. In one possible design, the PC bits of the third sequence are one or more of the following bit positions of the third sequence: 19, 21, 25, or 26. In one possible design, when the PC bit is the 19th bit in the third sequence, the bit checked by the PC bit is the 14th bit in the third sequence; or, when the PC bit is the 21st bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 11, 14; or, when the PC bit is the 25th bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 14, 22; or, when the PC bit is the 26th bit in the third sequence, the bit checked by the PC bit is the 13th bit in the third sequence. In one possible design, the first matrix is: In one possible design, the first matrix is: In one possible design, the processing module is further used to interleave the fourth sequence according to the first interleaving pattern to obtain a fifth sequence, and perform rate matching on the fifth sequence to obtain a first rate matching sequence. In one possible design, the first interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the fifth sequence; wherein the mapping relationship between A and B is: (5, 31), (26, 30), (11, 29), (9, 28), (28, 27), (7, 26), (30, 25), (16, 24), (31, 23), (21, 22), (10, 21), (24, 20), (27, 19), (6, 18), (3, 17), (12, 16), (17, 15), (8, 14), (13, 13), (0, 12), (2, 11), (1, 10), (4, 9), (14, 8), (25, 7), (23, 6), (22, 5), (19, 4). In one possible design, the first interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the fifth sequence; wherein the mapping relationship between A and B is: (4, 31), (22, 30), (27, 29), (17, 28), (8, 27), (2, 26), (15, 25), (21, 24), (29, 23), (23, 22), (6, 21), (26, 20), (20, 19), (7, 18), (0, 17), (13, 16), (19, 15), (11, 14), (14, 13), (16, 12), (25, 11), (3, 10), (10, 9), (5, 8), (12, 7), (1, 6), (18, 5), (24, 4). In one possible design, the processing module is further used to interleave the fourth sequence according to the second interleaving pattern to obtain a sixth sequence; and perform rate matching on the sixth sequence to obtain a second rate matching sequence. In one possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (12, 31), (9, 30), (19, 29), (18, 28), (1, 27), (15, 26), (14, 25), (29, 24), (16, 23), (10, 22), (28, 21), (23, 20), (20, 19), (6, 18), (21, 17), (7, 16), (2, 15), (25, 14), (0, 13), (3, 12), (5, 11), (31, 10), (30, 9), (4, 8), (22, 7), (13, 6), (27, 5), (8, 4); or wherein the mapping relationship between A and B is: The series are: (18, 31), (29, 30), (9, 29), (12, 28), (27, 27), (22, 26), (23, 25), (26, 24), (4, 23), (0, 22), (7, 21), (14, 20), (8, 19), (19, 18), (1, 17), (21, 16), (13, 15), (11, 14), (17 , 13), (20, 12), (16, 11), (15, 10), (6, 9), (10, 8), (28, 7), (25, 6), (24, 5); or, the mapping relationship between A and B is: (2, 31), (20, 30), (12, 29), (25, 28), (8, 27), (22, 26), (16, 25), (5, 24), (29, 23), (14, 22), (23, 21), (15, 20), (3, 19), (11, 18), (10, 17), (17, 16), (0, 15), (30, 14), (18, 13), (27, 12), (4, 11), (19, 10), (21, 9), (6, 8), (26, 7), (9, 6); or, the mapping relationship between A and B is: (19, 31), (23, 30), (16, 29), (18, 28), (29, 27), (0, 26), (21, 25), (8, 24), (11, 23), (4, 22), (13, 21), (2, 20), (20, 19), (24, 18), (25, 17), (6, 16), (28, 15), (14, 14), (10, 13), (9, 12), (31, 11), (26, 10), (7, 9), (17, 8), (1, 7); or, the mapping relationship between A and B is: (7, 31), (9, 30), (19, 29), (26, 28), (31, 27), (21, 26), (27, 25), (2, 24), (23, 23), (17, 22), (10, 21), (30, 20), (25, 19), (24 , 18), (0, 17), (16, 16), (4, 15), (11, 14), (20, 13), (12, 12), (29, 11), (18, 10), (13, 9), (3, 8); or, the mapping relationship between A and B is: (15, 31), (16, 30), (9, 29), (14, 28), (17, 27), (24, 26), (21, 25), (20, 24), (5, 23), (1, 22), (7, 21), (30, 20), (11, 19), (6, 18), (2, 17), (3, 16), (8, 15), (22, 14), (12, 13), (23, 12), (19, 11), (10, 10), (29, 9); or, the mapping relationship between A and B is: (17, 31), (21, 30), (15, 29), (14, 28), (4, 27), (24, 26), (8, 25), (29, 24), (19, 23), (16, 22), (7, 21), (2, 20), (9, 19), (25, 18), (26, 17), (23, 16), (28, 15), (30, 14), (13, 13), (6, 12), (22, 11), (0, 10);Or, the mapping relationship between A and B is: (28, 31), (29, 30), (14, 29), (26, 28), (8, 27), (23, 26), (24, 25), (30, 24), (0, 23), (31, 22), (10, 21), (5, 20), (20, 19), (4, 18), (16, 17), (12, 16), (9, 15), (21, 14), (1, 13), (11, 12), (22, 11); or, the mapping relationship between A and B is: (22, 31), (19, 30), (28, 29), (9, 28), (4, 27), (6, 26), (14, 25), (11, 24), (3, 23), (13, 22), (0, 21), (15, 20), (26, 19), (24, 18), (27, 17), (18, 16), (21, 15), (17, 14), (20, 13), (12, 12). ; In a possible design, the second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; wherein the mapping relationship between A and B is: (5, 31), (11, 30), (24, 29), (30, 28), (13, 27), (20, 26), (22, 25), (3, 24), (4, 23), (25, 22), (31, 21), (6, 20), (10, 19), (8, 18), (21, 17), (15, 16), (9, 15), (2, 14), (0, 13), (27, 12), (14, 11), ( 16, 10), (17, 9), (23, 8), (28, 7), (26, 6), (1, 5), (7, 4); or, the mapping relationship between A and B is: (16, 31), (28, 30), (10, 29), (30, 28), (19, 27), (7, 26), (13, 25), (9, 24), (11, 23), (6, 22), (8, 21), (26, 20), (21, 19), (20, 18), (23, 17), (25, 16), (0, 15), (17, 14), (27, 13), (22, 12), (18, 11), ( 15, 10), (5, 9), (12, 8), (2, 7), (29, 6), (24, 5); or, the mapping relationship between A and B is: (9, 31), (19, 30), (11, 29), (12, 28), (21, 27), (0, 26), (29, 25), (2, 24), (4, 23), (31, 22), (10, 21), (1, 20), (22, 19), (7, 18), (24, 17), (30, 16), (20, 15), (3, 14), (28, 13), (13, 12), (14, 11), (8, 10), (6, 9), (5, 8), (17, 7), (18, 6); or, the mapping relationship between A and B is: (11, 31), (25, 30), (31, 29), (27, 28), (14, 27), (0, 26), (22, 25), (19, 24), (18, 23), (3, 22), (20, 21), (2, 20), (4, 19), (17, 18), (23, 17), (24, 16), (12, 15), (1, 14), (7, 13), (10, 12), (28, 11), (26, 10), (6, 9), (5, 8), (8, 7);Or, the mapping relationship between A and B is: (7, 31), (12, 30), (2, 29), (5, 28), (26, 27), (6, 26), (27, 25), (24, 24), (4, 23), (19, 22), (1, 21), (29, 20), (9, 19), (8, 18), (13, 17), (11, 16), (28, 15), (10, 14), (25, 13), (16, 12), (30, 11), (0, 10), (21, 9), (3, 8); Or, the mapping relationship between A and B is: (7, 31), (30, 30), (17, 29), (16, 28), (19, 27), (6, 26), (29, 25), (18, 24), (10, 23) , (3, 22), (24, 21), (9, 20), (21, 19), (28, 18), (31, 17), (12, 16), (23, 15), (2, 14), (15, 13), (4, 12), (27, 11), (20, 10), (25, 9); or, the mapping relationship between A and B is: (28, 31), (25, 30), ( 17, 29), (6, 28), (11, 27), (21, 26), (27, 25), (30, 24), (3, 23), (1, 22), (4, 21), (8, 20), (15, 19), (26, 18), (29, 17), (18, 16), (9, 15), (19, 14), (2, 13), (20, 12), (23,; 11), (10, 10); or, wherein the mapping relationship between A and B is: (23, 31), (30, 30), (3, 29), (28, 28), (14, 27), (19, 26), (9, 25), (16, 24), (29, 23), (13, 22), (26, 21), (12, 20), (18, 19), (0, 18), (15, 17), (4, 16), (20, 15), (1, 14), (25, 13), (31, 12 ), (21, 11); or, the mapping relationship between A and B is: (1, 31), (24, 30), (14, 29), (15, 28), (25, 27), (12, 26), (26, 25), (13, 24), (27, 23), (31, 22), (8, 21), (5, 20), (20, 19), (21, 18), (3, 17), (28, 16), (17, 15), (6, 14), (19, 13), (11, 12). Among them, the technical effects brought about by the above-mentioned second aspect or any possible design in the second aspect can refer to the technical effects brought about by the above-mentioned first aspect or any possible design in the first aspect, and will not be repeated here. In a third aspect, an embodiment of the present application provides a communication device, wherein the communication device includes one or more processors; the one or more processors are used to run a computer program or instruction, and when the one or more processors execute the computer instruction or instruction, the communication device performs the encoding method of the polar code as described in the first aspect or any possible design of the first aspect. In one possible design, the communication device further includes one or more memories, one or more memories are coupled to one or more processors, and the one or more memories are used to store the above-mentioned computer programs or instructions. In one possible implementation, the memory is located outside the communication device. In another possible implementation, the memory is located inside the communication device. In an embodiment of the present application, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together. In one possible implementation, the communication device further includes a transceiver, and the transceiver is used to receive information and / or send information. In one possible design, the communication device also includes one or more communication interfaces, the one or more communication interfaces are coupled to the one or more processors, and the one or more communication interfaces are used to communicate with other modules outside the communication device. In a fourth aspect, an embodiment of the present application provides a communication device, comprising an input / output interface and a logic circuit; the input / output interface is used to input and / or output information; the logic circuit is used to execute the polar code encoding method described in the first aspect or any possible design of the first aspect, and process and / or generate information according to the information. In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer instruction or a program. When the computer instruction or the program is executed on a computer, the polar code encoding method described in the first aspect or any possible design of the first aspect is executed. In a sixth aspect, an embodiment of the present application provides a computer program product comprising computer instructions, which, when executed on a computer, enables the polar code encoding method described in the first aspect or any possible design of the first aspect to be executed. In a seventh aspect, an embodiment of the present application provides a computer program, which, when executed on a computer, enables the polar code encoding method described in the first aspect or any possible design of the first aspect to be executed. In an eighth aspect, an embodiment of the present application provides a chip, including: a processor, the processor being coupled to a memory, the memory being used to store a program or an instruction, and when the program or the instruction is executed by the processor, the chip executes the polar code encoding method described in the first aspect or any possible design of the first aspect. Among them, the technical effects brought about by any design method in the third to eighth aspects can refer to the technical effects brought about by the above-mentioned first aspect or any possible design in the first aspect, and will not be repeated here. In a ninth aspect, an embodiment of the present application provides a communication system, which may include a communication device as described in the second aspect or any possible design of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS FIG1 is a schematic diagram of a decoding process of an LTE-RM code provided in an embodiment of the present application; FIG2 is a schematic diagram of a PC-Polar code provided in an embodiment of the present application; FIG3 is a schematic diagram showing a comparison of decoding complexity of an LTE-RM code and a PC-Polar code provided in an embodiment of the present application; FIG4 is a schematic diagram of a communication system provided in an embodiment of the present application; FIG5 is a schematic diagram of encoding and decoding performed by a transmitting end device and a receiving end device provided in an embodiment of the present application; FIG6 is a schematic diagram of the composition of a communication device provided in an embodiment of the present application; FIG7 is a flow chart of a polar code encoding method provided in an embodiment of the present application; FIG8 is a schematic diagram of a first matrix provided in an embodiment of the present application; FIG9 is a schematic diagram of a first matrix provided in an embodiment of the present application; FIG10 is a schematic diagram of a search process for a first interlaced pattern provided in an embodiment of the present application; FIG11 is a schematic diagram of a first interlaced pattern provided in an embodiment of the present application; FIG12 is a schematic diagram of a first interlaced pattern provided in an embodiment of the present application; FIG13 is a schematic diagram of a second interlaced pattern provided in an embodiment of the present application; FIG14 is a schematic diagram of a second interlaced pattern provided in an embodiment of the present application; FIG15 is a schematic diagram of a performance comparison provided in an embodiment of the present application; FIG16 is a schematic diagram of a performance comparison provided in an embodiment of the present application; FIG17 is a schematic diagram of a performance comparison provided in an embodiment of the present application; FIG18 is a schematic diagram of a performance comparison provided in an embodiment of the present application; FIG19 is a schematic diagram of a performance comparison provided in an embodiment of the present application; FIG20 is a schematic diagram of a communication device provided in an embodiment of the present application; FIG21 is a diagram showing the structure of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION Before describing the embodiments of the present application, the technical terms involved in the embodiments of the present application are described. Long term evolution-reed-muller (LTE-RM) coding: The transmitting device can encode the ultra-short information bit sequence of 3 to 11 bits in the following way: Step 1: For the information bit sequence c0, c1, ..., c with a length of K K-1 Encode to obtain the encoded sequence d0, d1, ..., d with a length of N N-1 . Exemplarily, K may be any value between 3 and 11, and N may be 32. in, M i,k The value of can be determined according to the following Table 1, i = 0, 1, 2, ..., N-1. Table 1 Step 2: Encode the sequence d0, d1, ..., d of length N. N-1 Perform rate matching to obtain a rate matching sequence f0, f1, ..., f with a length of E. E-1 . Wherein, E is the actual transmission code length after rate matching, or described as E is the transmission code length after rate matching. The transmission code length E can be determined according to the rate matching related information. When it is determined that the transmission code length E is not equal to the coding length N (such as E is not equal to 32), the following rate matching method can be adopted: when the transmission code length E is less than N (such as E is less than 32), puncture from back to front; when the transmission code length E is greater than N (such as E is greater than 32), repeat from front to back. For example, the rate matching sequence f0, f1, ..., f E-1 You can obtain it by following the following method: for j=0to E-1 f j =d jmodN ; end for Step 3: Send rate matching sequence f0, f1, ..., f E-1 . LTE-RM decoding: The receiving end device may decode the encoding result of the ultra short information bit sequence of 3 to 11 bits in the following manner with reference to the decoding process diagram shown in FIG. 1: Step 1: Perform a simple decision (such as a hard decision) on the received sequence, and perform interleaving processing on the codeword (such as a bipolar codeword) or soft bit information after the simple decision to obtain a processed received codeword. The received sequence may be the above-mentioned rate matching sequence. Optionally, if the length of the codeword after simple judgment is not equal to N, high-order zero-adding processing can be performed. For example, if the codeword after simple judgment is b0, b1, ..., b with a length of 20 19 , 12 zeros can be added to the high bits to obtain a code word of length N = 32 0, ..., 0, b0, b1, ..., b 19 . Step 2: Interleave the received codeword processed in step 1 according to the mask vector. The interleaving process is the same as the interleaving process in step 1 above. Exemplarily, 128 mask vectors may be generated according to 7 basic mask sequences, and the 128 mask vectors are respectively multiplied with the received codeword processed in step 1 (ie, demasking is performed), to obtain 128 bipolar sequences of length 32. Step 3: Perform fast Hadamard transform (FHT) on the bipolar sequence obtained in step 2 and the 32-order Hadamard matrix to obtain a 128×32 correlation value matrix. Step 4: Find the number with the maximum absolute value from the correlation value matrix obtained in step 3, so that the binary form corresponding to the row number of this number with the maximum absolute value is the 2nd to 6th bits of the information bit sequence, and the binary form corresponding to the column number is the 7th to 13th bits of the information bit sequence. Step 5: The first bit of the information bit sequence is determined according to the actual sign of the number with the largest absolute value, that is, when it is positive, it is translated as 0; when it is negative, it is translated as 1. Among them, the 1st bit to the 12th bit in the above steps 4 and 5 define the information bit sequence starting from the 1st bit. It can be understood that the information bit sequence can also be defined starting from the 0th bit, that is, the above 1st bit, 2nd bit, ..., 12th bit are replaced by the 0th bit, 1st bit, ..., 11th bit respectively without limitation. However, the above LTE-RM decoding adopts FHT. When the length of the information bit sequence is greater than 6 bits, it is necessary to enumerate the mask vector and perform demasking, which results in a high complexity and high power consumption for the LTE-RM decoding scheme to achieve maximum likelihood (ML) decoding performance. In addition, when the length E of the rate matching sequence is small, the number of puncturing is large, and performance defects will occur, affecting the decoding performance. Parity check polar codes (PC-Polar codes): PC-Polar codes may include information bits, frozen bits, PC bits, and rate matching shortened bits. Information bits may be used to carry information bits, frozen bits may be used to carry frozen bits, PC bits may be used to carry PC bits, and rate matching shortened bits do not need to be sent to the channel. Among them, a part of the set can be selected from the frozen bits as PC bits, and the values ​​of the PC bits on these PC bits are different from those of other frozen bits. The PC bit is not fixed to 0, but is determined by the PC equation based on the value of the information bit in front of the PC bit. Therefore, the PC bit can also be called a dynamic frozen bit (that is, the position comes from the frozen bit, but the value is not fixed to 0). Exemplarily, taking the length of the information bit sequence as 7 as an example, the PC-Polar code corresponding to the information bit sequence may be the PC-Polar code shown in FIG. 2 , wherein the frozen bits may be the 0th, 1st, 2nd, 4th, and 8th bits, the information bits may be the 3rd, 5th, 6th, 10th, 11th, 13th, and 14th bits, the PC bits may be the 9th and 12th bits, and the rate matching shortening bits may be the 7th and 15th bits. Among them, the value of the PC bit at the 9th bit position can be: the XOR of the value of the information bit at the 3rd bit position and the value of the information bit at the 6th bit position, and the value of the PC bit at the 12th bit position can be: the XOR of the value of the information bit at the 3rd bit position and the value of the information bit at the 5th bit position. Based on the above description, compared with the LTE-RM encoding and decoding scheme, using PC-Polar code for encoding and decoding can reduce decoding complexity, reduce power consumption, and improve decoding performance. Exemplarily, as shown in FIG3 , it can be seen that, for different code rates, the decoding complexity of the PC-Polar code is less than the decoding complexity of the LTE-RM code. However, in PC-Polar codes, for information bit sequences of different lengths (or described as different numbers of information bits), the positions of the information bits are different, which will lead to different PC bits and PC equations (for example, the PC bits corresponding to an information bit sequence of length 4 may not be PC bits in an information bit sequence of length 3, and the corresponding PC equations are also inconsistent), resulting in the need to separately store the corresponding PC bits and PC equations for information bit sequences of different lengths, which results in high hardware complexity and high hardware overhead. In order to solve the technical problem, an embodiment of the present application provides a polarization code encoding method, in which a transmitting end device can map an information bit sequence of length k to k bits of a first sequence of length N according to a reliability sequence to obtain a second sequence, multiply the second sequence by the first matrix to obtain a third sequence, and polarization encode the third sequence to obtain a fourth sequence. Wherein, the length of the reliability sequence is N, the second sequence includes k information bits, x parity check PC bits and Nkx frozen bits, k≤K≤N, 1≤x, K is the maximum value of the length of the information bit sequence, k, K, N, x are all positive integers, the first matrix is ​​a matrix with all 0s below the diagonal and all 1s on the diagonal, the column weight of the column corresponding to the PC bit in the first matrix is ​​greater than 1, the column weight of the column corresponding to the frozen bit or the information bit is equal to 1, and the number of columns with column weight greater than 1 in the first matrix is ​​less than or equal to NK. In the embodiment of the present application, a reliability sequence with a length of N can be separately constructed for the information bit sequence, so that when puncturing sequentially from back to front, the number of performance bad points is reduced, the code spectrum characteristics are improved, and the decoding performance is improved. At the same time, different numbers of information bit sequences in the embodiment of the present application can construct polarization codes based on the same first matrix, that is, the PC bits and PC equations corresponding to different numbers of information bit sequences are nested, and there is no need to separately store the corresponding PC bits and PC equations for information bit sequences of different lengths, thereby reducing hardware complexity, reducing hardware overhead, improving code spectrum characteristics, reducing decoding complexity, and improving decoding performance. The implementation of the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. The polar code encoding method provided in the embodiment of the present application can be used in any communication system, and the communication system can be a third generation partnership project (3GPP) communication system, for example, a long term evolution (LTE) system, and can also be a fifth generation (5G) mobile communication system, a system of LTE and 5G hybrid networking, a new radio (NR) system, an NR vehicle to everything (V2X) system, a device-to-device (D2D) communication system, a machine to machine (M2M) communication system, an Internet of Things (IoT), a narrowband Internet of Things system (NB-IoT), a global system for mobile communications (GSM), an enhanced data rate for GSM evolution (EDGE), a wideband code division multiple access system (WCDMA), a code division multiple access 2000 system (CDMA 2000), and a plurality of other systems. The following types of communication systems are applicable to the wireless communication networks: (1) wireless communication (LTE, CDMA2000), (2) time division-synchronization code division multiple access (TD-SCDMA), (3) enhanced mobile broadband (eMBB), (4) ultra-reliable and low-latency communication (URLLC), (5) enhanced machine-type communication (eMTC), and various types of next-generation communication systems, such as the sixth generation (6G) mobile communication system, and may also be non-terrestrial network (NTN) system, non-3GPP communication system, etc., without restriction. The polar code encoding method provided in the embodiment of the present application can be applied to various communication scenarios, and is particularly suitable for channel coding scenarios in which the Polar code is used as a short code in a communication system. For example, it can be applied to one or more of the following communication scenarios: coding of a control channel, coding of a data channel, etc., without limitation. The following describes the communication system provided in an embodiment of the present application by taking Figure 4 as an example. FIG4 is a schematic diagram of a communication system provided in an embodiment of the present application. As shown in FIG4, the communication system may include at least one terminal device and at least one network device. Among them, the terminal device in Figure 4 can be located within the beam / cell coverage of the network device, and the network device can provide communication services for the terminal device. Exemplarily, the network device can use channel coding to encode the downlink data, and transmit it to the terminal device through the air interface after constellation modulation (that is, the network device is a transmitting device, and the terminal device is a receiving device); the terminal device can also use channel coding to encode the uplink data, and send it to the network device through the air interface after constellation modulation (that is, the terminal device is a transmitting device, and the network device is a receiving device). It can be understood that when network devices communicate with network devices, or when terminal devices communicate with terminal devices, they can also communicate based on channel coding, that is, the transmitting device and the receiving device can both be network devices, or both can be terminal devices, without limitation. The terminal device in FIG4 may be a device with wireless transceiver functions or a chip or chip system that can be set in the device, which can allow users to access the network and is a device for providing voice and / or data connectivity to users. The terminal device may also be called user equipment (UE), subscriber unit, terminal, mobile station (MS), mobile terminal (MT), etc. Exemplarily, the terminal device in FIG. 4 may be a mobile phone, a tablet computer, or a computer with a wireless transceiver function. The terminal device may also be a user station, a mobile station, a remote station, a remote terminal device, a mobile terminal device, a user terminal device, a wireless communication device, a user agent, a user device, a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA), a handheld device with wireless communication function, a computing device, a processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in the Internet of Things, a household appliance, a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in industrial control, a wireless terminal in unmanned driving, a wireless terminal in telemedicine, a wireless terminal in a smart grid, a wireless terminal in a smart city, a wireless terminal in a smart home, a vehicle with vehicle-to-vehicle (V2V) communication capability, an intelligent connected vehicle, a UAV to a UAV (UAV to Unmanned aerial vehicles (UAV, U2U) with communication capabilities, terminal devices in future networks, or terminal devices in future evolved public land mobile networks (PLMN), etc. are not restricted. The network device in FIG4 may be any device deployed in the access network and capable of wirelessly communicating with the terminal device, or may be a chip or chip system that can be set in the above device, or may be a logical node or a logical module or a function implemented in software, and may be used to implement wireless physical control functions, resource scheduling and wireless resource management, wireless access control, mobility management, etc. Specifically, the network device may be a device that supports wired access or a device that supports wireless access. Exemplarily, the network device may be composed of one or more access network (AN) / radio access network (RAN) nodes. The AN / RAN node may be: a gNB, a transmission reception point (TRP), an evolved NodeB (eNB), a radio network controller (RNC), a NodeB (NB), a base station controller (BSC), a base transceiver station (BTS), a home base station (e.g., home evolved NodeB, or home NodeB, HNB), a base band unit (BBU), or a wireless fidelity (Wi-Fi) access point (AP), etc. In another example, the network equipment may include a baseband unit (BBU) and a remote radio unit (RRU). The BBU and the RRU may be placed in different places, for example, the RRU is remotely located in an area with high traffic volume, and the BBU is placed in a central computer room. The BBU and the RRU may also be placed in the same computer room. The BBU and the RRU may also be different components under one rack. In another example, the network device may also be a device including a centralized unit (CU) node, or a distributed unit (DU) node, or a CU node and a DU node. For example, the network device can be divided into CU and DU from the perspective of logical functions, with the functions of some protocol layers centrally controlled by the CU, and the functions of the remaining part or all of the protocol layers distributed in the DU, which is centrally controlled by the CU. Furthermore, the centralized unit CU can also be divided into a control plane (CU-CP) and a user plane (CU-UP). In different systems, CU (including CU-CP or CU-UP) or DU may also have different names. For example, in an open radio access network (O-RAN) system, CU may also be referred to as O-CU (open CU), DU may also be referred to as O-DU, CU-CP may also be referred to as O-CU-CP, and CU-UP may also be referred to as O-CU-UP. Based on the above description of the terminal device and the network device, optionally, the polar code encoding method provided in the embodiment of the present application can be implemented by the above-mentioned terminal device or network device, or by a component of the terminal device or the network device, such as an application specific integrated circuit (ASIC) deployed in the terminal device or the network device, a field programmable gate array (FPGA), or software (such as a program code in a memory), etc., without limitation. Optionally, in the embodiment of the present application, the transmitting end device (or referred to as the information source) and the receiving end device (or referred to as the information sink) may adopt the following diagram: 5 is used for encoding and decoding. Among them, the transmitting device can perform source coding on the bits generated by itself to obtain a source bit stream, and channel code the source bit stream, and then after modulation, send the modulation symbols to the receiving device through a noisy channel. When the receiving device receives the modulation symbols through the noisy channel, it can demodulate, and then perform channel decoding to recover the source bit stream, and then perform source decoding to obtain the decoding result. In specific implementation, as shown in FIG4, each terminal device and network device may adopt the composition structure shown in FIG6, or include the components shown in FIG6. FIG6 is a schematic diagram of the composition of a communication device 600 provided in an embodiment of the present application. The communication device 600 may be a terminal device or a chip or a system on chip in a terminal device; or a network device or a chip or a system on chip in a network device. As shown in FIG6, the communication device 600 includes a processor 601, a transceiver 602, and a communication line 603. Furthermore, the communication device 600 may also include a memory 604. The processor 601, the memory 604 and the transceiver 602 may be connected via a communication line 603. The processor 601 is a central processing unit (CPU), a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 601 may also be other devices with processing functions, such as circuits, devices, or software modules, without limitation. The transceiver 602 is used to communicate with other devices or other communication networks. The other communication networks may be Ethernet, radio access networks (RAN), wireless local area networks (WLAN), etc. The transceiver 602 may be a module, a circuit, a transceiver or any device capable of achieving communication. The communication line 603 is used to transmit information between the components included in the communication device 600. The memory 604 is used to store instructions, where the instructions may be computer programs. Among them, the memory 604 can be a read-only memory (ROM) or other types of static storage devices that can store static information and / or instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and / or instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage devices, etc., without limitation. It should be noted that the memory 604 may exist independently of the processor 601, or may be integrated with the processor 601. The memory 604 may be used to store instructions or program codes or some data, etc. The memory 604 may be located in the communication device 600, or may be located outside the communication device 600, without limitation. The processor 601 is configured to execute the instructions stored in the memory 604 to implement the polar code encoding method provided in the following embodiments of the present application. In one example, the processor 601 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 6 . As an optional implementation manner, the communication device 600 includes multiple processors. For example, in addition to the processor 601 in FIG. 6 , it may also include a processor 607 . As an optional implementation, the communication device 600 further includes an output device 605 and an input device 606. Exemplarily, the input device 606 is a device such as a keyboard, a mouse, a microphone or a joystick, and the output device 605 is a device such as a display screen and a speaker. It should be noted that the communication device 600 may be a desktop computer, a portable computer, a network server, a mobile phone, a tablet computer, a wireless terminal, an embedded device, a chip system, or a device having a similar structure as shown in FIG6. In addition, the composition structure shown in FIG6 does not constitute a limitation on the communication device. In addition to the components shown in FIG6, the communication device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. In the embodiment of the present application, the chip system may be composed of a chip, or may include a chip and other discrete devices. In addition, the actions, terms, etc. involved in the various embodiments of the present application can refer to each other without limitation. The message name or parameter name in the message exchanged between the various devices in the embodiments of the present application is only an example, and other names can also be used in the specific implementation without limitation. In combination with the communication system shown in FIG4 , the polar code encoding method provided in the embodiment of the present application is described with reference to FIG7 below, wherein the transmitting end device may be any terminal device or network device in the communication system shown in FIG4 , and the receiving end device may also be any terminal device or network device in the communication system shown in FIG4 . The transmitting end device or the receiving end device described in the following embodiment may have the components shown in FIG6 . FIG. 7 is a flow chart of a polar code encoding method provided in an embodiment of the present application. As shown in FIG. 7 , the method may include: Step 701: The transmitting end device maps an information bit sequence of length k to k bits of a first sequence of length N according to a reliability sequence to obtain a second sequence. The reliability sequence may be used to indicate the reliability corresponding to each bit of the sequence. The larger the reliability value is, the more reliable the bit corresponding to the reliability is. The length of the reliability sequence may be N, where N is a positive integer. Optionally, N is less than 1024. Optionally, the reliability sequence may be determined based on one or more of the following: reliability, code spectrum, and performance optimization result. In an embodiment of the present application, a reliability sequence with a length of N can be separately constructed for the information bit sequence based on parameters such as reliability, code spectrum, and performance optimization results. When the encoded sequence is subsequently punctured in a back-to-front order, the number of performance bad points can be reduced, the code spectrum characteristics can be improved, and the decoding performance can be improved. For example, taking the reliability sequence length N as 32, the reliability sequence may be the reliability sequence shown in the following Table 2, where: Represents reliability, Indicates the bits corresponding to the reliability: Table 2 It can be understood that the above Table 2 is defined starting from bit 0, and can also be defined starting from bit 1, that is, the above 0, 1, ..., 31 can be replaced by 1, 2, ..., 32 respectively without limitation. Referring to the above reliability sequence, the transmitting end device may map the information bit sequence of length k to k bits of the first sequence of length N to obtain a second sequence. Wherein, k≤K≤N, K is the maximum length of the information bit sequence, and k, K, and N are all positive integers. Exemplarily, the length k of the information bit sequence can be any of the following values: 3, 4, 5, 6, 7, 8, 9, 10, 11; in this case, K is equal to 11. Exemplarily, the length N of the first sequence may be 32. Among them, the sending end device can select the first k bits of the first sequence as information bits according to the reliability sequence in descending order of reliability, and map the information bit sequence of length k to the k bits in sequence, that is, map the information bit sequence to the k information bits of the first sequence, and set the values ​​of the remaining Nk bits of the first sequence to 0 to obtain the second sequence. The second sequence may include k information bits, x PC bits and Nkx frozen bits, where 1≤x, and x is a positive integer. Optionally, taking the definition starting from bit 0 as an example, the information bit sequence can be recorded as The second sequence is recorded as It is understandable that the definition can also be started from 1 bit, that is, the information bit sequence can be recorded as The second sequence is recorded as No restrictions. The following uses the definition starting from bit 0 as an example to illustrate the generation process of the second sequence. Exemplarily, taking the reliability sequence as the reliability sequence with a length of 32 shown in Table 2 above, and the length of the first sequence as 32, when the length of the information bit sequence is 3, according to the reliability sequence shown in Table 2, it can be determined that the first 3 bits of reliability from high to low in the first sequence are {31 30 29}, then it can be determined that the information bits are {31 30 29}, and the information bit sequence with a length of 3 is mapped to these 3 bits of the first sequence, and the values ​​of the remaining 29 bits of the first sequence are set to 0 to obtain the second sequence. In another example, taking the reliability sequence as the reliability sequence with a length of 32 shown in Table 2 above, and the length of the first sequence as 32 as an example, when the length of the information bit sequence is 11, according to the reliability sequence shown in Table 2, it can be determined that the first 11 bits of reliability from high to low in the first sequence are {31 30 29 27 23 15 22 13 14 11 28}, then the information bits can be determined to be {31 30 29 27 23 15 22 13 14 11 28}, and the information bit sequence with a length of 11 is mapped to these 11 bits of the first sequence, and the values ​​of the remaining 21 bits of the first sequence are set to 0 to obtain the second sequence. Step 702: The transmitting device multiplies the second sequence by the first matrix to obtain a third sequence. The first matrix may be a matrix with all zeros below the diagonal and all ones on the diagonal. The column weights of the columns corresponding to the PC bits in the first matrix are greater than 1, the column weights of the columns corresponding to the frozen bits or information bits are equal to 1, and the number of columns with column weights greater than 1 in the first matrix is ​​less than or equal to NK. The first matrix may also be called an upper triangular matrix, a pre-transformation matrix, etc. The first matrix may also be denoted as T pre , without restriction. Exemplarily, taking N as 32 and K as 11 as an example, the first matrix may be a 32*32 matrix, and the number of columns with column weight greater than 1 in the first matrix is ​​less than or equal to 21. Optionally, the first matrix may be a sparse matrix. Optionally, the column weight of the first matrix may be less than or equal to the first value, thereby ensuring the sparsity of the first matrix and obtaining better code spectrum characteristics. Exemplarily, the first value may be any one of the following values: 4, 5, 6, or 7. Based on the above-mentioned first matrix, the transmitting device can determine one or more PC bits and PC bit check bits according to the first matrix, and determine the value of the PC bit in the second sequence according to the value of the PC bit check bit to obtain a third sequence, which may include one or more PC bits. Optionally, the value of the PC bit may be the exclusive OR of the values ​​of the bits of the PC bit check. Optionally, taking the definition starting from bit 0 as an example, the third sequence can be recorded as It is understandable that the definition can also be started from 1 bit, that is, the third sequence can be recorded as No restrictions. Optionally, the difference between the number of the PC bit and the number of the bit of the PC bit check may be a prime number. By limiting the difference between the number of the PC bit and the number of the bit of the PC bit check to a prime number, the search space can be greatly reduced, and while improving the code spectrum characteristics, the optimality can be lost as little as possible. Exemplarily, taking N as 32, the length k of the information bit sequence is 3 to 11, and is defined starting from bit 0, when k=11, the information bits corresponding to the information bit sequence are {31 30 29 27 23 15 22 13 14 11 28}; when k=10, the information bits corresponding to the information bit sequence are {31 30 29 27 23 15 22 13 14 11}; when k=9, the information bits corresponding to the information bit sequence are {31 30 29 27 23 15 22 13 14}; when k=8, the information bits corresponding to the information bit sequence are {31 30 29 27 23 15 22 13}; when k=7, the information bits corresponding to the information bit sequence are {31 30 29 27 23 15 22}; when k=6, the information bits corresponding to the information bit sequence are {31 30 29 27 23 15}; when k=5, the information bits corresponding to the information bit sequence are {31 30 29 27 23}; when k=4, the information bits corresponding to the information bit sequence are {31 30 29 27}; when k=3, the information bits corresponding to the information bit sequence are {31 30 29}. Since the PC bit is a frozen bit and there is at least one information bit before the PC bit, for the above information bit sequence k=11, the potential PC bits can be the following 10 bits: {12 16 17 18 19 20 21 24 25 26}. The information bits that can be checked by the 10 potential PC bits are the information bits shown in the following Table 3: Table 3 In the above Table 3, there are 2*(16 6 )*(64 3 )=8.7961*10 12 There are 1*(2 3 )*(4 4 )*(8 2 ) = 131072 potential PC functions, which can greatly reduce the search space and improve the code spectrum characteristics while losing as little optimality as possible. Table 4 Compared with the above k=11, as shown in the following Table 5, for the information bit sequence of k=10, 28 PC bits can be added on the basis of k=11 shown in Table 4; for the information bit sequence of k=9, 11 PC bits can be added on the basis of k=10; for the information bit sequence of k=8, 14 PC bits can be added on the basis of k=9; for the information bit sequence of k=7, 13 PC bits can be added on the basis of k=8; for the information bit sequence of k=6, 22 PC bits can be added on the basis of k=7; for the information bit sequence of k=5, 15 PC bits can be added on the basis of k=6; for the information bit sequence of k=4, 23 PC bits can be added on the basis of k=5; for the information bit sequence of k=3, 27 PC bits can be added on the basis of k=4. Thus, the search space is greatly reduced, and while the code spectrum characteristics are improved, the optimality is lost as little as possible. Table 5 Based on the PC bits and the information bits of the PC bit check shown in Tables 4 and 5 above, in a first possible exemplary embodiment, the first matrix may be the following 32*32 matrix, which may also be represented as a matrix as shown in FIG8: Based on the first matrix, the PC bits in the third sequence obtained according to step 702 may be one or more of the following bit positions of the third sequence: 16, 18, 21, or 25. Among them, when the PC bit is the 16th bit in the third sequence, the bit checked by the PC bit is the 13th bit in the third sequence; or, when the PC bit is the 18th bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 11, 13, 15; or, when the PC bit is the 21st bit in the third sequence, the bit checked by the PC bit is the 14th bit in the third sequence; or, when the PC bit is the 25th bit in the third sequence, the bit checked by the PC bit is the 22nd bit in the third sequence. In a second possible example, the first matrix may also be the following 32*32 matrix, and the first matrix may also be expressed as the matrix shown in FIG9: Based on the first matrix, the PC bits in the third sequence obtained according to step 702 may be one or more of the following bit positions in the first sequence: 19, 21, 25, or 26. Among them, when the PC bit is the 19th bit in the third sequence, the bit checked by the PC bit is the 14th bit in the third sequence; or, when the PC bit is the 21st bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 11, 14; or, when the PC bit is the 25th bit in the third sequence, the bit checked by the PC bit is one or more of the following bits of the third sequence: 14, 22; or, when the PC bit is the 26th bit in the third sequence, the bit checked by the PC bit is the 13th bit in the third sequence. In the first possible design, different from the above-mentioned use of the first matrix to represent the PC bits and the PC bit check bits, the PC bits and the PC bit check bits can also be represented by a set of PC equations, or described as representing the above-mentioned first matrix by a set of PC equations. The PC equation set may include one or more PC equations, and the number of PC equations included in the PC equation set is equal to the number of PC bits (or can also be described as being equal to the number of columns in the first matrix whose column magnitude is greater than 1). Each PC equation includes at least two elements, and the maximum value of the elements in each PC equation represents the PC bit (or can be described as the maximum value representing the column number in the first matrix whose column magnitude is greater than 1), and the other elements in each PC equation except the PC bit represent the bit of the PC bit check. In the first possible example, if the PC equation set is {[13 16]}, it can be determined that the number of PC bits is 1, the PC bit is 16, and the PC bit check bit is 13. If the PC equation set is {[11 13 15 18]}, it can be determined that the number of PC bits is 1, the PC bit is 18, and the PC bit check bits are 11, 13, and 15. If the PC equation set is {[14 21]}, it can be determined that the number of PC bits is 1, the PC bit is 21, and the PC bit check bit is 14. If the PC equation set is {[22 25]}, it can be determined that the number of PC bits is 1, the PC bit is 25, and the PC bit check bit is 21. If the PC equation set is {[13 16], [11 13 15 18], [14 21], [22 25]}, the number of PC bits can be determined It is 4, the PC bits are 16, 18, 21, and 25. The bit checked by PC bit 16 is 13, the bit checked by PC bit 18 is 11, 13, and 15, the bit checked by PC bit 21 is 14, and the bit checked by PC bit 25 is 22. In the second possible example, if the PC equation set is {[14 19]}, it can be determined that the number of PC bits is 1, the PC bit is 19, and the bit of the PC bit check is 14. If the PC equation set is {[11 14 21]}, it can be determined that the number of PC bits is 1, the PC bit is 21, and the bits of the PC bit check are 11 and 14. If the PC equation set is {[14 22 25]}, it can be determined that the number of PC bits is 1, the PC bit is 25, and the bits of the PC bit check are 14 and 22. If the PC equation set is {[13 26]}, it can be determined that the number of PC bits is 1, the PC bit is 26, and the bit of the PC bit check is 13. If the set of PC equations is {[14 19], [11 14 21], [14 22 25], [13 26]}, we can determine that the number of PC bits is 4, the PC bits are 19, 21, 25, 26, the bit checked by PC bit 19 is 14, the bits checked by PC bit 21 are 11 and 14, the bits checked by PC bit 25 are 14 and 22, and the bit checked by PC bit 26 is 13. Based on the first possible design, when the first matrix is ​​represented by a set of PC equations, the second sequence With the first matrix T pre Multiply them to get the third sequence It can be expressed as: Where N is the sequence length (e.g. 32, then N-1 can be 31), F is the frozen bit set, PF is the PC equation set, pcIdx is the PC bit, PF(p) is the pth PC equation in the PC equation set, chkIdx is the bit of the PC bit check, and v n represents the nth value of the third sequence, a i represents the i-th value in the second sequence, a n Represents the nth value in the second sequence. In a second possible design, different from the above-mentioned representation of PC bits and PC bit check bits by the first matrix or PC equation set, PC bits and PC bit check bits can also be represented by a PC bit set and a bit set corresponding to the PC bits, or described as representing the above-mentioned first matrix or the above-mentioned PC equation set by a PC bit set and a bit set corresponding to the PC bits. Among them, the PC bit set includes one or more PC bits (or is described as the elements in the PC bit set representing the column numbers in the first matrix whose column magnitude is greater than 1, and the number of elements included in the PC bit set is the number of columns in the first matrix whose column magnitude is greater than 1), and the bit set corresponding to the PC bit includes one or more bits of the PC bit check. In the first possible example, if the PC bit set is {16}, and the bit set corresponding to the PC bit is {13}, it can be determined that the number of PC bits is 1, the PC bit is 16, and the bit of the PC bit check is 13. If the PC bit set is {18}, and the bit set corresponding to the PC bit is {11 13 15}, it can be determined that the number of PC bits is 1, the PC bit is 18, and the bits of the PC bit check are 11, 13, and 15. If the PC bit set is {21}, and the bit set corresponding to the PC bit is {14}, it can be determined that the number of PC bits is 1, the PC bit is 21, and the bit of the PC bit check is 14. If the PC bit set is {25}, and the bit set corresponding to the PC bit is {22}, it can be determined that the number of PC bits is 1, the PC bit is 25, and the bit of the PC bit check is 21. If the PC bit set is {16 18 21 25}, and the bit set corresponding to the PC bit is {

[0013] , [11 13 15],

[0014] ,

[0022] }, it can be determined that the number of PC bits is 4, the PC bits are 16, 18, 21, 25, the bit checked by PC bit 16 is 13, the bits checked by PC bit 18 are 11, 13, 15, the bit checked by PC bit 21 is 14, and the bit checked by PC bit 25 is 22. In the second possible example, if the PC bit set is {19}, and the bit set corresponding to the PC bits is {14}, it can be determined that the number of PC bits is 1, the PC bits are 19, and the bit of the PC bit check is 14. If the PC bit set is {21}, and the bit set corresponding to the PC bits is {11 14}, it can be determined that the number of PC bits is 1, the PC bits are 21, and the bits of the PC bit check are 11 and 14. If the PC bit set is {25}, and the bit set corresponding to the PC bits is {14 22}, it can be determined that the number of PC bits is 1, the PC bits are 25, and the bits of the PC bit check are 14 and 22. If the PC bit set is {26}, and the bit set corresponding to the PC bits is {13}, it can be determined that the number of PC bits is 1, the PC bits are 26, and the PC bit check is The bit position is 13. If the PC bit set is {19 21 25 26}, and the bit set corresponding to the PC bit is {

[0014] , [11 14], [14 22],

[0013] }, it can be determined that the number of PC bits is 4, the PC bits are 19, 21, 25, 26, the bit position checked by PC bit 19 is 14, the bit position checked by PC bit 21 is 11, 14, the bit position checked by PC bit 25 is 14, 22, and the bit position checked by PC bit 26 is 13. Based on the second possible design, when the first matrix is ​​represented by a PC bit set and a bit set corresponding to the PC bit, the second sequence With the first matrix T pre Multiply them to get the third sequence It can be expressed as: Where N represents the sequence length (e.g. 32, then N-1 can be 31), v i represents the i-th value of the third sequence, a i represents the i-th value in the second sequence, a j represents the jth value in the second sequence, PBS represents the PC bit set, and CBS represents the bit set corresponding to the PC bit. Based on the above description of the PC bit and the bit of the PC bit check, in the above various examples, the PC bit and the bit of the PC bit check are defined starting from bit 0. It can be understood that they can also be defined starting from bit 1, that is, the above 0, 1, ..., 31 can be replaced by 1, 2, ..., 32 respectively without limitation. Step 703: The transmitting end device performs polarization encoding on the third sequence to obtain a fourth sequence. The transmitting device may multiply the third sequence by the Polar coding matrix to obtain a fourth sequence. For example, the Polar encoding matrix can be G N , G N is the log2N Kronecker product of G2, Optionally, taking the definition starting from bit 0 as an example, the fourth sequence can be recorded as It is understandable that the definition can also be started from 1 bit, that is, the third sequence can be recorded as No restrictions. Based on the method shown in FIG. 7 above, an embodiment of the present application provides a Polar code encoding scheme based on nested PCs, which can construct a reliability sequence of length N with nested characteristics for an information bit sequence separately, thereby reducing the number of performance bad points when puncturing sequentially from back to front, improving the code spectrum characteristics, and improving the decoding performance. At the same time, different numbers of information bit sequences in the embodiment of the present application can construct polar codes based on the same first matrix, that is, the first matrix has a nested characteristic for different numbers of information bit sequences, and the first matrix does not change with the number of information bit sequences, or can also be described as the PC bits and PC equations corresponding to different numbers of information bit sequences are nested, and there is no need to separately store the corresponding PC bits and PC equations for information bit sequences of different lengths, thereby reducing hardware complexity, reducing hardware overhead, improving code spectrum characteristics, reducing decoding complexity, and improving decoding performance (such as multiplexing a serial cancellation list (successive cancellation list, SCL) decoding module to improve the decoding performance under the SCL decoding module (such as SCL8)). Based on the method shown in FIG. 7 , after the transmitting end device determines the fourth sequence according to the polarization coding, it may also use an interleaving pattern to interleave the fourth sequence to obtain an interleaved sequence. In a first possible design, the fourth sequence may be interleaved using the first interleaving pattern to obtain a fifth sequence. Among them, the first interleaving pattern can be determined according to the sequence performance and the nesting characteristics by designing a search algorithm, that is, the first interleaving pattern has a nesting characteristic for different numbers of information bit sequences and does not change with the change of the length of the information bit sequence. Compared with the enumeration method to design the first interleaving pattern, it is necessary to enumerate N! cases (for example, when N is equal to 32, it is necessary to enumerate 32! = 2.6313 * 1035 cases), the embodiment of the present application designs the first interleaving pattern by designing a search algorithm, which can greatly reduce the complexity on the basis of satisfying the optimal sequence performance and the nesting characteristics. Exemplarily, a List search algorithm may be used to search for puncturing positions for multiple fourth sequence samples (the multiple fourth sequence samples may correspond to information bit sequences of different lengths, and the length of each information bit sequence is less than or equal to K). When the number of punctures increases by one, the average sequence performance of all sequences is calculated, and the average sequence performance is used as a metric. The position corresponding to the optimal average sequence performance is determined as the puncturing position to generate a first interleaving pattern. The average performance refers to the mean of the SNR@BLER=1E-2 of the sequence. Specifically, as shown in FIG10 , the search process may include: Step 1: Initialize the search space of puncture positions to 0 to N-1, and the number of punctures to 0. Step 2: Select a location from the current search space as a new punching location. Step 3: Simulate the sequence performance of all sequences according to the current puncture position. Step 4: Take the average of the sequence performance of all sequences to obtain the metrics corresponding to different puncturing positions under the current number of puncturing. Step 5: Keep the punching positions corresponding to the optimal Metric in List as the candidate punching positions under the current number of punchings. Step 6: Update the candidate search space of each List: Delete the current punching position from the search space. Step 7: Add one to the number of holes punched. Step 8: Determine whether the punching data is less than the maximum number of punching holes. If so, continue to execute from step 2 above until the number of punching holes reaches If the number is equal to the maximum puncturing data, then the first interleaving pattern (or also called the optimal puncturing pattern) is output. The first interleaving pattern determined according to the above search process can also be described as: the first interleaving pattern can be used to indicate that the value of the yth bit in the fourth sequence is swapped and placed on the Ny-1th bit in the fifth sequence, 0≤y≤Nk-2, y is an integer, k+1≤Ny-1≤N-1. The values ​​of the k+1 bits in the fourth sequence except the yth bit mentioned above can be randomly placed in the 0th bit to the kth bit of the fifth sequence without restriction. Among them, the y-th bit can be determined based on the average sequence performance after removing the same bit from Ny-1 bits of multiple fourth sequence samples, the length of multiple information bit sequence samples corresponding to the multiple fourth sequence samples is less than or equal to K, the length of the multiple information bit sequence samples includes k, and the Ny-1 bits do not include the first y-1 bits of the y-th bit. Optionally, when the same bit is removed from Ny-1 bits of multiple fourth sequence samples and the average sequence performance is optimal, the removed bit is the yth bit. Exemplarily, the following takes the fourth sequence sample including the fourth sequence corresponding to the information bit sequence with a length of k=k1 and the fourth sequence corresponding to the information bit sequence with a length of k=k2 as an example to describe in detail the generation method of the first interleaving pattern with a nested characteristic: Step 1: randomly generate a first random sequence (i.e., information bit sequence) of length k1 and a second random sequence (i.e., information bit sequence) of length k2, where k1 and k2 are the lengths of the information bit sequences to be encoded, and k1 and k2 are not equal. Step 2: Polarization encoding is performed on the first random sequence and the second random sequence respectively according to the method shown in FIG. 7 to obtain a first random codeword sequence (i.e., a fourth sequence) and a second random codeword sequence (i.e., the fourth sequence) having a length of N. Step 3: Determine the value of the first performance of the first random code word sequence and the second random code word sequence after the g-th position is deleted, 0≤g≤N-1. Step 4: Determine the average value A of the first value and the second value g , the first value is the value of the first performance of the sequence after the g-th position of the first random code word sequence is deleted, and the second value is the value of the first performance of the sequence after the g-th position of the second random code word sequence is deleted. Step 5: Determine the yth bit (y=0), the yth bit (y=0) is A0 to A N-1 The position corresponding to the smallest value in , the y-th bit (y=0) is the first puncturing position. Step 6: Determine that the number of puncturing positions 1 is equal to (NE), and generate a first interleaving pattern, wherein the first interleaving pattern indicates that after the fourth sequence is interleaved based on the first interleaving pattern, the value of the yth bit position (y=0) of the fourth sequence is swapped and placed on the last bit position of the fifth sequence. Wherein, E represents the length of the rate matching sequence. or Step 7: Determine that the number 1 of puncturing positions is less than (NE), and randomly generate a third random sequence (ie, information bit sequence) of length k1 and a fourth random sequence (ie, information bit sequence) of length k2. Step 8: Polarization encoding is performed on the third random sequence and the fourth random sequence according to the method shown in FIG. 7 to obtain a third random codeword sequence (i.e., the fourth sequence) and a fourth random codeword sequence (i.e., the fourth sequence) of length N. Step 9, determine the fifth random code word sequence and the sixth random code word sequence, the fifth random code word sequence is the sequence after the bit at the y-th bit position (y=0) is removed from the third random code word sequence, and the sixth random code word sequence is the sequence after the bit at the y-th bit position (y=0) is removed from the fourth random code word sequence. Step 10: Determine the value of the first performance of the sequence after the h-th position of the fifth random code word sequence and the sixth random code word sequence is deleted, 0≤h≤N-2. Step 11: Determine the average value A of the third value and the fourth value h , the third value is the value of the first performance of the sequence after the h-th position of the fifth random code word sequence is deleted, and the fourth value is the value of the first performance of the sequence after the h-th position of the sixth random code word sequence is deleted. Step 12: Determine the yth bit (y=1), the yth bit (y=1) is A1 to A N-2 The position corresponding to the smallest value in , the y-th bit (y=1) is the second puncture position. Step 13, determine that the number of puncturing positions 2 is equal to (NE), and generate a first interleaving pattern, wherein the first interleaving pattern indicates that after the fourth sequence is interleaved based on the first interleaving pattern, the value on the y-th bit position (y=0) of the fourth sequence is swapped and placed on the last bit position of the fifth sequence, and the value on the y-th bit position (y=1) of the fourth sequence is swapped and placed on the second to last bit position of the fifth sequence. or, Step 14: Determine that the number of puncturing positions 2 is less than (NE), repeat the above operation until the number of puncturing positions is equal to E, and generate the corresponding first interleaving pattern. The above is only explained by taking the generation of the first interleaving pattern with nested characteristics according to the fourth sequence corresponding to k1 and the fourth sequence corresponding to k2 (that is, the fourth sequence corresponding to k1 and the fourth sequence corresponding to k2 can both be interleaved using the above first interleaving pattern) as an example. It can be understood that for the fourth sequences corresponding to multiple different k, the first interleaving pattern with nested characteristics can be generated by referring to the above method. Exemplarily, taking k equal to 3, 4, ..., 11 as an example, a first interleaving pattern with a nested characteristic can be generated according to the fourth sequence corresponding to k equal to 3, 4, ..., 11, with reference to the above method, that is, the fourth sequence corresponding to k equal to 3, the fourth sequence corresponding to k equal to 4, ..., the fourth sequence corresponding to k equal to 11 can all be interleaved using the first interleaving pattern. Exemplarily, taking the maximum value of the length k of the information bit sequence as 11, the minimum value as 3, and N as 32, the first interleaving pattern can be used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the fifth sequence, where the mapping relationship between A and B is: (5, 31), (26, 30), (11, 29), (9, 28), (28, 27), (7, 26), (30, 25), (16, 24), (31, 23), (21, 22), (10, 21), (24, 20), (27, 19), (6, 18), (3, 17), (12, 16), (17, 15), (8, 14), (13, 13), (0, 12), (2, 11), (1, 10), (4, 9), (14, 8), (25, 7), (23, 6), (22, 5), (19, 4). Among them, the first A (i.e., 5) is the yth bit when y=0, the second A (i.e., 26) is the yth bit when y=1,…, the NK-1=32-11-1=20th A (i.e., 0) is the yth bit when y=NK-2=32-11-2=19,…, the Nk-1=32-3-1=28th A (i.e., 19) is the yth bit when y=Nk-2=32-11-2=27. The first interleaving pattern may be represented as the interleaving pattern shown in the following Table 6, or may be represented as the interleaving pattern shown in the following FIG. 11: Table 6 It can be understood that the mapping relationship between the first 4 groups A and B in the above Table 6 can be randomly determined, that is, 29, 20, 18 and 15 in A can randomly correspond to 0, 1, 2 and 3 in B without restriction. In another example, taking the maximum value of the length k of the information bit sequence as 11, the minimum value as 3, and N as 32, the first interleaving pattern can be used to indicate that the value on the Ath bit of the fourth sequence is swapped and placed on the Bth bit of the fifth sequence, where the mapping relationship between A and B is: (4, 31), (22, 30), (27, 29), (17, 28), (8, 27), (2, 26), (15, 25), (2 1, 24), (29, 23), (23, 22), (6, 21), (26, 20), (20, 19), (7, 18), (0, 17), (13, 16), (19, 15), (11, 14), (14, 13), (16, 12), (25, 11), (3, 10), (10, 9), (5, 8), (12, 7), (1, 6), (18, 5), (24, 4). Among them, the first A (i.e. 4) is the yth bit when y=0, the second A (i.e. 22) is the yth bit when y=1,…, the NK-1=32-11-1=20th A (i.e. 16) is the yth bit when y=NK-2=32-11-2=19,…, the Nk-1=32-3-1=28th A (i.e. 24) is the yth bit when y=Nk-2=32-11-2=27. The first interleaving pattern may be an interleaving pattern as shown in the following Table 7, or may be expressed as an interleaving pattern as shown in the following FIG. 12: Table 7 It can be understood that the mapping relationship between the first 4 groups A and B in the above Table 7 can be randomly determined, that is, 9, 28, 30 and 31 in A can randomly correspond to 0, 1, 2 and 3 in B without restriction. Based on the above first interleaving pattern, since the first interleaving pattern has a nested characteristic, it is not necessary to store interleaving patterns separately for different numbers of information bit sequences, which can reduce hardware complexity and hardware overhead. Since the above first interleaving pattern is determined based on sequence performance, it can ensure that the rate matching performance has no bad points (such as 1-bit fine-grained rate matching performance has no bad points), thereby improving decoding performance. It is understandable that interleaving patterns may also be saved separately for information bit sequences of different numbers, that is, for information bit sequences of different numbers The first interlaced pattern is saved separately without restriction. In a second possible design, the fourth sequence may also be interleaved using a second interleaving pattern to obtain a sixth sequence. Among them, different from the first interleaving pattern with nested characteristics in the first possible design mentioned above, in the second possible design, different numbers of information bit sequences can correspond to different second interleaving patterns, that is, second interleaving patterns are designed respectively for different numbers of information bit sequences. Among them, the embodiment of the present application can design the second interleaving pattern by referring to the search algorithm in the first possible design mentioned above, which can greatly reduce the complexity while satisfying the optimal sequence performance. Exemplarily, the List search algorithm described above can be referred to to search for puncturing positions for multiple fourth sequence samples (the multiple fourth sequence samples can correspond to information bit sequences of the same length, and the length of the information bit sequence is less than or equal to K). When the number of punctures increases by one, the average sequence performance of all sequences is calculated, and the average sequence performance is used as a metric. The position corresponding to the optimal average sequence performance is determined as the puncturing position to generate a second interleaving pattern. The average performance refers to the mean of the SNR@BLER=1E-2 of the sequence. The second interleaving pattern determined according to the above search process can also be described as: the second interleaving pattern is used to indicate that the value of the yth bit in the fourth sequence is swapped and placed on the Ny-1th bit in the sixth sequence, 1≤y≤Nk-2, y is a positive integer, k+1≤Ny-1≤N-1. The values ​​of the k+1 bits in the fourth sequence except the yth bit mentioned above can be randomly placed in the 0th bit to the kth bit of the sixth sequence without restriction. The y-th bit is determined based on the average sequence performance of Ny-1 bits of multiple fourth sequence samples after removing one bit, the lengths of multiple information bit sequence samples corresponding to the multiple fourth sequence samples are all k, and the Ny-1 bits do not include the first y-1 bits of the y-th bit. Optionally, when one bit is removed from Ny-1 bits of the fourth sequence samples and the average sequence performance is optimal, the removed bit is the yth bit. Exemplarily, taking the maximum value of the length k of the information bit sequence as 11, the minimum value as 3, and N as 32, the second interleaving pattern may be used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence: Among them, when k is 3, the mapping relationship between A and B is: (12, 31), (9, 30), (19, 29), (18, 28), (1, 27), (15, 26), (14, 25), (29, 24), (16, 23), (10, 22), (28, 21), (23, 20), (20, 19), (6, 18), (21, 17), (7, 16), (2, 15), (25, 14), (0, 13), (3, 12), (5, 11), (31, 10), (30, 9), (4, 8), (22, 7), (13, 6), (27, 5), (8, 4). Alternatively, when k is 4, the mapping relationship between A and B is: (18, 31), (29, 30), (9, 29), (12, 28), (27, 27), (22, 26), (23, 25), (26, 24), (4, 23), (0, 22), (7, 21), (14, 20), (8, 19), (19, 18), (1, 17), (21, 16), (13, 15), (11, 14), (17, 13), (20, 12), (16, 11), (15, 10), (6, 9), (10, 8), (28, 7), (25, 6), (24, 5). Alternatively, when k is 5, the mapping relationship between A and B is: (2, 31), (20, 30), (12, 29), (25, 28), (8, 27), (22, 26), (16, 25), (5, 24), (29, 23), (14, 22), (23, 21), (15, 20), (3, 19), (11, 18), (10, 17), (17, 16), (0, 15), (30, 14), (18, 13), (27, 12), (4, 11), (19, 10), (21, 9), (6, 8), (26, 7), (9, 6). Alternatively, when k is 6, the mapping relationship between A and B is: (19, 31), (23, 30), (16, 29), (18, 28), (29, 27), (0, 26), (21, 25), (8, 24), (11, 23), (4, 22), (13, 21), (2, 20), (20, 19), (24, 18), (25, 17), (6, 16), (28, 15), (14, 14), (10, 13), (9, 12), (31, 11), (26, 10), (7, 9), (17, 8), (1, 7). Alternatively, when k is 7, the mapping relationship between A and B is: (7, 31), (9, 30), (19, 29), (26, 28), (31, 27), (21, 26), (27, 25), (2, 24), (23, 23), (17, 22), (10, 21), (30, 20), (25, 19), (24, 18), (0, 17), (16, 16), (4, 15), (11, 14), (20, 13), (12, 12), (29, 11), (18, 10), (13, 9), (3, 8). Alternatively, when k is 8, the mapping relationship between A and B is: (15, 31), (16, 30), (9, 29), (14, 28), (17, 27), (24, 26), (21, 25), (20, 24), (5, 23), (1, 22), (7, 21), (30, 20), (11, 19), (6, 18), (2, 17), (3, 16), (8, 15), (22, 14), (12, 13), (23, 12), (19, 11), (10, 10), (29, 9). Or, when k is 9, the mapping relationship between A and B is: (17, 31), (21, 30), (15, 29), (14, 28), (4, 27), (24, 26), (8, 25), (29, 24), (19, 23), (16, 22), (7, 21), (2, 20), (9, 19), (25, 18), (26, 17), (23, 16), (28, 15), (30, 14), (13, 13), (6, 12), (22, 11), (0, 10). Alternatively, when k is 10, the mapping relationship between A and B is: (28, 31), (29, 30), (14, 29), (26, 28), (8, 27), (23, 26), (24, 25), (30, 24), (0, 23), (31, 22), (10, 21), (5, 20), (20, 19), (4, 18), (16, 17), (12, 16), (9, 15), (21, 14), (1, 13), (11, 12), (22, 11). Alternatively, when k is 11, the mapping relationship between A and B is: (22, 31), (19, 30), (28, 29), (9, 28), (4, 27), (6, 26), (14, 25), (11, 24), (3, 23), (13, 22), (0, 21), (15, 20), (26, 19), (24, 18), (27, 17), (18, 16), (21, 15), (17, 14), (20, 13), (12, 12). Among them, the first A is the yth bit when y=0, the second A is the yth bit when y=1,…, the NK-1=32-11-1=20th A (i.e. 0) is the yth bit when y=NK-2=32-11-2=19,…, the Nk-1th A is the yth bit when y=Nk-2. Optionally, the second interlacing pattern mentioned above can also be expressed as the interlacing pattern shown in the following FIG. 13 . Optionally, the second interleaving pattern may also be expressed as an interleaving pattern similar to that shown in Table 6 or Table 7. For example, taking k as 3 as an example, the second interleaving pattern may be an interleaving pattern shown in Table 8 below: Table 8 It can be understood that the mapping relationship between the first 4 groups A and B in the above Table 8 can be randomly determined, that is, 25, 16, 23 and 10 in A can randomly correspond to 0, 1, 2 and 3 in B without restriction. In another example, taking the maximum value of the length k of the information bit sequence as 11, the minimum value as 3, and N as 32 as an example, the second interleaving pattern can be used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence: Among them, when k is 3, the mapping relationship between A and B is: (5, 31), (11, 30), (24, 29), (30, 28), (13, 27), (20, 26), (22, 25), (3, 24), (4, 23), (25, 22), (31, 21), (6, 20), (10, 19), (8, 18), (21, 17), (15, 16), (9, 15), (2, 14), (0, 13), (27, 12), (14, 11), (16, 10), (17, 9), (23, 8), (28, 7), (26, 6), (1, 5), (7, 4). Among them, when k is 4, the mapping relationship between A and B is: (16, 31), (28, 30), (10, 29), (30, 28), (19, 27), (7, 26), (13, 25), (9, 24), (11, 23), (6, 22), (8, 21), (26, 20), (21, 19), (20, 18), (23, 17), (25, 16), (0, 15), (17, 14), (27, 13), (22, 12), (18, 11), (15, 10), (5, 9), (12, 8), (2, 7), (29, 6), (24, 5). Among them, when k is 5, the mapping relationship between A and B is: (9, 31), (19, 30), (11, 29), (12, 28), (21, 27), (0, 26), (29, 25), (2, 24), (4, 23), (31, 22), (10, 21), (1, 20), (22, 19), (7, 18), (24, 17), (30, 16), (20, 15), (3, 14), (28, 13), (13, 12), (14, 11), (8, 10), (6, 9), (5, 8), (17, 7), (18, 6). Among them, when k is 6, the mapping relationship between A and B is: (11, 31), (25, 30), (31, 29), (27, 28), (14, 27), (0, 26), (22, 25), (19, 24), (18, 23), (3, 22), (20, 21), (2, 20), (4, 19), (17, 18), (23, 17), (24, 16), (12, 15), (1, 14), (7, 13), (10, 12), (28, 11), (26, 10), (6, 9), (5, 8), (8, 7). Among them, when k is 7, the mapping relationship between A and B is: (7, 31), (12, 30), (2, 29), (5, 28), (26, 27), (6, 26), (27, 25), (24, 24), (4, 23), (19, 22), (1, 21), (29, 20), (9, 19), (8, 18), (13, 17), (11, 16), (28, 15), (10, 14), (25, 13), (16, 12), (30, 11), (0, 10), (21, 9), and (3, 8). When k is 8, the mapping relationship between A and B is: (7, 31), (30, 30), (17, 29), (16, 28), (19, 27), (6, 26), (29, 25), (18, 24), (10, 23), (3, 22), (24, 21), (9, 20), (21, 19), (28, 18), (31, 17), (12, 16), (23, 15), (2, 14), (15, 13), (4, 12), (27, 11), (20, 10), (25, 9). Among them, when k is 9, the mapping relationship between A and B is: (28, 31), (25, 30), (17, 29), (6, 28), (11, 27), (21, 26), (27, 25), (30, 24), (3, 23), (1, 22), (4, 21), (8, 20), (15, 19), (26, 18), (29, 17), (18, 16), (9, 15), (19, 14), (2, 13), (20, 12), (23, 11), (10, 10). Among them, when k is 10, the mapping relationship between A and B is: (23, 31), (30, 30), (3, 29), (28, 28), (14, 27), (19, 26), (9, 25), (16, 24), (29, 23), (13, 22), (26, 21), (12, 20), (18, 19), (0, 18), (15, 17), (4, 16), (20, 15), (1, 14), (25, 13), (31, 12), (21, 11). Among them, when k is 11, the mapping relationship between A and B is: (1, 31), (24, 30), (14, 29), (15, 28), (25, 27), (12, 26), (26, 25), (13, 24), (27, 23), (31, 22), (8, 21), (5, 20), (20, 19), (21, 18), (3, 17), (28, 16), (17, 15), (6, 14), (19, 13), (11, 12). Among them, the first A is the yth bit when y=0, the second A is the yth bit when y=1,…, the NK-1=32-11-1=20th A (i.e. 0) is the yth bit when y=NK-2=32-11-2=19,…, the Nk-1th A is the yth bit when y=Nk-2. Optionally, the second interlacing pattern mentioned above can also be expressed as the interlacing pattern shown in the following FIG. 14 . Optionally, the second interleaving pattern may also be expressed as an interleaving pattern similar to that shown in Table 6, Table 7, or Table 8. For example, taking k as 3 as an example, the second interleaving pattern may be an interleaving pattern shown in the following Table 9: Table 9 It can be understood that the mapping relationship between the first 4 groups A and B in the above Table 9 can be randomly determined, that is, 12, 18, 19 and 29 in A can randomly correspond to 0, 1, 2 and 3 in B without restriction. In the above two possible designs, various examples are defined starting from bit 0. It is understandable that the definition can also be started from bit 1, that is, the above 0, 1, ..., 31 can be replaced by 1, 2, ..., 32 respectively without limitation. Based on the above description, after the transmitting end device performs interleaving processing on the fourth sequence, it may also perform rate matching on the fourth sequence (such as the fifth sequence and the sixth sequence) after the interleaving processing. The lengths of the fifth sequence and the sixth sequence are both N. Among them, the transmission code length E (that is, the rate matching sequence length) can be determined according to the rate matching related information. When it is determined that the transmission code length E is not equal to N, the following rate matching method can be adopted: when the transmission code length E is less than N, puncture from back to front; when the transmission code length E is greater than N, repeat from front to back. That is, the transmitting end device may perform rate matching on the fifth sequence of length N to obtain a first rate matching sequence of length E. Alternatively, the transmitting end device may perform rate matching on the sixth sequence of length N to obtain a second rate matching sequence of length E. For example, the fourth sequence is For example, the fourth sequence can be interleaved based on the interleaving pattern (such as the first interleaving pattern or the second interleaving pattern) with reference to the following to obtain the interleaved sequence for n=0to N-1 e n =d P(n) end for Among them, e n represents the nth value in the sequence after interleaving, and P(n) represents the interleaving pattern. Refer to the following sequence after the above interleaving process Perform rate matching to obtain a rate matching sequence for j=0to E-1 f j =e j mod N end for Exemplarily, taking the information bit sequence length k corresponding to the fourth sequence of length 32 as 7, and the transmitting end device adopting the second interleaving pattern shown in FIG. 13 for interleaving processing as an example, assuming that the rate matching sequence length E is 22, it is necessary to place the values ​​of the 7th, 9th, 19th, 26th, 31st, 21st, 27th, 2nd, 23rd, and 17th bits in the fourth sequence in sequence on the 31st to 22nd bits of the sixth sequence, and randomly place the values ​​of the remaining 22 bits in the fourth sequence on the 0th to 21st bits of the sixth sequence, and discard the values ​​of the 22nd to 31st bits in the sixth sequence to obtain the second rate matching sequence. Alternatively, it can also be described as discarding the values ​​of the 7th, 9th, 19th, 26th, 31st, 21st, 27th, 2nd, 23rd, and 17th bits in the fourth sequence, and randomly arranging the values ​​of the remaining 22 bits to obtain the second rate matching sequence. In another exemplary embodiment, taking the case where the length k of the information bit sequence corresponding to the fourth sequence of length 32 is 3, and the transmitting device adopts the second interleaving pattern shown in Figure 13 for interleaving processing, assuming that the rate matching sequence length E is 4, it is necessary to place the values ​​of the 12th, 9th, 19th, 18th, 1, 15th, 14th, 29th, 16th, 10th, 28th, 23rd, 20th, 6th, 21st, 7th, 25th, 0th, 3rd, 5th, 31st, 30th, 4th, 22nd, 13th, 27th, and 8th bits in the fourth sequence in sequence on the 31st to 4th bits of the sixth sequence, and randomly place the values ​​of the remaining 4 bits in the fourth sequence on the 0th to 3rd bits of the sixth sequence, and discard the values ​​of the 4th to 31st bits in the sixth sequence to obtain a second rate matching sequence. Or it can also be described as removing the values ​​on the 12th, 9th, 19th, 18th, 1, 15, 14, 29, 16, 10, 28, 23, 20, 6, 21, 7, 2, 25, 0, 3, 5, 31, 30, 4, 22, 13, 27, and 8 bits in the fourth sequence, and randomly arranging the values ​​on the remaining 4 bits to obtain a second rate matching sequence. Based on the above description, it can be found that the larger the k is, the smaller the number of puncturing supported is, and a maximum of N-1-k puncturing positions are supported. Based on the above description of polarization coding, interleaving, and rate matching, the following Figures 15 to 19 respectively provide performance comparison diagrams of the simulation effects of LTE-RM codes and Polar codes provided by the embodiments of the present application under different code lengths and code rates. The simulation channel is an AWGN channel, the modulation mode is QPSK modulation, the coding mode is LTE-RM code, and the decoding mode is FHT decoding, or the coding mode is Polar code and the decoding mode is SCL8 decoding. Each performance comparison diagram has a total of 2 curves. Curve 1 is the performance after rate matching according to the LTE-RM code method, and curve 2 is the performance after rate matching using the Polar code method provided in the embodiment of the present application (i.e., according to the method shown in Figure 7 and the first interleaving pattern). The horizontal axis of the performance comparison diagram is the code length E after puncturing, ranging from k+1 to N (eg, 32), and the vertical axis is the SNR required to achieve BLER=0.01. The lower the curve, the better the performance. According to FIG. 15 to FIG. 17 , it can be seen that the polar code encoding method provided in the embodiment of the present application can greatly improve the encoding and decoding performance. It should be noted that, in the above method, very short codes with an information bit sequence length of 3 to 11 are used as an example for explanation. It can be understood that the length of the very short code is not limited to 3 to 11, but can also be other lengths. The information bit sequence can also be a pre-transformed polar code, a polarization adjusted convolutional (PAC) code, etc., without limitation. It should be noted that the various embodiments of the present application can be implemented independently or in combination without limitation. If there is no special explanation or logical conflict, the terms and / or descriptions of the different embodiments provided in the present application are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships. It is understandable that in the embodiments of the present application, the execution subject may execute some or all of the steps in the embodiments of the present application, and these steps or operations are only examples. The embodiments of the present application may also execute other operations or variations of various operations. In addition, the various steps may be executed in different orders presented in the embodiments of the present application, and it is possible that not all operations in the embodiments of the present application need to be executed. The above mainly introduces the solution provided by the embodiment of the present application from the perspective of interaction between devices. It is understandable that, in order to realize the above functions, each device includes a hardware structure and / or software module corresponding to each function. Those skilled in the art should easily realize that, in combination with the algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application. The embodiment of the present application can divide the functional modules of each device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In the case of dividing each functional module according to each function, Figure 20 shows a communication device 200, which can execute the actions performed by the sending end device in the method shown in Figures 7 to 19 above. All relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and the technical effects that can be obtained can refer to the above method embodiment, which will not be repeated here. Wherein, the communication device 200 may include a transceiver module 2001 and a processing module 2002. Exemplarily, the communication device 200 may be a communication device, or a chip applied to a communication device, or other combined devices, components, etc. having the functions of the above-mentioned communication device. When the communication device 200 is a communication device, the transceiver module 2001 may be a transceiver, and the transceiver may include an antenna and a radio frequency circuit, etc.; the processing module 2002 may be a processor (or a processing circuit), such as a baseband processor, and the baseband processor may include one or more CPUs. When the communication device 200 is a component having the functions of the above-mentioned communication device, the transceiver module 2001 may be a radio frequency unit; the processing module 2002 may be a processor (or a processing circuit), such as a baseband processor. When the communication device 200 is a chip system, the transceiver module 2001 may be an input and output interface of a chip (such as a baseband chip); the processing module 2002 may be a processor (or a processing circuit) of the chip system, and may include one or more central processing units. It should be understood that the transceiver module 2001 in the embodiment of the present application can be implemented by a transceiver or a transceiver-related circuit component; the processing module 2002 can be implemented by a processor or a processor-related circuit component (or, referred to as a processing circuit). For example, the transceiver module 2001 can be used to perform all transceiver operations performed by the communication device in the embodiments shown in Figures 7 to 19, and / or to support other processes of the technology described in this document; the processing module 2002 can be used to perform all operations except the transceiver operations performed by the communication device in the embodiments shown in Figures 7 to 19, and / or to support other processes of the technology described in this document. As another possible implementation, the transceiver module 2001 in FIG20 may be replaced by a transceiver, which may integrate the functions of the transceiver module 2001; the processing module 2002 may be replaced by a processor, which may integrate the functions of the processing module 2002. Furthermore, the communication device 200 shown in FIG20 may also include a memory. Alternatively, when the processing module 2002 is replaced by a processor and the transceiver module 2001 is replaced by a transceiver, the communication device 200 involved in the embodiment of the present application may also be the communication device 210 shown in FIG. 21, wherein the processor may be a logic circuit 2101 and the transceiver may be an interface circuit 2102. Furthermore, the communication device 210 shown in FIG. 21 may also include a memory 2103. The embodiments of the present application also provide a computer program product, which can implement the functions of any of the above method embodiments when executed by a computer. The embodiments of the present application also provide a computer program, which can implement the functions of any of the above method embodiments when executed by a computer. The embodiment of the present application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be completed by a computer program to instruct the relevant hardware, and the program can be stored in the above computer-readable storage medium. When the program is executed, it may include the processes of the above method embodiments. The computer-readable storage medium can be an internal storage unit of a terminal (including a data sending end and / or a data receiving end) in any of the above embodiments, such as a hard disk or memory of the terminal. The above computer-readable storage medium can also be an external storage device of the above terminal, such as a plug-in hard disk equipped on the above terminal, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. Further, the above computer-readable storage medium can also include both an internal storage unit of the above terminal and an external storage device. The above computer-readable storage medium is used to store the above computer program and other programs and data required by the above terminal. The above computer-readable storage medium can also be used to temporarily store data that has been output or is to be output. It should be noted that the terms "first" and "second" in the specification, claims and drawings of this application are used to distinguish different objects rather than to describe a specific order. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "multiple" means two or more. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices. It should be understood that in the present application, "at least one (item)" means one or more. "Multiple" means two or more. "At least two (items)" means two or three and more than three. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b and c can be single or multiple. “When” and “if” both mean that corresponding treatment will be taken under certain objective circumstances, not limiting the time, nor requiring judgment actions when implementing, nor implying other limitations. In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding. In this application, "sending information to ... (terminal device)" can be understood as the destination of the information being the terminal device. It can include sending information to the terminal device directly or indirectly. "Receiving information from ... (terminal device)" can be understood as the source of the information being the terminal device, which can include receiving information from the terminal device directly or indirectly. The information may be processed as necessary between the source and destination of the information, such as format changes, but the destination can understand the valid information from the source. Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can essentially or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

Claims

1. A polar code encoding method, characterized in that: include: According to the reliability sequence, an information bit sequence with a length of k is mapped to k bits of a first sequence with a length of N to obtain a second sequence; wherein the length of the reliability sequence is N, and the second sequence includes k information bits, x parity check PC bits and Nkx frozen bits, k≤K≤N, 1≤x, K is the maximum length of the information bit sequence, and k, K, N, and x are all positive integers; Multiply the second sequence by the first matrix to obtain a third sequence; wherein the first matrix is ​​a matrix with all zeros below the diagonal and all ones on the diagonal, the column weight of the column corresponding to the PC bit in the first matrix is ​​greater than 1, the column weight of the column corresponding to the frozen bit or the information bit is equal to 1, and the number of columns with column weight greater than 1 in the first matrix is ​​less than or equal to NK; Polarization encoding is performed on the third sequence to obtain a fourth sequence.

2. The method according to claim 1, characterized in that The step of multiplying the second sequence by the first matrix to obtain a third sequence comprises: Determine one or more of the PC bits and the bit positions of the PC bit check according to the first matrix; According to the value of the bit of the PC bit check, the value of the PC bit in the second sequence is determined to obtain the third sequence.

3. The method according to claim 1 or 2, characterized in that: The reliability sequence is determined according to one or more of the following: reliability, code spectrum, and performance optimization result.

4. The method according to any one of claims 1 to 3, characterized in that: The column weight of the first matrix is ​​less than or equal to a first value.

5. The method according to any one of claims 1 to 4, characterized in that: The first matrix is:

6. The method according to any one of claims 1 to 4, characterized in that: The first matrix is:

7. The method according to any one of claims 1 to 6, characterized in that: The third sequence includes one or more of the PC bits, and the difference between the number of the PC bits and the number of the bit of the PC bit check is a prime number.

8. The method according to claim 7, characterized in that The PC bits of the third sequence are one or more of the following bit positions of the third sequence: 16, 18, 21, or 25.

9. The method according to claim 8, characterized in that When the PC bit is the 16th bit in the third sequence, the bit for the PC bit check is the 13th bit in the third sequence; or When the PC bit is the 18th bit in the third sequence, the bit of the PC bit check is one or more of the following bit positions in the third sequence: 11, 13, 15; or When the PC bit is the 21st bit in the third sequence, the bit for the PC bit check is the 14th bit in the third sequence; or When the PC bit is the 25th bit in the third sequence, the bit for the PC bit check is the 22nd bit in the third sequence.

10. The method according to claim 7, characterized in that The PC bits of the third sequence are one or more of the following bit positions of the third sequence: 19, 21, 25, or 26.

11. The method according to claim 10, characterized in that When the PC bit is the 19th bit in the third sequence, the bit for the PC bit check is the 14th bit in the third sequence; or When the PC bit is the 21st bit in the third sequence, the bit of the PC bit check is one or more of the following bit positions in the third sequence: 11, 14; or When the PC bit is the 25th bit in the third sequence, the bit of the PC bit check is one or more of the following bits in the third sequence: 14, 22; or When the PC bit is the 26th bit in the third sequence, the bit for the PC bit check is the 13th bit in the third sequence.

12. The method according to any one of claims 1 to 11, characterized in that: The method further comprises: Interleaving the fourth sequence according to the first interleaving pattern to obtain a fifth sequence; Perform rate matching on the fifth sequence to obtain a first rate matching sequence.

13. The method according to claim 12, characterized in that The first interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the fifth sequence; Among them, the mapping relationship between A and B is: (5, 31), (26, 30), (11, 29), (9, 28), (28, 27), (7, 26), (30, 25), (16, 24), (31, 23), (21, 22), (10, 21), (24, 20), (27, 19), (6, 18), (3, 17), (12, 16), (17, 15), (8, 14), (13, 13), (0, 12), (2, 11), (1, 10), (4, 9), (14, 8), (25, 7), (23, 6), (22, 5), (19, 4).

14. The method according to claim 12, characterized in that The first interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the fifth sequence; Among them, the mapping relationship between A and B is: (4, 31), (22, 30), (27, 29), (17, 28), (8, 27), (2, 26), (15, 25), (21, 24), (29, 23), (23, 22), (6, 21), (26, 20), (20, 19), (7, 18), (0, 17), (13, 16), (19, 15), (11, 14), (14, 13), (16, 12), (25, 11), (3, 10), (10, 9), (5, 8), (12, 7), (1, 6), (18, 5), (24, 4).

15. The method according to any one of claims 1 to 11, characterized in that: The method further comprises: Interleaving the fourth sequence according to the second interleaving pattern to obtain a sixth sequence; Perform rate matching on the sixth sequence to obtain a second rate matching sequence.

16. The method according to claim 15, characterized in that The second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; The mapping relationship between A and B is: (12, 31), (9, 30), (19, 29), (18, 28), (1, 27), (15, 26), (14, 25), (29, 24), (16, 23), (10, 22), (28, 21), (23, 20), (20, 19), (6, 18), (21, 17), (7, 16), (2, 15), (25, 14), (0, 13), (3, 12), (5, 11), (31, 10), (30, 9), (4, 8), (22, 7), (13, 6), (27, 5), (8, 4); or The mapping relationship between A and B is: (18, 31), (29, 30), (9, 29), (12, 28), (27, 27), (22, 26), (23, 25), (26, 24), (4, 23), (0, 22), (7, 21), (14, 20), (8, 19), (19, 18), (1, 17), (21, 16), (13, 15), (11, 14), (17, 13), (20, 12), (16, 11), (15, 10), (6, 9), (10, 8), (28, 7), (25, 6), (24, 5); or The mapping relationship between A and B is: (2, 31), (20, 30), (12, 29), (25, 28), (8, 27), (22, 26), (16, 25), (5, 24), (29, 23), (14, 22), (23, 21), (15, 20), (3, 19), (11, 18), (10, 17), (17, 16), (0, 15), (30, 14), (18, 13), (27, 12), (4, 11), (19, 10), (21, 9), (6, 8), (26, 7), (9, 6); or The mapping relationship between A and B is: (19, 31), (23, 30), (16, 29), (18, 28), (29, 27), (0, 26), (21, 25), (8, 24), (11, 23), (4, 22), (13, 21), (2, 20), (20, 19), (24, 18), (25, 17), (6, 16), (28, 15), (14, 14), (10, 13), (9, 12), (31, 11), (26, 10), (7, 9), (17, 8), (1, 7); or The mapping relationship between A and B is: (7, 31), (9, 30), (19, 29), (26, 28), (31, 27), (21, 26), (27, 25), (2, 24), (23, 23), (17, 22), (10, 21), (30, 20), (25, 19), (24, 18), (0, 17), (16, 16), (4, 15), (11, 14), (20, 13), (12, 12), (29, 11), (18, 10), (13, 9), (3, 8); or The mapping relationship between A and B is: (15, 31), (16, 30), (9, 29), (14, 28), (17, 27), (24, 26), (21, 25), (20, 24), (5, 23), (1, 22), (7, 21), (30, 20), (11, 19), (6, 18), (2, 17), (3, 16), (8, 15), (22, 14), (12, 13), (23, 12), (19, 11), (10, 10), (29, 9); or The mapping relationship between A and B is: (17, 31), (21, 30), (15, 29), (14, 28), (4, 27), (24, 26), (8, 25), (29, 24), (19, 23), (16, 22), (7, 21), (2, 20), (9, 19), (25, 18), (26, 17), (23, 16), (28, 15), (30, 14), (13, 13), (6, 12), (22, 11), (0, 10); or The mapping relationship between A and B is: (28, 31), (29, 30), (14, 29), (26, 28), (8, 27), (23, 26), (24, 25), (30, 24), (0, 23), (31, 22), (10, 21), (5, 20), (20, 19), (4, 18), (16, 17), (12, 16), (9, 15), (21, 14), (1, 13), (11, 12), (22, 11); or Among them, the mapping relationship between A and B is: (22, 31), (19, 30), (28, 29), (9, 28), (4, 27), (6, 26), (14, 25), (11, 24), (3, 23), (13, 22), (0, 21), (15, 20), (26, 19), (24, 18), (27, 17), (18, 16), (21, 15), (17, 14), (20, 13), (12, 12).

17. The method according to claim 15, characterized in that The second interleaving pattern is used to indicate that the value on the Ath bit position of the fourth sequence is swapped and placed on the Bth bit position of the sixth sequence; The mapping relationship between A and B is: (5, 31), (11, 30), (24, 29), (30, 28), (13, 27), (20, 26), (22, 25), (3, 24), (4, 23), (25, 22), (31, 21), (6, 20), (10, 19), (8, 18), (21, 17), (15, 16), (9, 15), (2, 14), (0, 13), (27, 12), (14, 11), (16, 10), (17, 9), (23, 8), (28, 7), (26, 6), (1, 5), (7, 4); or The mapping relationship between A and B is: (16, 31), (28, 30), (10, 29), (30, 28), (19, 27), (7, 26), (13, 25), (9, 24), (11, 23), (6, 22), (8, 21), (26, 20), (21, 19), (20, 18), (23, 17), (25, 16), (0, 15), (17, 14), (27, 13), (22, 12), (18, 11), (15, 10), (5, 9), (12, 8), (2, 7), (29, 6), (24, 5); or The mapping relationship between A and B is: (9, 31), (19, 30), (11, 29), (12, 28), (21, 27), (0, 26), (29, 25), (2, 24), (4, 23), (31, 22), (10, 21), (1, 20), (22, 19), (7, 18), (24, 17), (30, 16), (20, 15), (3, 14), (28, 13), (13, 12), (14, 11), (8, 10), (6, 9), (5, 8), (17, 7), (18, 6); or The mapping relationship between A and B is: (11, 31), (25, 30), (31, 29), (27, 28), (14, 27), (0, 26), (22, 25), (19, 24), (18, 23), (3, 22), (20, 21), (2, 20), (4, 19), (17, 18), (23, 17), (24, 16), (12, 15), (1, 14), (7, 13), (10, 12), (28, 11), (26, 10), (6, 9), (5, 8), (8, 7); or The mapping relationship between A and B is: (7, 31), (12, 30), (2, 29), (5, 28), (26, 27), (6, 26), (27, 25), (24, 24), (4, 23), (19, 22), (1, 21), (29, 20), (9, 19), (8, 18), (13, 17), (11, 16), (28, 15), (10, 14), (25, 13), (16, 12), (30, 11), (0, 10), (21, 9), (3, 8); or The mapping relationship between A and B is: (7, 31), (30, 30), (17, 29), (16, 28), (19, 27), (6, 26), (29, 25), (18, 24), (10, 23), (3, 22), (24, 21), (9, 20), (21, 19), (28, 18), (31, 17), (12, 16), (23, 15), (2, 14), (15, 13), (4, 12), (27, 11), (20, 10), (25, 9); or The mapping relationship between A and B is: (28, 31), (25, 30), (17, 29), (6, 28), (11, 27), (21, 26), (27, 25), (30, 24), (3, 23), (1, 22), (4, 21), (8, 20), (15, 19), (26, 18), (29, 17), (18, 16), (9, 15), (19, 14), (2, 13), (20, 12), (23, 11), (10, 10); or The mapping relationship between A and B is: (23, 31), (30, 30), (3, 29), (28, 28), (14, 27), (19, 26), (9, 25), (16, 24), (29, 23), (13, 22), (26, 21), (12, 20), (18, 19), (0, 18), (15, 17), (4, 16), (20, 15), (1, 14), (25, 13), (31, 12), (21, 11); or Among them, the mapping relationship between A and B is: (1, 31), (24, 30), (14, 29), (15, 28), (25, 27), (12, 26), (26, 25), (13, 24), (27, 23), (31, 22), (8, 21), (5, 20), (20, 19), (21, 18), (3, 17), (28, 16), (17, 15), (6, 14), (19, 13), (11, 12).

18. A communication device, characterized in that: include: A processing module, configured to map an information bit sequence of length k to k bits of a first sequence of length N according to a reliability sequence, to obtain a second sequence; wherein the length of the reliability sequence is N, the second sequence includes k information bits, x parity check PC bits and Nkx frozen bits, k≤K≤N, 1≤x, K is the maximum length of the information bit sequence, and k, K, N, and x are all positive integers; The processing module is further used to multiply the second sequence by the first matrix to obtain a third sequence; wherein the first matrix is ​​a matrix with all zeros below the diagonal and all ones on the diagonal, the column weight of the column corresponding to the PC bit in the first matrix is ​​greater than 1, the column weight of the column corresponding to the frozen bit or the information bit is equal to 1, and the number of columns with column weight greater than 1 in the first matrix is ​​less than or equal to NK; The transceiver module is further used to perform polarization encoding on the third sequence to obtain a fourth sequence.

19. A communication device, characterized in that: The communication device includes a processor; the processor is used to run a computer program or an instruction so that the communication device performs the polar code encoding method according to any one of claims 1 to 17.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions or programs. When the computer instructions or programs are executed on a computer, the polar code encoding method according to any one of claims 1 to 17 is executed.

21. A computer program product, characterized in that The computer program product includes computer instructions; when part or all of the computer instructions are run on a computer, the polar code encoding method according to any one of claims 1 to 17 is executed.

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