Display panel and preparation method therefor, and display apparatus

Abstract

A display panel, the display panel having a display region, and a frame region which surrounds the display region. The display panel comprises: a substrate; an electrically conductive shielding layer, an orthographic projection thereof onto the substrate being at least located in the frame region; a shift register circuit and a first potential line, which are located in the frame region and on the side of the electrically conductive shielding layer facing away from the substrate; and a first insulating layer, located between the electrically conductive shielding layer and the first potential line and the shift register circuit, the shift register circuit and the first potential line being sequentially arranged along a direction away from the display region; the shift register circuit comprises multiple first-type transistors, and the orthographic projection of the electrically conductive shielding layer onto the substrate covers the orthographic projections of at least a portion of the first-type transistors onto the substrate; the orthographic projections of the electrically conductive shielding layer and the first potential line onto the substrate at least partially overlap, a first opening is formed in the first insulating layer, the orthographic projection of the first opening onto the substrate is located in a region where the orthographic projections of the electrically conductive shielding layer and the first potential line overlap, and at least a local region of the electrically conductive shielding layer is electrically connected to the first potential line via the first opening.

Description

Display panel, manufacturing method thereof, and display device Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display panel, a manufacturing method thereof, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, brilliant colors, high contrast, and fast response rate.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a display panel having a display area and a frame area, wherein the frame area surrounds the display area, wherein the display panel includes: a substrate;

[0005] a conductive shielding layer, located on one side of the substrate, with its orthographic projection on the substrate at least located in the border area;

[0006] a shift register circuit, located in the border area and on a side of the conductive shielding layer facing away from the substrate;

[0007] a first potential line, located in the border area and on a side of the conductive shielding layer facing away from the substrate;

[0008] a first insulating layer, located between the conductive shielding layer, the first potential line, and the shift register circuit;

[0009] The shift register circuit and the first potential line are arranged in sequence in a direction away from the display area;

[0010] The shift register circuit includes a plurality of first-type transistors, and the orthographic projection of the conductive shielding layer on the substrate covers at least a portion of the orthographic projection of the first-type transistors on the substrate;

[0011] The orthographic projections of the conductive shielding layer and the first potential line on the substrate at least partially overlap, a first opening is provided in the first insulating layer, the orthographic projection of the first opening on the substrate is located in the overlapping area of ​​the orthographic projections of the conductive shielding layer and the first potential line, and at least a partial area of ​​the conductive shielding layer is electrically connected to the first potential line through the first opening.

[0012] In some embodiments, the first potential line includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are sequentially stacked away from the substrate, and the orthographic projections of the first conductive layer and the second conductive layer on the substrate at least partially overlap;

[0013] The first conductive layer is electrically connected to at least a partial area of ​​the conductive shielding layer through the first opening;

[0014] The display panel also includes a first flat layer located between the first conductive layer and the second conductive layer, a second opening being provided in the first flat layer, the orthographic projection of the second opening on the substrate being located in an overlapping region of the orthographic projections of the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer being electrically connected through the second opening.

[0015] In some embodiments, the first potential line includes a first conductive layer, a second conductive layer, and a third conductive layer, wherein the first conductive layer, the third conductive layer, and the second conductive layer are sequentially stacked away from the substrate, and the orthographic projections of any two adjacent ones of the first conductive layer, the third conductive layer, and the second conductive layer on the substrate at least partially overlap;

[0016] The first conductive layer is electrically connected to at least a partial area of ​​the conductive shielding layer through the first opening;

[0017] The display panel further includes a first flat layer located between the first conductive layer and the third conductive layer, a second opening being defined in the first flat layer, an orthographic projection of the second opening on the substrate being located in an overlapping region of the orthographic projections of the first conductive layer and the third conductive layer, and the first conductive layer and the third conductive layer being electrically connected via the second opening;

[0018] The display panel also includes a second flat layer located between the third conductive layer and the second conductive layer, a third opening being provided in the second flat layer, the orthographic projection of the third opening on the substrate being located in an overlapping region of the orthographic projections of the second conductive layer and the third conductive layer, and the third conductive layer and the second conductive layer being electrically connected through the third opening.

[0019] In some embodiments, the first type of transistor includes a gate, an active layer, a first electrode, and a second electrode, wherein the first electrode and the second electrode are arranged in the same layer, and the gate, the active layer, and the first electrode are respectively located in different layers.

[0020] The first conductive layer is provided on the same layer as the first electrode and the second electrode;

[0021] The display panel further includes a light emitting element located in the display area.

[0022] The light emitting element includes a first electrode, a light emitting functional layer and a second electrode stacked sequentially away from the substrate.

[0023] The second conductive layer is provided on the same layer as the first electrode;

[0024] The second electrode further extends to the border area and partially overlaps with the orthographic projection of the second conductive layer on the substrate.

[0025] The display panel further includes a second insulating layer located between the first electrode and the second electrode, and the second insulating layer extends from the display area to the frame area, and a fourth opening is formed in a portion of the second insulating layer located in the frame area.

[0026] The second electrode is electrically connected to the second conductive layer through the fourth opening.

[0027] In some embodiments, the display panel further includes a pixel circuit located in the display area and between the light emitting element and the substrate.

[0028] The pixel circuit includes a conductive connection structure and a plurality of second-type transistors, wherein the plurality of second-type transistors and the plurality of first-type transistors are arranged in the same layer, and the conductive connection structure is located on a side of the second-type transistors away from the substrate.

[0029] The first planar layer further extends between the second type transistor and the conductive connection structure. A fifth opening is further formed in a portion of the first planar layer located in the display area. The first electrode of the second type transistor is electrically connected to the conductive connection structure through the fifth opening.

[0030] The second planar layer further extends between the conductive connection structure and the first electrode, and a sixth opening is further formed in a portion of the second planar layer located in the display area, and the conductive connection structure is electrically connected to the first electrode through the sixth opening;

[0031] The third conductive layer is provided on the same layer as the conductive connection structure.

[0032] In some embodiments, the first dam and the second dam are further included, located in the border area and on a side of the second conductive layer away from the substrate.

[0033] The first dam and the second dam are sequentially arranged in a direction away from the display area and spaced apart from each other, and the first dam and the second dam at least partially overlap with the orthographic projection of the first potential line on the substrate.

[0034] An orthographic projection of the first opening on the substrate is located between the first dam and an orthographic projection of the shift register circuit on the substrate.

[0035] In some embodiments, the first dam and the second dam are further included, located in the border area and on a side of the second conductive layer away from the substrate.

[0036] The first dam and the second dam are sequentially arranged in a direction away from the display area and spaced apart from each other, and the first dam and the second dam at least partially overlap with the orthographic projection of the first potential line on the substrate.

[0037] An orthographic projection of the first opening on the substrate is located between orthographic projections of the first dam and the second dam on the substrate.

[0038] In some embodiments, the first potential line surrounds at least three sides of the frame area outside the display area.

[0039] The first openings are continuously distributed along an extending direction of the first potential line.

[0040] In some embodiments, the first potential line surrounds at least three sides of the frame area outside the display area.

[0041] There are multiple first openings, and the multiple first openings are sequentially spaced and distributed along the extending direction of the first potential line.

[0042] In some embodiments, the conductive shielding layer located in the border area is planar.

[0043] The orthographic projection of the conductive shielding layer on the substrate at least covers the orthographic projections of all the first-type transistors in the shift register circuit on the substrate.

[0044] In some embodiments, a plurality of hollows are provided in the conductive shielding layer located in the border area.

[0045] The orthographic projection of the area of ​​the conductive shielding layer outside the hollowing out on the substrate at least covers the orthographic projection of all the first-type transistors in the shift register circuit on the substrate.

[0046] In some embodiments, the conductive shielding layer located in the border area includes a first area and a second area, and the first area and the second area are disconnected from each other.

[0047] The first region at least partially overlaps with an orthographic projection of the first conductive layer on the substrate, and the second region at least partially overlaps with an orthographic projection of the shift register circuit on the substrate.

[0048] The first region is electrically connected to the first conductive layer through the first opening, and the second region is electrically connected to a second potential line.

[0049] In some embodiments, there are multiple first openings, and the multiple first openings are sequentially spaced apart along a line width direction of the first potential line away from the display area.

[0050] In some embodiments, the first potential line surrounds at least three sides of the frame area outside the display area.

[0051] The first openings are continuously distributed along the extending direction of the first potential line.

[0052] In some embodiments, the first potential line surrounds at least three sides of the frame area outside the display area.

[0053] Each of the first openings includes a plurality of sub-openings, and the plurality of sub-openings of each of the first openings are sequentially spaced and distributed along an extending direction of the first potential line.

[0054] In some embodiments, the display panel further has a binding connection area located on at least one side of the frame area outside the display area.

[0055] The display panel further includes a plurality of first wirings and a plurality of second potential lines, wherein at least a portion of the plurality of first wirings, the plurality of second potential lines, and the first potential line are located in the binding connection area, and the plurality of first wirings and the plurality of second potential lines are located on a side of the conductive shielding layer away from the substrate.

[0056] The plurality of first wirings are electrically connected to the shift register circuit,

[0057] The conductive shielding layer further includes a third area, the orthographic projection of the third area on the substrate is located in the binding connection area, and the orthographic projection of the third area on the substrate at least covers the orthographic projections of the plurality of first traces on the substrate.

[0058] The third area is disconnected from the first area and the second area, and is electrically connected to the first potential line located in the binding connection area, or the third area is electrically connected to the second potential line located in the binding connection area.

[0059] In some embodiments, the conductive shielding layer further includes a fourth area, the orthographic projection of the fourth area on the substrate is located in the display area,

[0060] The orthographic projection of the fourth region on the substrate covers at least a portion of the orthographic projection of the second type transistor on the substrate,

[0061] The fourth region is disconnected from the first region, the second region, and the third region, and is electrically connected to the second potential line.

[0062] In some embodiments, the shift register circuit includes a first gate driving shift register circuit, a light emitting control shift register circuit, and a second gate driving shift register circuit.

[0063] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel.

[0064] In a third aspect, an embodiment of the present disclosure further provides a method for manufacturing a display panel, which includes: preparing a conductive shielding layer on a substrate;

[0065] preparing a first insulating layer, a shift register circuit and a first potential line on a side of the conductive shielding layer facing away from the substrate;

[0066] Preparing the shift register circuit includes preparing a plurality of first-type transistors, wherein the orthographic projection of the conductive shielding layer on the substrate covers at least a portion of the orthographic projection of the first-type transistors on the substrate;

[0067] Preparing the first insulating layer includes preparing a pattern of first openings, and at least a partial area of ​​the conductive shielding layer is electrically connected to the first potential line through the first openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0069] FIG1a is a schematic diagram showing the principle of static electricity causing the transistor characteristics in the gate shift register circuit to be forward biased.

[0070] FIG1 b is a circuit diagram of a gate shift register circuit.

[0071] FIG1c is a schematic diagram showing a comparison between a gate shift register circuit with normal pulse output without screen flickering and a gate shift register circuit with multi-pulse output with screen flickering.

[0072] FIG. 2 a is a schematic top view of a display panel according to an embodiment of the present disclosure.

[0073] FIG. 2 b is a schematic cross-sectional view of the structure along the AA′ section line in FIG. 2 a .

[0074] FIG. 2 c is a schematic cross-sectional view of the structure along the BB′ section line in FIG. 2 a .

[0075] FIG3 a is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0076] FIG3 b is a schematic cross-sectional view of a portion of a shift register circuit and a portion of a display area in an embodiment of the present disclosure.

[0077] FIG. 4 a is a schematic cross-sectional view of another structure along the AA′ section line in FIG. 2 a .

[0078] FIG4 b is a schematic cross-sectional view of another structure along the BB′ section line in FIG2 a .

[0079] FIG5a is an enlarged schematic top view of portion C in FIG2a.

[0080] FIG5 b is a schematic cross-sectional view of another structure along the AA′ section line in FIG2 a .

[0081] FIG5c is a schematic cross-sectional view of another structure along the AA′ section line in FIG2a.

[0082] FIG5 d is another enlarged schematic top view of portion C in FIG2 a .

[0083] FIG6 a is a schematic top view of another display panel according to an embodiment of the present disclosure.

[0084] FIG6 b is a schematic top view of another display panel according to an embodiment of the present disclosure.

[0085] FIG6c is a schematic cross-sectional view of the structure along the DD′ section line in FIG6b.

[0086] FIG6 d is a schematic cross-sectional view of another structure along the DD′ section line in FIG6 b .

[0087] FIG7 a is a partial top view schematically showing the area where the shift register circuit is located in an embodiment of the present disclosure.

[0088] FIG7 b is another partial top view schematic diagram of the area where the shift register circuit is located in an embodiment of the present disclosure.

[0089] FIG8 a is another partial top view schematically showing the area where the shift register circuit is located in an embodiment of the present disclosure.

[0090] FIG8 b is another partial top view schematic diagram of the area where the shift register circuit is located in an embodiment of the present disclosure.

[0091] FIG. 9 a is a schematic cross-sectional view of another structure along the AA′ section line in FIG. 2 a .

[0092] FIG9 b is a schematic cross-sectional view of another structure along the AA′ section line in FIG2 a .

[0093] FIG10 a is a schematic top view of another display panel according to an embodiment of the present disclosure.

[0094] FIG10 b is a schematic cross-sectional view of the structure along the EE′ section line in FIG10 a .

[0095] FIG10c is a schematic cross-sectional view of another structure along the EE′ section line in FIG10a.

[0096] FIG10 d is a schematic top view of another display panel according to an embodiment of the present disclosure.

[0097] FIG. 11 a is a schematic top view of a display panel binding connection area in an embodiment of the present disclosure.

[0098] FIG11 b is an enlarged schematic diagram of portion F in FIG11 a.

[0099] FIG11c is an enlarged schematic diagram of portion G in FIG11a.

[0100] FIG. 11 d is a schematic top view of the third region of the conductive shielding layer within the binding connection region of the display panel in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0101] To enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display panel, a manufacturing method thereof, and a display device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0102] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0103] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0104] Flexible AMOLED (Active-matrix organic light-emitting diode) wearable products (such as watches and bracelets) have a full copper foil on the back to channel and release static electricity. However, for ease of use, AMOLED wearable products often incorporate NFC (Near Field Communication) and antennas on the back of the copper foil.

[0105] The setting of the entire copper foil on the back side of the wearable product will shield the NFC signal and the antenna signal, affecting the normal transmission of the NFC signal and the antenna signal. Therefore, the current trend is to not set copper foil on the back side of the wearable product or to set copper foil partially. Referring to Figures 1a, 1b and 1c, Figure 1a is a schematic diagram of the principle of static electricity causing the transistor characteristics in the gate shift register circuit to be forward biased; Figure 1b is a circuit diagram of a gate shift register circuit; Figure 1c is a comparative schematic diagram of the gate shift register circuit with normal pulse output without screen flickering and with multiple pulse outputs causing screen flickering. The absence of copper foil or the partial setting of copper foil will weaken the anti-static ability of the wearable product screen, and the negative static charge will easily accumulate and remain in the back film layer of the screen, causing the transistor characteristics (i.e., Gate GOA TFT) in the gate shift register circuit in the screen to be forward biased, resulting in multiple pulse outputs (mainly affected by the forward bias of T2), inducing screen flickering defects.

[0106] Referring to Figure 1a, if the adverse phenomenon can be reproduced through an electrostatic field test of a certain intensity (for example, -6KV) or a belt friction wearable product screen cover, essentially there is a negative charge accumulated on the surface of the screen cover, the negative charge is conducted downward along the edge sides of the screen, and finally accumulated in the overall back film such as the foam and copper foil on the back of the screen.

[0107] Currently, the main electrostatic protection measures for AMOLED wearable products include using a metal middle frame for the entire device and adding partial copper foil on the back of the screen.

[0108] In order to solve the problem of poor screen flickering caused by the lack of copper foil or partial copper foil setting on the back side of current AMOLED wearable products, on the first hand, an embodiment of the present disclosure provides a display panel, referring to Figures 2a, 2b and 2c, Figure 2a is a top view schematic diagram of a display panel in the embodiment of the present disclosure; Figure 2b is a structural cross-sectional schematic diagram along the AA' section line in Figure 2a; Figure 2c is a structural cross-sectional schematic diagram along the BB' section line in Figure 2a; wherein, the display panel has a display area 101 and a frame area 102, the frame area 102 surrounds the display area 101, and the display panel includes: a substrate 1; a conductive shielding layer 2, located on one side of the substrate 1, and its orthographic projection on the substrate 1 is at least located in the frame area 102; a shift register circuit 3, located in the frame area 102 , and is located on the side of the conductive shielding layer 2 away from the substrate 1; the first potential line 4 is located in the frame area 102, and is located on the side of the conductive shielding layer 2 away from the substrate 1; the first insulating layer 5 is located between the conductive shielding layer 2 and the first potential line 4 and the shift register circuit 3; the shift register circuit 3 and the first potential line 4 are arranged in sequence along the direction away from the display area 101; the shift register circuit 3 includes a plurality of first-class transistors, and the positive projection of the conductive shielding layer 2 on the substrate 1 covers at least part of the positive projection of the first-class transistors on the substrate 1; the positive projections of the conductive shielding layer 2 and the first potential line 4 on the substrate 1 at least partially overlap, and a first opening 50 is opened in the first insulating layer 5, and at least a local area of ​​the conductive shielding layer 2 is electrically connected to the first potential line 4 through the first opening 50.

[0109] By setting a conductive shielding layer 2 under the shift register circuit 3, the positive projection of the conductive shielding layer 2 on the substrate 1 covers the positive projection of at least part of the first type of transistors in the shift register circuit 3 on the substrate 1, and at least a local area of ​​the conductive shielding layer 2 is electrically connected to the first potential line 4 through the first opening 50, so that at least a local area of ​​the conductive shielding layer 2 has a first potential, and at the same time, at least a local area of ​​the conductive shielding layer 2 is connected to the first potential line 4 in the first opening 50 and surrounded to form a three-dimensional shielding structure. The three-dimensional shielding structure can shield at least part of the first type of transistors in the shift register circuit 3 to prevent the static electricity accumulated on the back side of the substrate 1 from affecting the characteristics of at least part of the first type of transistors, thereby avoiding the display panel from flickering, and at the same time enhancing the anti-static ability of the display panel and improving the display panel's ability to resist static electricity abnormal display flicker.

[0110] In some embodiments, referring to FIG3a, which is a circuit diagram of a pixel circuit in an embodiment of the present disclosure, the shift register circuit 3 includes a first gate drive shift register circuit, a light emitting control shift register circuit, and a second gate drive shift register circuit. The first gate drive shift register circuit is used to provide a drive signal for the gates of the second transistor T2 and the fourth transistor T4 in the pixel circuit; the light emitting control shift register circuit is used to provide a drive signal for the gates of the fifth transistor T5 and the sixth transistor T6 in the pixel circuit; and the second gate drive shift register circuit is used to provide a drive signal for the gates of the first transistor T1 and the seventh transistor T7 in the pixel circuit. In the pixel circuit, the first transistor T1 and the second transistor T2 may be oxide semiconductor thin film transistors, and the other transistors may be amorphous silicon thin film transistors or polycrystalline silicon thin film transistors.

[0111] In some embodiments, referring to Figures 2b and 2c, the first potential line 4 includes a first conductive layer 41 and a second conductive layer 42, which are stacked in sequence away from the substrate 1, and the orthographic projections of the first conductive layer 41 and the second conductive layer 42 on the substrate 1 at least partially overlap; the first conductive layer 41 is electrically connected to at least a local area of ​​the conductive shielding layer 2 through a first opening 50; the display panel also includes a first flat layer 6, which is located between the first conductive layer 41 and the second conductive layer 42, and a second opening 60 is opened in the first flat layer 6, and the orthographic projection of the second opening 60 on the substrate 1 is located in the overlapping area of ​​the orthographic projections of the first conductive layer 41 and the second conductive layer 42, and the first conductive layer 41 and the second conductive layer 42 are electrically connected through the second opening 60.

[0112] In some embodiments, referring to Figure 2b, the portion of the conductive shielding layer 2 located in the border area 102 is connected as a whole, that is, the portion of the conductive shielding layer 2 located in the border area 102 is not partitioned, and the portion of the conductive shielding layer 2 located in the border area 102 is electrically connected to the first conductive layer 41 through the first opening 50.

[0113] In some embodiments, referring to FIG3b, a schematic cross-sectional view of a portion of a shift register circuit and a portion of a display area in an embodiment of the present disclosure is shown, wherein the first type transistor 31 includes a gate 310, an active layer 311, a first electrode 312, and a second electrode 313. The first electrode 312 and the second electrode 313 are arranged in the same layer, the gate 310, the active layer 311, and the first electrode 312 are respectively located in different layers, and the first conductive layer 41 is arranged in the same layer as the first electrode 312 and the second electrode 313; the display panel further includes a light-emitting element 7, which is located in the display area 101, and the light-emitting element 7 includes a first electrode 312 and a second electrode 313, which are sequentially away from the substrate. 1, a first electrode 71, a light-emitting functional layer 72, and a second electrode 73 are stacked, and the second conductive layer 42 is provided on the same layer as the first electrode 71. The second electrode 73 further extends to the frame area 102 and partially overlaps with the orthographic projection of the second conductive layer 42 on the substrate 1. The display panel further includes a second insulating layer 8 located between the first electrode 71 and the second electrode 73. The second insulating layer 8 extends from the display area 101 to the frame area 102. A fourth opening 80 is defined in the portion of the second insulating layer 8 located in the frame area 102. The second electrode 73 is electrically connected to the second conductive layer 42 through the fourth opening 80.

[0114] 3 b , the first electrode 71 is the anode of the light emitting element 7 , the second electrode 73 is the cathode of the light emitting element 7 , the second electrode 73 is electrically connected to the first potential line 4 , and the potential signal on the first potential line 4 is a low potential signal, such as VSS.

[0115] In some embodiments, referring to Figure 3b, the first insulating layer 5 extends from the display area 101 to the frame area 102. The first insulating layer 5 includes an inorganic insulating layer 51, a first buffer layer 52, a first gate insulating layer 53, a second gate insulating layer 54, a second buffer layer 55, a third gate insulating layer 56 and an intermediate dielectric layer 57, which are stacked in sequence in a direction away from the substrate 1. Each film layer in the first insulating layer 5 is made of an inorganic insulating material, such as silicon nitride, silicon oxide or silicon oxynitride. The second insulating layer 8 includes a pixel defining layer 81 and a supporting spacer layer 82, which are stacked in sequence in a direction away from the substrate 1. Each film layer in the second insulating layer 8 is made of an organic resin material, such as polyimide, polyurethane, etc.

[0116] In some embodiments, referring to Figures 4a and 4b, Figure 4a is another structural cross-sectional schematic diagram along the AA' section line in Figure 2a; Figure 4b is another structural cross-sectional schematic diagram along the BB' section line in Figure 2a; wherein, the first potential line 4 includes a first conductive layer 41, a second conductive layer 42 and a third conductive layer 43, the first conductive layer 41, the third conductive layer 43 and the second conductive layer 42 are stacked away from the substrate 1 in sequence, and the orthographic projections of any adjacent two of the first conductive layer 41, the third conductive layer 43 and the second conductive layer 42 on the substrate 1 at least partially overlap; the first conductive layer 41 is electrically connected to at least a local area of ​​the conductive shielding layer 2 through the first opening 50; the display panel also includes a first The flat layer 6 is located between the first conductive layer 41 and the third conductive layer 43, and a second opening 60 is opened in the first flat layer 6. The orthographic projection of the second opening 60 on the substrate 1 is located in the overlapping area of ​​the orthographic projections of the first conductive layer 41 and the third conductive layer 43. The first conductive layer 41 and the third conductive layer 43 are electrically connected through the second opening 60; the display panel also includes a second flat layer 9, located between the third conductive layer 43 and the second conductive layer 42, and a third opening 90 is opened in the second flat layer 9. The orthographic projection of the third opening 90 on the substrate 1 is located in the overlapping area of ​​the orthographic projections of the second conductive layer 42 and the third conductive layer 43. The third conductive layer 43 and the second conductive layer 42 are electrically connected through the third opening 90.

[0117] In some embodiments, referring to Figure 4a, the portion of the conductive shielding layer 2 located in the border area 102 is connected as a whole, that is, the portion of the conductive shielding layer 2 located in the border area 102 is not partitioned, and the portion of the conductive shielding layer 2 located in the border area 102 is electrically connected to the first conductive layer 41 through the first opening 50.

[0118] In some embodiments, referring to Figure 3b, the display panel also includes a pixel circuit 10, which is located in the display area 101 and between the light-emitting element 7 and the substrate 1. The pixel circuit 10 includes a conductive connection structure 11 and a plurality of second-type transistors 12. The plurality of second-type transistors 12 and the plurality of first-type transistors 31 are arranged on the same layer. The conductive connection structure 11 is located on the side of the second-type transistor 12 away from the substrate 1. The first flat layer 6 also extends between the second-type transistor 12 and the conductive connection structure 11. A fifth opening 61 is also provided in the portion of the first flat layer 6 located in the display area 101. The first electrode 121 of the second-type transistor 12 is electrically connected to the conductive connection structure 11 through the fifth opening 61; the second flat layer 9 also extends between the conductive connection structure 11 and the first electrode 71. A sixth opening 91 is also provided in the portion of the second flat layer 9 located in the display area 101. The conductive connection structure 11 is electrically connected to the first electrode 71 through the sixth opening 91; the third conductive layer 43 is arranged on the same layer as the conductive connection structure 11.

[0119] 3 b , the second type transistor 12 further includes a gate 120 , an active layer 122 and a second electrode 123 , the first electrode 121 and the second electrode 123 are arranged in the same layer, and the gate 120 , the active layer 122 and the first electrode 121 are located in different layers.

[0120] In some embodiments, referring to Figures 2b, 4a and 5a, Figure 5a is an enlarged top view of part C in Figure 2a; the display panel also includes a first dam 13 and a second dam 14, which are located in the border area 102 and on the side of the second conductive layer 42 away from the substrate 1. The first dam 13 and the second dam 14 are arranged in sequence and spaced apart from each other in a direction away from the display area 101. The first dam 13 and the second dam 14 at least partially overlap with the orthographic projection of the first potential line 4 on the substrate 1, and the orthographic projection of the first opening 50 on the substrate 1 is located between the first dam 13 and the orthographic projection of the shift register circuit 3 on the substrate 1.

[0121] In some embodiments, referring to Figures 5b, 5c and 5d, Figure 5b is another structural cross-sectional schematic diagram along the AA' section line in Figure 2a; Figure 5c is another structural cross-sectional schematic diagram along the AA' section line in Figure 2a; Figure 5d is another enlarged top schematic diagram of part C in Figure 2a; wherein, the display panel also includes a first dam 13 and a second dam 14, which are located in the border area 102 and on the side of the second conductive layer 42 away from the substrate 1, and the first dam 13 and the second dam 14 are arranged in sequence and spaced from each other in a direction away from the display area 101, the first dam 13 and the second dam 14 at least partially overlap with the orthographic projection of the first potential line 4 on the substrate 1, and the orthographic projection of the first opening 50 on the substrate 1 is located between the orthographic projections of the first dam 13 and the second dam 14 on the substrate 1.

[0122] In some embodiments, referring to FIG. 2 b , FIG. 4 a , FIG. 5 b and FIG. 5 c , the first dam 13 and the second dam 14 are provided in the same layer as the second insulating layer 8 .

[0123] In some embodiments, refer to Figure 6a, which is a top view schematic diagram of another display panel in an embodiment of the present disclosure; wherein, the first potential line 4 at least surrounds the three side frame areas 102 outside the display area 101, and the first openings 50 are continuously distributed along the extension direction of the first potential line 4.

[0124] In some embodiments, referring to Figures 6b, 6c and 6d, Figure 6b is a top view schematic diagram of another display panel in an embodiment of the present disclosure; Figure 6c is a structural cross-sectional schematic diagram along the DD' section line in Figure 6b; Figure 6d is another structural cross-sectional schematic diagram along the DD' section line in Figure 6b; wherein, the first potential line 4 at least surrounds the three side frame areas 102 outside the display area 101, and the number of the first openings 50 is multiple, and the multiple first openings 50 are distributed in sequence along the extension direction of the first potential line 4.

[0125] In some embodiments, referring to Figures 7a and 7b, Figure 7a is a partial top view schematic diagram of the area where the shift register circuit is located in the embodiment of the present disclosure; Figure 7b is another partial top view schematic diagram of the area where the shift register circuit is located in the embodiment of the present disclosure; wherein, the conductive shielding layer 2 located in the border area 102 is planar, and the positive projection of the conductive shielding layer 2 on the substrate 1 at least covers the positive projection of all the first-class transistors 31 in the shift register circuit 3 on the substrate 1. The advantage of the planar design of the conductive shielding layer 2 is better shielding effect, and the disadvantage is that large pieces of metal have ESD (electro-static discharge) risk during the process. The ESD risk of the hollow design is smaller.

[0126] In some embodiments, referring to Figures 8a and 8b, Figure 8a is another partial top view schematic diagram of the area where the shift register circuit is located in the embodiment of the present disclosure; Figure 8b is another partial top view schematic diagram of the area where the shift register circuit is located in the embodiment of the present disclosure; wherein, a plurality of hollows 20 are provided in the conductive shielding layer 2 located in the border area 102, and the orthographic projection of the area outside the hollows 20 of the conductive shielding layer 2 on the substrate 1 at least covers the orthographic projection of all first-class transistors 31 in the shift register circuit 3 on the substrate 1. The advantage of the hollow 20 design of the conductive shielding layer 2 is that the risk of ESD (electrostatic discharge) during the process is relatively low.

[0127] In some embodiments, referring to Figures 9a and 9b, Figure 9a is another structural cross-sectional schematic diagram along the AA' section line in Figure 2a; Figure 9b is another structural cross-sectional schematic diagram along the AA' section line in Figure 2a; the conductive shielding layer 2 located in the border area 102 includes a first area 21 and a second area 22, the first area 21 and the second area 22 are disconnected from each other, the first area 21 at least partially overlaps with the orthographic projection of the first conductive layer 41 on the substrate 1, the second area 22 at least partially overlaps with the orthographic projection of the shift register circuit 3 on the substrate 1, the first area 21 is electrically connected to the first conductive layer 41 through the first opening 50, and the second area 22 is electrically connected to the second potential line.

[0128] In some embodiments, referring to Figures 10a, 10b, and 10c, Figure 10a is a top view of another display panel according to an embodiment of the present disclosure; Figure 10b is a schematic cross-sectional view of a structure along the EE' section line in Figure 10a; and Figure 10c is another schematic cross-sectional view of a structure along the EE' section line in Figure 10a. In particular, there are multiple first openings 50, and the multiple first openings 50 are sequentially spaced apart along the line width direction of the first potential line 4 away from the display area 101. Such a distribution of the multiple first openings 50 can form multiple shielding for the shift register circuit 3 along the line width direction of the first potential line 4 away from the display area 101, thereby better preventing the shift register circuit 3 from being affected by accumulated static electricity.

[0129] In some embodiments, referring to FIG. 10 a , the first potential line 4 at least surrounds three side frame regions 102 outside the display region 101 , and the first openings 50 are continuously distributed along the extension direction of the first potential line 4 .

[0130] In some embodiments, refer to Figure 10d, which is a top view schematic diagram of another display panel in an embodiment of the present disclosure; the first potential line 4 surrounds at least three side frame areas 102 outside the display area 101, and each first opening 50 includes multiple sub-openings 501, and the multiple sub-openings 501 of each first opening 50 are distributed in sequence along the extension direction of the first potential line 4.

[0131] In some embodiments, referring to FIG2a, FIG11a is a schematic top view of the binding connection area of ​​the display panel in the embodiment of the present disclosure; FIG11b is an enlarged schematic view of part F in FIG11a; FIG11c is an enlarged schematic view of part G in FIG11a; FIG11d is a schematic top view of the third area of ​​the conductive shielding layer in the binding connection area of ​​the display panel in the embodiment of the present disclosure; the display panel further has a binding connection area 103, Located in at least one side frame area 102 outside the display area 101, the display panel also includes multiple first traces 15 and multiple second potential lines 16, and at least part of the multiple first traces 15, the multiple second potential lines 16 and the first potential line 4 are located in the binding connection area 103. The multiple first traces 15 and the multiple second potential lines 16 are located on the side of the conductive shielding layer 2 away from the substrate 1. The multiple first traces 15 are electrically connected to the shift register circuit 3. The conductive shielding layer 2 also includes a third area 23. The orthographic projection of the third area 23 on the substrate 1 is located in the binding connection area 103. The orthographic projection of the third area 23 on the substrate 1 at least covers the orthographic projection of the multiple first traces 15 on the substrate 1. The third area 23 is disconnected from the first area 21 and the second area 22, and the third area 23 is electrically connected to the second potential line 16 located in the binding connection area 103.

[0132] In some embodiments, the third region 23 is electrically connected to the first potential line 4 located in the bonding connection region 103 .

[0133] The third region 23 shields the plurality of first traces 15 distributed within the bonding connection region 103, thereby further preventing static electricity accumulated on the back side of the substrate 1 from affecting the shift register circuit 3 and thus preventing screen flickering on the display panel. The third region 23 is electrically connected to the second potential line 16 or the first potential line 4, thereby further enhancing its shielding function. The potential signal on the second potential line 16 is a high potential signal, such as VDD. The potential of the second potential line 16 is higher than that of the first potential line 4.

[0134] In some embodiments, the first trace 15 within the bonding connection area 103 can be selectively shielded and blocked by providing a pattern of the conductive shielding layer 2. In some embodiments, the bonding connection area 103 includes a peripheral circuit board (i.e., FPC) bonding pad area 104 and a driver chip (IC) bonding pad area 105. The peripheral circuit board (i.e., FPC) bonding pad area 104 enables a bonding connection between the display panel and the peripheral circuit board; and the driver chip (IC) bonding pad area 105 enables a bonding connection between the display panel and a driver chip (e.g., a data driver chip and a shift register circuit driver chip).

[0135] In some embodiments, the second potential line 16 is disposed in the same layer as the first conductive layer 41 or the third conductive layer 43. The first trace 15 is disposed in the same layer as the first conductive layer 41.

[0136] In some embodiments, referring to Figures 2b, 3b, 4a, 5b, 5c, 6c, 6d, 9a and 9b, and 10b and 10c, the conductive shielding layer 2 further includes a fourth region 24, the orthographic projection of the fourth region 24 on the substrate 1 is located in the display area 101, the orthographic projection of the fourth region 24 on the substrate 1 covers at least part of the orthographic projection of the second type transistor 12 on the substrate 1, the fourth region 24 is disconnected from the first region 21, the second region 22 and the third region 23, and the fourth region 24 is electrically connected to the second potential line 16.

[0137] The fourth region 24 of the conductive shielding layer 2 can block and shield at least a portion of the second-type transistors 12, preventing static electricity accumulated on the back side of the substrate 1 from affecting the characteristics of at least a portion of the second-type transistors 12, thereby ensuring good display quality of the display panel. The fourth region 24 is electrically connected to the second potential line 16, thereby effectively shielding the surrounding electric field.

[0138] The display panel provided by the embodiment of the present disclosure is configured by arranging a conductive shielding layer 2 below the shift register circuit 3, wherein the positive projection of the conductive shielding layer 2 on the substrate 1 covers the positive projection of at least part of the first type of transistors in the shift register circuit 3 on the substrate 1, and at least a local area of ​​the conductive shielding layer 2 is electrically connected to the first potential line 4 through the first opening 50, so that at least a local area of ​​the conductive shielding layer 2 has a first potential, and at the same time, at least a local area of ​​the conductive shielding layer 2 is connected to the first potential line 4 in the first opening 50 and surrounded to form a three-dimensional shielding structure. The three-dimensional shielding structure can shield at least part of the first type of transistors in the shift register circuit 3 to prevent static electricity accumulated on the back side of the substrate 1 from affecting the characteristics of at least part of the first type of transistors, thereby avoiding screen flickering of the display panel, and at the same time enhancing the anti-static ability of the display panel and improving the anti-static display flickering ability of the display panel.

[0139] In a second aspect, an embodiment of the present disclosure further provides a method for preparing the above-mentioned display panel, which includes: preparing a conductive shielding layer on a substrate.

[0140] A first insulating layer, a shift register circuit and a first potential line are prepared on a side of the conductive shielding layer facing away from the substrate.

[0141] Among them, preparing the shift register circuit includes preparing multiple first-type transistors, and the orthographic projection of the conductive shielding layer on the substrate covers at least part of the orthographic projection of the first-type transistors on the substrate; preparing the first insulating layer includes preparing a pattern of a first opening, and at least a local area of ​​the conductive shielding layer is electrically connected to the first potential line through the first opening.

[0142] In some embodiments, the conductive shielding layer is made of a conductive metal material, such as molybdenum, aluminum, or copper. A pattern forming the conductive shielding layer is produced through a patterning process. The patterning process includes steps such as deposition, exposure, development, and etching. The specific process is well-established in the art and will not be further described here.

[0143] In some embodiments, the conductive film layers in the shift register circuit and the pixel circuit and the insulating film layers located between adjacent conductive film layers are sequentially prepared from bottom to top on the side of the conductive shielding layer facing away from the substrate. During this process, the film layers in the first insulating layer and the first conductive layer and the third conductive layer in the first potential line are simultaneously prepared. Then, a light-emitting element is prepared on the side of the pixel circuit facing away from the substrate. The preparation of the light-emitting element specifically includes the steps of sequentially preparing a first electrode, a pixel defining layer, a supporting spacer layer, a light-emitting functional layer, and a second electrode on the substrate forming the pixel circuit. Subsequently, an encapsulation layer is prepared to encapsulate the light-emitting element.

[0144] In some embodiments, when forming the first opening in the first insulating layer, a masking process is first performed to form an opening in a portion of the first insulating layer that is farther from the substrate (e.g., the interlayer dielectric layer, the third gate insulating layer, the second buffer layer, the second gate insulating layer, and the first gate insulating layer). A masking process is then performed to form an opening in another portion of the first insulating layer that is closer to the substrate (e.g., the first buffer layer and the inorganic insulating layer). The openings in the two portions of the first insulating layer together constitute the first opening in the first insulating layer. The masking process includes the steps of photoresist coating, exposure, development, and etching (e.g., dry etching).

[0145] In this embodiment, the specific preparation processes of each film layer in the display panel are relatively mature technologies in this field and will not be described in detail here.

[0146] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising the display panel in the above embodiment.

[0147] By adopting the display panel in the above embodiment, the anti-static capability of the display device is enhanced, and the display quality of the display device is improved.

[0148] The display device can be a wearable display product such as a watch or a bracelet.

[0149] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as an OLED panel, an OLED TV, an OLED billboard, a display, a mobile phone, or a navigation system.

[0150] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel having a display area and a frame area, wherein the frame area surrounds the display area, wherein: The display panel comprises: a substrate; A conductive shielding layer, located on one side of the substrate, and its orthographic projection on the substrate is at least located in the border area; A shift register circuit is located in the frame area and on a side of the conductive shielding layer away from the substrate; A first potential line, located in the border area and on a side of the conductive shielding layer away from the substrate; a first insulating layer, located between the conductive shielding layer, the first potential line and the shift register circuit; The shift register circuit and the first potential line are arranged in sequence in a direction away from the display area; The shift register circuit comprises a plurality of first-type transistors, and the orthographic projection of the conductive shielding layer on the substrate covers at least a portion of the orthographic projection of the first-type transistors on the substrate; The orthographic projections of the conductive shielding layer and the first potential line on the substrate at least partially overlap, a first opening is opened in the first insulating layer, the orthographic projection of the first opening on the substrate is located in the overlapping area of ​​the orthographic projections of the conductive shielding layer and the first potential line, and at least a partial area of ​​the conductive shielding layer is electrically connected to the first potential line through the first opening.

2. The display panel according to claim 1, wherein: The first potential line comprises a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are sequentially stacked away from the substrate, and the orthographic projections of the first conductive layer and the second conductive layer on the substrate at least partially overlap; The first conductive layer is connected to at least a partial area of ​​the conductive shielding layer through the first opening. Electrical connection; The display panel also includes a first flat layer located between the first conductive layer and the second conductive layer, a second opening is opened in the first flat layer, the orthographic projection of the second opening on the substrate is located in the overlapping area of ​​the orthographic projections of the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer are electrically connected through the second opening.

3. The display panel according to claim 1, wherein: The first potential line comprises a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer, the third conductive layer and the second conductive layer are stacked in sequence away from the substrate, and the orthographic projections of any two adjacent ones of the first conductive layer, the third conductive layer and the second conductive layer on the substrate at least partially overlap; The first conductive layer is electrically connected to at least a partial area of ​​the conductive shielding layer through the first opening; The display panel further includes a first flat layer, which is located between the first conductive layer and the third conductive layer. A second opening is formed in the first flat layer. The orthographic projection of the second opening on the substrate is located in an overlapping region of the orthographic projections of the first conductive layer and the third conductive layer. The first conductive layer and the third conductive layer are electrically connected via the second opening. The display panel also includes a second flat layer located between the third conductive layer and the second conductive layer, a third opening is opened in the second flat layer, the orthographic projection of the third opening on the substrate is located in the overlapping area of ​​the orthographic projections of the second conductive layer and the third conductive layer, and the third conductive layer and the second conductive layer are electrically connected through the third opening.

4. The display panel according to claim 2 or 3, wherein: The first type of transistor includes a gate, an active layer, a first electrode and a second electrode, the first electrode and the second electrode are arranged in the same layer, and the gate, the active layer and the first electrode are respectively located in different layers. The first conductive layer is disposed in the same layer as the first electrode and the second electrode; The display panel further includes a light emitting element located in the display area. The light emitting element comprises a first electrode, a light emitting functional layer and a second electrode which are sequentially stacked away from the substrate. The second conductive layer is disposed on the same layer as the first electrode; The second electrode also extends to the border area and partially overlaps with the orthographic projection of the second conductive layer on the substrate. The display panel further includes a second insulating layer located between the first electrode and the second electrode, and the second insulating layer extends from the display area to the frame area, and a fourth opening is formed in a portion of the second insulating layer located in the frame area. The second electrode is electrically connected to the second conductive layer through the fourth opening.

5. The display panel according to claim 4, wherein: The display panel further includes a pixel circuit located in the display area and between the light emitting element and the substrate. The pixel circuit includes a conductive connection structure and a plurality of second-type transistors, wherein the plurality of second-type transistors and the plurality of first-type transistors are arranged in the same layer, and the conductive connection structure is located on a side of the second-type transistors away from the substrate. The first planar layer further extends between the second type transistor and the conductive connection structure, a fifth opening is further provided in a portion of the first planar layer located in the display area, and a first electrode of the second type transistor is electrically connected to the conductive connection structure through the fifth opening; The second planar layer further extends between the conductive connection structure and the first electrode, a sixth opening is further formed in a portion of the second planar layer located in the display area, and the conductive connection structure is electrically connected to the first electrode through the sixth opening; The third conductive layer is arranged on the same layer as the conductive connection structure.

6. The display panel according to claim 4, wherein: It also includes a first dam and a second dam, which are located in the border area and on a side of the second conductive layer away from the substrate. The first dam and the second dam are arranged in sequence and spaced apart from each other in a direction away from the display area, and the first dam and the second dam at least partially overlap with the orthographic projection of the first potential line on the substrate. An orthographic projection of the first opening on the substrate is located between the first dam and an orthographic projection of the shift register circuit on the substrate.

7. The display panel according to claim 4, wherein: It also includes a first dam and a second dam, which are located in the border area and on a side of the second conductive layer away from the substrate. The first dam and the second dam are arranged in sequence and spaced apart from each other in a direction away from the display area, and the first dam and the second dam at least partially overlap with the orthographic projection of the first potential line on the substrate. An orthographic projection of the first opening on the substrate is located between orthographic projections of the first dam and the second dam on the substrate.

8. The display panel according to claim 6 or 7, wherein: The first potential line at least surrounds the frame area on three sides outside the display area. The first openings are continuously distributed along an extending direction of the first potential line.

9. The display panel according to claim 6 or 7, wherein: The first potential line at least surrounds the frame area on three sides outside the display area. There are a plurality of first openings, and the plurality of first openings are sequentially spaced and distributed along an extension direction of the first potential line.

10. The display panel according to claim 1, wherein: The conductive shielding layer located in the border area is planar. The orthographic projection of the conductive shielding layer on the substrate at least covers the shift register circuit The orthographic projections of all the first-type transistors on the substrate.

11. The display panel according to claim 1, wherein: The conductive shielding layer located in the border area is provided with a plurality of hollows. The orthographic projection of the area of ​​the conductive shielding layer outside the hollowing out on the substrate at least covers the orthographic projection of all the first-type transistors in the shift register circuit on the substrate.

12. The display panel according to claim 5, wherein: The conductive shielding layer located in the border area includes a first area and a second area, the first area and the second area are disconnected from each other, The first region at least partially overlaps with an orthographic projection of the first conductive layer on the substrate, and the second region at least partially overlaps with an orthographic projection of the shift register circuit on the substrate. The first region is electrically connected to the first conductive layer through the first opening, and the second region is electrically connected to a second potential line.

13. The display panel according to claim 2 or 3, wherein: There are a plurality of first openings, and the plurality of first openings are sequentially spaced apart from each other along a line width direction of the first potential line away from the display area.

14. The display panel according to claim 13, wherein: The first potential line at least surrounds the frame area on three sides outside the display area. The first openings are continuously distributed along the extension direction of the first potential line.

15. The display panel according to claim 13, wherein: The first potential line at least surrounds the frame area on three sides outside the display area. Each of the first openings includes a plurality of sub-openings, and the plurality of sub-openings of each of the first openings The sub-openings are distributed in sequence and at intervals along the extension direction of the first potential line.

16. The display panel according to claim 12, wherein: The display panel also has a binding connection area located on at least one side of the frame area outside the display area. The display panel further comprises a plurality of first wirings and a plurality of second potential lines, wherein at least a portion of the plurality of first wirings, the plurality of second potential lines and the first potential line are located in the binding connection area, and the plurality of first wirings and the plurality of second potential lines are located on a side of the conductive shielding layer away from the substrate, The plurality of first wirings are electrically connected to the shift register circuit, The conductive shielding layer further includes a third area, the orthographic projection of the third area on the substrate is located in the binding connection area, and the orthographic projection of the third area on the substrate at least covers the orthographic projections of the plurality of first traces on the substrate, The third area is disconnected from the first area and the second area, and is electrically connected to the first potential line located in the binding connection area, or the third area is electrically connected to the second potential line located in the binding connection area.

17. The display panel according to claim 16, wherein: The conductive shielding layer further includes a fourth area, the orthographic projection of the fourth area on the substrate is located in the display area, The orthographic projection of the fourth region on the substrate covers at least a portion of the orthographic projection of the second type transistor on the substrate, The fourth region is disconnected from the first region, the second region, and the third region, and the fourth region is electrically connected to the second potential line.

18. The display panel according to claim 1, wherein: The shift register circuit includes a first gate driving shift register circuit, a light emitting control shift register circuit and a second gate driving shift register circuit.

19. A display device, wherein: A display panel comprising any one of claims 1-18.

20. A method for preparing a display panel, wherein: include: preparing a conductive shielding layer on a substrate; Preparing a first insulating layer, a shift register circuit and a first potential line on a side of the conductive shielding layer away from the substrate; Preparing the shift register circuit includes preparing a plurality of first-type transistors, wherein the orthographic projection of the conductive shielding layer on the substrate covers at least a portion of the orthographic projection of the first-type transistors on the substrate; Preparing the first insulating layer includes preparing a pattern of first openings, and at least a partial area of ​​the conductive shielding layer is electrically connected to the first potential line through the first openings.

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