Driving circuit structure, array substrate, display apparatus and manufacturing method for array substrate

Abstract

Provided are a driving circuit structure, an array substrate, a display apparatus and a manufacturing method for the array substrate. The driving circuit structure comprises a substrate; an initial signal line located on the substrate; a clock signal line located on the substrate; and a first insulating layer located on the side of the initial signal line away from the substrate and comprising a first via hole. The initial signal line is connected to the clock signal line via the first via hole.

Description

Driving circuit structure, array substrate, display device, and method for manufacturing array substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit structure, an array substrate, a display device, and a method for manufacturing the array substrate. Background Art

[0002] In the field of display technology, for example, a display panel, its pixel array generally includes multiple rows of gate lines and multiple columns of data lines interlaced therewith. The driving of the gate lines can be achieved by a bound integrated driving circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line driving circuit can also be directly integrated on the array substrate to form a GOA (Gate driver On Array) to drive the gate lines. For example, a GOA composed of multiple cascaded shift register units can be used to provide scanning signals for multiple rows of gate lines, thereby controlling the opening and closing of multiple rows of gate lines. Currently, more and more display panels use GOA technology to drive the gate lines. GOA technology helps to achieve a narrow frame design for the display panel and can reduce the production cost of the display panel.

[0003] Summary of the Invention

[0004] According to one aspect of the present disclosure, a driving circuit structure is provided, comprising: a substrate; an initial signal line located on the substrate; a clock signal line located on the substrate; and a first insulating layer located on a side of the initial signal line away from the substrate and comprising a first via. The initial signal line is connected to the clock signal line via the first via.

[0005] In some embodiments, the driving circuit structure further includes: a second insulating layer located on a side of the first insulating layer away from the substrate and including a second via hole; and a protection pad filling at least the second via hole. An orthographic projection of the protection pad on the substrate at least partially overlaps with an orthographic projection of the first via hole on the substrate.

[0006] In some embodiments, the clock signal line is located on a side of the initial signal line away from the substrate, a conductive portion is provided in the first via, one end of the conductive portion is directly connected to the initial signal line, and the other end of the conductive portion is directly connected to the clock signal line.

[0007] In some embodiments, the orthographic projection of the initial signal line on the substrate partially overlaps with the orthographic projection of the clock signal line on the substrate to form an overlapping region, and the orthographic projection of the first via on the substrate falls within the overlapping region.

[0008] In some embodiments, the initial signal line and the clock signal line are located in the same layer, and an orthographic projection of the initial signal line on the substrate does not overlap with an orthographic projection of the clock signal line on the substrate.

[0009] In some embodiments, the drive circuit structure further includes: a first routing group including at least one initial signal line extending along a first direction; a second routing group including at least one clock signal line extending along the first direction, wherein the orthographic projection of the second routing group on the substrate does not overlap with the orthographic projection of the first routing group on the substrate; and at least one first connecting line extending along a second direction intersecting the first direction and located on a side of the first insulating layer away from the substrate. At least one clock signal line in the second routing group is connected to any one of the initial signal lines in the first routing group via the first connecting line.

[0010] In some embodiments, the clock signal line includes a hollow portion and a solid portion, the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the solid portion on the substrate, and the orthographic projection of the first connecting line and the first via on the substrate do not overlap with the orthographic projection of the hollow portion on the substrate.

[0011] In some embodiments, the driving circuit structure further includes at least one second connecting line extending along the second direction. Each clock signal line in the second routing group is connected to a corresponding second connecting line, and an orthographic projection of the first connecting line on the substrate does not overlap with an orthographic projection of the second connecting line on the substrate.

[0012] In some embodiments, the first insulating layer further includes a plurality of groups of third vias, and each clock signal line in the second wiring group is connected to the corresponding second connection line via a group of third vias in the plurality of groups of third vias.

[0013] In some embodiments, a clock signal line in the second routing group has two cutting openings. A first connecting line among the at least one first connecting line is connected to the clock signal line having two cutting openings, an orthographic projection of the first connecting line on the substrate partially overlaps with an orthographic projection of the clock signal line having two cutting openings on the substrate, the overlapping portion being a first orthographic projection, an orthographic projection of one group of the plurality of groups of third vias on the substrate being a second orthographic projection, the second orthographic projection falling within the orthographic projection of the clock signal line having two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection being located between the orthographic projections of the two cutting openings on the substrate.

[0014] In some embodiments, the first connecting line includes a first end and a second end relative to each other, the first end of the first connecting line is connected to any initial signal line in the first routing group via the first via, and the second end of the first connecting line is connected to any clock signal line in the second routing group via the first via.

[0015] In some embodiments, the second routing group includes a plurality of clock signal lines arranged in parallel along the first direction, the first connecting line crosses the plurality of clock signal lines in the second routing group along the second direction, the first connecting line includes a first end and a second end relative to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first routing group via the first via, and the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the plurality of clock signal lines of the second routing group on the substrate.

[0016] In some embodiments, one of the at least one first connecting line is fused to the clock signal line having the two cutting openings.

[0017] In some embodiments, the drive circuit structure further includes a first power signal line and a second power signal line extending along the first direction. The first power signal line and the second power signal line are located on a side of the second wiring group away from the first wiring group, and the orthographic projections of the cutting opening and the fusion region of the clock signal line on the substrate do not overlap with the orthographic projections of the first power signal line and the second power signal line on the substrate.

[0018] In some embodiments, one of the at least one first connecting line is connected to the clock signal line having two cutting openings through the first via hole.

[0019] In some embodiments, the first via includes a first opening and a second opening opposite to each other, the first opening and the second opening are circular or elliptical in shape, the longitudinal section of the first via is rectangular or inverted trapezoidal, and the longitudinal section is parallel to the thickness direction of the substrate.

[0020] According to another aspect of the present disclosure, an array substrate is provided, which includes the driving circuit structure described in any of the above embodiments.

[0021] In some embodiments, the array substrate further includes: a first conductive layer, which is located on the same layer as the initial signal line; a second conductive layer, which is located on a side of the first insulating layer away from the substrate, and the first conductive layer is connected to the second conductive layer through a conductive portion in the first via; a second insulating layer, which is located on a side of the second conductive layer away from the substrate and includes a fourth via; and a third conductive layer, which is located on a side of the second insulating layer away from the substrate and is connected to the second conductive layer via the fourth via.

[0022] In some embodiments, the second insulating layer further includes a fifth via hole, the third conductive layer fills the fourth via hole and the fifth via hole, and a depth of the fifth via hole is greater than a depth of the fourth via hole.

[0023] According to yet another aspect of the present disclosure, a display device is provided, comprising the array substrate described in any one of the foregoing embodiments.

[0024] In some embodiments, the display device includes a display area and a peripheral area arranged around the display area, and the driving circuit structure is arranged in the peripheral area.

[0025] According to another aspect of the present disclosure, a method for preparing an array substrate is provided, comprising: providing a substrate; forming a plurality of initial signal lines on the substrate; forming a plurality of clock signal lines on the substrate; and forming a first insulating layer comprising a plurality of first vias on a side of the initial signal lines away from the substrate, the initial signal lines being connected to the clock signal lines via the first vias.

[0026] In some embodiments, the initial signal line, the clock signal line, and the first insulating layer are respectively formed using different masks having a first size, so that the array substrate has a second size that is different from the first size.

[0027] In some embodiments, the first size is greater than the second size, and the array substrate having the second size has a bar shape.

[0028] In some embodiments, the first dimension is 65 inches and the second dimension is 58.5 inches.

[0029] In some embodiments, a plurality of initial signal lines, a plurality of clock signal lines, and a first insulating layer are formed on the substrate, including: depositing a first metal layer on the substrate, and patterning the first metal layer by blocking a portion of a first mask having the first size to form the plurality of initial signal lines; depositing a first intermediate insulating layer on a side of the initial signal line away from the substrate, and patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form the first insulating layer including a plurality of first vias, wherein the first vias expose a portion of the surface of the initial signal line; and depositing a second metal layer on a side of the first insulating layer away from the substrate, and patterning the second metal layer by blocking a portion of a third mask having the first size to form the plurality of clock signal lines on a side of the first insulating layer away from the substrate, and forming a conductive portion in the first via, wherein the initial signal line is connected to the clock signal line via the conductive portion.

[0030] In some embodiments, the method also includes: depositing a second intermediate insulating layer on a side of the clock signal line away from the substrate, and composing the second intermediate insulating layer by blocking a portion of the second mask plate to form a second insulating layer including a plurality of second vias, wherein the second vias expose a portion of the surface of the clock signal line; and depositing a third metal layer on a side of the second insulating layer away from the substrate, and composing the third metal layer by blocking a portion of a fourth mask plate having the first size to form a protective pad, wherein the protective pad at least fills the second vias.

[0031] In some embodiments, a plurality of initial signal lines and a plurality of clock signal lines are formed on the substrate, including: depositing a first metal layer on the substrate, and patterning the first metal layer by blocking a portion of a first mask having the first size to form a first routing group and a second routing group, the first routing group including a plurality of initial signal lines arranged along a first direction, the second routing group including a plurality of clock signal lines arranged along the first direction, and an orthographic projection of the first routing group on the substrate and an orthographic projection of the second routing group on the substrate do not overlap.

[0032] In some embodiments, the method further includes: depositing a first intermediate insulating layer on a side of the initial signal line and the clock signal line away from the substrate, and patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and a plurality of groups of third vias, the first vias exposing a portion of the surface of the initial signal line and the clock signal line, and the third vias exposing a portion of the surface of the clock signal line; depositing a second metal layer on a side of the first insulating layer away from the substrate, and patterning the second metal layer by blocking a portion of a third mask having the first size to form at least one first connecting line and at least one second connecting line arranged along a second direction, the first connecting line including a first end and a second end opposite to each other, the first end of the first connecting line being connected to the first connecting line via the first via. The hole is connected to any initial signal line in the first routing group, the second end of the first connecting line is connected to any clock signal line in the second routing group via the first via hole, each clock signal line in the second routing group is connected to a corresponding second connecting line via a group of third via holes in the multiple groups of third via holes, and the second direction intersects with the first direction; a second intermediate insulating layer is deposited on the side of the first connecting line and the second connecting line away from the substrate, and the second intermediate insulating layer is composed by blocking a part of the second mask plate to form a second insulating layer including a plurality of second via holes; and a third metal layer is deposited on the side of the second insulating layer away from the substrate, and the third metal layer is composed by blocking a part of the fourth mask plate having the first size to form a protective pad, and the protective pad at least fills the second via hole.

[0033] In some embodiments, the method further includes: cutting a clock signal line in the second routing group so that the clock signal line has two cutting openings. The orthographic projection on the substrate of a first connecting line connected to the clock signal line having the two cutting openings partially overlaps with the orthographic projection of the clock signal line having the two cutting openings on the substrate, the overlapping portion being the first orthographic projection, the orthographic projection on the substrate of a group of third vias in the plurality of groups of third vias being the second orthographic projection, the second orthographic projection falling within the orthographic projection on the substrate of the clock signal line having the two cutting openings, and the first orthographic projection and the second orthographic projection being located between the orthographic projections of the two cutting openings on the substrate.

[0034] In some embodiments, the method further includes: depositing a first intermediate insulating layer and a second metal layer in sequence on a side of the initial signal line and the clock signal line away from the substrate, and patterning the first intermediate insulating layer and the second metal layer by blocking a portion of a second mask having the first size to form a first insulating layer including the multiple first vias and multiple groups of third vias, and at least one first connecting line and at least one second connecting line arranged along a second direction, the first via exposing a portion of the surface of the initial signal line, the third via exposing a portion of the surface of the clock signal line, the first connecting line crossing over multiple clock signal lines in the second routing group along the second direction, the first connecting line including a first end and a second end opposite to each other, the first end of the first connecting line being connected to any one of the first routing group via the first via. an initial signal line, the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the multiple clock signal lines of the second routing group on the substrate, each clock signal line in the second routing group is connected to a corresponding second connecting line via a group of third vias in the multiple groups of third vias, and the second direction intersects with the first direction; a second intermediate insulating layer is deposited on a side of the first connecting line and the second connecting line away from the substrate, and the second intermediate insulating layer is composed by blocking a portion of the third mask template having the first size to form a second insulating layer; and a third metal layer is deposited on a side of the second insulating layer away from the substrate, and the third metal layer is composed by blocking a portion of the fourth mask template having the first size to form a pixel electrode.

[0035] In some embodiments, the method further includes: cutting a clock signal line in the second routing group so that the clock signal line has two cutting openings; and fusing the clock signal line having the two cutting openings to a first connection line located between the two cutting openings at a fusing region. The fusing region has an orthographic projection on the substrate as a first orthographic projection, and a group of third vias in the plurality of groups of third vias has an orthographic projection on the substrate as a second orthographic projection, the second orthographic projection falls within the orthographic projection of the clock signal line having the two cutting openings on the substrate, and the first and second orthographic projections are located between the orthographic projections of the two cutting openings on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, in which:

[0037] FIG1 shows a schematic diagram of the arrangement of a driving circuit;

[0038] FIG2 shows a partial enlarged view of area ① in FIG1 ;

[0039] FIG3 shows a top view and a cross-sectional view of a local area of ​​a driving circuit structure according to an embodiment of the present disclosure;

[0040] FIG4 is a plan view showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0041] FIG5 shows an electron microscope image of a first via hole according to an embodiment of the present disclosure;

[0042] FIG6 shows an electron microscope image of a local area of ​​a driving circuit structure during the preparation stage according to an embodiment of the present disclosure;

[0043] FIG7 shows a top view of a local area of ​​a driving circuit structure according to an embodiment of the present disclosure under an electron microscope during the preparation stage;

[0044] FIG8 shows a cross-sectional view of the driving circuit structure taken along the cutting line of FIG7 ;

[0045] FIG9 is a schematic diagram showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0046] FIG10 is a schematic cross-sectional view of a local area of ​​the driving circuit structure taken along line BB′ of FIG9 ;

[0047] FIG11 is a schematic cross-sectional view of a local area of ​​a driving circuit structure;

[0048] FIG12 is a schematic diagram showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0049] FIG13 is a schematic diagram showing a circuit arrangement of a driving circuit structure according to an embodiment of the present disclosure;

[0050] FIG14 shows a schematic structural diagram of a local area of ​​an array substrate;

[0051] FIG15 shows a top view of a local area of ​​an array substrate according to an embodiment of the present disclosure;

[0052] FIG16 is a schematic cross-sectional view of a local area of ​​the array substrate taken along line CC′ of FIG15 ;

[0053] FIG17 shows comparative data of contact resistance and current resistance parameters of a conventional array substrate and an array substrate according to an embodiment of the present disclosure;

[0054] FIG18 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0055] FIG19 shows a flow chart of a method for preparing an array substrate according to an embodiment of the present disclosure;

[0056] FIG20 is a schematic diagram showing how to respectively prepare a first-size product and a second-size product using a first-size mask according to an embodiment of the present disclosure;

[0057] FIG21 is a schematic diagram showing a method for preparing a first metal layer using an embodiment of the present disclosure;

[0058] FIG22 is a schematic diagram showing a method for preparing a first insulating layer using an embodiment of the present disclosure;

[0059] FIG23 is a schematic diagram showing a method for preparing a second metal layer using an embodiment of the present disclosure;

[0060] FIG24 shows a schematic diagram of preparing a second insulating layer using the method provided in an embodiment of the present disclosure; and

[0061] FIG25 shows a schematic diagram of preparing a third metal layer using the method provided in an embodiment of the present disclosure.

[0062] It should be understood that the accompanying drawings are merely schematic illustrations of exemplary embodiments of the present disclosure and are not intended to limit the present disclosure and are not necessarily drawn to scale. In addition, in the accompanying drawings, identical or similar components are indicated by identical or similar reference numerals. DETAILED DESCRIPTION

[0063] The following will clearly describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0064] Before formally describing the technical solutions of the embodiments of the present disclosure, certain terms used in the embodiments of the present disclosure are explained and defined as follows to help those skilled in the art to more clearly understand the technical solutions of the embodiments of the present disclosure.

[0065] As used herein, terms such as "A and B are located in the same layer" mean that A and B are formed by the same patterning process, but this does not limit layer A and layer B to having the same height or thickness. In the case of "A and B are located in the same layer," layer A and layer B are generally composed of the same material. Similarly, terms such as "A and B are located in different layers" mean that A and B are generally formed by different patterning processes, layer A and layer B can be composed of the same material or different materials, and layer A and layer B can have the same height and / or thickness or different heights and / or thicknesses.

[0066] As used herein, the term "patterning process" or "patterning" includes, but is not limited to, processes such as depositing a film layer, applying a photoresist, exposing, developing, etching, and stripping the photoresist. After the "patterning process" or "patterning," the "layer" contains at least one pattern.

[0067] GOA technology integrates gate drive circuits onto an array substrate to scan and drive gate lines. This improves the integration of the array substrate and reduces the number of gate drive circuits used. GOA technology helps achieve narrow-bezel designs for display panels and reduces production costs.

[0068] To further reduce product development costs and quickly respond to customer demand for products of different sizes, the inventors of this application discovered that it is possible to utilize the mask used to produce products of existing sizes to produce products of other sizes through blocked exposure and partial exposure. Because GOA products typically place the GOA's initial signal line (or STV trace) on the opposite side of the data line pad, when using the existing product mask to produce other products of different sizes, some GOA units and initial signal lines need to be cut off. This prevents the STV signal on the initial signal line from being transmitted to the GOA unit, causing the product to malfunction.

[0069] Currently, one method to solve the above problem is to use a maintenance method of cutting and welding, using the clock signal line (or CLK line) to introduce the STV signal to achieve GOA drive. As shown in Figure 1, it shows five rows of GOA units, namely GOA1 to GOA4 and Dummy GOA. GOA3 is the 1084th row of GOA units, GOA2 is the 1085th row of GOA units, GOA1 is the 1086th row of GOA units, and Dummy GOA is the 1087th row of GOA units. The scanning direction is from GOA1 to GOA4. As mentioned above, in order to share the existing product mask to produce a product of another size, part of the structure of GOA1 to GOA3 needs to be cut off. The cutting position is the position shown by the black solid line in Figure 1, and a total of about 12 cuts are required. To introduce the STV signal via the CLK trace, the CLK and STV traces need to be spliced. Figure 1 shows five splice locations, with two at position ① and three at position ②. By splicing the CLK and STV traces, the STV signal at position ① can be introduced via the CLK trace to the three wires at position ②. The three wires at position ② are then connected to GOA1 to GOA3 units, respectively, allowing the STV signal to be introduced to GOA1 to GOA3 units.

[0070] Figure 2 is a zoomed-in view of point ① in Figure 1. As shown in Figure 2, the CLK line is flanked by VDDO and VDDE lines, respectively. Both VDDO and VDDE lines partially overlap the STV line, and the STV, CLK, VDDO, and VDDE lines are arranged relatively closely together. During the welding process of the STV and CLK lines at repair point ①, a short circuit between the STV line and the adjacent VDDO and / or VDDE lines can easily occur, causing display abnormalities or even failure on the display panel, reducing product production yield.

[0071] In view of this, embodiments of the present disclosure provide some drive circuit structures. These drive circuit structures include: a substrate, an initial signal line (also referred to as an STV line) arranged on the substrate, a clock signal line (also referred to as a CLK line) arranged on the substrate, and a first insulating layer located on a side of the initial signal line away from the substrate, the first insulating layer including a first via, and the initial signal line is connected to the clock signal line via the first via. The drive circuit structure can be, for example, a gate drive circuit structure, which can use a GOA composed of multiple cascaded shift register units to provide scan signals for multiple rows of gate lines, thereby controlling the opening and closing of the multiple rows of gate lines.

[0072] It should be noted that the phrase "the initial signal line is connected to the clock signal line via the first via" means that the connection between the initial signal line and the clock signal line requires the participation of the first via, but this does not exclude the presence of other electrical components. For example, the initial signal line can be connected to the clock signal line only via the first via (and the conductive material contained in the first via), that is, one end of the first via is directly connected to the initial signal line, and the other end of the first via is directly connected to the clock signal line. Alternatively, the initial signal line can be connected to the clock signal line via the first via and other electrical components (including but not limited to wires).

[0073] In the driver circuit structure provided by the disclosed embodiment, the initial signal line is connected to the clock signal line via a first via, thereby introducing the STV signal on the initial signal line into the GOA unit. This prevents short circuits between the initial signal line and other lines, allowing the display panel to display normally and helping to improve the production yield of the display panel.

[0074] The following describes in more detail the arrangement of various driving circuit structures provided by the embodiments of the present disclosure with the help of several exemplary embodiments.

[0075] Figure 3 shows a schematic diagram of a partial region of a driver circuit structure 100, wherein the left figure is a top view of the partial region of the driver circuit structure 100, and the right figure is a cross-sectional view taken along line AA' of the left figure. As shown in Figure 3, the driver circuit structure 100 includes: a substrate 101, an initial signal line 102 disposed on the substrate 101, a first insulating layer 104 located on a side of the initial signal line 102 away from the substrate 101, and a clock signal line 103 located on a side of the first insulating layer 104 away from the substrate 101. The first insulating layer 104 includes a first via 105, through which the initial signal line 102 is connected to the clock signal line 103. More specifically, as shown in Figure 3, a conductive portion 106 is provided in the first via 105, one end 1061 of the conductive portion 106 is directly connected to the initial signal line 102, and the other end 1062 of the conductive portion 106 is directly connected to the clock signal line 103, so that the initial signal line 102 is connected to the clock signal line 103 through the conductive portion 106 in the first via 105.

[0076] The initial signal line 102 is connected to the clock signal line 103 via the conductive portion 106 in the first via 105, without having to be connected to the clock signal line 103 by welding. This prevents short circuits between the initial signal line 102 and other surrounding lines during the welding process, allowing the display panel including the driving circuit structure 100 to display normally. In addition, because the depth of the first via 105 is generally shallow (for example, a depth of approximately several hundred nanometers), connecting the initial signal line 102 to the clock signal line 103 via the first via 105 can improve the reliability and success rate of the connection between the initial signal line 102 and the clock signal line 103, thereby significantly improving the production yield of the display panel including the driving circuit structure 100. If the first via 105 has a deeper depth, then in the process of etching the first insulating layer 104 to form the first via 105, due to the metal induced plasma effect, the etching rate of the portion of the first insulating layer 104 close to the clock signal line 103 is usually greater than the etching rate of other portions, which can easily cause the first insulating layer 104 at the bottom of the clock signal line 103 to be hollowed out, thereby forming a chamfer (Undercut). The presence of the chamfer can easily cause other film layers to break at the chamfer, thereby leading to problems such as abnormal connection and electrostatic breakdown. In contrast, in the driving circuit structure 100 of Figure 3, the first via 105 has a shallower depth. In the process of forming the first via 105, the first insulating layer 104 will not be chamfered, which can avoid the negative impact of the chamfer and help improve the reliability of the product. In addition, the presence of the first via 105 can improve the recognition of the maintenance point, which helps to improve the efficiency of maintenance personnel and the success rate of maintenance.

[0077] The initial signal line 102 can be used to provide a start signal (STV signal) for the driving circuit structure 100, the clock signal line 103 can be used to provide a clock signal for the driving circuit structure 100, and at least one clock signal line 103 can be used to transmit the STV signal on the initial signal line 102 to the driving circuit structure 100.

[0078] The first via 105 penetrates the first insulating layer 104 and includes a first opening 1051 and a second opening 1052 facing each other. The first opening 1051 and the second opening 1052 can be circular or elliptical. For example, the longitudinal cross-section of the first via 105 can be rectangular or inverted trapezoidal. The longitudinal cross-section of the first via 105 is the cross-section shown in the right figure of FIG. 3 , which is parallel to the thickness direction of the substrate 101. The inverted trapezoidal shape of the first via 105 further facilitates the connection between the clock signal line 103 and the initial signal line 102, resulting in a lower via resistance.

[0079] It should be noted that the first insulating layer 104 includes a plurality of first vias 105, but not all of the first vias 105 are used to connect the initial signal line 102 and the clock signal line 103. For example, some of the first vias 105 can be used to connect the initial signal line 102 and the clock signal line 103, while some of the first vias 105 can be used to connect the initial signal line 102 to other traces, or to connect the metal layer located on the same layer as the initial signal line 102 to other metal layers.

[0080] As shown in FIG3 , the initial signal line 102 and the clock signal line 103 are located in different layers. The initial signal line 102 can, for example, be located in the same layer as the gate line, the gate electrode, etc., and the same mask plate can be used to form the initial signal line 102, the gate line, the gate electrode, and other structures. The clock signal line 103 can, for example, be located in the same layer as the first power signal line 110, the second power signal line 111, the source / drain (not shown), etc., and the same mask plate can be used to form the clock signal line 103, the first power signal line 110, the second power signal line 111, the source / drain, etc. The orthographic projection of the initial signal line 102 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line 103 on the substrate 101 to form an overlapping region R, and the orthographic projection of the first via 105 on the substrate 101 falls within the overlapping region R.

[0081] The first power signal line 110 (e.g., a VDDO line) and the second power signal line 111 (e.g., a VDDE line) can be used to transmit voltage signals. As shown in FIG3 , the first power signal line 110 and the second power signal line 111 are arranged on either side of the clock signal line 103, and the orthographic projections of the first power signal line 110 and the second power signal line 111 on the substrate 101 partially overlap with the orthographic projection of the initial signal line 102 on the substrate 101. Because the initial signal line 102 and the clock signal line 103 are connected through the first via 105 rather than by welding, even if the first power signal line 110 and the second power signal line 111 are arranged relatively close to the initial signal line 102, the initial signal line 102 will not short-circuit with the nearby first power signal line 110 and / or second power signal line 111, thereby ensuring normal display of the display panel and helping to improve the production yield of the product.

[0082] In some embodiments, the driving circuit structure 100 may further include a second insulating layer 107 and a protective pad 109. The second insulating layer 107 is located on a side of the clock signal line 103 away from the substrate 101 and includes a second via 108. The protective pad 109 at least fills the second via 108, and the orthographic projection of the protective pad 109 on the substrate 101 at least partially overlaps with the orthographic projection of the first via 105 on the substrate 101. The protective pad 109 may cover the surface of the clock signal line 103 exposed by the second via 108. The protective pad 109 may be used to prevent corrosion of the clock signal line 103 and the conductive portion 106 in the first via 105 by external moisture, thereby protecting the clock signal line 103 and the conductive portion 106 in the first via 105.

[0083] FIG4 shows a schematic diagram of the layout of the driving circuit structure 100 on the array substrate, which shows regions I and II, wherein the enlarged view of region I in FIG4 is the left view of FIG3 . Region I in FIG4 shows two first vias 105, and region II shows three first vias 105. In region I, the initial signal line 102 is connected to the clock signal line 103 via two first vias 105, and the clock signal line 103 is connected to three horizontal connection lines at region II via three first vias 105, respectively. The three horizontal connection lines are respectively connected to corresponding GOA units. In this way, the STV signal on the initial signal line 102 can be introduced into the corresponding GOA unit with the help of the clock signal line 103 to realize GOA drive.

[0084] Fig. 5 is a top view of the first via hole 105, which is an electron microscope image of the first via hole 105. As shown in the figure, the shape of the first via hole 105 can be circular or elliptical, and its size can be determined according to product requirements.

[0085] Figure 6 is a cross-sectional view after the deposition of the SD metal layer, which is an electron microscope image. In Figure 6, the Gate layer can be the aforementioned initial signal line 102, gate line, gate, and other structures. The GI layer represents the aforementioned first insulating layer 104, which can be a gate insulating layer. The SD layer can be structures such as the clock signal line 103, the first power signal line 110, the second power signal line 111, and the source / drain electrodes. As shown in the figure, the first via 105 in the GI layer is filled with the deposited SD layer. This connects the Gate layer and the SD layer via the first via 105, thus avoiding short circuit issues caused by welding. For example, the thickness of the Gate layer can be approximately 456.4nm, the thickness of the GI layer can be approximately 390.3nm, and the thickness of the SD layer can be approximately 562.2nm. The thickness of the intermediate layer between the GI layer and the SD layer can be approximately 36.38nm, and the thickness of the intermediate layer between the Gate layer and the substrate can be approximately 39.69nm. In some examples, the slope angle of the SD layer near the first via 105 in the GI layer is approximately 54.69°. In some examples, the first via hole 105 may be in an inverted trapezoidal shape, and the slope angle of the side surface of the first via hole 105 is approximately 84.09°.

[0086] Figure 7 shows an electron microscope image after a second insulating layer 107 (also called a PVX layer) is formed on the SD layer, and Figure 8 is a cross-sectional view taken along the black solid line in Figure 7. As shown in Figures 7 and 8, the SD layer is not only located on the side of the GI layer away from the Gate layer, but also fills the first via 105 in the GI layer. The PVX layer is located on the side of the SD layer away from the GI layer, and the SD layer in the first via 105 is encapsulated by the PVX layer.

[0087] The display panel including the above-mentioned driving circuit structure 100 can be a display panel of various appropriate types and various appropriate sizes. Exemplarily, the display panel including the above-mentioned driving circuit structure 100 can be a bar-shaped display panel, for example, it can be used to be installed on a subway for display. In some embodiments, the display panel including the above-mentioned driving circuit structure 100 is a bar screen, and its size is 58.5 inches. The existing 65-inch mask for non-bar screens (for example, a mask for preparing a 65-inch TV) can be optimized and designed, for example, the pattern of the first via 105 and / or the pattern of the protective pad 109 are added to the 65-inch mask, and then the optimized 65-inch mask is used to prepare a 58.5-inch bar screen to achieve the sharing of the mask. The specific preparation method will be described later and will not be described in detail here.

[0088] 9 shows a schematic layout diagram of another driving circuit structure 200. Different from the driving circuit structure 100, in the driving circuit structure 200, the initial signal line 102 and the clock signal line 103 are located in the same layer.

[0089] Figure 10 shows a cross-sectional view taken along line BB' in Figure 9 . As shown in Figures 9 and 10 , the driving circuit structure 200 includes: a substrate 101; a first routing group arranged on substrate 101, comprising at least one initial signal line 102 extending along a first direction D1; and a second routing group arranged on substrate 101, comprising at least one clock signal line 103 extending along the first direction D1. The initial signal line 102 and the clock signal line 103 are located on the same layer, and the orthographic projections of the initial signal lines 102 and the orthographic projections of the clock signal lines 103 on substrate 101 do not overlap. As an example, Figure 9 shows that the first routing group includes two initial signal lines 102, designated STV1 and STV2. Of course, this is merely an example, and the first routing group may include more initial signal lines. FIG9 shows that the second routing group includes 12 clock signal lines 103, respectively denoted as CLK1 to CLK12. Of course, this is only an example, and the second routing group may include more or fewer clock signal lines. The embodiment of the present disclosure does not specifically limit the number of initial signal lines 102 and clock signal lines 103.

[0090] The inventors of the present application have discovered that in products where the initial signal line 102 and the clock signal line 103 are located in different layers, when preparing the clock signal line 103, the metal layer where the clock signal line 103 is located needs to climb over the metal layer where the initial signal line 102 is located, and the two will overlap. Since the initial signal line 102 has a certain thickness, when the clock signal line 103 climbs over the initial signal line 102, it is possible that the line will be broken. Therefore, during the preparation stage and the detection stage, it is necessary to pay attention to whether the relevant lines are broken. In the driving circuit structure 200, the initial signal line 102 and the clock signal line 103 are located in the same layer, which can reduce or even avoid the problem of the clock signal line 103 being broken. In addition, the initial signal line 102 and the clock signal line 103 do not overlap each other, which helps to reduce the load on the signal line.

[0091] As shown in Figures 9 and 10, the driving circuit structure 200 further includes: a first insulating layer 104 located on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, the first insulating layer 104 including a plurality of first vias 105 and a plurality of groups of third vias 114; at least one first connecting line 112 extending along a second direction D2 and located on the side of the first insulating layer 104 away from the substrate 101; and at least one second connecting line 113 extending along the second direction D2 and located on the same layer as the first connecting line 112, wherein the first direction D1 intersects the second direction D2. For simplicity, Figure 9 schematically illustrates only three first connecting lines 112 and two second connecting lines 113. However, in reality, the number of first connecting lines 112 can be any number, for example, the number of first connecting lines 112 can be equal to the number of clock signal lines 103 in the second routing group. The number of second connecting lines 113 can also be any number, for example, the number of second connecting lines 113 can be equal to the number of clock signal lines 103 in the second routing group.

[0092] The first connection line 112 includes a first end 1121 and a second end 1122 opposite each other. The first end 1121 of the first connection line 112 is connected to any initial signal line 102 in the first routing group via a first via 105. The second end 1122 of the first connection line 112 is connected to any clock signal line 113 in the second routing group via another first via 115. For example, with respect to the embodiment of FIG. 9 , twelve first connection lines 112 may be provided. The first end 1121 of one of the twelve first connection lines 112 may be connected to any initial signal line STV1 or STV2 via a first via 105. The second end 1122 of the first connection line 112 may be connected to any clock signal line CLK1-CLK12 via another first via 105. The first end 1121 of another of the twelve first connection lines 112 can be connected to any one of the initial signal lines STV1 and STV2 via the first via 105, and the second end 1122 of the first connection line 112 can be connected to any one of the remaining 11 clock signal lines via another first via 105, and so on. In this way, the first end 1121 of each first connection line 112 is connected to the initial signal line 102 via the first via 105, and the second end 1122 of each first connection line 112 is connected to the clock signal line 103 via the first via 105. In addition, each clock signal line 103 in the second routing group is connected to a corresponding second connection line 113 via a group of third vias 114. The other end of the second connection line 113 not connected to the clock signal line 103 can be connected to the GOA unit, thereby realizing a complete signal transmission path.

[0093] Any clock signal line in the second routing group has two cut openings 115 and 116. The clock signal line selected in the second routing group is cut to transmit the STV signal on the initial signal line 102. Uncut clock signal lines do not transmit the STV signal. Any clock signal line from CLK1 to CLK12 can be selected to transmit the STV signal. Figure 9 uses clock signal line CLK3 as an example to transmit the STV signal. As shown in Figure 9, the clock signal line CLK3 has two cutting openings 115 and 116. The first end 1121 of the first connecting line 112 is connected to the initial signal line STV2 via the first via 105, and the second end 1122 of the first connecting line 112 is connected to the clock signal line CLK3 via the first via 105. The orthographic projection of the first connecting line 112 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line CLK3 on the substrate 101, and the overlapping part is the first orthographic projection. The clock signal line CLK3 is connected to the second connecting line 113 via a group of third vias 114. The second orthographic projection of the group of third vias 114 on the substrate 101 falls within the orthographic projection of the clock signal line CLK3 on the substrate 101. The first orthographic projection and the second orthographic projection need to be located between the orthographic projections of the two cutting openings 115 and 116 on the substrate 101 to form an effective transmission path for the STV signal. The clock signal line CLK3 is selected to transmit the STV signal. The effective transmission path of the STV signal is: the STV signal on the initial signal line STV2 is transmitted to the clock signal line CLK3 via the first connection line 112, and the clock signal line CLK3 transmits the STV signal to the GOA unit via the second connection line 113.

[0094] Each clock signal line in the second routing group can be connected to a corresponding first connecting line 112. In this way, even if a clock signal line is found to be broken during the production process, one of the other clock signal lines that has not been broken can be selected to be cut to transmit the STV signal. This design greatly increases the selectivity of the cutting position. In addition, in the driving circuit structure 200, the initial signal line 102 is connected to the first connecting line 112 via the first via 105, and the first connecting line 112 is connected to the clock signal line 103 via the first via 105. That is, the initial signal line 102 is connected to the clock signal line 103 via the first via 105 and the first connecting line 112, avoiding welding with the clock signal line 103. Therefore, in the driving circuit structure 200, only the clock signal line 103 needs to be cut, and there is no need to weld the clock signal line 103 to realize the introduction of the STV signal into the GOA unit via the clock signal line 103 to realize GOA drive.

[0095] As shown in FIG9 , to reduce resistance, the initial signal line 102 and the clock signal line 103 are designed to include hollow portions and solid portions. The orthographic projection of the first connecting line 112 on the substrate 101 can partially overlap with the orthographic projection of the solid portion of the clock signal line 103 on the substrate 101. However, the orthographic projections of the first connecting line 112 and the first via 105 on the substrate 101 do not overlap with the orthographic projections of the hollow portion of the clock signal line 103 on the substrate 101, i.e., they avoid the hollow portion of the clock signal line 103. Because the first connecting line 112 and the clock signal line 103 are located on different layers, by ensuring that the first connecting line 112 and the first via 105 avoid the hollow portion of the clock signal line 103, the risk of disconnection that may occur when the first connecting line 112 climbs over the clock signal line 103 of a certain thickness can be reduced or even avoided, thereby improving the success rate of connecting the clock signal line 103 to the first connecting line 112.

[0096] In some embodiments, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the second connection line 113 on the substrate 101, thereby preventing a short circuit between the two. For example, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the third via 114 on the substrate 101.

[0097] As shown in FIG9 , the driving circuit structure 200 may further include a first power signal line 110 (or VDDO line), a second power signal line 111 (or VDDE line), a common electrode lead COM, a third power signal line LVGL, etc. extending along a first direction D1. The second line group is located between the first line group and the first power signal line 110, and the display area of ​​the display panel may be located on a side of the third power signal line LVGL away from the second line group.

[0098] As shown in FIG10 , in some embodiments, the driving circuit structure 200 may further include a second insulating layer 107 and a protective pad 109. The second insulating layer 107 is located on a side of the first connecting line 112 away from the substrate 101 and includes a second via 108. The protective pad 109 at least fills the second via 108, and the orthographic projection of the protective pad 109 on the substrate 101 at least partially overlaps with the orthographic projection of the first via 105 on the substrate 101. The protective pad 109 may cover the surface of the first connecting line 112 exposed by the second via 108. The protective pad 109 may be used to prevent corrosion of the first connecting line 112 and the conductive portion 106 in the first via 105 by external moisture, thereby protecting the first connecting line 112 and the conductive portion 106 in the first via 105. The first connecting line 112 and the conductive portion 106 may be formed using the same patterning process.

[0099] The display panel including the above-mentioned driving circuit structure 200 can be a display panel of various appropriate types and sizes. Exemplarily, the display panel including the above-mentioned driving circuit structure 200 can be a strip display panel, which can be used to be installed on a subway for display. In some embodiments, the display panel including the above-mentioned driving circuit structure 200 is a strip screen with a size of 58.5 inches. The existing 65-inch mask plate can be optimized and designed, for example, the pattern of the first via 105, the pattern of the first connecting line 112, the pattern of the protective pad 109, etc. can be pre-added to the existing 65-inch mask plate, and then the optimized 65-inch mask plate is used to prepare a 58.5-inch strip screen to achieve the sharing of the mask plate. The specific preparation method will be described later and will not be described in detail here.

[0100] Of course, the optimized 65-inch mask can continue to be used to manufacture 65-inch non-strip screen products (such as TVs) without any adverse impact on the structure of non-strip screen products. For example, Figure 11 shows a cross-sectional view of a partial area of ​​the drive circuit structure of a non-strip screen product. As shown in Figure 11, the drive circuit structure includes a substrate 11, initial signal lines 12, a first insulating layer 14, a second insulating layer 17, a clock signal line 18, a protective pad 19, and other structures.

[0101] 12 shows a schematic layout diagram of another driving circuit structure 300. Different from the driving circuit structure 100, in the driving circuit structure 300, the initial signal line 102 and the clock signal line 103 are located in the same layer.

[0102] As shown in FIG12 , a driving circuit structure 300 includes: a substrate 101 (not shown); a first routing group arranged on substrate 101, comprising at least one initial signal line 102 extending along a first direction D1; and a second routing group arranged on substrate 101, comprising at least one clock signal line 103 extending along the first direction D1. The initial signal line 102 and the clock signal line 103 are located on the same layer, and the orthographic projections of the initial signal lines 102 and the clock signal lines 103 on substrate 101 do not overlap. As an example, FIG12 shows that the first routing group includes two initial signal lines 102, designated STV1 and STV2. Of course, this is merely an example, and the first routing group may include more initial signal lines 102. As an example, FIG12 shows that the second routing group includes 12 clock signal lines 103, designated CLK1 through CLK12. Of course, this is merely an example, and the second routing group may include more or fewer clock signal lines 103. The disclosed embodiment does not impose any specific restrictions on the number of initial signal lines 102 and clock signal lines 103. In the driver circuit structure 300, the initial signal lines 102 and the clock signal lines 103 are located on the same layer. This prevents the clock signal lines 103 from climbing over the thick initial signal lines 102, thereby reducing or even preventing the problem of clock signal line 103 breaking. In addition, the initial signal lines 102 and the clock signal lines 103 do not overlap, which helps reduce the load on the signal lines.

[0103] The driving circuit structure 300 also includes: a first insulating layer 104 located on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, the first insulating layer 104 including a plurality of first vias 105 and a plurality of groups of third vias 114; at least one first connecting line 112 extending along the second direction D2 and located on the side of the first insulating layer 104 away from the substrate 101; and at least one second connecting line 113 extending along the second direction D2 and located on the same layer as the first connecting line 112. For simplicity, FIG12 schematically illustrates only three first connecting lines 112 and three second connecting lines 113. However, in reality, any number of first connecting lines 112 may be arranged, as long as the first connecting lines 112 avoid the hollowed-out areas of the third vias 114 and the clock signal line 103. The number of second connecting lines 113 may be equal to the number of clock signal lines 103 in the second routing group.

[0104] First connecting line 112 includes a first end 1121 and a second end 1122 opposite each other. First end 1121 of first connecting line 112 is connected to any initial signal line 102 in the first routing group via first via 105. The orthographic projection of second end 1122 of first connecting line 112 on substrate 101 falls within the orthographic projection of clock signal line 103, farthest from initial signal line 102, among the multiple clock signal lines in the second routing group. That is, first connecting line 112 spans across multiple clock signal lines in the second routing group along second direction D2. Unlike driving circuit structure 200, first connecting line 112 is not connected to clock signal line 103 through first via 105, but is instead connected to clock signal line 103 by being fused to clock signal line 103 at fusion zone 117. Since the first connecting line 112 crosses multiple clock signal lines in the second routing group along the second direction D2, the first connecting line 112 can be welded to any clock signal line 103 in the second routing group, thereby greatly increasing the selectivity of the location of the welding area 117 and making the selection of the welding area 117 more flexible. Moreover, by adopting the arrangement of the first connecting line 112 crossing multiple clock signal lines in the second routing group along the second direction D2, even if a clock signal line 103 in the second routing group has a fault such as a break, other clock signal lines 103 in the second routing group that have not experienced the fault can be selected to be welded to the first connecting line 102, thereby greatly improving the connection reliability between the first connecting line 112 and the clock signal line 103 and improving the production yield of the product.

[0105] Each clock signal line 103 in the second wiring group is connected to one end of a corresponding second connection line 113 via a group of third vias 114 , and the other end of the second connection line 113 may be connected to a GOA unit.

[0106] Any clock signal line in the second routing group has two cut openings 115 and 116. First connecting line 112 is fused to clock signal line 103 with two cut openings at fusion zone 117. The clock signal line in the second routing group that is cut and fused determines which clock signal line is used to transmit the STV signal on initial signal line 102. Uncut and unfused clock signal lines do not transmit the STV signal. Any clock signal line from CLK1 to CLK12 can be selected to transmit the STV signal. Figure 12 uses clock signal line CLK3 as an example to transmit the STV signal. As shown in Figure 12, the clock signal line CLK3 has two cutting openings 115 and 116. The first end 1121 of the first connecting line 112 is connected to the initial signal line STV2 via the first via 105, and the first connecting line 112 is fused to the clock signal line CLK3 at the fusion zone 117. The initial signal line STV2 is connected to the clock signal line CLK3 by means of the first via 105, the first connecting line 112, and the fusion zone 117. The orthographic projection of the first connecting line 112 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line CLK3 on the substrate 101. The overlapping portion is the first orthographic projection. The clock signal line CLK3 is connected to the second connecting line 113 via a set of third vias 114. The second orthographic projection of the set of third vias 114 on the substrate 101 falls within the orthographic projection of the clock signal line CLK3 on the substrate 101. The first and second orthographic projections need to be located between the orthographic projections of the two cutting openings 115 and 116 on the substrate 101 to form an effective transmission path for the STV signal. For example, if the clock signal line CLK3 is selected to transmit the STV signal, the effective transmission path for the STV signal is as follows: the STV signal on the initial signal line STV2 is transmitted to the clock signal line CLK3 via the first connecting line 112. The clock signal line CLK3 then transmits the STV signal to the GOA unit via the second connecting line 113.

[0107] As shown in FIG12 , the driving circuit structure 300 may further include a first power signal line 110 (or VDDO line), a second power signal line 111 (or VDDE line), a common electrode lead COM, a third power signal line LVGL, and the like extending along a first direction D1. The display area of ​​the display panel may be located on a side of the third power signal line LVGL away from the second line group. The first power signal line 110 and the second power signal line 111 are located on a side of the second line group away from the first line group, and the orthographic projections of the cutting openings 115 and 116 and the fusion zone 117 of the clock signal line on the substrate 101 do not overlap with the orthographic projections of the first power signal line 110 and the second power signal line 111 on the substrate 101. As previously mentioned, in the related art, the initial signal line is very close to the first and second power signal lines. When the initial signal line and the clock signal line are fused, it is easy to cause a short circuit between the initial signal line and the nearby first and second power signal lines, thereby causing display abnormalities on the display panel. In contrast, in the driving circuit structure 300 of the embodiment of the present disclosure, the first power signal line 110 and the second power signal line 111 are designed to be away from the initial signal line 102, and the cutting openings 115, 116 and the welding area 117 of the clock signal line 103 do not overlap with the first power signal line 110 and the second power signal line 111. In this way, even if the STV signal is introduced into the GOA unit by cutting and welding the clock signal line 103, it will not cause a short circuit between the initial signal line 102 and the first power signal line 110 and the second power signal line 111.

[0108] As shown in FIG12 , to reduce resistance, the initial signal line 102 and the clock signal line 103 are designed to include hollow portions and solid portions. The orthographic projection of the first connecting line 112 on the substrate 101 may partially overlap with the orthographic projection of the solid portion of the clock signal line 103 on the substrate 101. However, the orthographic projections of the first connecting line 112 and the first via 105 on the substrate 101 do not overlap with the orthographic projections of the hollow portion of the clock signal line 103 on the substrate 101, i.e., they avoid the hollow portion of the clock signal line 103. Because the first connecting line 112 and the clock signal line 103 are located on different layers, by ensuring that the first connecting line 112 and the first via 105 avoid the hollow portion of the clock signal line 103, the problem of disconnection that occurs when the first connecting line 112 crosses a clock signal line 103 of a certain thickness can be reduced or even avoided, thereby improving the success rate of connecting the clock signal line 103 to the first connecting line 112.

[0109] In some embodiments, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the second connection line 113 on the substrate 101, thereby preventing a short circuit between the two. For example, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the third via 114 on the substrate 101.

[0110] Because the first connecting wire 112 is connected to the clock signal wire 103 by welding, it is possible to avoid providing the first via 105 at the location corresponding to the clock signal wire 103 in the first insulating layer 104. Furthermore, because the first via 105 is not provided at the location corresponding to the clock signal wire 103, external moisture will not corrode the clock signal wire 103 and / or the first connecting wire 112, thereby eliminating the need to provide a protective pad at the location corresponding to the first via 105.

[0111] The display panel including the above-mentioned driving circuit structure 300 can be a display panel of various appropriate types and sizes. For example, the display panel including the above-mentioned driving circuit structure 300 can be a strip display panel, which can be used to be installed on a subway for display. In some embodiments, the display panel including the above-mentioned driving circuit structure 300 is a strip screen with a size of 58.5 inches. The existing 65-inch mask plate can be optimized and designed, for example, a pattern of the first connecting line 112 is added to the existing 65-inch mask plate, and then the optimized 65-inch mask plate is used to prepare a 58.5-inch strip screen to achieve the sharing of the mask plate. The specific preparation method will be described later and will not be described in detail here.

[0112] FIG13 provides a schematic diagram of another arrangement of a drive circuit structure 400, which is a variation of the drive circuit structure 300. The drive circuit structure 400 shown in FIG13 has substantially the same construction as the drive circuit structure 300 shown in FIG12, and therefore, the same reference numerals are used to refer to the same components. For the sake of brevity, the similarities between the drive circuit structure 400 and the drive circuit structure 300 will not be repeated, and only the differences will be described below.

[0113] Unlike the driving circuit structure 300, in the driving circuit structure 400, the first connecting line 112 is connected to the clock signal line 103 through the first via 105. Specifically, the first connecting line 112 crosses multiple clock signal lines 103 in the second routing group along the second direction D2. The first connecting line 112 includes a first end 1121 and a second end 1122 that are opposite to each other. The first end 1121 of the first connecting line 112 is connected to any initial signal line 102 in the first routing group via the first via 105. The orthographic projection of the second end 1122 of the first connecting line 112 on the substrate 101 falls within the orthographic projection of the clock signal line 103 farthest from the initial signal line 102 among the multiple clock signal lines in the second routing group on the substrate 101. Any clock signal line 103 in the second routing group has two cutouts 115 and 116. The first connecting line 112 is connected to the clock signal line 103 having two cutouts via the first via 105.

[0114] In the driving circuit structure 400, the initial signal line 102 is connected to the first connection line 112 via the first via 105, and the first connection line 112 is connected to the clock signal line 103 via the first via 105. That is, the initial signal line 102 is connected to the clock signal line 103 via the first via 105 and the first connection line 112, avoiding welding with the clock signal line 103. Therefore, in the driving circuit structure 400, only the clock signal line 103 needs to be cut, without welding the clock signal line 103, to achieve the STV signal introduced into the GOA unit via the clock signal line 103 to achieve GOA driving.

[0115] For other technical effects of the driving circuit structure 400 , reference may be made to the technical effects of the driving circuit structure 300 , and for the sake of brevity, they will not be described in detail here.

[0116] Figure 14 provides a schematic structural diagram of a partial area of ​​a conventional array substrate 20. As shown in Figure 14, array substrate 20 includes: a substrate 11; a first conductive layer 21; a first insulating layer 22; a second conductive layer 23; a second insulating layer 24 including vias 26 and 27; and a third conductive layer 25. The second conductive layer 23 is connected to the third conductive layer 25 via vias 26, and the first conductive layer 21 is connected to the third conductive layer 25 via vias 27. That is, the second conductive layer 23 is connected to the first conductive layer 21 via the third conductive layer 25 (and vias 26 and 27). The first conductive layer 21 can be an initial signal line, and the second conductive layer 23 can be a clock signal line.

[0117] The array substrate 20 has two major problems: First, the second conductive layer 23 must be connected to the first conductive layer 21 via the third conductive layer 25. The material of the third conductive layer 25 is usually different from that of the first and second conductive layers 21, 23, and the third conductive layer 25 usually has a certain area. This results in a large contact resistance of the third conductive layer 25, which is not conducive to meeting the electrical requirements of the array substrate 20. Second, the second conductive layer 23 must be connected to the first conductive layer 21 via vias 26 and 27, and the via 27 is deep. During the etching process of the first and second insulating layers 22 and 24 to form the via 27, the metal-induced plasma effect causes the etching rate of the first and second insulating layers 22 and 24 near the second conductive layer 23 to be greater than the etching rate of other parts. This can easily lead to the hollowing of the first insulating layer 22 below the second conductive layer 23, resulting in the formation of a chamfer. The presence of the chamfer can easily cause other film layers to break at the chamfer, leading to problems such as abnormal connection and electrostatic breakdown.

[0118] The embodiment of the present disclosure provides an array substrate, which includes the driving circuit structure described in any of the above embodiments. The array substrate provided by the embodiment of the present disclosure can at least overcome the technical problems existing in the conventional array substrate 20.

[0119] Figure 15 shows a top view of a partial structure of an array substrate 500, and Figure 16 shows a cross-sectional view taken along line CC' in Figure 15. As shown in Figures 15 and 16, the array substrate 500 includes: a substrate 101; a first conductive layer 501 located on the substrate 101, the first conductive layer 501 being located on the same layer as the initial signal line 101; a first insulating layer 104 including a first via 105; a second conductive layer 502 located on a side of the first insulating layer 104 away from the substrate 101 and connected to the first conductive layer 501 via a conductive portion 106 in the first via 105; a second insulating layer 107 located on a side of the second conductive layer 502 away from the substrate 101 and including a fourth via 504; and a third conductive layer 503 located on a side of the second insulating layer 107 away from the substrate 101 and connected to the second conductive layer 502 via the fourth via 504.

[0120] Figures 15 and 16 illustrate a local area of ​​the array substrate 500. The local area may be the GOA area of ​​the array substrate 500, the fan-out area of ​​the array substrate 500, or the display area of ​​the array substrate 500. When the local area is the GOA area of ​​the array substrate 500, the first conductive layer 501 may refer to the initial signal line 102, and the second conductive layer 502 may refer to the clock signal line 103, i.e., this structure corresponds to the driving circuit structure 100. Alternatively, the first conductive layer 501 may refer to the initial signal line 102 and / or the clock signal line 103, and the second conductive layer 502 may refer to the first connecting line 112, i.e., this structure corresponds to the driving circuit structures 200, 300, or 400. When the local area is the display area of ​​the array substrate 500, the first conductive layer 501 may refer to the gate line and / or the gate electrode, the second conductive layer 502 may refer to the source and drain electrodes, and the third conductive layer 503 may be the pixel electrode.

[0121] Unlike array substrate 20, in array substrate 500, first conductive layer 501 is connected to second conductive layer 502 via conductive portion 106 in first via 105, not via third conductive layer 503. Second conductive layer 502 and conductive portion 106 in first via 105 are formed through the same patterning process. Therefore, conductive portion 106 in first via 105 and second conductive layer 502 are made of the same material. Consequently, the contact resistance of conductive portion 106 in first via 105 is negligible, i.e., zero, thereby improving the current withstand capability of array substrate 500. Furthermore, compared to via 27 in array substrate 20, first via 105 in array substrate 500 is shallower. This prevents chamfering of first insulating layer 104 during formation, thereby preventing problems such as film breakage, abnormal connections, and electrostatic breakdown, thereby improving the reliability of array substrate 500.

[0122] As shown in FIG16 , in some embodiments, the second insulating layer 107 may further include a fifth via 505, the third conductive layer 503 fills the fourth via 504 and the fifth via 505, and the depth T2 of the fifth via 505 is greater than the depth T1 of the fourth via 504. During the product design phase, the size of the fourth via 504 may be smaller than that of the fifth via 505. This is because, during the actual manufacturing process, the shallower fourth via 504 must be formed first, followed by the deeper fifth via 505. During the etching process of the fifth via 505, the fourth via 504 will inevitably be further etched, resulting in a further increase in the size of the fourth via 504. Therefore, during the design phase, the size of the fourth via 504 is designed to be smaller than that of the fifth via 505 to prevent a significant size difference between the fourth and fifth vias 504, 505. On the premise of meeting the design rules, the larger the size of the fourth via 504 and the fifth via 505, the better, because the fourth via 504 and the fifth via 505 are connected through the third conductive layer 503. The larger the size of the fourth via 504 and the fifth via 505, the larger the contact area of ​​the third conductive layer 503, and thus the lower the resistance of the fourth via 504 and the fifth via 505, and the better the current resistance of the product, thereby avoiding the electrostatic problem caused by excessive via current.

[0123] FIG17 shows comparative data of the contact resistance and current resistance parameters of a conventional array substrate 20 and an array substrate 500 according to an embodiment of the present disclosure. In the via pattern of FIG17 , the light-colored area refers to the first conductive layer, the dark-colored area refers to the second conductive layer, the squares in the light-colored area represent deep holes, and the squares in the dark-colored area represent shallow holes. In the conventional array substrate 20, the first conductive layer 21 is connected to the second conductive layer 23 via the via 26 (shallow hole) and the via 27 (deep hole). In the array substrate 500, the first conductive layer 501 is connected to the second conductive layer 502 via the conductive portion 106 in the first via 105. It can be seen from the data in FIG17 that the conventional array substrate 20 has a larger resistance value and a smaller current resistance value at the via; while the array substrate 500 has a negligible resistance value (0Ω) and a larger current resistance value (>10Ω) at the via. 3 mA).

[0124] In some alternative embodiments, the second insulating layer 107 may include only the fourth via hole 504 but not the fifth via hole 505, that is, the fifth via hole 505 may be filled. In this way, during the manufacturing process, there is no need to etch the deeper fifth via hole 505, thereby reducing etching time, reducing the size of the fourth via hole 504, and reducing the sizes of other via holes in the display area formed by the same process as the fourth via hole 504. This helps increase the aperture ratio of the display area, improves the transmittance of the array substrate 500, and reduces the power consumption of the array substrate 500.

[0125] FIG18 is a schematic structural diagram of a display device 600, which includes an array substrate 500. The array substrate 500 may include the driving circuit structure 100, 200, 300, or 400 described in any of the previous embodiments. Examples of the display device 600 include, but are not limited to, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, and navigation systems.

[0126] The display device 600 includes a display area 601 and a peripheral area 602 arranged on all sides of the display area 601. The driving circuit structure 100, 200, 300, 400 can be arranged at an appropriate position in the peripheral area 602. The driving circuit structure 100, 200, 300, 400 can be a gate drive circuit structure, which can include a plurality of cascaded shift register circuits. The gate drive circuit structure can generate a plurality of gate drive signals for outputting to gate lines, and a plurality of gate drive signals can be sequentially applied to each gate line. For example, the gate drive circuit structure can be integrated in the display device 600 as an array substrate row drive (gate driver on array, GOA) circuit.

[0127] The technical effects of the display device 600 can refer to the technical effects of the driving circuit structures described in the previous embodiments. For the sake of simplicity, the technical effects of the display device 600 will not be repeatedly described here.

[0128] FIG19 shows a flow chart of a method 700 for manufacturing an array substrate, wherein the array substrate may include the driving circuit structure described in any of the above embodiments. The method 700 may include the following steps:

[0129] S701: Provide a substrate 101.

[0130] S702 : forming a plurality of initial signal lines 102 on the substrate 101 .

[0131] S703 : forming a plurality of clock signal lines 103 on the substrate 101 .

[0132] S704 : forming a first insulating layer 104 including a plurality of first via holes 105 on a side of the initial signal line 102 away from the substrate 101 , wherein the initial signal line 102 is connected to the clock signal line 103 via the first via holes 105 .

[0133] In method 700, the initial signal line 102 is connected to the clock signal line 103 via the first via 105, thereby introducing the STV signal on the initial signal line 102 into the GOA unit via the clock signal line 103. This prevents short circuits between the initial signal line 102 and other lines, thereby helping to improve the production yield of the array substrate.

[0134] First, the general process of a method for preparing a conventional array substrate 20 can be described with reference to FIG. 14 .

[0135] A substrate 11 is provided.

[0136] Then, a first metal layer is deposited on the substrate 11, and photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed on the metal layer using mask template 1 to form a first conductive layer 21. The first conductive layer 21 can be an initial signal line, gate line, gate, etc.

[0137] Then, a gate insulating layer, an amorphous silicon layer, an ohmic contact layer, and a second metal layer are sequentially deposited on the side of the first conductive layer 21 away from the substrate 11. Using mask template 2, photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed on the second metal layer to form a first insulating layer 22 and a second conductive layer 23. The second conductive layer 23 includes, for example, a clock signal line, a first power signal line, a second power signal line, a source and a drain, etc.

[0138] Afterwards, an insulating layer is deposited on the side of the second conductive layer 23 away from the substrate 11, and photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed on the insulating layer using mask template three to form a second insulating layer 24. The second insulating layer 24 is formed with via patterns in the display area and the GOA area, for example, including vias 26 and 27.

[0139] Finally, an electrode layer is deposited on the side of the second insulating layer 24 away from the substrate 11. Using mask sheet 4, photoresist coating, exposure, development, etching, and photoresist stripping are performed on the second insulating layer 24 to form a third conductive layer 25. The third conductive layer 25 may include pixel electrodes in the display area and a connection layer in the GOA area. As shown in FIG14 , there are no vias between the first conductive layer 21 and the second conductive layer 23; the first conductive layer 21 and the second conductive layer 23 are connected via the third conductive layer 25.

[0140] In some embodiments, the size of the first, second, third, and fourth masks is 65 inches. For example, the array substrate 20 can be applied to a 65-inch TV.

[0141] The above-mentioned mask plates one, two, three, and four can be optimized and improved accordingly, and the array substrate provided by the embodiment of the present disclosure can be prepared by blocking exposure and local exposure to achieve the sharing of the mask plates. The size of the array substrate provided by the embodiment of the present disclosure is different from the size of the above-mentioned mask plates one, two, three, and four. The size of the above-mentioned mask plates one, two, three, and four is a first size, and the size of the array substrate formed by method 700 is a second size, and the first size is different from the second size. Exemplarily, the size of the above-mentioned mask plates one, two, three, and four is 65 inches, and the size of the array substrate formed by method 700 is 58.5 inches, which can be formed into a strip display screen. The strip display screen can be installed on a subway, for example, for display.

[0142] It should be noted that terms such as "the size of mask plates one, two, three, and four is the first size" mean that the length of the diagonal of mask plates one, two, three, and four is the first size. Similarly, terms such as "the size of the array substrate is the second size" mean that the length of the diagonal of the array substrate is the second size.

[0143] By optimizing and improving existing mask plates, they can be used to produce products of not only the first size, but also the second size, thereby increasing mask plate utilization and reducing development costs. Furthermore, since existing mask plates can be optimized to produce film layers of other sizes, eliminating the need to redesign and produce new mask plates, customer demands for products of different sizes can be met more quickly.

[0144] 20 , a more detailed description will be given of how to prepare an array substrate of the second size using an existing mask of the first size.

[0145] In the example of FIG20 , the existing mask has a length of y inches along the first direction D1, a width of 2x inches along the second direction D2, and a diagonal length of 65 inches, i.e., a first size. The existing mask can be used to form a certain film layer(s) on an array substrate, or a certain film layer(s) on a color filter substrate. By blocking half of the existing mask along the second direction D2, such that its length along the first direction D1 remains y inches, its width along the second direction D2 becomes x inches, and its diagonal length becomes 58.5 inches, a second size mask is formed. By blocking half of an existing mask during exposure on a substrate that is 2940 mm long in the first direction D1 and 3370 mm long in the second direction D2, ten substrates with a diagonal length of 58.5 inches can be formed. Substrate A1 can be a 58.5-inch array substrate, and substrate C1 can be a 58.5-inch color filter substrate. By performing normal exposure using an existing mask, two substrates A2 with a diagonal length of 65 inches can be formed on the right side of the substrate. Therefore, ten 58.5-inch strip-shaped substrates and two 65-inch non-strip-shaped substrates can be formed on a substrate that is 2940 mm long in the first direction D1 and 3370 mm long in the second direction D2.

[0146] It should be noted that using a 65-inch mask to create a 58.5-inch strip screen is just one example of how this can be done. The specific size of the strip screen can be determined based on customer needs and application scenarios. If a strip screen of another size is needed, a strip screen of the corresponding size can be obtained by blocking 1 / 3, 1 / 4, etc. of the 65-inch mask. Alternatively, a strip screen of another desired size can be obtained by partially blocking a mask of another size.

[0147] 21-25 , a method for preparing an array substrate including the driving circuit structure 100 will be described below.

[0148] The left side of Figure 21 is a top view, and the right side of Figure 21 is a cross-sectional view taken along line DD' of the top view. As shown in Figure 21, a substrate 101 is first provided. The material of the substrate 101 can be, for example, glass. A first metal layer is then deposited on the substrate 101, a portion of a first mask having a first size is shielded, and then processes such as photoresist coating, exposure, development, etching, and photoresist stripping are performed to pattern the first metal layer to form a plurality of initial signal lines 102, gate lines, gates, and other structures. The first mask can be the aforementioned mask 1. The material of the first metal layer includes, but is not limited to, molybdenum aluminum molybdenum (Mo / Al / Mo), molybdenum copper (Mo / Cu), molybdenum niobium copper (Mo / Nb / Cu), and molybdenum niobium copper molybdenum titanium (Mo / Nb / Cu / Mo / Ti).

[0149] The left side of Figure 22 is a top view, and the right side of Figure 22 is a cross-sectional view taken along line EE' of the top view. As shown in Figure 22, a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer are sequentially deposited on the side of the initial signal line 102 away from the substrate 101, blocking a portion of a second mask having a first size. Then, processes such as photoresist coating, exposure, development, etching, and photoresist stripping are performed to form a first insulating layer 104 and a plurality of first vias 105 penetrating the first insulating layer 104. The first vias 105 expose a portion of the surface of the initial signal line 102. The first vias 105 are located at the position where the initial signal line 102 overlaps with the clock signal line 103. By adding a design pattern of the first vias 105 to the aforementioned mask three at the position where the initial signal line 102 overlaps with the clock signal line 103, a second mask can be obtained.

[0150] Compared to FIG14 , the method provided in the embodiment of the present disclosure adds a separate masking process for forming the first insulating layer 104. In FIG14 , the first insulating layer 22 does not have vias at locations corresponding to the second conductive layer 23, and the first insulating layer 22 and the second conductive layer 23 are formed using a common mask. In contrast, in FIG22 , the first insulating layer 104 includes a first via 105 at locations corresponding to the clock signal line 103, requiring patterning of the first intermediate insulating layer. Therefore, a separate masking process is required to form the first insulating layer 104.

[0151] The left side of Figure 23 is a top view, and the right side of Figure 23 is a cross-sectional view taken along line FF' of the top view. As shown in Figure 23, a second metal layer is deposited on the side of the first insulating layer 104 away from the substrate 101, shielding a portion of a third mask having a first size. Then, processes such as photoresist coating, exposure, development, etching, and photoresist stripping are performed to pattern the second metal layer. Multiple clock signal lines 103, a first power signal line 110, a second power signal line 111, and source and drain electrodes (not shown) are formed on the side of the first insulating layer 104 away from the substrate 101. At the same time, a conductive portion 106 is formed in the first via 105. The initial signal line 102 is connected to the clock signal line 103 via the conductive portion 106 in the first via 105. The third mask can be the aforementioned mask 2. In some embodiments, the material of the second metal layer includes but is not limited to molybdenum aluminum molybdenum (Mo / AL / Mo), molybdenum copper (Mo / Cu), molybdenum niobium copper (Mo / Nb / Cu), and molybdenum niobium copper molybdenum titanium (Mo / Nb / Cu / Mo / Ti).

[0152] The initial signal line 102 is connected to the clock signal line 103 via the conductive portion 106 in the first via 105, without the need for welding. This prevents short circuits between the initial signal line 102 and other surrounding traces during the welding process, allowing the display panel including the driver circuit structure 100 to display normally. Furthermore, in Figure 23, the initial signal line 102 is connected to the clock signal line 103 via the conductive portion 106 in the first via 105. The depth of the first via 105 is significantly smaller than that of the via 27 in the conventional array substrate 20. Therefore, during the etching process of the first intermediate insulating layer to form the first via 105, no chamfers are formed, thereby preventing problems such as film breakage, abnormal connections, and electrostatic breakdown. Furthermore, the presence of the first via 105 improves the visibility of the repair point, helping to improve the efficiency and success rate of repairs by maintenance personnel. The design of the first via 105 enriches product design rules and expands the utilization rate of the mask.

[0153] The left side of Figure 24 is a top view, and the right side of Figure 24 is a cross-sectional view taken along line GG' of the top view. As shown in Figure 24, a second intermediate insulating layer is deposited on the side of the clock signal line 103 facing away from the substrate 101, shielding a portion of a second mask having a first size. Then, photoresist coating, exposure, development, etching, and photoresist stripping processes are performed to form a second insulating layer 107. Second insulating layer 107 includes multiple vias in the display area and multiple second vias 108 in the GOA area. Second vias 108 expose portions of the surface of the clock signal line 103. The first insulating layer 104 and the second insulating layer 107 are formed using a common second mask.

[0154] The left side of Figure 25 is a top view, and the right side of Figure 25 is a cross-sectional view taken along line AA' of the top view. As shown in Figure 25, a third metal layer is deposited on the side of the second insulating layer 107 away from the substrate 101 to block a portion of the fourth mask having a first size, and then photoresist coating, exposure, development, etching, photoresist stripping and other processes are performed to form pixel electrodes in the display area and protective pads 109 in the GOA area, and the protective pads 109 at least fill the second vias 108. The protective pads 109 are mainly used to prevent the corrosion of the clock signal line 103 and the conductive portion 106 by water vapor in the external environment. By adding a pattern of the protective pad 109 to the aforementioned mask four, a fourth mask can be obtained.

[0155] In preparing an array substrate including the drive circuit structure 100, by optimizing and improving the structures of some of the aforementioned mask plates, for example, by adding a design pattern for the first via 105 at the location corresponding to the clock signal line 103 on mask plate 3, and by adding a design pattern for the protective pad 109 on mask plate 4, first, second, third, and fourth mask plates can be obtained. By performing block exposure and partial exposure on the first, second, third, and fourth mask plates of a first size, an array substrate of a second size can be prepared, thereby enabling mask sharing. In this way, the mask plate of the first size can be used to prepare array substrates of both the first and second sizes, thereby improving mask utilization and saving product investment costs. In some embodiments, the first size can be 65 inches and the second size can be 58.5 inches. By blocking half of the mask plate of the first size and performing partial exposure, an array substrate of the second size can be obtained. The array substrate of the second size can be in the form of a strip to form a strip display screen, which can be installed on a subway for display, for example.

[0156] Next, a method for preparing an array substrate including a driving circuit structure 200 is briefly described with reference to FIG. 9 .

[0157] A substrate 101 is provided. A first metal layer is then deposited on the substrate 101. The first metal layer is patterned by masking a portion of a first mask having a first size to form a first routing group, a second routing group, gate lines, a gate electrode, and other structures. The first routing group includes a plurality of initial signal lines 102, and the second routing group includes a plurality of clock signal lines 103. The initial signal lines 102 and the clock signal lines 103 are arranged along a first direction and located on the same layer. Furthermore, the orthographic projections of the initial signal lines 102 and the clock signal lines 103 on the substrate 101 do not overlap. The first mask may be the aforementioned mask 1.

[0158] A first intermediate insulating layer is deposited on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101. The first intermediate insulating layer is patterned by masking a portion of a second mask having a first size to form a first insulating layer 104 including a plurality of first vias 105 and a plurality of groups of third vias 114. The first vias 105 partially expose the surfaces of the initial signal line 102 and the clock signal line 103, while the third vias 114 partially expose the surfaces of the clock signal line 103. A second mask is obtained by adding a design pattern of first vias 105 to the aforementioned third mask at positions corresponding to the clock signal lines 103.

[0159] A second metal layer is deposited on a side of the first insulating layer 104 away from the substrate 101, and the second metal layer is patterned by blocking a portion of a third mask having a first size to form structures such as at least one first connecting line 112 and at least one second connecting line 113 arranged along a second direction D2, a first power signal line 110, a second power signal line 111, and a source and drain (not shown). The first connecting line 112 includes a first end 1121 and a second end 1122 opposite each other. The first end 1121 of the first connecting line 112 is connected to any initial signal line 102 in the first routing group via a first via 105. The second end 1122 of the first connecting line 112 is connected to any clock signal line 103 in the second routing group via a first via 105. Each clock signal line 103 in the second routing group is connected to a corresponding second connecting line 113 via a set of third vias 114. By adding the design pattern of the first connecting line 112 to the aforementioned second mask, a third mask can be obtained.

[0160] A second intermediate insulating layer is deposited on a side of the first and second connecting lines 112 and 113 away from the substrate 101. The second intermediate insulating layer is patterned by masking a portion of the second mask to form a second insulating layer 107 including a plurality of second vias 108. The first insulating layer 104 and the second insulating layer 107 can be formed using a common second mask.

[0161] A third metal layer is deposited on the side of the second insulating layer 107 facing away from the substrate 101. The third metal layer is patterned by masking a portion of a fourth mask having the first size to form pixel electrodes in the display area and protective pads 109 in the GOA area. Protective pads 109 at least fill the second vias 108. Protective pads 109 primarily prevent corrosion of the first and second connecting lines 112, 113, and the conductive material in the first vias 105 by external moisture and the like. By adding the design pattern of protective pads 109 to the aforementioned mask four, a fourth mask is obtained.

[0162] Any clock signal line 103 in the second routing group is cut so that the clock signal line 103 has two cut openings 115 and 116. The orthographic projection of the clock signal line 103 with the two cut openings 115 and 116 on the substrate 101 partially overlaps with the orthographic projection of the first connection line 112 connected to the clock signal line 103 on the substrate 101. The overlapping portion is the first orthographic projection. The orthographic projection of one of the plurality of groups of third vias 114 on the substrate 101 is the second orthographic projection. The second orthographic projection falls within the orthographic projection of the clock signal line 103 with the two cut openings 115 and 116 on the substrate 101. The first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cut openings 115 and 116 on the substrate 101. The clock signal line 103 to be cut determines the clock signal line 103 selected to transmit the STV signal on the initial signal line 102. The clock signal lines 103 not cut do not transmit the STV signal. By locating the two cutting openings 115 and 116 on the clock signal line 103 above and below the first connecting line 112 and the third via 114, an effective transmission path for the STV signal is formed. In this embodiment, the initial signal line 102 is connected to the clock signal line 103 via the first via 105 and the first connecting line 112. This allows the STV signal to be transmitted via the clock signal line 103 by simply cutting the clock signal line 103, without the need to weld the clock signal line 103 to the first connecting line 112, thereby improving production efficiency.

[0163] In the preparation of an array substrate including the driving circuit structure 200, the structures of some of the aforementioned mask plates, namely, mask plates 1, 2, 3, and 4, are optimized and improved. For example, a design pattern for the first connecting line 112 is added to mask plate 2, a design pattern for the first via 105 is added to mask plate 3 at the location corresponding to the clock signal line 103, and a design pattern for the protective pad 109 is added to mask plate 4. First, second, third, and fourth mask plates of a first size are subjected to masking exposure and partial exposure, thereby producing an array substrate of a second size. This allows mask plates to be shared. In this way, a mask plate of the first size can be used to produce array substrates of both the first and second sizes, thereby improving mask utilization and saving product investment costs. In some embodiments, the first size can be 65 inches and the second size can be 58.5 inches. By masking half of the mask plate of the first size and performing partial exposure, an array substrate of the second size can be produced. The array substrate of the second size may be in a bar shape to form a bar display screen. The bar display screen may be installed on a subway for display, for example.

[0164] Next, a method for preparing an array substrate including a driving circuit structure 300 is briefly described with reference to FIG. 12 .

[0165] A substrate 101 is provided. A first metal layer is then deposited on the substrate 101. The first metal layer is patterned by masking a portion of a first mask having a first size to form a first routing group, a second routing group, gate lines, a gate electrode, and other structures. The first routing group includes a plurality of initial signal lines 102, and the second routing group includes a plurality of clock signal lines 103. The initial signal lines 102 and the clock signal lines 103 are arranged along a first direction D1 and are located on the same layer. Furthermore, the orthographic projections of the initial signal lines 102 and the clock signal lines 103 on the substrate 101 do not overlap. The first mask may be the aforementioned mask 1.

[0166] A first intermediate insulating layer and a second metal layer are sequentially deposited on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101. The first intermediate insulating layer and the second conductive layer are patterned by blocking a portion of a second mask having a first size to form a first insulating layer 104 including a plurality of first vias 105 and a plurality of groups of third vias 114, at least one first connecting line 112 and at least one second connecting line 113 arranged along a second direction D2, a first power signal line 110, a second power signal line 111, and a source and drain (not shown). Note that unlike the driving circuit structure 200, in this embodiment, the first insulating layer 104 includes first vias 105 only at locations corresponding to the initial signal line 102, and does not include first vias 105 at locations corresponding to the clock signal line 103. A first connecting line 112 spans multiple clock signal lines 103 in the second routing group along a second direction D2. The first connecting line 112 includes opposing first and second ends 1121 and 1122. The first end 1121 of the first connecting line 112 is connected to any initial signal line 102 in the first routing group via a first via 105. The orthographic projection of the second end 1122 of the first connecting line 112 on the substrate 101 falls within the orthographic projection of the clock signal line 103 farthest from the initial signal line 102 among the multiple clock signal lines in the second routing group. The first connecting line 112 spans multiple clock signal lines, providing multiple splice points and significantly increasing the selectivity of splice locations. Each clock signal line 103 in the second routing group is connected to one end of a corresponding second connecting line 113 via a set of third vias 114. The other end of the second connecting line 113 is connected to a GOA unit.

[0167] In this embodiment, first insulating layer 104 does not include additional first vias 105 at locations corresponding to clock signal lines 103. The structure of first insulating layer 104 is identical to that of first insulating layer 22 in the related art. Therefore, during the fabrication of driver circuit structure 300, first insulating layer 104 can share a second mask sheet with first connecting lines 112 and second connecting lines 113, eliminating the need for a separate masking process for first insulating layer 104. By adding the design pattern for second connecting lines 112 to the aforementioned second mask sheet, a second mask sheet can be obtained.

[0168] A second intermediate insulating layer is deposited on the side of first and second connecting lines 112 and 113 away from substrate 101. The second intermediate insulating layer is patterned by masking a portion of a third mask having the first size to form second insulating layer 107. Because first insulating layer 104 does not include additional first vias 105 at locations corresponding to clock signal lines 103, there is no need to provide protective pads to protect the metal. Consequently, there is no need to form second vias 108 in second insulating layer 107 at locations corresponding to first vias 105 to accommodate the protective pads. The third mask may be the aforementioned mask three.

[0169] A third metal layer is deposited on a side of the second insulating layer 107 facing away from the substrate 101. The third metal layer is patterned by masking a portion of a fourth mask having the first size to form pixel electrodes in the display area. As described above, since a protective pad is not required, there is no need to form a protective pad in the GOA area. Only the pixel electrodes need to be formed in the display area. The fourth mask can be the aforementioned mask 4.

[0170] Any clock signal line 103 in the second routing group is cut so that the clock signal line 103 has two cutting openings 115 and 116. The clock signal line 103 having the two cutting openings 115 and 116 is then welded to the first connecting line 112 located between the two cutting openings 115 and 116 at a welding point 117. The orthographic projection of the clock signal line 103 having the two cutting openings 115 and 116 on the substrate 101 partially overlaps with the orthographic projection of the first connecting line 112 welded to the clock signal line 103 on the substrate 101. The overlapping portion is a first orthographic projection. The orthographic projection of one of the plurality of groups of third vias 114 on the substrate 101 is a second orthographic projection. The second orthographic projection falls within the orthographic projection of the clock signal line 103 having the two cutting openings 115 and 116 on the substrate 101. The first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings 115 and 116 on the substrate 101.

[0171] The clock signal line 103 to be cut and spliced ​​determines which clock signal line 103 is used to transmit the STV signal on the initial signal line 102. Clock signal lines 103 that are not cut and spliced ​​do not transmit the STV signal. By locating the two cut openings 115 and 116 on the clock signal line 103 above and below the first connecting line 112 and the third via 114, an effective transmission path for the STV signal is formed. In this embodiment, although the clock signal line 103 needs to be cut and spliced ​​to transmit the STV signal, the first power signal line 110 and the second power signal line 111 are designed to be away from the initial signal line 102, and the cut openings 115, 116 and the splice area 117 of the clock signal line 103 do not overlap with the first power signal line 110 and the second power signal line 111. In this way, even if the STV signal is introduced into the GOA unit via the clock signal line 103 by cutting and welding, the initial signal line 102 will not be short-circuited with the first power signal line 110 and the second power signal line 111.

[0172] In the process flow for preparing an array substrate including the driving circuit structure 300, only the design pattern of the first connecting line 112 needs to be added to mask plate 2. There is no need to add the design pattern of the first via 105 to mask plate 3 or the design pattern of the protective pad 109 to mask plate 4. There is also no need to set up a separate mask process for the first insulating layer 104. Therefore, compared to the array substrate 20 of the related art, except for the need to add the design pattern of the first connecting line 112 to mask plate 2, the process flow of the array substrate including the driving circuit structure 300 is basically the same as that of the array substrate 20. By sharing the aforementioned first-sized mask plates 1, 3, and 4 and the improved mask plate 2, an array substrate of the second size can be prepared, thereby achieving mask sharing. In this way, the mask plate of the first size can be used to prepare not only the array substrate of the first size, but also the array substrate of the second size, thereby improving the utilization rate of the mask plates and saving product investment costs. In some embodiments, the first size can be 65 inches and the second size can be 58.5 inches. By blocking half of the first-sized mask plate for partial exposure, an array substrate of the second size can be obtained. The array substrate of the second size may be in a bar shape to form a bar display screen. The bar display screen may be installed on a subway for display, for example.

[0173] It will be understood that although the terms first, second, third, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another element, component, area, layer or part. Therefore, the first element, component, area, layer or part discussed above can be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0174] Spatially relative terms such as "row," "column," "under," "above," "left," "right," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, the element described as "under other elements or features" will be oriented as "above other elements or features." Thus, the exemplary term "under" can encompass both orientations of above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or one or more intermediate layers can also be present.

[0175] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" when used in this specification specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, wholes, steps, operations, elements, parts and / or their groups or add one or more other features, wholes, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of this specification, the description of the reference terms "one embodiment", "another embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. In this specification, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. Furthermore, those skilled in the art may combine different embodiments or examples and features of different embodiments or examples described in this specification without mutual contradiction.

[0176] It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, no intervening elements or layers are present. However, in no case should “on” or “directly on” be interpreted as requiring that one layer completely cover the underlying layer.

[0177] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. Because of this, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.

[0178] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0179] As will be appreciated by those skilled in the art, although the various steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order unless the context clearly indicates otherwise. Additionally or alternatively, multiple steps can be combined into a single step and / or a single step can be broken down into multiple steps and performed. In addition, other method steps can be inserted between steps. The inserted steps can represent improvements to the method described herein or can be unrelated to the method. In addition, a given step may not be fully completed before the next step begins.

[0180] Although the foregoing discussion contains several specific implementation details, these should not be construed as limitations on any invention or the scope of what may be claimed, but rather as descriptions of features that may be limited to specific embodiments of specific inventions. Specific features described in different embodiments throughout this specification may also be implemented in combination in a single embodiment. Conversely, different features described in a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination.

[0181] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A driving circuit structure, comprising: substrate; an initial signal line, located on the substrate; A clock signal line, located on the substrate; as well as a first insulating layer, located on a side of the initial signal line away from the substrate and comprising a first via hole, Wherein, the initial signal line is connected to the clock signal line via the first via hole.

2. The driving circuit structure according to claim 1, further comprising: A second insulating layer, located on a side of the first insulating layer away from the substrate and comprising a second via hole; as well as A protection pad, filling at least the second via hole, The orthographic projection of the protection pad on the substrate at least partially overlaps with the orthographic projection of the first via hole on the substrate.

3. The driving circuit structure according to claim 1, wherein: The clock signal line is located on a side of the initial signal line away from the substrate. A conductive portion is provided in the first via hole. One end of the conductive portion is directly connected to the initial signal line, and the other end of the conductive portion is directly connected to the clock signal line.

4. The driving circuit structure according to claim 3, wherein: The orthographic projection of the initial signal line on the substrate partially overlaps with the orthographic projection of the clock signal line on the substrate to form an overlapping area, and the orthographic projection of the first via on the substrate falls within the overlapping area.

5. The driving circuit structure according to claim 1, wherein: The initial signal line and the clock signal line are located in the same layer, and an orthographic projection of the initial signal line on the substrate does not overlap with an orthographic projection of the clock signal line on the substrate.

6. The driving circuit structure according to claim 5, further comprising: A first wiring group, comprising at least one initial signal line extending along a first direction; A second routing group, comprising at least one of the clock signal lines extending along the first direction, wherein an orthographic projection of the second routing group on the substrate does not overlap with an orthographic projection of the first routing group on the substrate; as well as at least one first connecting line extending along a second direction intersecting the first direction and located on a side of the first insulating layer away from the substrate, At least one clock signal line in the second wiring group is connected to any initial signal line in the first wiring group via the first connecting line.

7. The driving circuit structure according to claim 6, wherein: The clock signal line includes a hollow portion and a solid portion, the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the solid portion on the substrate, and the orthographic projection of the first connecting line and the first via on the substrate does not overlap with the orthographic projection of the hollow portion on the substrate.

8. The driving circuit structure according to claim 6, further comprising at least one second connecting line extending along the second direction, wherein: Each clock signal line in the second wiring group is connected to a corresponding second connecting line, and an orthographic projection of the first connecting line on the substrate does not overlap with an orthographic projection of the second connecting line on the substrate.

9. The driving circuit structure according to claim 8, wherein: The first insulating layer further includes a plurality of groups of third via holes, and each clock signal line in the second wiring group is connected to the corresponding second connecting line via a group of third via holes in the plurality of groups of third via holes.

10. The driving circuit structure according to claim 9, wherein: A clock signal line in the second wiring group has two cutting openings, Among them, one of the at least one first connecting line is connected to the clock signal line having two cutting openings, and the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the clock signal line having two cutting openings on the substrate, and the overlapping part is the first orthographic projection, and the orthographic projection of one group of third vias among the multiple groups of third vias on the substrate is the second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line having two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate.

11. The driving circuit structure according to claim 10, wherein: The first connection line includes a first end and a second end opposite to each other. The first end of the first connection line is connected to any initial signal line in the first wiring group via the first via hole. The second end of the first connection line is connected to any clock signal line in the second wiring group via the first via hole.

12. The driving circuit structure according to claim 10, wherein: The second routing group includes a plurality of clock signal lines arranged in parallel along the first direction, the first connecting line crosses the plurality of clock signal lines in the second routing group along the second direction, the first connecting line includes a first end and a second end opposite to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first routing group via the first via, and the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the plurality of clock signal lines of the second routing group on the substrate.

13. The driving circuit structure according to claim 12, wherein: One of the at least one first connecting line is fused to the clock signal line having two cutting openings.

14. The driving circuit structure according to claim 13, further comprising a first power signal line and a second power signal line extending along the first direction, wherein: The first power signal line and the second power signal line are located on a side of the second routing group away from the first routing group, and the orthographic projections of the cutting opening and the fusion area of ​​the clock signal line on the substrate do not overlap with the orthographic projections of the first power signal line and the second power signal line on the substrate.

15. The driving circuit structure according to claim 12, wherein: One of the at least one first connecting line is connected to the clock signal line having two cutting openings through the first via hole.

16. The driving circuit structure according to any one of claims 1 to 15, wherein: The first via hole includes a first opening and a second opening opposite to each other. The first opening and the second opening are circular or elliptical in shape. The longitudinal section of the first via hole is rectangular or inverted trapezoidal, and the longitudinal section is parallel to the thickness direction of the substrate.

17. An array substrate, comprising the driving circuit structure according to any one of claims 1-16.

18. The array substrate according to claim 17, further comprising: A first conductive layer, located at the same layer as the initial signal line; A second conductive layer is located on a side of the first insulating layer away from the substrate, and the first conductive layer is connected to the second conductive layer through a conductive portion in the first via hole; a second insulating layer, located on a side of the second conductive layer away from the substrate and comprising a fourth via hole; and The third conductive layer is located at a side of the second insulating layer away from the substrate and is connected to the second conductive layer via the fourth via hole.

19. The array substrate according to claim 18, wherein: The second insulating layer further includes a fifth via hole, the third conductive layer fills the fourth via hole and the fifth via hole, and a depth of the fifth via hole is greater than a depth of the fourth via hole.

20. A display device comprising the array substrate according to any one of claims 17 to 19.

21. The display device according to claim 20, wherein: The display device comprises a display area and a peripheral area arranged around the display area, and the driving circuit structure is arranged in the peripheral area.

22. A method for preparing an array substrate, comprising: providing a substrate; forming a plurality of initial signal lines on the substrate; forming a plurality of clock signal lines on the substrate; as well as A first insulating layer including a plurality of first via holes is formed on a side of the initial signal line away from the substrate, and the initial signal line is connected to the clock signal line via the first via holes.

23. The method according to claim 22, wherein: The initial signal line, the clock signal line, and the first insulating layer are formed respectively using different masks having a first size, so that the array substrate has a second size, the first size is larger than the second size, and the array substrate having the second size has a strip shape.

24. The method according to claim 23, wherein: A plurality of initial signal lines, a plurality of clock signal lines, and a first insulating layer are formed on the substrate, comprising: Depositing a first metal layer on the substrate, and patterning the first metal layer by masking a portion of a first mask having the first size to form the plurality of initial signal lines; Depositing a first intermediate insulating layer on a side of the initial signal line away from the substrate, and patterning the first intermediate insulating layer by covering a portion of a second mask having the first size to form the first insulating layer including a plurality of first via holes, wherein the first via holes expose a portion of the surface of the initial signal line; Depositing a second metal layer on a side of the first insulating layer away from the substrate, patterning the second metal layer by covering a portion of a third mask having the first size, so as to form the plurality of clock signal lines on a side of the first insulating layer away from the substrate, and forming a conductive portion in the first via hole, wherein the initial signal line is connected to the clock signal line via the conductive portion; Depositing a second intermediate insulating layer on a side of the clock signal line away from the substrate, and patterning the second intermediate insulating layer by blocking a portion of the second mask to form a second insulating layer including a plurality of second via holes, wherein the second via holes expose a portion of the surface of the clock signal line; and A third metal layer is deposited on a side of the second insulating layer away from the substrate, and the third metal layer is patterned by covering a portion of a fourth mask having the first size to form a protection pad, which at least fills the second via hole.

25. The method according to claim 23, wherein: A plurality of initial signal lines and a plurality of clock signal lines are formed on the substrate, comprising: A first metal layer is deposited on the substrate, and the first metal layer is patterned by covering a portion of a first mask having the first size to form a first routing group and a second routing group, wherein the first routing group includes a plurality of initial signal lines arranged along a first direction, and the second routing group includes a plurality of clock signal lines arranged along the first direction, and an orthographic projection of the first routing group on the substrate and an orthographic projection of the second routing group on the substrate do not overlap.

26. The method according to claim 25, further comprising: Depositing a first intermediate insulating layer on a side of the initial signal line and the clock signal line away from the substrate, and patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and a plurality of groups of third vias, wherein the first vias expose a portion of the surface of the initial signal line and the clock signal line, and the third vias expose a portion of the surface of the clock signal line; A second metal layer is deposited on a side of the first insulating layer away from the substrate, and the second metal layer is patterned by covering a portion of a third mask having the first size to form at least one first connecting line and at least one second connecting line arranged along a second direction, wherein the first connecting line comprises a first end and a second end opposite to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first wiring group via the first via hole, the second end of the first connecting line is connected to any one of the clock signal lines in the second wiring group via the first via hole, each of the clock signal lines in the second wiring group is connected to a corresponding one of the second connecting lines via a group of third via holes in the plurality of groups of third via holes, and the second direction intersects with the first direction; Depositing a second intermediate insulating layer on a side of the first connecting line and the second connecting line away from the substrate, and patterning the second intermediate insulating layer by covering a portion of the second mask to form a second insulating layer including a plurality of second via holes; Depositing a third metal layer on a side of the second insulating layer away from the substrate, and patterning the third metal layer by covering a portion of a fourth mask having the first size to form a protection pad, wherein the protection pad at least fills the second via hole; as well as cutting a clock signal line in the second wiring group so that the clock signal line has two cutting openings, Among them, the orthographic projection of the first connecting line connected to the clock signal line with two cutting openings on the substrate partially overlaps with the orthographic projection of the clock signal line with two cutting openings on the substrate, and the overlapping part is the first orthographic projection, and the orthographic projection of one group of third vias among the multiple groups of third vias on the substrate is the second orthographic projection, and the second orthographic projection falls within the orthographic projection of the clock signal line with two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate.

27. The method of claim 25, further comprising: A first intermediate insulating layer and a second metal layer are sequentially deposited on a side of the initial signal line and the clock signal line away from the substrate, and the first intermediate insulating layer and the second metal layer are patterned by covering a portion of the second mask having the first size to form a first insulating layer including the plurality of first vias and the plurality of groups of third vias, and at least one first connecting line and at least one second connecting line arranged along a second direction, wherein the first via exposes a portion of the surface of the initial signal line, the third via exposes a portion of the surface of the clock signal line, the first connecting line crosses over a plurality of clock signal lines in the second routing group along the second direction, the first connecting line includes a first end and a second end opposite to each other, the first end of the first connecting line is connected to any one of the initial signal lines in the first routing group via the first via, the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line farthest from the initial signal line among the plurality of clock signal lines in the second routing group on the substrate, each clock signal line in the second routing group is connected to a corresponding second connecting line via a group of third vias in the plurality of groups of third vias, and the second direction intersects with the first direction; Depositing a second intermediate insulating layer on a side of the first connecting line and the second connecting line away from the substrate, and patterning the second intermediate insulating layer by blocking a portion of a third mask having the first size to form a second insulating layer; Depositing a third metal layer on a side of the second insulating layer away from the substrate, and patterning the third metal layer by covering a portion of a fourth mask having the first size to form a pixel electrode; Cutting a clock signal line in the second wiring group so that the clock signal line has two cutting openings; and The clock signal line having the two cutting openings is welded with the first connecting line located between the two cutting openings in the welding area, Among them, the orthographic projection of the fusion zone on the substrate is the first orthographic projection, the orthographic projection of a group of third vias among the multiple groups of third vias on the substrate is the second orthographic projection, the second orthographic projection falls within the orthographic projection of the clock signal line with two cutting openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cutting openings on the substrate.

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