Shift register unit, display device, and driving method

Abstract

The present application relates to the technical field of display, and discloses a shift register unit, a display device, and a driving method. The shift register unit comprises: a decoding control sub-circuit which enables a first gating clock end to be connected to a first node in response to a signal of a gating control end; a node control sub-circuit which is coupled to the first node, a second node, and a third node, and controls signals of the second node and the third node in response to a signal of the first gating clock end, a signal of a second gating clock end, and a signal of the first node; and an output sub-circuit which is coupled to the second node, the third node, and driving output ends, wherein a plurality of driving output ends are electrically connected to a plurality of output clock signal ends, and the output sub-circuit provides signals of the plurality of output clock signal ends to the driving output ends in response to the signal of the second node, and provides a signal of a reference signal end to the plurality of driving output ends in response to the signal of the third node. Therefore, the output flexibility of the driving output ends is improved.

Description

A shift register unit, a display device and a driving method Technical Field

[0001] The present application relates to the field of display technology and provides a shift register unit, a display device and a driving method. Background Art

[0002] Currently, high-end monitors have stringent requirements for image quality, especially professional gaming monitors, which require extremely high refresh rates. To achieve a good balance between power consumption and extremely high refresh rates, regional high refresh rate technology (i.e., intra-frame frequency conversion, where only dynamic images use the high refresh rate) is generally used. This technology requires the driver circuit to be able to flexibly turn on and off and have random gating capabilities.

[0003] With the increasing PPI of displays and the growing popularity of VR, AR, and 3D display applications, the need for random gating in driver circuits is increasing to reduce frame transmission data, ensuring high-definition, high-frequency drive in dynamic or focused areas. Existing shift register circuits can only sequentially open pixel cells from the top row to the bottom row, resulting in a limited display drive capability and an inability to adjust to the image in real time, failing to meet the demands of high-end displays. As shown in Figure 1, to achieve regional high refresh rate technology, traditional shift registers must be divided into several zones during design. This allows for localized high refresh rate control of a specific zone. Furthermore, once the zones are set, the maximum number of zones cannot be changed. As shown in Figure 1, the maximum number of zones is limited to eight. Requirement of more zones requires additional STU signals and dummy units. This means that traditional shift register partitioning increases hardware complexity.

[0004] Summary of the Invention

[0005] Embodiments of the present application provide a shift register unit, a display device, and a driving method to enhance the output flexibility of the display device.

[0006] The specific technical solutions provided in this application are as follows:

[0007] In a first aspect, an embodiment of the present application provides a shift register unit, comprising:

[0008] Decoding control subcircuit, node control subcircuit and output subcircuit;

[0009] The decoding control subcircuit is configured to connect the first gating clock terminal to the first node in response to the signal of the gating control terminal;

[0010] The node control subcircuit is coupled to the first node, the second node, and the third node, and is configured to control signals of the second node and the third node in response to a signal of the first gating clock terminal, a signal of the second gating clock terminal, and a signal of the first node;

[0011] The output sub-circuit is coupled to the second node, the third node and a plurality of driving output terminals. The plurality of driving output terminals are electrically connected to a plurality of output clock signal terminals. The output sub-circuit is configured to provide signals from the plurality of output clock signal terminals to the driving output terminals in response to a signal from the second node; and to provide a signal from the reference signal terminal to the plurality of driving output terminals in response to a signal from the third node.

[0012] In some possible implementations, the decoding control subcircuit includes: N gating transistors, where N is a positive integer greater than or equal to 1;

[0013] The control terminal of the gate transistor is coupled to the gate control terminal, the first terminal of the gate transistor is coupled to the first gate clock terminal, and the second terminal of the gate transistor is coupled to the first node.

[0014] In some possible implementations, the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit, and a fourth node control subcircuit;

[0015] The first node control subcircuit is coupled to the first node and is configured to provide the signal of the first node and the signal of the first high-level signal terminal to the second node in response to the signal of the second selection clock terminal;

[0016] The second node control subcircuit is coupled to the second node and configured to provide a signal from the second gating clock terminal to the second node in response to a signal from the first node;

[0017] The third node control subcircuit is coupled to the first gating clock terminal, the second node, and the third node, and is configured to provide the signal of the second high level signal terminal and the first gating clock terminal to the third node in response to the signal of the second node and the third gating clock terminal;

[0018] The fourth node control sub-circuit is coupled to the third node and is configured to provide the signal of the first low-level control terminal to the third node in response to the signal of the second selection clock terminal.

[0019] In some possible implementations, the first node control subcircuit includes: a first transistor and a first capacitor;

[0020] The control terminal of the first transistor is coupled to the second selection clock terminal, the first terminal of the first transistor is coupled to the first high level signal terminal, and the second terminal of the first transistor is coupled to the second node;

[0021] A first terminal of the first capacitor is coupled to the first high-level signal terminal, and a second terminal of the first capacitor is coupled to the second node.

[0022] In some possible implementations, the second node control subcircuit includes: a second transistor, a third transistor, and a fourth transistor;

[0023] The control terminal of the second transistor is coupled to the first node, the first terminal of the second transistor is coupled to the second selection clock terminal, and the second terminal of the second transistor is coupled to the first terminal of the third transistor;

[0024] A control terminal of the third transistor is coupled to the first node, and a second terminal of the third transistor is coupled to the second node;

[0025] The control terminal of the fourth transistor is coupled to the second node, the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, and the second terminal of the fourth transistor is coupled to the first high-level signal terminal.

[0026] In some possible implementations, the third node control subcircuit includes: a fifth transistor, a sixth transistor, and a seventh transistor;

[0027] The control terminal of the fifth transistor is coupled to the second node, the first terminal of the fifth transistor is coupled to the second terminal of the sixth transistor, and the second terminal of the fifth transistor is coupled to the first terminal of the seventh transistor;

[0028] The control terminal of the sixth transistor is coupled to the first selection clock terminal, the first terminal of the sixth transistor is coupled to the second high level signal terminal, and the second terminal of the sixth transistor is coupled to the first terminal of the fifth transistor;

[0029] The control terminal of the seventh transistor is coupled to the third gating clock terminal, and the second terminal of the seventh transistor is coupled to the first gating clock terminal.

[0030] In some possible implementations, the fourth node control subcircuit includes: an eighth transistor, a ninth transistor, and a second capacitor;

[0031] The control terminal of the eighth transistor is coupled to the second gating clock terminal, the first terminal of the eighth transistor is coupled to the first node, and the second terminal of the eighth transistor is coupled to the first gating clock terminal;

[0032] The control terminal of the ninth transistor is coupled to the fifth node, the first terminal of the ninth transistor is coupled to the third node, and the second terminal of the ninth transistor is coupled to the first low-level control terminal;

[0033] A first terminal of the second capacitor is coupled to the third node, and a second terminal of the second capacitor is coupled to the first low-level control terminal.

[0034] In some possible implementations, the output sub-circuit includes: a first gating control sub-circuit and a plurality of output control sub-circuits;

[0035] a first gating control subcircuit configured to provide a signal from the first high-level signal terminal to the fourth node in response to a signal from the second node and a signal from the third gating clock terminal, provide a signal from the third gating clock terminal to the fourth node in response to a signal from the second gating clock terminal, and provide a signal from the leakage control terminal to the fourth node in response to a signal from the fifth node;

[0036] The plurality of output control sub-circuits correspond one-to-one to the plurality of drive output terminals and the plurality of output clock signal terminals. The output control sub-circuit is configured to connect the fourth node and the fifth node in response to the signal of the third selection clock terminal, and to provide the signal of the corresponding output clock signal terminal to the drive output terminal in response to the signal of the fifth node, and to provide the signal of the reference signal terminal to the corresponding drive output terminal in response to the signal of the third node, and to provide the signal of the first low-level control terminal to the fifth node and the drive output terminal in response to the signal of the third node.

[0037] In some possible implementations, the first gating control subcircuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor;

[0038] The control terminal of the tenth transistor is coupled to the second node, the first terminal of the tenth transistor is coupled to the second terminal of the eleventh transistor, and the second terminal of the tenth transistor is coupled to the fourth node;

[0039] The control terminal of the eleventh transistor is coupled to the third selection clock terminal, and the first terminal of the eleventh transistor is coupled to the first high level signal terminal;

[0040] The control terminal of the twelfth transistor is coupled to the second selection clock terminal, the first terminal of the twelfth transistor is coupled to the third selection clock terminal, and the second terminal of the twelfth transistor is coupled to the first terminal of the fourteenth transistor;

[0041] a control terminal of the thirteenth transistor coupled to the second selection clock terminal, a first terminal of the thirteenth transistor coupled to the first terminal of the twelfth transistor, and a second terminal of the thirteenth transistor coupled to the fourth node;

[0042] The control terminal of the fourteenth transistor is coupled to the fifth node, and the second terminal of the fourteenth transistor is coupled to the leakage control terminal.

[0043] In some possible implementations, the output control subunit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a third capacitor;

[0044] A control terminal of the fifteenth transistor is coupled to the third selection clock terminal, a first terminal of the fifteenth transistor is coupled to the fourth node, and a second terminal of the fifteenth transistor is coupled to the fifth node;

[0045] A control terminal of the sixteenth transistor is coupled to the fifth node, a first terminal of the sixteenth transistor is coupled to the first output clock signal terminal, and a second terminal of the sixteenth transistor is coupled to the driving output terminal;

[0046] The control terminal of the seventeenth transistor is coupled to the third node, the first terminal of the seventeenth transistor is coupled to the driving output terminal, and the second terminal of the seventeenth transistor is coupled to the second low-level control terminal;

[0047] a control terminal of the eighteenth transistor coupled to the third node, a first terminal of the eighteenth transistor coupled to the fifth node, and a second terminal of the eighteenth transistor coupled to the first terminal of the nineteenth transistor;

[0048] The control terminal of the nineteenth transistor is coupled to the third node, and the second terminal of the nineteenth transistor is coupled to the first low-level control terminal;

[0049] A first terminal of the third capacitor is coupled to the fifth node, and a second terminal of the third capacitor is coupled to the driving output terminal.

[0050] In some possible embodiments, an initialization control subcircuit is further included, which is coupled to the second node and the third node and is configured to provide a signal from the first low-level control terminal to the second node in response to a signal from the initialization signal terminal, and to provide a signal from the first high-level signal terminal to the third node in response to a signal from the initialization signal terminal.

[0051] In some possible implementations, the initialization control subcircuit includes: a twentieth transistor, a twenty-first transistor, and a twenty-second transistor;

[0052] A control terminal of the 20th transistor is coupled to the initialization signal terminal, a first terminal of the 20th transistor is coupled to the second node, and a second terminal of the 20th transistor is coupled to the first terminal of the 22nd transistor;

[0053] A control terminal of the twenty-first transistor is coupled to the initialization signal terminal, a first terminal of the twenty-first transistor is coupled to the first high-level signal terminal, and a second terminal of the twenty-first transistor is coupled to the third node;

[0054] The control terminal of the twenty-second transistor is coupled to the initialization signal terminal, and the second terminal of the twenty-second transistor is coupled to the second terminal of the second capacitor.

[0055] In a second aspect, an embodiment of the present application further provides a display device, comprising: the above-mentioned gate driving circuit.

[0056] In a third aspect, an embodiment of the present application further provides a display device, comprising: a plurality of gate lines and a plurality of shift register units according to any one of the above items;

[0057] The plurality of gate lines are coupled to the driving output terminals of the plurality of shift register units in a one-to-one correspondence.

[0058] In some possible implementations, the first clock signal terminals CK1 of the 3k-2 stage shift register units are all coupled to the same clock terminal, namely, the second gate clock terminal CLKD1; the second clock signal terminals CK2 are all coupled to the same clock terminal, namely, the first gate clock terminal CLKD2; and the third clock signal terminals CK3 are all coupled to the same clock terminal, namely, the third gate clock terminal CLKD3.

[0059] The first clock signal terminals CK1 of the 3k-1th stage shift register units are all coupled to the same clock terminal, namely the first selection clock terminal CLKD2; the second clock signal terminals CK2 are all coupled to the same clock terminal, namely the third selection clock terminal CLKD3; and the third clock signal terminals CK3 are all coupled to the same clock terminal, namely the second selection clock terminal CLKD1;

[0060] The first clock signal terminals CK1 of the 3k-stage shift register units are all coupled to the same clock terminal, namely the third selection clock terminal CLKD3; the second clock signal terminals CK2 are all coupled to the same clock terminal, namely the second selection clock terminal CLKD1; and the third clock signal terminals CK3 are all coupled to the same clock terminal, namely the first selection clock terminal CLKD2; wherein k is a positive integer.

[0061] In some possible implementations, the selection control terminals of the 3k-2th stage shift register unit, the 3k-1th stage shift register unit, and the 3kth stage shift register unit are coupled to the same signal line group, where k is a positive integer.

[0062] In some possible implementations, the gating control terminals of the 6k-5th stage shift register unit, the 6k-4th stage shift register unit, and the 6k-3th stage shift register unit are coupled to the first group of signal lines;

[0063] The selection control ends of the 6k-2th shift register unit, the 6k-1th shift register unit and the 6kth shift register unit are coupled to the second group of signal line groups, wherein the output signals in the first group of signal line groups and the second group of signal line groups are different, and k is a positive integer.

[0064] In some possible implementations, a decoder is further included, and an output terminal of the decoder provides different output signals to the first group of signal lines and the second group of signal lines.

[0065] In some possible implementations, the shift register units connected to the signal line group with the same output signal are in the same display partition.

[0066] In a fourth aspect, an embodiment of the present application further provides a method for driving a shift register unit, comprising:

[0067] The decoding control subcircuit connects the first strobe clock terminal to the first node in response to the signal of the strobe control terminal;

[0068] The node control subcircuit controls the signals of the second node and the third node in response to the signal of the first gating clock terminal, the signal of the second gating clock terminal and the signal of the first node;

[0069] The output sub-circuit provides signals from the plurality of output clock signal terminals to the driver output terminals in response to a signal at the second node; and provides signals from the reference signal terminal to the plurality of driver output terminals in response to a signal at the third node.

[0070] The beneficial effects of this application are as follows:

[0071] In summary, the embodiments of the present application provide a shift register unit, a display device, and a driving method. The shift register unit includes: a decoding control subcircuit, a node control subcircuit, and an output subcircuit. The decoding control subcircuit is configured to connect the first selection clock terminal to the first node in response to the signal of the selection control terminal. The node control subcircuit is coupled to the first node, the second node, and the third node, and is configured to control the signals of the second node and the third node in response to the signal of the first selection clock terminal, the signal of the second selection clock terminal, and the signal of the first node. The output subcircuit is coupled to the second node, the third node, and a plurality of driving output terminals. The plurality of driving terminals are connected to the first node, the second node, and the third node. The driving output terminal is electrically connected to multiple output clock signal terminals, and the output sub-circuit is configured to provide signals from multiple output clock signal terminals to the driving output terminal in response to the signal of the second node, and to provide the signal from the reference signal terminal to the multiple driving output terminals in response to the signal of the third node. That is, the partition setting of the driving output terminal of the shift register unit is realized by different signal combinations of multiple selection control terminals, and the group setting within the partition is realized by different combinations of multiple selection clock terminals, thereby realizing the selection control of the above-mentioned partitions and groups, and improving the flexibility of the selection output of the above-mentioned driving output terminal without the need to add any additional hardware units.

[0072] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0074] FIG1 is a schematic diagram of a shift register unit in the related art;

[0075] FIG2 is a schematic diagram of a shift register unit in an embodiment of the present application;

[0076] FIG3 is a schematic diagram of display division of a display device in an embodiment of the present application;

[0077] FIG4 is a connection diagram of a shift register unit according to an embodiment of the present application;

[0078] FIG5 is a circuit connection diagram of a shift register unit in an embodiment of the present application;

[0079] FIG6 is a connection diagram of another shift register unit in an embodiment of the present application;

[0080] FIG7 is a timing diagram of the operation of the shift register unit in an embodiment of the present application;

[0081] FIG8 is a signal timing diagram of the strobe control terminal in an embodiment of the present application;

[0082] FIG9 is a connection diagram of a display device according to an embodiment of the present application;

[0083] FIG. 10 is a flow chart of a driving method of a shift register unit in the related art. DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0085] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0086] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0087] In related art, achieving regional high refresh rate technology requires pre-dividing the display device's shift register into several fixed zones during design. This allows for localized high refresh rate control of a particular zone. Obviously, the shift register itself cannot be flexibly switched on demand. Furthermore, once the display device is partitioned, the maximum number of zones cannot be changed. As shown in Figure 1, the maximum number of zones is limited to eight. Demanding more zones requires additional hardware, such as STU signals and dummy GOA units.

[0088] In Figure 1 above, 8 STU signals are added at both ends of the AA area to connect with the 8 GOA partitions located in the AA area, and the STU signal provides a start signal for the driving GOA in each partition to ensure that the pixel units in each partition display normally.

[0089] In addition, two dummy GOA units are required in the AA area to provide a set cascade signal for the first row of GOA in the first partition and a reset cascade signal for the last row of GOA in the eighth partition, respectively, to ensure that the pixel units in the entire AA area are displayed in the next frame. It should be noted that in the related art, after using STU signals and dummy GOA units for partition design, the maximum number of partitions cannot be changed. Only fixed rows can be enabled, and no rows can be enabled at will.

[0090] Referring to Figures 2 and 3, an embodiment of the present application shows a shift register unit, a display device and a driving method. In the present application, the shift register included in the display device is divided into multiple display partitions according to different combinations of signals in multiple selection control terminals, and the shift register included in the same display partition is further divided into multiple display groups, i.e., shift register units, according to different combinations of signals in multiple selection clock terminals. In this way, flexible output display of different display partitions and different shift register units in the display device is achieved according to the different selection conditions of the selection control terminal and the selection clock terminal.

[0091] As shown in FIG2 , there is no need to divide the AA area into display zones through STU signals and dummyGOA units. Instead, circuit improvements are made inside the GOA, and the improved multiple GOA units drive the output display of the corresponding row pixel units.

[0092] The display device shown in FIG2 of an embodiment of the present application includes: a plurality of pixel units arranged in an array, a plurality of gate lines, a plurality of data lines, a plurality of shift register units, and a source drive circuit. Each pixel unit includes a plurality of sub-pixels. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve a color display. Alternatively, a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve a color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0093] Exemplarily, multiple shift register units are coupled to multiple gate lines, and source driver circuits are coupled to multiple data lines. When the display device is operating, control signals are input to the shift register units, causing them to output signals to the coupled gate lines, thereby driving the gate lines. Furthermore, the source driver circuits input data voltages to the data lines based on display data, thereby charging the sub-pixels and causing them to receive corresponding data voltages, thereby achieving image display.

[0094] For example, two source driver circuits may be provided, wherein one source driver circuit may be connected to half the number of data lines, and the other source driver circuit may be connected to the other half of the number of data lines. Of course, in actual applications, three, four, or more source driver circuits may also be provided, which may be determined according to the requirements of the actual application environment, and this disclosure is not limited thereto.

[0095] In some embodiments of the present disclosure, one column of sub-pixels may correspond to one data line, or alternatively, one column of sub-pixels may correspond to multiple data lines, which is not limited here.

[0096] In some embodiments of the present disclosure, the plurality of gate lines may include: a plurality of first gate lines and a plurality of second gate lines. Alternatively, a row of sub-pixels may correspond to one first gate line and one second gate line. Of course, a row of sub-pixels may also correspond to a plurality of first gate lines, and a row of sub-pixels may also correspond to a plurality of second gate lines, which are not limited herein.

[0097] In some embodiments of the present disclosure, the display device further includes: a plurality of light-emission control signal lines and a plurality of reset control signal lines. Optionally, a row of sub-pixels may correspond to one light-emission control signal line and one reset control signal line. Of course, a row of sub-pixels may also correspond to multiple light-emission control signal lines, and a row of sub-pixels may also correspond to multiple reset control signal lines, without limitation herein.

[0098] The display device can adopt single-sided drive or double-sided drive. For example, referring to FIG2 , when double-sided drive is adopted, the shift register includes a GOA unit on the left side and another GOA unit on the right side, coupled to both sides of the gate line. The GOA unit on the left side and the other GOA unit on the right side are used to simultaneously drive the coupled gate lines.

[0099] In the embodiment of the present application, the configuration of the above-mentioned GOA unit enables the display partition to be adjusted through the selection signal, which is flexible and changeable, and can realize the opening of any row to a certain extent.

[0100] Referring to FIG3 , it is assumed that the entire display area AA is divided into three display partitions, namely display partition 1, display partition 2 and display partition 3. In order to more flexibly select the output of the relevant pixel units, the display partitions can be further subdivided. For example, using the scheme shown in FIG3 , each display partition is further divided into three display groups, that is, display partition 1 is divided into display group 1, display group 2 and display group 3, display partition 2 is divided into display group 4, display group 5 and display group 6, and display partition 3 is divided into display group 7, display group 8 and display group 9. In this way, the division of the entire AA area is achieved.

[0101] It should be supplemented that the shift register unit in the present application includes at least two driving output terminals, and the at least two driving output terminals simultaneously output signals to the outside to achieve high refresh rate display of the picture.

[0102] The preferred embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0103] 4 , in an embodiment of the present application, a shift register unit includes a decoding control subcircuit 100 , a node control subcircuit 200 , and an output subcircuit 300 .

[0104] The decoding control sub-circuit 100 is configured to connect the first strobe clock terminal CLKD1 to the first node N1 in response to signals from the strobe control terminals D0 to D7.

[0105] In the embodiment of the present application, there are multiple selection control terminals D0~D7. After the signals of the above multiple selection control terminals D0~D7 are combined, a shift register unit, that is, an output sub-circuit 300, can be correspondingly selected. Unlike a traditional shift register, the above output sub-circuit 300 includes multiple driving output terminals Output1~Output4. After a certain output sub-circuit 300 is selected by the signal of the selection control terminal D0~D7, the above multiple driving output terminals Output1~Output4 are output simultaneously, that is, the output display of a shift register unit is realized.

[0106] During implementation, when one of the signals of the selection control terminals D0-D7 is valid, the decoding control sub-circuit 100 connects the first selection clock terminal CLKD1 to the first node N1, that is, the voltage of the first node N1 is high through the first selection clock terminal CLKD1.

[0107] After setting up multiple display partitions for the display device, different shift register units are further set up for the display partitions. The division of the shift register units is achieved by multiple gated clock terminals. In the embodiment of the present application, a first gated clock terminal CLKD1, a second gated clock terminal CLKD2, and a third gated clock terminal CLKD3 are included, so that three shift register units are set up in one display partition. It should be noted that the signal provided by the first gated clock terminal CLKD1 is a pulse signal. The rising and falling edges of the first gated clock terminal CLKD1, the second gated clock terminal CLKD2, and the third gated clock terminal CLKD3 correspond to different times, as shown in FIG7 . In this way, different combinations of the first gated clock terminal CLKD1, the second gated clock terminal CLKD2, and the third gated clock terminal CLKD3 correspond to different shift register units (i.e., the output sub-circuit 300).

[0108] 5 , the decoding control sub-circuit 100 includes N gate transistors, where N is a positive integer greater than or equal to 1.

[0109] The control terminal of the gate transistor is coupled to the gate control terminals D0 to D7 , the first terminal of the gate transistor is coupled to the first gate clock terminal CLKD1 , and the second terminal of the gate transistor is coupled to the first node N1 .

[0110] In order to receive the signals of the selection control terminals D0~D7, N selection transistors are provided in the embodiment of the present application. The control terminal of each selection transistor is coupled to one of the selection control terminals D0~D7, the first terminal of the selection transistor is coupled to the first selection clock terminal CLKD1, and the second terminal of the selection transistor is coupled to the first node N1, so that when the selection transistor is turned on, the signal of the first selection clock terminal CLKD1 is provided to the first node N1.

[0111] As shown in FIG5 , the gate control terminals D0-D7 include gate transistors M1, M2, M3, M4, M5, M6, M7, and M8. It should be noted that the number of these transistors is related to the number of display sub-regions required in the display device. When the number of display sub-regions required in the display device is large, the number of these transistors is also large. For example, when there are eight transistors, the signal of each gate control terminal D0-D7 can have two states, 0 and 1. Therefore, there are 256 possible signal combinations of the gate control terminals D0-D7. This means that a maximum of 256 display sub-regions, i.e., output sub-circuits 300, can be enabled to meet the display requirements of the display device.

[0112] For example, when the signal of the selection control terminal D0 coupled to the selection transistor M1 is at a high potential, the corresponding selection transistor M1 is turned on, and when the signals of the remaining selection control terminals D1 to D7 coupled to the selection transistors M2, M3, M4, M5, M6, M7 and M8 are all at low potentials, the selection transistors M2, M3, M4, M5, M6, M7 and M8 are all turned off, and the high potential signal of the first selection clock terminal CLKD1 is provided to the first node N1 via the turned-on selection transistor M1.

[0113] It should be noted that, when any one of the gate transistors M1, M2, M3, M4, M5, M6, M7, and M8 is turned on, the high-potential signal of the first gate clock terminal CLKD1 is provided to the first node N1 via the turned-on gate transistor. Only when the signals of the gate control terminals D0 to D7 are all at a low level, and the gate transistors M1, M2, M3, M4, M5, M6, M7, and M8 are all turned off, the high-potential signal of the first gate clock terminal CLKD1 cannot be provided to the first node N1 via the transistors, and the potential of the first node N1 is low.

[0114] Assume that the above-mentioned selection transistors M1, M2, M3, M4, M5, M6, M7 and M8 are all turned off, that is, when the signals of the selection control terminals D0 to D7 are 10000000, the signal of the first node N1 is at a high potential. In this case, the second transistor T2 and the third transistor T3, whose control terminals are coupled to the above-mentioned first node N1, are both turned on, and the low potential signal of the second selection clock terminal CLKD2 is provided to the second node N2. The signal of the second node N2 is at a low potential, that is, the pull-up node is invalid, and no display partition can be selected.

[0115] It should be noted that the above 0 represents a low-level signal, and the above 1 represents a high-level signal.

[0116] Similarly, when only one of the selection transistors M1, M2, M3, M4, M5, M6, M7, and M8 is turned on, that is, when the signals at the selection control terminals D0-D7 are not 00000000, the signal at the second node N2 is at a low potential, and no display subarea can be selected. Only when the signals at the selection control terminals D0-D7 are 00000000, the signal at the first node N1 is at a low potential, and the signal at the second node N2 is at a high potential, can a display subarea on the display device be selected.

[0117] Continuing with the above assumptions, further explanation is provided. Since signals D0-D7 are transmitted in parallel, the corresponding negated signals D0'-D7' are also transmitted in parallel. Therefore, upon receiving the externally input signals D0-D7, each of the aforementioned gate control terminals simultaneously provides the signals D0-D7 to the gate transistors of different display subareas. Similarly, the signals D0'-D7' are also simultaneously provided to the gate transistors of different display subareas. That is, at the same moment, the signals at each of the gate control terminals D0-D7 are unique and depend on the externally input signals. However, since the connection relationships between the gate transistors of different display subareas and the gate control terminals D0-D7 and D0'-D7' are different, the signals received by each gate transistor are any eight of D0-D7 and D0'-D7'. Therefore, only one display subarea can receive the aforementioned signal 00000000 at a time; the other display subareas receive signals other than 000000000.

[0118] After determining the display partition to be selected, the decoding control subcircuit 100 needs to cooperate with the node control subcircuit 200 to select which shift register unit in the display partition, that is, the driving output terminals Output1 to Output4 corresponding to the output subcircuit 300 for display output.

[0119] 5 , the node control sub-circuit 200 is coupled to the first node N1, the second node N2, and the third node N3, and is configured to control the signals of the second node N2 and the third node N3 in response to the signal of the first selection clock terminal CLKD1, the signal of the second selection clock terminal CLKD2, and the signal of the first node N1.

[0120] During the implementation process, in order to effectively control the driving output terminals Output1 to Output4, it is necessary to control the pull-up nodes and the pull-down nodes, that is, it is necessary to control the signals of the second node N2 and the third node N3, that is, the signals of the second node N2 and the third node N3 are controlled according to the signal of the first selection clock terminal CLKD1, the signal of the second selection clock terminal CLKD2 and the signal of the first node N1.

[0121] Specifically, the node control subcircuit 200 includes: a first node control subcircuit 201 , a second node control subcircuit 202 , a third node control subcircuit 203 and a fourth node control unit 204 .

[0122] The first node control sub-circuit is coupled to the first node N1 and is configured to provide the signal of the first node N1 and the signal of the first high level signal terminal GVDD1 to the second node N2 in response to the signal of the second gate clock terminal CLKD2.

[0123] The first node control subcircuit 201 mainly provides an initialization signal for the second node N2. During implementation, when the signal of the second selection clock terminal CLKD2 is at a high potential, the signal of the first selection clock terminal CLKD1 is at a low potential. Even if the selection transistor is turned on, the signal of the first node N1 is also at a low potential. In this case, the second transistor T2 and the third transistor T3 are both turned off, and the high potential signal of the first high-level signal terminal GVDD1 is provided to the second node N2, that is, the initialization potential of the second node N2 is high.

[0124] 5 , the first node control sub-circuit 201 includes a first transistor T1 and a first capacitor C1 .

[0125] The control terminal of the first transistor T1 is coupled to the second selection clock terminal CLKD2 , the first terminal of the first transistor T1 is coupled to the first high level signal terminal GVDD1 , and the second terminal of the first transistor T1 is coupled to the second node N2 .

[0126] During implementation, when the potential of the second selection clock terminal CLKD2 is high, the first transistor T1 is turned on, and the signal of the first high-level signal terminal GVDD1 is provided to the second node N2 via the turned-on first transistor T1.

[0127] A first terminal of the first capacitor C1 is coupled to the first high-level signal terminal GVDD1 , and a second terminal of the first capacitor C1 is coupled to the second node N2 .

[0128] During implementation, the first capacitor C1 mainly functions to stabilize voltage.

[0129] The second node control sub-circuit 202 is coupled to the second node N2 and is configured to provide a signal from the second selection clock terminal CLKD2 to the second node N2 in response to a signal from the first node N1.

[0130] During implementation, the potential of the first node N1 will affect the potential of the second node N2. Referring to FIG5 , when the potential of the first node N1 is high, the potential of the second node N2 is low; when the potential of the first node N1 is low, the potential of the second node N2 is high.

[0131] 5 , the second node control sub-circuit 202 includes a second transistor T2 , a third transistor T3 , and a fourth transistor T4 .

[0132] The control terminal of the second transistor T2 is coupled to the first node N1 , the first terminal of the second transistor T2 is coupled to the second gate clock terminal CLKD2 , and the second terminal of the second transistor T2 is coupled to the first terminal of the third transistor T3 .

[0133] During implementation, when the potential of the first node N1 is high, the control terminal of the second transistor T2 is high, and the second transistor T2 is turned on.

[0134] A control terminal of the third transistor T3 is coupled to the first node N1 , and a second terminal of the third transistor T3 is coupled to the second node N2 .

[0135] Similarly, when the potential of the first node N1 is high, the third transistor T3 is turned on, and the low potential of the second selection clock terminal CLKD2 is provided to the second node N2 via the turned-on second transistor T2 and third transistor T3, and the potential of the second node N2 changes from high to low.

[0136] It should be supplemented that, when the first selection clock terminal CLKD1 is at a high potential, the second selection clock terminal CLKD2 and the third selection clock terminal CLKD3 are both at a low potential.

[0137] A control terminal of the fourth transistor T4 is coupled to the second node N2 , a first terminal of the fourth transistor T4 is coupled to the first terminal of the third transistor T3 , and a second terminal of the fourth transistor T4 is coupled to the first high-level signal terminal GVDD1 .

[0138] It should be noted that when the potential of the second node N2 is high, the control terminal of the fourth transistor T4 is at a high potential, the fourth transistor T4 is turned on, and the signal of the first high-level signal terminal GVDD1 is provided to the initialization control subcircuit 400 via the turned-on fourth transistor T4.

[0139] The third node control sub-circuit 203 is coupled to the first selection clock terminal CLKD1, the second node N2 and the third node N3, and is configured to respond to the signals of the second node N2 and the third selection clock terminal CLKD3, and provide the signals of the second high-level signal terminal GVDD2 and the first selection clock terminal CLKD1 to the third node N3.

[0140] In the embodiment of the present application, when the second node N2 is at a high potential, the fifth transistor T5 is turned on, when the signal of the first selection clock terminal CLKD1 is at a high potential, the sixth transistor T6 is turned on, and when the signal of the third selection clock terminal CLKD3 is at a high potential, the seventh transistor T7 is turned on. Under the action of the above transistors, the signals of the second high-level signal terminal GVDD2 and the first selection clock terminal CLKD1 are provided to the third node N3, that is, the pull-down node.

[0141] 5 , the third node control sub-circuit 203 includes a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 .

[0142] The connection relationship between the fifth transistor T5 and other transistors in the figure is: the control end of the fifth transistor T5 is coupled to the second node N2, the first end of the fifth transistor T5 is coupled to the second end of the sixth transistor T6, and the second end of the fifth transistor T5 is coupled to the first end of the seventh transistor T7.

[0143] During implementation, when the second node N2 is at a high potential, the control terminal of the fifth transistor T5 is at a high potential, and the fifth transistor T5 is turned on.

[0144] The connection relationship between the sixth transistor T6 and other transistors in the figure is: the control end of the sixth transistor T6 is coupled to the first selection clock end CLKD1, the first end of the sixth transistor T6 is coupled to the second high level signal end GVDD2, and the second end of the sixth transistor T6 is coupled to the first end of the fifth transistor T5.

[0145] During implementation, when the signal of the first selection clock terminal CLKD1 is at a high potential, the control terminal of the sixth transistor T6 is at a high potential, and the sixth transistor T6 is turned on.

[0146] The connection relationship between the seventh transistor T7 and other transistors in the figure is: the control terminal of the seventh transistor T7 is coupled to the third selection clock terminal CLKD3, and the second terminal of the seventh transistor T7 is coupled to the first selection clock terminal CLKD1.

[0147] During implementation, when the signal at the third selection clock terminal CLKD3 is at a high level, the seventh transistor T7 is turned on. Thus, the high level at the second high-level signal terminal GVDD2 is applied to the third node N3 via the applied sixth transistor T6, thereby causing the pull-down node to be at a high level. The signal at the first selection clock terminal CLKD1 is applied to the third node N3 via the applied fifth and seventh transistors T5 and T7, causing the third node N3 to be at a low level.

[0148] The fourth node N4 control unit is coupled to the third node N3 and is configured to provide the signal of the first low level control terminal LVGL to the third node N3 in response to the signal of the second gate clock terminal CLKD2.

[0149] During implementation, the fourth node N4 control unit is mainly used to control the potentials of the first node N1 and the third node N3.

[0150] 5 , the fourth node control unit includes an eighth transistor T8 , a ninth transistor T9 and a second capacitor C2 .

[0151] A control terminal of the eighth transistor T8 is coupled to the second selection clock terminal CLKD2 , a first terminal of the eighth transistor T8 is coupled to the first node N1 , and a second terminal of the eighth transistor T8 is coupled to the first selection clock terminal CLKD1 .

[0152] During implementation, when the signal of the second selection clock terminal CLKD2 is at a high potential, the control terminal of the eighth transistor T8 is at a high potential, the eighth transistor T8 is turned on, and the signal of the first selection clock terminal CLKD1 is provided to the first node N1. Here, the setting of the eighth transistor T8 is mainly used to clear the first node N1, that is, the low potential signal of the first selection clock terminal CLKD1 is provided to the first node N1.

[0153] A control terminal of the ninth transistor T9 is coupled to the fifth node N5 , a first terminal of the ninth transistor T9 is coupled to the third node N3 , and a second terminal of the ninth transistor T9 is coupled to the first low-level control terminal LVGL.

[0154] During implementation, when the fifth node N5 is at a high potential, that is, each driving output terminal Output1 to Output4 outputs a signal, the signal of the first low-level control terminal LVGL is provided to the third node N3 via the turned-on ninth transistor T9, that is, the pull-down node is at a low potential.

[0155] A first terminal of the second capacitor C2 is coupled to the third node N3 , and a second terminal of the second capacitor C2 is coupled to the first low-level control terminal LVGL.

[0156] The second capacitor C2 is provided between the first low-level control terminal LVGL and the pull-down node to play a role in voltage stabilization.

[0157] The following focuses on the output sub-circuit 300. The output sub-circuit 300 is coupled to the second node N2, the third node N3, and a plurality of driving output terminals Output1 to Output4. The plurality of driving output terminals Output1 to Output4 correspond one-to-one to the plurality of output clock signal terminals CLKE1 to CLKE4. The output sub-circuit 300 is configured to provide the signals of the plurality of output clock signal terminals CLKE1 to CLKE4 to the corresponding driving output terminals Output1 to Output4 in response to the signal of the second node N2; and to provide the signal of the reference signal terminal VGL to the plurality of driving output terminals Output1 to Output4 in response to the signal of the third node N3.

[0158] The output subcircuit 300 in the present embodiment includes multiple driver output terminals, Output1 through Output4, which simultaneously output the signals from the output clock signal terminals, CLKE1 through CLKE4. Referring to FIG. 5 , an output subcircuit 300 includes four driver output terminals, Output1 through Output4, which simultaneously output signals.

[0159] It should be noted that the rising edge timing and the falling edge timing of the output clock signal terminal are different.

[0160] The function of the output sub-circuit 300 is to output the signals of the output clock signal terminals CLKE1~CLKE4 by driving the output terminals Output1~Output4 when the second node N2, that is, the pull-up node, is at a high potential, or to output the signal of the reference signal terminal VGL by driving the output terminals Output1~Output4 when the third node N3, that is, the pull-down node, is at a high potential.

[0161] In the embodiment of the present application, the output sub-circuit 300 includes: a first gating control sub-circuit 301 and a plurality of output control sub-circuits 302 .

[0162] The first gating control sub-circuit 301 is configured to provide the signal of the first high-level signal terminal GVDD1 to the fourth node N4 in response to the signal of the second node N2 and the signal of the third gating clock terminal CLKD3, and to provide the signal of the third gating clock terminal CLKD3 to the fourth node N4 in response to the signal of the second gating clock terminal CLKD2, and to provide the signal of the leakage control terminal VGH to the output control sub-circuit 302 in response to the signal of the fifth node N5.

[0163] During implementation, the first gating control sub-circuit 301 controls the potential of the fourth node N4, and the potential of the fourth node N4 directly determines whether the driving output terminals Output1 to Output4 are on or off. In addition, the first gating control sub-circuit 301 also suppresses leakage of the transistor coupled to the fourth node N4 through the leakage control terminal VGH.

[0164] 5 , the first gating control sub-circuit 301 includes a tenth transistor T10 , an eleventh transistor T11 , a twelfth transistor T12 , a thirteenth transistor T13 and a fourteenth transistor T14 .

[0165] The connection relationship between the tenth transistor T10 and the transistors in Figure 5 is: the control end of the tenth transistor T10 is coupled to the second node N2, the first end of the tenth transistor T10 is coupled to the second end of the eleventh transistor T11, and the second end of the tenth transistor T10 is coupled to the fourth node N4.

[0166] During implementation, when the potential of the second node N2 is high, the control terminal of the tenth transistor T10 is high, and the tenth transistor T10 is turned on.

[0167] The connection relationship between the eleventh transistor T11 and the transistors in FIG. 5 is as follows: the control terminal of the eleventh transistor T11 is coupled to the third selection clock terminal CLKD3 , and the first terminal of the eleventh transistor T11 is coupled to the first high level signal terminal GVDD1 .

[0168] During implementation, when the signal of the third selection clock terminal CLKD3 is high, the control terminal of the eleventh transistor T11 is high, and the eleventh transistor T11 is turned on. The high potential of the first high-level signal terminal GVDD1 is provided to the fourth node N4 through the turned-on tenth transistor T10 and the eleventh transistor T11.

[0169] The connection relationship between the twelfth transistor T12 and the transistors in Figure 5 is as follows: the control end of the twelfth transistor T12 is coupled to the second selection clock end CLKD2, the first end of the twelfth transistor T12 is coupled to the third selection clock end CLKD3, and the second end of the twelfth transistor T12 is coupled to the first end of the fourteenth transistor T14.

[0170] During implementation, when the second selection clock terminal CLKD2 is at a high potential, the control terminal of the twelfth transistor T12 is at a high potential, and the twelfth transistor T12 is turned on.

[0171] The connection relationship between the thirteenth transistor T13 and the transistors in Figure 5 is as follows: the control end of the thirteenth transistor T13 is coupled to the second selection clock end CLKD2, the first end of the thirteenth transistor T13 is coupled to the first end of the twelfth transistor T12, and the second end of the thirteenth transistor T13 is coupled to the fourth node N4.

[0172] During implementation, when the second selection clock terminal CLKD2 is at a high level, the thirteenth transistor T13 is also turned on, and the signal of the third selection clock terminal CLKD3 is provided to the fourth node N4 via the turned-on twelfth transistor T12 and the thirteenth transistor T13.

[0173] The connection relationship between the fourteenth transistor T14 and the transistors in FIG. 5 is as follows: the control terminal of the fourteenth transistor T14 is coupled to the fifth node N5 , and the second terminal of the fourteenth transistor T14 is coupled to the leakage control terminal VGH.

[0174] During implementation, when the signal at the fifth node N5 is at a high potential, the fourteenth transistor T14 is turned on, the control terminal of the fourteenth transistor T14 is at a high potential, and the signal at the leakage control terminal VGH is provided to the sixth node via the turned-on fourteenth transistor T14, so as to suppress leakage of the eighteenth transistor T18 and the nineteenth transistor T19 coupled to the sixth node N6.

[0175] After introducing the first selection control sub-circuit 301 , the multiple output control sub-circuits 302 are introduced. The number of the output control sub-circuits 302 is a positive integer greater than or equal to 2.

[0176] In the embodiment of the present application, multiple output control sub-circuits 302 correspond one-to-one to multiple driving output terminals Output1~Output4 and multiple output clock signal terminals CLKE1~CLKE4. During the implementation process, the output control sub-circuit is configured to respond to the signal of the third selection clock terminal CLKD3 to connect the fourth node N4 and the fifth node N5, and, in response to the signal of the fifth node N5, provide the signals of the corresponding output clock signal terminals CLKE1~CLKE4 to the corresponding driving output terminals Output1~Output4, and, in response to the signal of the third node N3, provide the signal of the reference signal terminal VGL to the corresponding driving output terminals Output1~Output4, and, in response to the signal of the third node N3, provide the signal of the first low-level control terminal LVGL to the fifth node N5 and the driving output terminals Output1~Output4.

[0177] It should be noted that there is a one-to-one correspondence between the output control subcircuit 302 and the driver output terminals Output1-Output4. As shown in FIG5 , there are four output control subcircuits 302 and four driver output terminals Output1-Output4. There is also a one-to-one correspondence between the driver output terminals Output1-Output4 and the output clock signal terminals CLKE1-CLKE4. As shown in FIG6 , there are also four output clock signal terminals CLKE1-CLKE4.

[0178] Exemplarily, referring to FIG5 , the output control subcircuit 302 of the first path includes: a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19 and a third capacitor C3. The output clock signal terminal corresponding to the output control subcircuit 302 is CLKE1, and the corresponding drive output terminal is Output1.

[0179] Exemplarily, referring to FIG5 , the second output control subcircuit 302 includes: a fifteenth transistor T15′, a sixteenth transistor T16′, a seventeenth transistor T17′, an eighteenth transistor T18′, a nineteenth transistor T19′, and a third capacitor C3′. The output clock signal terminal corresponding to the output control subcircuit 302 is CLKE2, and the corresponding drive output terminal is Output2.

[0180] For example, referring to FIG5 , the output control subcircuit 302 of the third path includes: a fifteenth transistor T15″, a sixteenth transistor T16″, a seventeenth transistor T17″, an eighteenth transistor T18″, a nineteenth transistor T19″ and a third capacitor C3″. The output clock signal terminal corresponding to the output control subcircuit 302 is CLKE3, and the corresponding drive output terminal is Output3.

[0181] Exemplarily, referring to FIG5 , the output control subcircuit 302 of the fourth path includes: a fifteenth transistor T15″′, a sixteenth transistor T16″′, a seventeenth transistor T17″′, an eighteenth transistor T18″′, a nineteenth transistor T19″′, and a third capacitor C3″′. The output clock signal terminal corresponding to the output control subcircuit 302 is CLKE4, and the corresponding drive output terminal is Output4.

[0182] During implementation, when the signal at the third selection clock terminal CLKD3 is at a high level, the high level of the fourth node N4 is provided to the fifth node N5. When the fifth node N5 is at a high level, the sixteenth transistor T16 coupled to the driver output terminals Output1-Output4 is turned on, and the signals of the output clock signal terminals CLKE1-CLKE4 are provided to the corresponding driver output terminals Output1-Output4 via the turned-on sixteenth transistor T16. When the third node N3 is at a high level, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, and the signal of the reference signal terminal VGL is provided to the corresponding driver output terminals Output1-Output4 via the turned-on eighteenth transistor T18 and nineteenth transistor T19. When the third node N3 is at a high level, the seventeenth transistor T17 is turned on, and the signal of the first low-level control terminal LVGL is provided to the fifth node N5 and the driver output terminals Output1-Output4.

[0183] 5 , the output control subunit includes a fifteenth transistor T15 , a sixteenth transistor T16 , a seventeenth transistor T17 , an eighteenth transistor T18 , a nineteenth transistor T19 and a third capacitor C3 .

[0184] The connection relationship between the fifteenth transistor T15 and the transistors in Figure 5 is: the control end of the fifteenth transistor T15 is coupled to the third selection clock end CLKD3, the first end of the fifteenth transistor T15 is coupled to the fourth node N4, and the second end of the fifteenth transistor T15 is coupled to the fifth node N5.

[0185] During implementation, when the signal of the third selection clock terminal CLKD3 is at a high potential, the control terminal of the fifteenth transistor T15 is at a high potential, the fifteenth transistor T15 is turned on, and the signal of the fourth node N4 is provided to the fifth node N5 via the turned-on fifteenth transistor T15. When the fourth node N4 is at a high potential, the fifth node N5 is also at a high potential.

[0186] The connection relationship between the sixteenth transistor T16 and the transistors in Figure 5 is: the control end of the sixteenth transistor T16 is coupled to the fifth node N5, the first end of the sixteenth transistor T16 is coupled to the first output clock signal end CLKE1, and the second end of the sixteenth transistor T16 is coupled to the driving output ends Output1~Output4.

[0187] During the implementation process, when the fifth node N5 is at a high potential, the control end of the sixteenth transistor T16 is at a high potential, the sixteenth transistor T16 is turned on, and the signal of the first output clock signal end CLKE1 is provided to the corresponding connected driving output ends Output1~Output4 through the turned-on sixteenth transistor T16; when the fifth node N5 is at a low potential, the sixteenth transistor T16 is turned off, and the corresponding connected driving output ends Output1~Output4 do not output.

[0188] The connection relationship between the seventeenth transistor T17 and the transistors in Figure 5 is: the control end of the seventeenth transistor T17 is coupled to the third node N3, the first end of the seventeenth transistor T17 is coupled to the driving output ends Output1~Output4, and the second end of the seventeenth transistor T17 is coupled to the second low-level control end.

[0189] During the implementation process, when the third node N3 is at a high potential, the seventeenth transistor T17 is turned on, and the low potential of the second low-level control terminal is provided to the driving output terminals Output1 to Output4 and the fifth node N5 through the turned-on seventeenth transistor T17, so as to achieve the reset of the driving output terminals Output1 to Output4 and the fifth node N5.

[0190] The connection relationship between the eighteenth transistor T18 and the transistors in Figure 5 is: the control end of the eighteenth transistor T18 is coupled to the third node N3, the first end of the eighteenth transistor T18 is coupled to the fifth node N5, and the second end of the eighteenth transistor T18 is coupled to the first end of the nineteenth transistor T19.

[0191] 5 , when the third node N3 is at a high potential, the control terminal of the eighteenth transistor T18 is at a high potential, and the eighteenth transistor T18 is turned on.

[0192] The connection relationship between the nineteenth transistor T19 and the transistors in FIG. 5 is as follows: the control terminal of the nineteenth transistor T19 is coupled to the third node N3 , and the second terminal of the nineteenth transistor T19 is coupled to the first low-level control terminal LVGL.

[0193] 5 , when the third node N3 is at a high potential, the control terminal of the nineteenth transistor T19 is at a high potential, and the nineteenth transistor T19 is turned on.

[0194] During implementation, the low potential of the first low-level control terminal LVGL is provided to the fifth node N5 via the turned-on eighteenth transistor T18 and the turned-on nineteenth transistor T19, so as to reset the fifth node N5.

[0195] The connection relationship between the third capacitor C3 and each transistor in FIG. 5 is as follows: a first end of the third capacitor C3 is coupled to the fifth node N5 , and a second end of the third capacitor C3 is coupled to the driving output terminals Output1 - Output4 .

[0196] It should be noted that the number of third capacitors C3 coupled to the driving output terminals Output1 to Output4 corresponds one-to-one to the number of driving output terminals Output1 to Output4. The provision of the third capacitors C3 stabilizes the voltage at the fifth node N5. Furthermore, the provision of the third capacitors C3 effectively filters the signals from the driving output terminals Output1 to Output4.

[0197] In addition, it should be noted that, referring to Figure 5, the shift register unit in the embodiment of the present application also includes an initialization control sub-circuit 400, which is coupled to the second node N2 and the third node N3, and is configured to respond to the signal of the initialization signal terminal. Provide the signal of the first low-level control terminal LVGL to the second node N2, and, in response to the signal of the initialization signal terminal, provide the signal of the first high-level signal terminal GVDD1 to the third node N3.

[0198] The above-mentioned initialization control subcircuit 400 is used to initialize the potentials of the second node N2 and the third node N3 after power-on and before the first selection clock terminal CLKD1, the second selection clock terminal CLKD2 and the third selection clock terminal CLKD3 are valid, that is, the initial potential of the second node N2 is set to a low potential, that is, the pull-up node is at a low potential, so that the corresponding drive output terminals Output1 to Output4 will not be selected to output signals. At the same time, the initial potential of the third node N3 is set to a high potential, that is, the pull-down node is at a high potential.

[0199] 5 , the initialization control sub-circuit 400 includes a twentieth transistor T20 , a twenty-first transistor T21 , and a twenty-second transistor T22 .

[0200] The connection relationship between the twentieth transistor T20 and the transistors in FIG5 is as follows: the control terminal of the twentieth transistor T20 is coupled to the initialization signal terminal, the first terminal of the twentieth transistor T20 is coupled to the second node N2, and the second terminal of the twentieth transistor T20 is coupled to the first terminal of the twenty-second transistor T22.

[0201] During implementation, when the initialization signal terminal is at a high potential, the control terminal of the twentieth transistor T20 is at a high potential, and the twentieth transistor T20 is turned on.

[0202] The connection relationship between the twenty-first transistor T21 and the transistors in Figure 5 is: the control end of the twenty-first transistor T21 is coupled to the initialization signal end, the first end of the twenty-first transistor T21 is coupled to the first high level signal end GVDD1, and the second end of the twenty-first transistor T21 is coupled to the third node N3.

[0203] During implementation, when the initialization signal terminal is at a high potential, the twenty-first transistor T21 is turned on, and the high potential of the first high-level signal terminal GVDD1 is provided to the third node N3, so that the initial potential of the pull-down node is a high potential.

[0204] The connection relationship between the 22nd transistor T22 and the transistors in FIG. 5 is as follows: the control terminal of the 22nd transistor T22 is coupled to the initialization signal terminal, and the second terminal of the 22nd transistor T22 is coupled to the second terminal of the second capacitor C2 .

[0205] During implementation, when the initialization signal terminal is at a high potential, the control terminal of the twenty-second transistor T22 is at a high potential, and the twenty-second transistor T22 is turned on. The low potential of the first low-level control terminal LVGL is provided to the second node N2 via the turned-on 20 and 22 transistors T20 and T22, causing the initial potential of the pull-up node to be low. The potential of the pull-up node is an invalid potential, and the output transistor cannot be selected, resulting in no output signal from the driven output terminal.

[0206] It should be noted that the shift register unit described above is illustrated using the N-type transistors shown in FIG5 . In some embodiments, when the N-type transistors are replaced with P-type transistors, the potentials provided to the various transistors and nodes mentioned above need to be adjusted to match those of the P-type transistors. However, the control logic of the display partitions and display groups (i.e., the shift register unit) mentioned in the embodiments of the present application remains unchanged and will not be further described here.

[0207] 5, 7 and 8, the main working process of the shift register will be described below in conjunction with the timing diagram.

[0208] Timing t0 stage: initialization signal terminal TRS = 1, second selection clock terminal CLKD2 = 0, first selection clock terminal CLKD1 = 0, third selection clock terminal CLKD3 = 0, CLKE1 ~ CLKE12 are all 0, selection control terminals D0 ~ D7 are all 1, first node N1 = 0, second node N2 = 0, third node N3 = 0, fifth node N5 = 0, fifth node N5' = 0, fifth node N5" = 0, fifth node N5'' = 0, drive output terminal Output1 = 0, drive output terminal Output2 = 0, drive output terminal Output3 = 0, drive output terminal Output4 = 0

[0209] After the shift register unit is powered on, the signal at the initialization signal terminal TRS is at a high level, the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22 are all turned on, the high-level signal at the first high-level signal terminal GVDD1 causes the potential of the third node N3 to be high via the turned-on twenty-first transistor T21, and the high-level signal at the first high-level signal terminal GVDD1 is provided to the second capacitor C2 via the turned-on twenty-first transistor T21 and the twenty-second transistor T22.

[0210] Timing t1 stage: initialization signal terminal TRS = 0, second selection clock terminal CLKD2 = 1, first selection clock terminal CLKD1 = 0, third selection clock terminal CLKD3 = 0, selection control terminals D0 to D7 are all 1, first node N1 = 0, second node N2 = 1, third node N3 = 1, fifth node N5 = 0, fifth node N5' = 0, fifth node N5" = 0, fifth node N5'' = 0, driving output terminal Output1 = 0, driving output terminal Output2 = 0, driving output terminal Output3 = 0, driving output terminal Output4 = 0

[0211] The signal at the second selection clock terminal CLKD2 is at a high level, the first transistor T1 is turned on, and the high-level signal at the first high-level signal terminal GVDD1 is provided to the second node N2 through the turned-on first transistor T1. Before entering the selection phase at this timing, the signals at each selection control terminal D0-D7 are all set high, and the selection control terminals D0-D7 are all 1.

[0212] In this timing, due to the existence of the second capacitor C2, the third node N3 maintains a high potential.

[0213] In this timing, since the signal of the third selection clock terminal CLKD3 is at a low level, the potential of the fifth node N5 is also at a low level, and the driving output terminals Output1 to Output4 cannot output signals.

[0214] Timing t2 stage: initialization signal terminal TRS = 0, second selection clock terminal CLKD2 = 0, first selection clock terminal CLKD1 = 1, third selection clock terminal CLKD3 = 0, selection control terminals D0 to D7 are all 0, first node N1 = 0, second node N2 = 1, third node N3 = 1, fifth node N5 = 0, fifth node N5' = 0, fifth node N5" = 0, fifth node N5'' = 0, drive output terminal Output1 = 0, drive output terminal Output2 = 0, drive output terminal Output3 = 0, drive output terminal Output4 = 0

[0215] Take the eight signals of the strobe control terminals D0 to D7 as an example for explanation. Then, in the timing t2 phase, since the strobe control signal corresponds to 256 (2 8 ) states, so when the signals at the selection control terminals D0~D7 are all 0, the selection transistors M1, M2, M3, M4, M5, M6, and M7 are all turned off, and the signal at the first selection clock terminal CLKD1 is at a high potential, but cannot be provided to the first node N1 through any selection transistor. The second node N2 maintains a high potential under the action of the first capacitor C1. In this timing sequence, the display partition 1 corresponding to the driving output terminal Output1, the driving output terminal Output2, the driving output terminal Output3, and the driving output terminal Output4 is selected.

[0216] It should be noted that when display partition 1 is selected, since the selection transistors of other display partitions are connected to signals other than the selection control terminals D0 to D7, including the selection control terminal D0', the selection control terminals D1 to D7..., the selection control terminals D0 to D6, D7', etc., the signals received by the selection transistors of other display partitions are signals other than 00000000, for example, 10000000...00000001, etc. In this way, at least one of the selection transistors in other display partitions is turned on, so that the potential of the first node N1 is high, the second transistor T2 is turned on, the third transistor T3 is turned on, and the signal of the second selection clock terminal CLKD2 is low. The low-potential signal can be provided to the second node N2 through the turned-on second transistor T2 and the third transistor T3, that is, the pull-up node is low. Correspondingly, the transistors coupled to the various drive output terminals Output1 to Output4 (for example, the sixteenth transistor T16) cannot be turned on, and the corresponding drive output terminals Output1 to Output4 have no signal output.

[0217] Timing t3 stage: initialization signal terminal TRS = 0, second selection clock terminal CLKD2 = 0, first selection clock terminal CLKD1 = 0, third selection clock terminal CLKD3 = 1, selection control terminals D0 to D7 are all 0, first node N1 = 0, second node N2 = 1, third node N3 = 0, fifth node N5 = 0, fifth node N5' = 0, fifth node N5" = 0, fifth node N5'' = 0, drive output terminal Output1 = 0, drive output terminal Output2 = 0, drive output terminal Output3 = 0, drive output terminal Output4 = 0

[0218] The signal of the third selection clock terminal CLKD3 is at a high level. The high level of the third selection clock terminal CLKD3 turns on the eleventh transistor T11. The high level signal maintained at the second node N2 turns on the tenth transistor T10. The high level signal of the first high-level signal terminal GVDD1 is provided to the sixth node via the turned-on eleventh transistor T11. The high level signal of the sixth node is provided to the fourth node N4 via the turned-on tenth transistor T10. Thus, the fourth node N4 has a high level signal.

[0219] In addition, the high potential of the third selection clock terminal CLKD3 turns on the fifteenth transistor T15, and the high potential signal of the fourth node N4 is provided to the fifth node N5 through the turned-on fifteenth transistor T15. Thus, the signal of the fifth node N5 is also high potential.

[0220] It should be noted that, in the embodiment of the present application, since the output sub-circuit 300 includes multiple output control sub-circuits, the number of the driven output terminals Output1 to Output4 corresponds one-to-one to the output control sub-circuits, and the number of the above-mentioned fifth nodes N5 also corresponds one-to-one to the output control sub-circuits. Referring to Figure 5, the fifth node N5 includes the fifth node N5 node, the fifth node N5' node, the fifth node N5" node and the fifth node N5"' node in the figure.

[0221] At the timing t3, the signal at the second node N2 is at a high level, the fifth transistor T5 is turned on, the high level of the third selection clock terminal CLKD3 turns on the seventh transistor T7, and the low level of the first selection clock terminal CLKD1 is provided to the third node N3 through the turned-on seventh transistor T7 and the fifth transistor T5, so that the signal at the third node N3 is at a low level.

[0222] Timing stage t4: initialization signal terminal TRS = 0, second selection clock terminal CLKD2 = 0, first selection clock terminal CLKD1 = 0, third selection clock terminal CLKD3 = 0, selection control terminals D0 to D7 are all 0, first node N1 = 0, second node N2 = 1, third node N3 = 0, fifth node N5 = 1, fifth node N5' = 1, fifth node N5" = 1, fifth node N5'' = 1, drive output terminal Output1 = 1, drive output terminal Output2 = 1, drive output terminal Output3 = 1, drive output terminal Output4 = 1

[0223] When the signal of the third selection clock terminal CLKD3 is at a low level, the sixth node can be reset to the low level of the third selection clock terminal CLKD3 by the twelfth transistor and the thirteenth transistor when the signal of the second selection clock terminal CLKD2 is at a high level. However, such a reset is not necessary, and the above-mentioned twelfth transistor and the thirteenth transistor can also be omitted.

[0224] Since the potentials of the fifth node N5, the fifth node N5', the fifth node N5", and the fifth node N5'" are maintained at high potentials, the high potential of the fifth node N5 turns on the sixteenth transistor T16, and the multiple output clock signal terminals CLKE1 to CLKE4 are turned on in sequence according to a preset timing. The signal of the first output clock signal terminal CLKE1 is provided to the driving output terminal Output1 via the turned-on sixteenth transistor T16, the signal of the second output clock signal terminal CLKE2 is provided to the driving output terminal Output2 via the turned-on sixteenth transistor T16, the signal of the third output clock signal terminal CLKE3 is provided to the driving output terminal Output3 via the turned-on sixteenth transistor T16, and the signal of the fourth output clock signal terminal CLKE4 is provided to the driving output terminal Output4 via the turned-on sixteenth transistor T16.

[0225] Timing t5 stage: initialization signal terminal TRS = 0, second selection clock terminal CLKD2 = 0, first selection clock terminal CLKD1 = 1, third selection clock terminal CLKD3 = 0, the signal of selection control terminal D0~D7D0 is 1, the signal of selection control terminal D0' is 0, selection control terminals D1~D7 are all 0, first node N1 = 1, second node N2 = 0, third node N3 = 1, fifth node N5 = 0, fifth node N5' = 0, fifth node N5" = 0, fifth node N5"' = 0, driving output terminal Output1 = 0, driving output terminal Output2 = 0, driving output terminal Output3 = 0, driving output terminal Output4 = 0

[0226] During the timing t5, the display partition 1 is mainly reset. Since the signals of the strobe control terminals D0 to D7 are 00000001, the display partition 1 will not be strobed. As shown in FIG9 , the drive output terminals Output1 to Output4 corresponding to GOA1, GOA2 and GOA3 will not output any signals.

[0227] At timing t5, since the selection transistor M1 is turned on, the signal at the first node N1 is at a high level. The high level of the first node N1 turns on the second transistor T2 and the third transistor T3. The low level of the second selection clock terminal CLKD2 is provided to the point P via the turned-on second transistor T2 and the turned-on third transistor T3. The point P is reset to a low level.

[0228] At the same time, the high potential of the first selection clock terminal CLKD1 turns on the sixth transistor T6, and the high potential of the second high-level signal terminal GVDD2 is provided to the third node N3 via the turned-on sixth transistor T6. The signal at the third node N3 is at a high potential, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, and the low potential signal of the first low-level control terminal LVGL is provided to the fifth node N5 via the turned-on eighteenth transistor T18 and the nineteenth transistor T19, so that the signal at the fifth node N5 is at a low potential. In this way, the driving transistors connected to the respective driving output terminals Output1 to Output4 in the display partition 1 are turned off.

[0229] It should be noted that, in the timing stage t5, when the display partition 1 is not subsequently selected, the above reset operation will be repeated, so that the corresponding circuit can reduce noise.

[0230] In addition, since the signals of the strobe control terminals D0 to D7 are 00000001, the next display partition, assuming that the next display partition is display partition 2, and the signal strobe control terminals D0 to D7 connected to the display partition 2 are strobe control terminals D0' and strobe control terminals D1 to D7, in fact, the signals received by the strobe control terminals D0 to D7 in the display partition 2 are 00000000, that is, the display partition 2 is selected. The subsequent specific working process of the display partition 2 is similar to that of the above-mentioned display partition 1, and will not be repeated here.

[0231] It should be supplemented that the complete working timing diagram of the signals of the above-mentioned strobe control terminals D0 to D7 is shown in FIG8 .

[0232] Based on the same inventive concept, an embodiment of the present application provides a gate driving circuit, which includes multiple gate lines and multiple shift register units according to any one of the above items.

[0233] The plurality of gate lines are coupled to the driving output terminals Output1 - Output4 in the plurality of shift register units in a one-to-one correspondence.

[0234] Based on the same inventive concept, an embodiment of the present application provides a display device, including: the above-mentioned gate driving circuit.

[0235] The display device provided in the embodiments of the present application can be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, etc. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present application.

[0236] In order to provide signals from the driving output terminals Output1 to Output4 of the shift register unit to the pixel units in the display device, the display device includes a plurality of gate lines, each gate line being coupled to the driving output terminals Output1 to Output4 in a one-to-one correspondence.

[0237] The following describes different display partitions in the display device and the division of different shift register units in the same display partition with reference to FIG. 9 .

[0238] First, let's explain the division rules of different shift register units in the same display partition:

[0239] The first clock signal terminal CK1 of the 3k-2 stage shift register unit is coupled to the same clock terminal, i.e., the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1, the second clock signal terminal CK2 is coupled to the same clock terminal, i.e., the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2, and the third clock signal terminal CK3 is coupled to the same clock terminal, i.e., the third selection clock terminal CLKD3 and the third selection clock terminal CLKD3.

[0240] The first clock signal terminal CK1 of the 3k-1th level shift register unit is coupled to the same clock terminal, namely the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2, the second clock signal terminal CK2 is coupled to the same clock terminal, namely the third selection clock terminal CLKD3 and the third clock signal terminal CK3 is coupled to the same clock terminal, namely the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1.

[0241] The first clock signal terminal CK1 of the 3k-stage shift register unit is coupled to the same clock terminal, namely, the third selection clock terminal CLKD3, the second clock signal terminal CK2 is coupled to the same clock terminal, namely, the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1, and the third clock signal terminal CK3 is coupled to the same clock terminal, namely, the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2; wherein k is a positive integer.

[0242] A detailed description will be given by assuming that the same display partition is display partition a, and k=1.

[0243] In order to select the first-stage shift register unit in display partition a, the first clock signal terminal CK1 of the first-stage shift register unit is coupled to the same clock terminal, i.e., the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1, the second clock signal terminal CK2 is coupled to the same clock terminal, i.e., the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2, and the third clock signal terminal CK3 is coupled to the same clock terminal, i.e., the third selection clock terminal CLKD3 and the third selection clock terminal CLKD3, that is, the clock signal terminals input to the first-stage shift register unit are the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1, the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2, and the third selection clock terminal CLKD3 and the third selection clock terminal CLKD3 in sequence.

[0244] In order to select the second-stage shift register unit in display partition a, the first clock signal terminal CK1 of the second-stage shift register unit is coupled to the same clock terminal, namely the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2, the second clock signal terminal CK2 is coupled to the same clock terminal, namely the third selection clock terminal CLKD3 and the third selection clock terminal CLKD3, and the third clock signal terminal CK3 is coupled to the same clock terminal, namely the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1, that is, the clock signal terminals input to the second-stage shift register unit are the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2, the third selection clock terminal CLKD3 and the first selection clock terminal CLKD1 and the first selection clock terminal CLKD1 in sequence.

[0245] In order to select the third-stage shift register unit in display partition a, the first clock signal terminal CK1 of the third-stage shift register unit is coupled to the same clock terminal, namely the third selection clock terminal CLKD3, the second clock signal terminal CK2 is coupled to the same clock terminal, namely the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2, and the third clock signal terminal CK3 is coupled to the same clock terminal, namely the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1, that is, the clock signal terminals input to the third-stage shift register unit are the third selection clock terminal CLKD3 and the third selection clock terminal CLKD3, the second selection clock terminal CLKD2 and the first selection clock terminal CLKD1, and the first selection clock terminal CLKD1 and the second selection clock terminal CLKD2.

[0246] 9 , in the same display partition a, different combinations of the signals in the first selection clock terminal CLKD1, the second selection clock terminal CLKD2, and the third selection clock terminal CLKD3 can uniquely select a shift register unit in the display partition, thereby achieving simultaneous output of multiple drive output terminals Output1 to Output4 included in the shift register unit.

[0247] It should be noted that, referring to Figure 9, in the embodiment of the present application, the selection of the shift register units in other display partitions is also achieved through the first selection clock terminal CLKD1, the second selection clock terminal CLKD2 and the third selection clock terminal CLKD3. That is to say, in other display partitions, the first selection clock terminal CLKD1, the second selection clock terminal CLKD2 and the third selection clock terminal CLKD3 are also connected to each shift register unit using the above-mentioned connection relationship. The signals corresponding to the same group of selection clock terminals (i.e., the first selection clock terminal CLKD1, the second selection clock terminal CLKD2 and the third selection clock terminal CLKD3) in different display partitions can select the shift register units accordingly.

[0248] However, since the display partitions are uniquely selected by signals from the selection control terminals D0 to D7, the shift register units selected by the same group of selection clock terminals in different display partitions will not output signals simultaneously. Only when both the display partitions and the shift register units are selected simultaneously will the shift register unit output signals.

[0249] To ensure that each shift register unit outputs signals at different times, the timing of the signals connected to the output clock signal terminals of each display group within the same display partition do not overlap. Referring to Figures 8 and 9 , when a display partition includes three display groups, each of which includes four output clock terminals, i.e., when a display partition includes twelve output clock terminals (Output 1, Output 2, ..., Output 12), the corresponding output clock signal terminals are CLKE1, CLKE2, CLKE3, ..., CLKE12. The timing of CLKE1, CLKE2, CLKE3, ..., CLKE12 is shown in Figure 7 .

[0250] Furthermore, to ensure that only one display group within a display partition of the display device can be uniquely enabled at any given time, the number of signals at the output clock signal terminals will also change accordingly if the number of display groups and the number of driver output terminals within a display partition vary. For example, if the number of display groups within a display partition is M and the number of driver output terminals within a display group is N, then the number of output clock signal terminals required to be connected to the display partition is M*N.

[0251] The following describes the division rules of different display partitions in the display device:

[0252] The strobe control terminals D0 to D7 of the 3k-2 th stage shift register unit, the 3k-1 th stage shift register unit and the 3k th stage shift register unit are coupled to the same signal line group, where k is a positive integer.

[0253] In the embodiment of the present application, a display partition includes adjacent three-stage shift register units. In other embodiments, the number of shift register units included in a display partition is variable. However, in order to enable different shift register units in the same display partition, the number of gate clock terminals included in the same group of gate clock terminals must also be adjusted accordingly to ensure that the combination of each gate clock terminal can uniquely enable a shift register unit.

[0254] In addition, it should be noted that the number of display partitions included in a display device can also be adjusted. However, in order to enable only one display partition in the display device to be gated for output, the number of the gate control terminals D0 to D7 also needs to be adjusted accordingly, which will not be detailed here.

[0255] In addition, in the embodiment of the present application, in order to distinguish different display partitions, different groups of signal line groups are connected to the shift register units belonging to different display partitions. The signal line groups are used to receive signals from the respective selection control terminals D0 to D7.

[0256] The strobe control terminals D0 to D7 of the 6k-5th stage shift register unit, the 6k-4th stage shift register unit, and the 6k-3th stage shift register unit are coupled to the first group of signal lines.

[0257] The selection control terminals D0 to D7 of the 6k-2th shift register unit, the 6k-1th shift register unit and the 6kth shift register unit are coupled to the second group of signal line groups, wherein the output signals in the first group of signal line groups and the second group of signal line groups are different, and k is a positive integer.

[0258] In the embodiment of the present application, the shift register units connected to the signal line group with the same output signal are in the same display partition.

[0259] The division of display partitions is determined by the above-mentioned signal line groups. The shift register units connected to the signal line groups with the same output signals are the same display partition, and the shift register units connected to the signal line groups with different output signals are different display partitions.

[0260] The following describes in detail the division of the display device into a display partition a and a display partition b, with k=1 and k=2.

[0261] The first-stage shift register unit, the second-stage shift register unit and the third-stage shift register unit constitute a display partition a, and the fourth-stage shift register unit, the fifth-stage shift register unit and the sixth-stage shift register unit constitute a display partition b.

[0262] The strobe control terminals D0 to D7 corresponding to the display partition a are coupled to the same group of signal lines. As shown in FIG9 , the strobe control terminals D0 to D7 connected to the same group of signal lines coupled to the display partition a are strobe control terminals D0, D1, D2, D3, D4, D5, D6 and D7.

[0263] The strobe control terminals D0 to D7 corresponding to the display partition b are coupled to another group of signal lines. As shown in FIG9 , the strobe control terminals D0 to D7 connected to the same group of signal lines coupled to the display partition a are strobe control terminals D0′, D1, D2, D3, D4, D5, D6 and D7.

[0264] In order to facilitate providing signals to the above-mentioned selection control terminals D0 to D7, in the embodiment of the present application, the display device further includes a decoder, and the output terminal of the decoder provides different output signals to the first group of signal lines and the second group of signal lines.

[0265] The decoder is a multi-input multi-output combinational logic circuit device. Assume that the decoder has a total of 8 output ports, namely output port 1, output port 2, output port 3, output port 4, output port 5, output port 6, output port 7 and output port 8.

[0266] In order to allow the corresponding selection control terminals D0~D7 to receive more signals, in the embodiment of the present application, the above-mentioned output port 1, output port 2, output port 3, output port 4, output port 5, output port 6, output port 7 and output port 8 are all inverted and expanded, that is, the signal of output port 1 is inverted and output through output port 9, the signal of output port 2 is inverted and output through output port 10, and so on, thereby obtaining output port 9, output port 10, output port 11, output port 12, output port 13, output port 14, output port 15 and output port 16.

[0267] In the embodiment of the present application, when the number of selection transistors is 8, the corresponding selection control terminals D0~D7 can be connected to the 8 output ports among the above-mentioned output port 1 to output port 16. It should be noted that there cannot be duplicate ports among the output ports connected to the selection control terminals D0~D7. The duplicate ports here include the output port and the output port inverted therefrom. That is to say, only one of the output port and the output port inverted therefrom can be selected for connection.

[0268] The above is merely an example to illustrate the specific structure of the display device provided in the embodiment of the present invention. In specific implementation, the above specific structure is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0269] Based on the same inventive concept, referring to FIG. 10 , an embodiment of the present application provides a driving method for a shift register unit, including:

[0270] Step 201: The decoding control sub-circuit 100 connects the first strobe clock terminal CLKD1 to the first node N1 in response to the signals of the strobe control terminals D0-D7.

[0271] During implementation, when the signals of the selection control terminals D0 to D7 are valid signals, at least one of the selection transistors included in the decoding control sub-circuit 100 is turned on, and the high-potential signal of the first selection clock terminal CLKD1 is provided to the first node N1 through the turned-on selection transistor, and the first node N1 is at a high potential.

[0272] When the signals of the selection control terminals D0 to D7 are invalid signals, the selection transistors included in the decoding control sub-circuit 100 are turned off, and the high-voltage signal of the first selection clock terminal CLKD1 cannot be provided to the first node N1 through the turned-on selection transistors, and the first node N1 is at a low voltage.

[0273] It should be noted that, in the embodiment of the present application, the signals of the strobe control terminals D0-D7 are provided by an external decoder. At the same time, the signal provided by the decoder to the strobe control terminals D0-D7 can make the signal of at least one of the strobe control terminals D0-D7 a valid signal, that is, the first node N1 corresponding to at least one shift register unit is at a high potential. However, at the same time, the signal provided by the decoder to the strobe control terminals D0-D7 can make the signal of only one of the strobe control terminals D0-D7 an invalid signal, that is, the first node N1 corresponding to only one shift register unit is at a low potential.

[0274] Step 202 : the node control sub-circuit 200 controls the signals of the second node N2 and the third node N3 in response to the signal of the first selection clock terminal CLKD1 , the signal of the second selection clock terminal CLKD2 and the signal of the first node N1 .

[0275] In the embodiment of the present application, the second node N2 is a pull-up node in the shift register, and the third node N3 is a pull-down node in the shift register. During implementation, under the influence of the signal from the first selection clock terminal CLKD1, the signal from the second selection clock terminal CLKD2, and the signal from the first node N1, the node control subcircuit 200 controls the signals at the second node N2 and the third node N3. In other words, the node control subcircuit 200 sets the potentials of the second node N2 and the third node N3.

[0276] During the implementation process, when the first node N1 is at a high potential, the second node N2 is at a low potential, so the output signals of the coupled driving output terminals Output1~Output4 cannot be selected; when the first node N1 is at a low potential, the second node N2 is at a high potential. In this case, the output signals of the driving output terminals Output1~Output4 coupled to the second node N2 can be selected.

[0277] Step 203: The output sub-circuit 300 provides the signals of the multiple output clock signal terminals CLKE1~CLKE4 to the corresponding driving output terminals Output1~Output4 in response to the signal of the second node N2; and, in response to the signal of the third node N3, provides the signal of the reference signal terminal VGL to the multiple driving output terminals Output1~Output4.

[0278] In an embodiment of the present application, the output sub-circuit 300 includes a first selection control sub-circuit and multiple output control sub-circuits. The multiple output control sub-circuits belonging to the same shift register unit include multiple driving output terminals Output1~Output4. When the second node N2 is at a high potential, that is, the pull-up node is at a high potential, the fifth node N5 will correspondingly be at a high potential. In this way, the transistors respectively connected to each driving output terminal Output1~Output4 are turned on, and the signals of the output clock signal terminals CLKE1~CLKE4 corresponding to each driving output terminal Output1~Output4 are provided to the corresponding driving output terminals Output1~Output4 through the above-mentioned turned-on transistors, thereby realizing the output display of the shift register unit. The number of driving output terminals Output1~Output4 included in the shift register unit corresponds to the number of rows of pixel units displayed in the display device.

[0279] When the signal at the third node N3 is high, that is, the pull-down node is low, the corresponding transistor connected to the reference signal terminal VGL is turned on, and the signal at the reference signal terminal VGL is provided to the corresponding driving output terminals Output1 to Output4 through the turned-on transistor.

[0280] In summary, in the embodiments of the present application, a shift register unit, a display device, and a driving method are provided. The shift register unit includes a decoding control subcircuit, a node control subcircuit, and an output subcircuit. The decoding control subcircuit is configured to connect the first selection clock terminal to the first node in response to the signal of the selection control terminal. The node control subcircuit is coupled to the first node, the second node, and the third node, and is configured to control the signals of the second node and the third node in response to the signal of the first selection clock terminal, the signal of the second selection clock terminal, and the signal of the first node. The output subcircuit is coupled to the second node, the third node, and a plurality of driving output terminals. The plurality of driving terminals are connected to the first node, the third node, and the output subcircuit. The driving output terminal is electrically connected to multiple output clock signal terminals, and the output sub-circuit is configured to provide signals from multiple output clock signal terminals to the driving output terminal in response to the signal of the second node, and to provide the signal from the reference signal terminal to the multiple driving output terminals in response to the signal of the third node. That is, the partition setting of the driving output terminal of the shift register unit is realized by different signal combinations of multiple selection control terminals, and the group setting within the partition is realized by different combinations of multiple selection clock terminals, thereby realizing the selection control of the above-mentioned partitions and groups, and improving the flexibility of the selection output of the above-mentioned driving output terminal without the need to add any additional hardware units.

[0281] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program product systems. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0282] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present application. It should be understood that each flow and / or box in the flow chart and / or block diagram, as well as the combination of the flow chart and / or box in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more flow charts and / or one or more boxes in the block diagram.

[0283] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0284] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0285] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A shift register unit, wherein: include: A decoding control subcircuit, a node control subcircuit and an output subcircuit; The decoding control subcircuit is configured to connect the first gating clock terminal to the first node in response to a signal from the gating control terminal; The node control subcircuit is coupled to the first node, the second node and the third node, and is configured to control the signals of the second node and the third node in response to the signal of the first gating clock terminal, the signal of the second gating clock terminal and the signal of the first node; The output subcircuit is coupled to the second node, the third node and a plurality of driving output terminals, the plurality of driving output terminals are electrically connected to a plurality of output clock signal terminals, and the output subcircuit is configured to provide signals of the plurality of output clock signal terminals to the driving output terminals in response to a signal of the second node; And, in response to the signal of the third node, providing the signal of the reference signal terminal to the plurality of driving output terminals.

2. The shift register unit according to claim 1, wherein: The decoding control subcircuit comprises: N gate transistors, wherein N is a positive integer greater than or equal to 1; The control terminal of the gating transistor is coupled to the gating control terminal, the first terminal of the gating transistor is coupled to the first gating clock terminal, and the second terminal of the gating transistor is coupled to the first node.

3. The shift register unit according to claim 1 or 2, wherein: The node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit and a fourth node control subcircuit; The first node control subcircuit is coupled to the first node and is configured to provide the signal of the first node and the signal of the first high level signal terminal to the second node in response to the signal of the second selection clock terminal; The second node control subcircuit is coupled to the second node and is configured to provide a signal of a second gating clock terminal to the second node in response to a signal of the first node; The third node control subcircuit is connected to the first selection clock terminal, the second node and the third node coupling, configured to provide the signal of the second high level signal terminal and the first gating clock terminal to the third node in response to the signal of the second node and the third gating clock terminal; The fourth node control subcircuit is coupled to the third node, and is configured to provide a signal from a first low level control terminal to the third node in response to a signal from the second selection clock terminal.

4. The shift register unit according to claim 3, wherein: The first node control subcircuit includes: a first transistor and a first capacitor; The control terminal of the first transistor is coupled to the second gate clock terminal, the first terminal of the first transistor is coupled to the first high level signal terminal, and the second terminal of the first transistor is coupled to the second node; A first end of the first capacitor is coupled to the first high level signal end, and a second end of the first capacitor is coupled to the second node.

5. The shift register unit according to claim 3, wherein: The second node control subcircuit includes: a second transistor, a third transistor and a fourth transistor; The control terminal of the second transistor is coupled to the first node, the first terminal of the second transistor is coupled to the second gate clock terminal, and the second terminal of the second transistor is coupled to the first terminal of the third transistor; The control terminal of the third transistor is coupled to the first node, and the second terminal of the third transistor is coupled to the second node; The control terminal of the fourth transistor is coupled to the second node, the first terminal of the fourth transistor is coupled to the first terminal of the third transistor, and the second terminal of the fourth transistor is coupled to the first high level signal terminal.

6. The shift register unit according to claim 3, wherein: The third node control subcircuit includes: a fifth transistor, a sixth transistor and a seventh transistor; The control terminal of the fifth transistor is coupled to the second node, the first terminal of the fifth transistor is coupled to the second terminal of the sixth transistor, and the second terminal of the fifth transistor is coupled to the first terminal of the seventh transistor; The control terminal of the sixth transistor is coupled to the first gate clock terminal, and the sixth transistor The first end of the transistor is coupled to the second high level signal end, and the second end of the sixth transistor is coupled to the first end of the fifth transistor; The control terminal of the seventh transistor is coupled to the third gating clock terminal, and the second terminal of the seventh transistor is coupled to the first gating clock terminal.

7. The shift register unit according to claim 3, wherein: The fourth node control subcircuit includes: an eighth transistor, a ninth transistor and a second capacitor; The control terminal of the eighth transistor is coupled to the second gating clock terminal, the first terminal of the eighth transistor is coupled to the first node, and the second terminal of the eighth transistor is coupled to the first gating clock terminal; The control terminal of the ninth transistor is coupled to the fifth node, the first terminal of the ninth transistor is coupled to the third node, and the second terminal of the ninth transistor is coupled to the first low level control terminal; A first terminal of the second capacitor is coupled to the third node, and a second terminal of the second capacitor is coupled to the first low level control terminal.

8. The shift register unit according to any one of claims 1 to 7, wherein: The output subcircuit comprises: a first gating control subcircuit and a plurality of output control subcircuits; The first gating control subcircuit is configured to provide a signal of the first high-level signal terminal to a fourth node in response to a signal of the second node and a signal of the third gating clock terminal, and to provide a signal of the third gating clock terminal to the fourth node in response to a signal of the second gating clock terminal, and to provide a signal of the leakage control terminal to the fourth node in response to a signal of the fifth node; The multiple output control sub-circuits correspond one-to-one to the multiple driving output terminals and the multiple output clock signal terminals. The output control sub-circuit is configured to connect the fourth node and the fifth node in response to the signal of the third selection clock terminal, and to provide the signal of the corresponding output clock signal terminal to the corresponding driving output terminal in response to the signal of the fifth node, and to provide the signal of the reference signal terminal to the corresponding driving output terminal in response to the signal of the third node, and to provide the signal of the first low-level control terminal to the fifth node and the driving output terminal in response to the signal of the third node.

9. The shift register unit according to claim 8, wherein: The first gating control subcircuit includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor; The control terminal of the tenth transistor is coupled to the second node, the first terminal of the tenth transistor is coupled to the second terminal of the eleventh transistor, and the second terminal of the tenth transistor is coupled to the fourth node; The control terminal of the eleventh transistor is coupled to the third gate clock terminal, and the first terminal of the eleventh transistor is coupled to the first high level signal terminal; The control terminal of the twelfth transistor is coupled to the second gate clock terminal, the first terminal of the twelfth transistor is coupled to the third gate clock terminal, and the second terminal of the twelfth transistor is coupled to the first terminal of the fourteenth transistor; The control terminal of the thirteenth transistor is coupled to the second gate clock terminal, the first terminal of the thirteenth transistor is coupled to the first terminal of the twelfth transistor, and the second terminal of the thirteenth transistor is coupled to the fourth node; The control terminal of the fourteenth transistor is coupled to the fifth node, and the second terminal of the fourteenth transistor is coupled to the leakage control terminal.

10. The shift register unit according to claim 8, wherein: The output control subunit includes: a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a third capacitor; The control terminal of the fifteenth transistor is coupled to the third gate clock terminal, the first terminal of the fifteenth transistor is coupled to the fourth node, and the second terminal of the fifteenth transistor is coupled to the fifth node; The control terminal of the sixteenth transistor is coupled to the fifth node, the first terminal of the sixteenth transistor is coupled to the first output clock signal terminal, and the second terminal of the sixteenth transistor is coupled to the driving output terminal; The control terminal of the seventeenth transistor is coupled to the third node, the first terminal of the seventeenth transistor is coupled to the driving output terminal, and the second terminal of the seventeenth transistor is coupled to the second low level control terminal; The control terminal of the eighteenth transistor is coupled to the third node, the first terminal of the eighteenth transistor is coupled to the fifth node, and the second terminal of the eighteenth transistor is coupled to the first terminal of the nineteenth transistor; The control terminal of the nineteenth transistor is coupled to the third node, and the second terminal of the nineteenth transistor is coupled to the first low level control terminal; A first terminal of the third capacitor is coupled to the fifth node, and a second terminal of the third capacitor is coupled to the driving output terminal.

11. The shift register unit according to any one of claims 1 to 10, wherein: It also includes an initialization control subcircuit, which is coupled to the second node and the third node and is configured to provide a signal from a first low-level control terminal to the second node in response to a signal from an initialization signal terminal, and to provide a signal from a first high-level signal terminal to the third node in response to a signal from an initialization signal terminal.

12. The shift register unit according to claim 11, wherein: The initialization control subcircuit includes: a twentieth transistor, a twenty-first transistor and a twenty-second transistor; A control terminal of the 20th transistor is coupled to the initialization signal terminal, a first terminal of the 20th transistor is coupled to the second node, and a second terminal of the 20th transistor is coupled to the first terminal of the 22nd transistor; The control terminal of the 21st transistor is coupled to the initialization signal terminal, the first terminal of the 21st transistor is coupled to the first high level signal terminal, and the second terminal of the 21st transistor is coupled to the third node; The control terminal of the 22nd transistor is coupled to the initialization signal terminal, and the second terminal of the 22nd transistor is coupled to the second terminal of the second capacitor.

13. A gate drive circuit, wherein: include: A plurality of gate lines and a plurality of shift register units as claimed in any one of claims 1 to 12; The plurality of gate lines are coupled to the driving output terminals of the plurality of shift register units in a one-to-one correspondence.

14. A display device, wherein: include: The gate drive circuit as claimed in claim 13.

15. The display device according to claim 14, wherein: The first clock signal terminals of the 3k-2 stage shift register units are all coupled to the same clock terminal, i.e., the second gated clock terminal; the second clock signal terminals are all coupled to the same clock terminal, i.e., the first gated clock terminal; and the third clock signal terminals are all coupled to the same clock terminal, i.e., the third gated clock terminal; The first clock signal terminals of the 3k-1th stage shift register units are all coupled to the same clock terminal, i.e., the first gated clock terminal; the second clock signal terminals are all coupled to the same clock terminal, i.e., the third gated clock terminal; and the third clock signal terminals are all coupled to the same clock terminal, i.e., the second gated clock terminal. The first clock signal terminals of the 3k-th level shift register units are all coupled to the same clock terminal, namely the third enable clock terminal, the second clock signal terminals are all coupled to the same clock terminal, namely the second enable clock terminal, and the third clock signal terminals are all coupled to the same clock terminal, namely the first enable clock terminal; wherein k is a positive integer.

16. The display device according to claim 15, wherein: The selection control terminals of the 3k-2th stage shift register unit, the 3k-1th stage shift register unit and the 3kth stage shift register unit are coupled to the same signal line group, wherein k is a positive integer.

17. The display device according to claim 16, wherein: The gating control terminals of the 6k-5th stage shift register unit, the 6k-4th stage shift register unit and the 6k-3th stage shift register unit are coupled to the first group of signal line groups; The selection control end of the 6k-2 level shift register unit, the 6k-1 level shift register unit and the 6k level shift register unit is coupled to the second group of signal line groups, wherein the output signals in the first group of signal line groups are different from those in the second group of signal line groups, and k is a positive integer.

18. The display device according to claim 16, wherein: A decoder is also included, and an output terminal of the decoder provides different output signals for the first group of signal lines and the second group of signal lines.

19. The display device according to claim 14, wherein: The shift register units connected to the signal line group with the same output signal correspond to the same display partition.

20. A method for driving a shift register unit, wherein: include: The decoding control subcircuit connects the first gate clock terminal to the first node in response to the signal of the gate control terminal; The node control subcircuit controls the signals of the second node and the third node in response to the signal of the first gating clock terminal, the signal of the second gating clock terminal and the signal of the first node; The output sub-circuit provides signals from a plurality of output clock signal terminals to corresponding driving output terminals in response to a signal from the second node; And, in response to the signal of the third node, providing the signal of the reference signal terminal to the plurality of driving output terminals.

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