Display panel and display device

Abstract

The embodiments of the present application provide a display panel and a display device. The display panel comprises a display area and a non-display area, wherein the display area comprises a first special-shaped display area, a second special-shaped display area and a regular display area, and the non-display area comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area, the second non-display area being provided with a bonding pad. The first non-display area, the first special-shaped display area, the regular display area, the second special-shaped display area and the second non-display area are sequentially arranged in a first direction, and the third non-display area, the regular display area and the fourth non-display area are sequentially arranged in a second direction. The non-display area is provided with a gate driving circuit. Some of the shift register units therein are located in the first non-display area and are electrically connected to gate lines in the first special-shaped display area, whilst the other shift register units are located in the third non-display area and / or the fourth non-display area.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311124849.5, filed on August 31, 2023, entitled “Display Panel and Display Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Art

[0004] With the development of technology, display panels are increasingly used in people's production and daily life. The pursuit of narrow bezels for display panels has become a key development direction in current display technology. However, the problem of large bezels still exists in current display panels.

[0005] Application Contents

[0006] Embodiments of the present application provide a display panel and a display device, which can improve the space utilization of the frame of the display panel and facilitate the realization of a narrow frame of the display panel.

[0007] In a first aspect, an embodiment of the present application provides a display panel, which includes a display area and a non-display area, the display area including a first special-shaped display area, a second special-shaped display area and a regular display area, the non-display area including a first non-display area and a second non-display area relative to each other, and a third non-display area and a fourth non-display area relative to each other, the second non-display area being provided with a binding pad, the binding pad being electrically connected to a driving chip and / or a flexible circuit board; along a first direction, the first non-display area, the first special-shaped display area, the regular display area, the second special-shaped display area and the second non-display area are arranged in sequence, along a second direction, the third non-display area, the regular display area and the fourth non-display area are arranged in sequence, and the first direction intersects the second direction; the non-display area is provided with a gate driving circuit, the gate driving circuit including a plurality of cascaded shift register units, wherein a part of the shift register units are located in the first non-display area and are electrically connected to the gate line in the first special-shaped display area, and another part of the shift register units are located in the third non-display area and / or the fourth non-display area and are electrically connected to the gate line in the regular display area, and the gate line is used to provide a control signal to the pixel circuit in the display panel.

[0008] In a second aspect, an embodiment of the present application provides a display device, which includes the display panel provided in the first aspect.

[0009] In the display panel and display device of the embodiments of the present application, at least part of the shift register units are arranged in the first non-display area. On the one hand, since the original space utilization rate of the first non-display area is low, that is, there is a certain amount of free space in the first non-display area, the space utilization rate of the first non-display area can be improved by moving at least part of the shift register units to the first non-display area; on the other hand, since at least part of the shift register units are moved to the first non-display area, the circuit structure of other areas of the frame can be simplified, which is conducive to reducing the frame size and realizing a narrow frame of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] FIG1 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0012] FIG2 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0013] FIG3 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0014] FIG4 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0015] FIG5 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0016] FIG6 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0017] FIG7 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0018] FIG8 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0019] FIG9 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0020] FIG10 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0021] FIG11 is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0022] FIG12 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0023] FIG13 is another partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application;

[0024] FIG14 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application;

[0025] FIG15 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] It should be noted that the transistors in the embodiments of the present application can be either N-type transistors or P-type transistors. For N-type transistors, the on-level is a high level, and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second electrodes of the transistor are conductive, and when the gate of the N-type transistor is at a low level, the first and second electrodes of the transistor are disconnected. For P-type transistors, the on-level is a low level, and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the first and second electrodes of the transistor are conductive, and when the control terminal of the P-type transistor is at a high level, the first and second electrodes of the transistor are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors serves as its control terminal, and depending on the signal of the gate of each transistor and its type, the first electrode of the transistor can serve as the source and the second electrode as the drain, or the first electrode can serve as the drain and the second electrode as the source, without distinction being made here. In addition, the on-level and off-level in the embodiments of the present application are both general terms. The on-level refers to any level that can turn the transistor on, and the off-level refers to any level that can turn the transistor off / on.

[0027] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0028] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0029] With the development of technology, display panels are increasingly used in people's production and daily life. The pursuit of narrow bezels for display panels has become a key development direction in current display technology. However, the problem of large bezels still exists in current display panels.

[0030] In view of the above research findings of the inventors, the embodiments of the present application provide a display panel and a display device that can solve the technical problem in the related art that it is difficult to achieve a narrow frame of the display panel.

[0031] The technical concept of the embodiment of the present application is that: at least part of the shift register unit is set in the first non-display area. On the one hand, since the original space utilization rate of the first non-display area is low, that is, there is a certain amount of free space in the first non-display area, the space utilization rate of the first non-display area can be improved by moving at least part of the shift register unit to the first non-display area; on the other hand, since at least part of the shift register unit is moved to the first non-display area, the circuit structure of other areas of the frame can be simplified, which is conducive to reducing the frame size and realizing a narrow frame of the display panel.

[0032] The following first introduces the display panel provided in the embodiment of the present application.

[0033] FIG1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. As shown in FIG1 , the display panel 10 provided in an embodiment of the present application may include a display area AA and a non-display area NA. The display area AA may include a first irregular display area A1, a regular display area A2, and a second irregular display area A3. For example, the shape of the regular display area A2 may be rectangular. The non-display area NA may include a first non-display area NA1 and a second non-display area NA2 that are opposite to each other, and a third non-display area NA3 and a fourth non-display area NA4 that are opposite to each other. That is, the first non-display area NA1 is opposite to the second non-display area NA2, and the third non-display area NA3 is opposite to the fourth non-display area NA4. The second non-display area NA2 is provided with a bonding pad (not shown in the figure), which can be electrically connected to a driver chip and / or a flexible circuit board. For example, the first non-display area NA1 may be the upper frame of the display panel, the second non-display area NA2 may be the lower frame of the display panel, the third non-display area NA3 may be the left frame of the display panel, and the fourth non-display area NA4 may be the right frame of the display panel. There is an R angle at the connection between the first non-display area NA1 and the third non-display area NA3 , and there is an R angle at the connection between the first non-display area NA1 and the fourth non-display area NA4 .

[0034] Along a first direction Y, the first non-display area NA1, the first irregular display area A1, the regular display area A2, the second irregular display area A3, and the second non-display area NA2 are arranged in sequence. For example, the first direction Y may be the column direction of the display panel. The first non-display area NA1 may be located at the far IC end of the display panel, and the second non-display area NA2 may be located at the near IC end of the display panel. That is, the first non-display area NA1 may be the upper frame of the display panel, and the second non-display area NA2 may be the lower frame of the display panel.

[0035] Along the second direction X, the third non-display area NA3, the regular display area A2, and the fourth non-display area NA4 may be arranged in sequence, with the first direction Y intersecting the second direction X. For example, the first direction Y may be the column direction of the display panel, and the second direction X may be the row direction of the display panel. For example, the third non-display area NA3 may be the left border of the display panel, and the fourth non-display area NA4 may be the right border of the display panel.

[0036] The non-display area NA is provided with a gate drive circuit 11, which can be used to output a control signal to control the on / off switching of transistors in pixel circuits (not shown in FIG1 ) in the display panel. The gate drive circuit 11 can include a plurality of cascaded shift register units 110 .

[0037] In the embodiment of the present application, a portion of the shift register units 110 are located in the first non-display area NA1 and are electrically connected to the gate lines 12 in the first special-shaped display area A1. Another portion of the shift register units 110 are located in the third non-display area NA3 and / or the fourth non-display area NA4 and are electrically connected to the gate lines 12 in the regular display area A2. The gate lines 12 can be used to transmit control signals output by the shift register units 110 in the gate driver circuit 11 to the pixel circuits in the display panel.

[0038] It should be noted that in the embodiments of the present application, the drawings are all shown as an example of bilateral driving, that is, the non-display area NA includes two groups of gate driving circuits 11, but it can be understood that the embodiments of the present application can also be unilateral driving, that is, the non-display area NA can only include one group of gate driving circuits 11.

[0039] In the display panel of the embodiment of the present application, at least part of the shift register units are arranged in the first non-display area. On the one hand, since the original space utilization rate of the first non-display area is low, that is, there is a certain amount of free space in the first non-display area, the space utilization rate of the first non-display area can be improved by moving at least part of the shift register units to the first non-display area; on the other hand, since at least part of the shift register units are moved to the first non-display area, the circuit structure of other areas of the frame can be simplified, which is conducive to reducing the frame size and realizing a narrow frame of the display panel.

[0040] In some embodiments, the gate driving circuit 11 may include a scan driving circuit or a light emitting control driving circuit, or may include both a scan driving circuit and a light emitting control driving circuit.

[0041] FIG2 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application. As shown in FIG2 , according to some embodiments of the present application, the gate drive circuit 11 may optionally include a scan drive circuit 21 and / or a light-emission control drive circuit 22. The shift register unit 110 may include a first shift register unit 210 and / or a second shift register unit 220. The scan drive circuit 21 includes a plurality of cascaded first shift register units 210, and the light-emission control drive circuit 22 includes a plurality of cascaded second shift register units 220. The scan drive circuit 21 may be used to output a scan signal, and the light-emission control drive circuit 22 may be used to output a light-emission control signal.

[0042] Accordingly, the gate lines 12 may include scan signal lines Scan and / or light emission control signal lines EM. The scan signal lines Scan are used to transmit scan signals output by the first shift register unit 210 in the scan driving circuit 21 to the pixel circuit, and the light emission control signal lines EM are used to transmit light emission control signals output by the second shift register unit 220 in the light emission control driving circuit 22 to the pixel circuit.

[0043] Specifically, a portion of the first shift register unit 210 can be located in the first non-display area NA1 and electrically connected to the scan signal line Scan in the first special-shaped display area A1, and another portion of the first shift register unit 210 can be located in the third non-display area NA3 and / or the fourth non-display area NA4 and electrically connected to the scan signal line Scan in the regular display area A2.

[0044] And / or, a portion of the second shift register unit 220 is located in the first non-display area NA1 and is electrically connected to the light-emitting control signal line EM in the first special-shaped display area A1, and another portion of the second shift register unit 220 is located in the third non-display area NA3 and / or the fourth non-display area NA4 and is electrically connected to the light-emitting control signal line EM in the regular display area A2.

[0045] In this way, at least part of the first shift register unit of the scanning drive circuit and / or at least part of the second shift register unit of the light-emitting control drive circuit are arranged in the first non-display area. On the one hand, since the original space utilization rate of the first non-display area is low, that is, there is a certain amount of free space in the first non-display area, by moving at least part of the first shift register unit of the scanning drive circuit and / or at least part of the second shift register unit of the light-emitting control drive circuit to the first non-display area, the space utilization rate of the first non-display area can be improved; on the other hand, since at least part of the first shift register unit of the scanning drive circuit and / or at least part of the second shift register unit of the light-emitting control drive circuit are moved to the first non-display area, the circuit structure of other areas of the frame (such as the R corner) can be simplified, which is conducive to reducing the frame size and realizing a narrow frame of the display panel.

[0046] FIG3 is another schematic diagram of the partial structure of the display panel provided in an embodiment of the present application. As shown in FIG3 , according to some embodiments of the present application, optionally, the first-stage shift register unit 110 to the x-stage shift register unit 110 are located in the first non-display area NA1, where x is an integer greater than 1. The size of x can be flexibly adjusted according to actual conditions, and the embodiment of the present application does not limit this. For ease of explanation, 110a represents the first-stage shift register unit, and 110b represents the x-stage shift register unit 110. The input end of the first-stage shift register unit 110a can be electrically connected to the trigger signal line SIN. At the beginning of each frame, the trigger signal line SIN can be used to provide an enable level that triggers the gate drive circuit to operate.

[0047] The second direction X may include a first target direction X1 directed toward the center of the display panel along the edge of the display panel or a second target direction X2 directed toward the edge of the display panel along the center of the display panel.

[0048] As shown in FIG3 , along the second target direction X2, the first-stage shift register unit 110a to the x-stage shift register unit 110b can be arranged in sequence. The first-stage shift register unit 110a to the x-stage shift register unit 110b can be electrically connected to the first gate line 12 to the x-stage gate line 12 in the first special-shaped display area, respectively. Among them, one shift register unit 110 can be connected to one gate line 12. For example, the first-stage shift register unit 110a is connected to the first gate line 12 closest to the first non-display area NA1, the second-stage shift register unit 110 is connected to the second gate line 12, ..., and the x-stage shift register unit 110b is connected to the x-th gate line 12 farthest from the first non-display area NA1. One gate line 12 can be connected to a row of pixel circuits (not shown in the figure).

[0049] In this way, when the arrangement shown in Figure 3 is adopted, the distance between the x-th shift register unit 110b and the x+1-th shift register unit 110 located in the third non-display area NA3 and / or the fourth non-display area NA4 is closer, so the length of the cascade routing between the x-th shift register unit 110b and the x+1-th shift register unit 110 can be set shorter to facilitate wiring, and at the same time, the signal delay between the x-th shift register unit 110b and the x+1-th shift register unit 110 can also be reduced.

[0050] FIG4 is another partial structural schematic diagram of a display panel provided by an embodiment of the present application. As shown in FIG4 , unlike the embodiment shown in FIG3 , according to other embodiments of the present application, optionally, along the first target direction X1, the first-stage shift register unit 110a to the x-stage shift register unit 110b can be arranged in sequence. The first-stage shift register unit 110a to the x-stage shift register unit 110b can be electrically connected to the first gate line 12 to the x-stage gate line 12 in the first special-shaped display area, respectively. Among them, one shift register unit 110 can be connected to one gate line 12. For example, the first-stage shift register unit 110a is connected to the first gate line 12 closest to the first non-display area NA1, the second-stage shift register unit 110 is connected to the second gate line 12, ..., and the x-stage shift register unit 110b is connected to the x-th gate line 12 farthest from the first non-display area NA1. One gate line 12 can be connected to a row of pixel circuits (not shown in the figure).

[0051] FIG5 is another partial structural diagram of a display panel provided in an embodiment of the present application. As shown in FIG5 , according to some embodiments of the present application, the gate drive circuit 11 may optionally include a scan drive circuit 21 and a light-emitting control drive circuit 22. Specifically, the first shift register unit 210 of the first stage to the x1-th first shift register unit 210 may be located in the first non-display area NA1, and the second shift register unit 220 of the first stage to the x2-th second shift register unit 220 may be located in the first non-display area NA1, where x1 and x2 are both integers greater than 1. x1 and x2 may be equal or different, and this is not limited in the embodiment of the present application.

[0052] The first shift register unit 210 to the x1-th first shift register unit 210 sequentially arranged along the second direction X constitute a first shift register unit group 51, and the first second shift register unit 220 to the x2-th second shift register unit 220 sequentially arranged along the second direction X constitute a second shift register unit group 52. The first shift register unit group 51 and the second shift register unit group 52 can be arranged along the first direction Y. That is, the first shift register unit group 51 and the second shift register unit group 52 can be stacked in the first direction Y.

[0053] As shown in conjunction with FIG3 , FIG4 and FIG5 , the first shift register unit 210 of the first stage to the x1-th stage first shift register unit 210 in the first shift register unit group 51 can be sequentially arranged along the first target direction X1 or along the second target direction X2. Similarly, the second shift register unit 220 of the first stage to the x2-th stage second shift register unit 220 in the second shift register unit group 52, which constitute the second shift register unit group 52, can be sequentially arranged along the first target direction X1 or along the second target direction X2.

[0054] FIG6 is another partial structural diagram of a display panel provided in an embodiment of the present application. As shown in FIG6 , unlike the embodiment shown in FIG5 , according to other embodiments of the present application, the first shift register unit group 51 and the second shift register unit group 52 may optionally be arranged along the second direction X. That is, the first shift register unit group 51 and the second shift register unit group 52 may be arranged in parallel in the second direction X.

[0055] In this way, since the first shift register unit group 51 and the second shift register unit group 52 are arranged along the second direction X, the impact on the height (or width) of the first non-display area along the first direction can be reduced, which is conducive to reducing the height (or width) of the first non-display area along the first direction.

[0056] FIG7 is a schematic diagram of another partial structure of a display panel provided in an embodiment of the present application. As shown in FIG7 , unlike the embodiments shown in FIG5 and FIG6 , according to some other embodiments of the present application, the first shift register units 210 in the first non-display area NA1 and the second shift register units 220 in the first non-display area NA2 can optionally be arranged alternately along the second direction X. That is, a second shift register unit 220 can exist between any two adjacent first shift register units 210 in the first non-display area NA1, and a first shift register unit 210 can exist between any two adjacent second shift register units 220 in the first non-display area NA2.

[0057] In this way, since the first shift register unit 210 in the first non-display area NA1 and the second shift register unit 220 in the first non-display area NA2 are alternately arranged along the second direction X, the impact on the height (or width) of the first non-display area along the first direction can be reduced, which is conducive to reducing the height (or width) of the first non-display area along the first direction.

[0058] 1 , according to some embodiments of the present application, optionally, the non-display area NA may further include a first R angle r1 connecting the first non-display area NA1 and the third non-display area NA3 and a second R angle r2 connecting the first non-display area NA1 and the fourth non-display area NA4.

[0059] The clock signal line CLK in the display panel can be connected to the shift register unit 110 located in the first non-display area NA1 and the shift register unit 110 located in the third non-display area NA3 via the first R corner r1, and / or, the clock signal line CLK can be connected to the shift register unit 110 located in the first non-display area NA1 and the shift register unit 110 located in the fourth non-display area NA4 via the second R corner r2.

[0060] As shown in FIG5, FIG6 or FIG7, the clock signal line CLK may include a first clock signal line CLK1 and a second clock signal line CLK2. The first clock signal line CLK1 may connect the first shift register unit 210 located in the first non-display area NA1 and the first shift register unit 210 located in the third non-display area NA3 via a first R angle r1, and / or the first clock signal line CLK1 may connect the first shift register unit 210 located in the first non-display area NA1 and the first shift register unit 210 located in the fourth non-display area NA4 via a second R angle r2. The second clock signal line CLK2 may connect the second shift register unit 220 located in the first non-display area NA1 and the second shift register unit 220 located in the third non-display area NA3 via the first R angle r1, and / or the second clock signal line CLK2 may connect the second shift register unit 220 located in the first non-display area NA1 and the second shift register unit 220 located in the fourth non-display area NA4 via a second R angle r2.

[0061] It should be noted that there may be multiple first clock signal lines CLK1 and multiple second clock signal lines CLK2. For example, each stage of the first shift register unit 210 may be electrically connected to three first clock signal lines CLK1, and each stage of the second shift register unit 220 may be electrically connected to three second clock signal lines CLK2. This is not limited in the present embodiment.

[0062] Continuing with FIG. 1 , according to some embodiments of the present application, optionally, in addition to the clock signal line CLK, a negative power supply voltage signal line VSS (not shown in the figure) may be provided at the first R corner r1 and the second R corner r2. The negative power supply voltage signal line may be electrically connected to the cathode of the light-emitting element in the display area, and is used to provide a voltage signal with a negative voltage value to the cathode of the light-emitting element in the display area. In some specific embodiments, the negative power supply voltage signal line VSS located in the non-display area NA may circle the display area AA at least once, that is, the negative power supply voltage signal line VSS passes through the second non-display area NA2, the third non-display area NA3, the first R corner r1, the first non-display area NA1, the second R corner r2, and the fourth non-display area NA4, and then circles back to the second non-display area NA2.

[0063] The R angle size is a difficulty in achieving a narrow frame, and reducing the R angle size can play a key role in achieving a narrow frame. The inventors of this application have found that the main reason for limiting the R angle size is the presence of the shift register unit in the gate drive circuit, which occupies a large space.

[0064] In this way, the shift register unit originally located at the R corner (the first R corner r1 and / or the second R corner r2) is moved to the first non-display area. On the one hand, since the original space utilization rate of the first non-display area is low, that is, there is a certain amount of free space in the first non-display area, the space utilization rate of the first non-display area can be improved by moving the shift register unit originally located at the R corner to the first non-display area; on the other hand, since the shift register unit originally located at the R corner is moved to the first non-display area, the circuit structure within the R corner frame is simplified, which is conducive to reducing the size of the R corner, and thus is conducive to achieving a narrow frame of the display panel.

[0065] In this way, only the clock signal line CLK and the negative power supply voltage signal line VSS need to be set at the first R corner r1 and the second R corner r2, so the circuit structure within the R corner frame can be greatly simplified, which is beneficial to reducing the size of the R corner and further beneficial to achieving a narrow frame of the display panel.

[0066] FIG8 is another partial structural diagram of a display panel provided in an embodiment of the present application. As shown in FIG8 , according to some embodiments of the present application, the first special-shaped display area A1 may optionally be provided with a connecting line L extending along the first direction Y, and the shift register unit 110 in the first non-display area NA1 may be electrically connected to the gate line 12 in the first special-shaped display area A1 via the connecting line L.

[0067] In this way, on the one hand, the connection line L located in the first special-shaped display area A1 connects the shift register unit 110 in the first non-display area NA1 and the gate line 12 in the first special-shaped display area A1. That is, the connection line L is arranged in the first special-shaped display area A1 instead of at the R corner, which can further help reduce the size of the R corner and achieve a narrow frame. On the other hand, because the connection line L extends along the first direction Y and is perpendicular to the gate line 12 extending along the second direction X, the length of the connection line L can be set to be shorter, which is beneficial for wiring design. In addition, it can ensure that the shift register unit 110 in the first non-display area NA1 is connected to the gate line 12 in the first special-shaped display area A1 in sequence, ensuring normal driving of the pixel circuit.

[0068] To prevent the connection line L from being shorted to multiple gate lines simultaneously, in some embodiments, the connection line L and the gate line 12 in the first special-shaped display area A1 can be located in different film layers, and the connection line L is electrically connected to the gate line 12 in the first special-shaped display area A1 through a via. In this way, it can be ensured that a connection line L is electrically connected to only one corresponding gate line 12, preventing a connection line L from being shorted to multiple gate lines simultaneously.

[0069] Figure 9 is another partial structural diagram of a display panel provided in an embodiment of the present application. As shown in Figure 9, according to some embodiments of the present application, optionally, the display area AA may include multiple columns of real sub-pixel units 91 and multiple columns of virtual sub-pixel units 92. A column of real sub-pixel units 91 may include multiple real sub-pixel units 91 arranged along a first direction Y, and a column of virtual sub-pixel units 92 may include multiple virtual sub-pixel units 92 arranged along a first direction Y. Among them, the real sub-pixel unit 91 may include a pixel circuit and a light-emitting element connected to the pixel circuit, and the virtual sub-pixel unit 92 may include a pixel circuit. That is, the real sub-pixel unit 91 is normally provided with a pixel circuit and a light-emitting element, while the virtual sub-pixel unit 92 is only provided with a pixel circuit, and no light-emitting element is provided. Exemplarily, the light-emitting element includes but is not limited to an organic light-emitting diode (OLED).

[0070] The display area AA is provided with a first dummy signal line dummy1 extending along the first direction Y. Along the thickness direction of the display panel, the orthographic projection of the first dummy signal line dummy1 may at least partially overlap with the orthographic projection of the dummy sub-pixel unit 92. Among them, the connecting line L may specifically include the first dummy signal line dummy1. That is, the connecting line L reuses the first dummy signal line dummy1. Exemplarily, the first dummy signal line dummy1 includes but is not limited to a dummy data signal line or a dummy positive power supply voltage signal line. Among them, the dummy data signal line can be understood as a data signal line overlapping with the orthographic projection of the dummy sub-pixel unit 92, and the dummy positive power supply voltage signal line can be understood as a positive power supply voltage signal line overlapping with the orthographic projection of the dummy sub-pixel unit 92.

[0071] In the embodiment shown in FIG9 , the sub-pixel structure of the display area AA can be compressed, for example, by reducing the size of the pixel circuit through process or by reducing the number of transistors in the pixel circuit, thereby achieving compression of the sub-pixel structure of the display area AA. In this way, a column of dummy sub-pixel units 92 is compressed for every several columns of real sub-pixel units 91, which is used to arrange the dummy sub-pixel units 92. Along the thickness direction of the display panel, a first dummy signal line dummy1 can be set above the dummy sub-pixel unit 92 to serve as a connecting line L.

[0072] In this way, without adding an extra metal film layer, the shift register unit 110 in the first non-display area NA1 can be electrically connected to the gate line 12 in the first special-shaped display area A1 by reusing the first dummy signal line dummy1 as the connecting line L.

[0073] Figure 10 is another partial structural schematic diagram of the display panel provided by an embodiment of the present application. As shown in Figure 10, different from the embodiment shown in Figure 9, according to other embodiments of the present application, optionally, a dummy sub-pixel unit may not be provided, but only a first dummy signal line may be provided. Specifically, the display area AA may include multiple columns of real sub-pixel units 91 and a first dummy signal line dummy1 located between two adjacent columns of real sub-pixel units 91. The first dummy signal line dummy1 extends along the first direction Y, and a column of real sub-pixel units 91 includes multiple real sub-pixel units 91 arranged along the first direction Y. Among them, the connecting line L may include the first dummy signal line dummy1. That is, the connecting line L reuses the first dummy signal line dummy1. Exemplarily, the first dummy signal line dummy1 includes but is not limited to a dummy data signal line or a dummy positive power supply voltage signal line.

[0074] In the embodiment shown in FIG10 , the sub-pixel structure of display area AA can be compressed, for example, by reducing the size of the pixel circuit through process or by reducing the number of transistors in the pixel circuit, thereby achieving compression of the sub-pixel structure of display area AA. Thus, space for at least one first dummy signal line dummy1 is compressed for every several columns of real sub-pixel units 91, for arranging the first dummy signal line dummy1.

[0075] In this way, without adding an extra metal film layer, the shift register unit 110 in the first non-display area NA1 can be electrically connected to the gate line 12 in the first special-shaped display area A1 by reusing the first dummy signal line dummy1 as the connecting line L.

[0076] Continuing to refer to Figure 9 or Figure 10, according to some embodiments of the present application, optionally, the first dummy signal line dummy1 may include at least a first routing portion b1 and a second routing portion b2 located on the same straight line. The shift register unit 110 in the first non-display area NA1 is electrically connected to the gate line 12 in the first special-shaped display area A1 through the first routing portion b1, and the first routing portion b1 is not connected to the second routing portion b2. The second routing portion b2 may include a first conductive routing line, the first conductive routing line is floating, or the first conductive routing line is electrically connected to the dummy sub-pixel unit, or the first conductive routing line is electrically connected to a constant potential. The constant potential includes but is not limited to a positive power supply voltage signal line or a negative power supply voltage signal line.

[0077] In other words, after the shift register unit 110 in the first non-display area NA1 is connected to the gate line 12 in the first special-shaped display area A1 through the first dummy signal line dummy1, it can be disconnected from the first dummy signal line dummy1 below on the same straight line, thereby avoiding redundant load.

[0078] According to some further embodiments of the present application, optionally, an additional metal film layer may be added to the current array substrate structure, and the connecting traces L may be provided through the additional metal film layer.

[0079] FIG11 is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. As shown in FIG11 , according to some further embodiments of the present application, the display panel 10 may optionally include a substrate 01 and multiple metal layers M stacked along the thickness direction Z of the display panel, and the connection trace L may be located on at least one of the metal layers M.

[0080] FIG12 is another partial structural schematic diagram of a display panel provided in an embodiment of the present application. As shown in FIG11 and FIG12 , the display area AA may include multiple columns of real sub-pixel units 91, where a column of real sub-pixel units 91 includes multiple real sub-pixel units 91 arranged along a first direction Y. Along the thickness direction Z of the display panel, the orthographic projection of the connecting trace L at least partially overlaps with the orthographic projection of the real sub-pixel unit 91. For example, the connecting trace L may be located on the side of the real sub-pixel unit 91 away from the substrate 01, i.e., above the real sub-pixel unit 91.

[0081] Continuing to refer to FIG11 , in some specific embodiments, for example, the display panel 10 includes a stacked substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, a fifth metal layer M5, an anode layer RE, and an insulating layer between any two metal layers. In some examples, along the thickness direction Z of the display panel, a semiconductor layer (or active layer) may be provided between the substrate 01 and the first metal layer M1 to form a channel region of a thin film transistor. The first metal layer M1 may be used to form the gate of the thin film transistor, the second metal layer M2 may be used to form one of the plates (such as the upper plate) of the storage capacitor, the third metal layer M3 may be used to form a connection structure for the source and / or drain of the thin film transistor, and the fourth metal layer M4 may be used to form a trace extending along the first direction. The anode layer RE may be used to form the anode of the light-emitting element. Along the thickness direction Z of the display panel, an interlayer dielectric layer ILD may be provided between the second metal layer M2 and the third metal layer M3, and the interlayer dielectric layer ILD may be provided with a connection via. A first planarization layer PLN1 may be provided between the third metal layer M3 and the fourth metal layer M4, a second planarization layer PLN2 may be provided between the fourth metal layer M4 and the fifth metal layer M5, and a third planarization layer PLN3 may be provided between the fifth metal layer M5 and the anode layer RE. The anode of the light-emitting element in the anode layer RE may be located within an opening formed by the pixel definition layer PDL. A support pillar SPC may also be provided on the side of the pixel definition layer PDL away from the third planarization layer PLN3.

[0082] The fifth metal layer M5 may be a newly added metal film layer, and the connecting trace L may be located in the fifth metal layer M5.

[0083] In this way, by adding an extra metal film layer in the display area to form the connecting line L, the shift register unit 110 in the first non-display area NA1 can be electrically connected to the gate line 12 in the first special-shaped display area A1.

[0084] 11 , in some specific embodiments, the data signal line data and the positive power supply voltage signal line VDD in the display panel may be located in the third metal layer M3 and / or the fourth metal layer M4. Both the data signal line data and the positive power supply voltage signal line VDD may extend along the first direction.

[0085] Continuing with FIG. 12 , in some specific embodiments, the connecting trace L includes at least a third trace portion L3 and a fourth trace portion L4 located on the same straight line. The shift register unit 110 in the first non-display area NA1 is electrically connected to the gate line 12 in the first special-shaped display area A1 via the third trace portion L3. The third trace portion L3 is disconnected from the fourth trace portion L4. The fourth trace portion L4 may include a second conductive trace, which is either floating or electrically connected to a constant potential. The constant potential includes, but is not limited to, a positive power supply voltage signal line or a negative power supply voltage signal line.

[0086] In other words, after the shift register unit 110 in the first non-display area NA1 is connected to the gate line 12 in the first special-shaped display area A1 through the connecting line L, it can be disconnected from the lower connecting line L on the same straight line, thereby avoiding redundant load.

[0087] FIG13 is another partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present application. As shown in FIG13 , according to some embodiments of the present application, optionally, along the thickness direction Z of the display panel, the display panel 10 may include a substrate 01 and a plurality of metal layers M arranged in a stacked manner. The display panel may also include a data signal line data and a positive power supply voltage signal line VDD extending along a first direction (not shown in FIG13 , i.e., the first direction Y). Without adding an additional metal film layer, the first dummy signal line dummy1 may be located in the same metal layer as the data signal line data and / or the positive power supply voltage signal line VDD.

[0088] For example, in some specific embodiments, the display panel 10 may include a stacked substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, an anode layer RE, and an insulating layer between any two metal layers. In some examples, along the thickness direction Z of the display panel, a semiconductor layer (or active layer) may be provided between the substrate 01 and the first metal layer M1 to form a channel region of a thin film transistor. The first metal layer M1 may be used to form the gate of the thin film transistor, the second metal layer M2 may be used to form one of the plates (such as the upper plate) of the storage capacitor, the third metal layer M3 may be used to form a connection structure of the source and / or drain of the thin film transistor, and the fourth metal layer M4 may be used to form a trace extending along the first direction. The anode layer RE may be used to form the anode of the light-emitting element. Along the thickness direction Z of the display panel, an interlayer dielectric layer ILD may be provided between the second metal layer M2 and the third metal layer M3, and the interlayer dielectric layer ILD may be provided with a connection via. A first planarization layer PLN1 may be provided between the third metal layer M3 and the fourth metal layer M4, and a second planarization layer PLN2 may be provided between the fourth metal layer M4 and the anode layer RE. The anode of the light-emitting element in the anode layer RE may be located within an opening formed by the pixel definition layer PDL. A support pillar SPC may also be provided on a side of the pixel definition layer PDL away from the third planarization layer PLN3.

[0089] The first dummy signal line dummy1 , the data signal line data and the positive power supply voltage signal line VDD may be located in the third metal layer M3 and / or the fourth metal layer M4 .

[0090] The inventors of this application further discovered that the first dummy signal line dummy1, especially the first dummy signal line dummy1 connected to the second shift register unit 220 of the light-emitting control driving circuit, may couple with the gate node of the driving transistor of the adjacent real sub-pixel unit when transmitting the control signal, thereby causing abnormal changes in the light-emitting brightness.

[0091] FIG14 is another partial structural diagram of a display panel provided in an embodiment of the present application. As shown in FIG14 , according to some embodiments of the present application, the display area AA is optionally further provided with a second dummy signal line dummy2 extending along the first direction Y. The second dummy signal line dummy2 can be electrically connected to a constant voltage source (such as a positive power supply voltage signal line VDD or a negative power supply voltage signal line VSS) to maintain a constant potential.

[0092] Along the second direction X, the second dummy signal line dummy2 is located between the first dummy signal line dummy1 and the adjacent column of real sub-pixel units 91. The adjacent column of real sub-pixel units 91 may be a column of real sub-pixel units 91 adjacent to at least one side (e.g., left and / or right) of the first dummy signal line dummy1.

[0093] In this way, since there is a second dummy signal line dummy2 between the first dummy signal line dummy1 and the adjacent column real sub-pixel unit 91, and the second dummy signal line dummy2 maintains a constant potential, the influence of the control signal transmitted by the first dummy signal line dummy1 on the gate node of the driving transistor of the adjacent real sub-pixel unit can be better shielded, thereby maintaining brightness stability and uniformity.

[0094] In the embodiment shown in Figure 14, the gate driving circuit 11 may include at least a light emitting control driving circuit. Of course, in the embodiment shown in Figure 14, the gate driving circuit 11 may also include a scanning driving circuit.

[0095] In the embodiment shown in FIG. 14 , the first dummy signal line dummy1 may include a dummy positive power supply voltage signal line, and the second dummy signal line dummy2 may include a dummy data signal line.

[0096] It should be noted that the embodiment shown in FIG14 is applicable to both the solution shown in FIG9 with the dummy sub-pixel unit 92 and the solution shown in FIG10 without the dummy sub-pixel unit 92 , and the embodiment of the present application does not limit this.

[0097] Based on the display panel provided in the above embodiments, the present application also provides a display device, including the display panel provided in the present application. Please refer to Figure 15, which is a structural schematic diagram of the display device provided in the embodiment of the present application. The display device 1000 provided in Figure 15 includes the display panel 10 provided in any of the above embodiments of the present application. The embodiment of Figure 15 takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display device with a display function, and the present application does not impose specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 10 provided in the embodiment of the present application. For details, please refer to the specific description of the display panel 10 in the above embodiments, and this embodiment will not be repeated here.

Claims

1. A display panel, comprising a display area and a non-display area, wherein the display area comprises a first special-shaped display area, a second special-shaped display area and a regular display area, wherein the non-display area comprises a first non-display area and a second non-display area opposite to each other, and a third non-display area and a fourth non-display area opposite to each other, wherein the second non-display area is provided with a binding pad, and the binding pad is electrically connected to a driving chip and / or a flexible circuit board; Along a first direction, the first non-display area, the first irregular display area, the regular display area, the second irregular display area and the second non-display area are arranged in sequence, and along a second direction, the third non-display area, the regular display area and the fourth non-display area are arranged in sequence, and the first direction intersects the second direction; The non-display area is provided with a gate driving circuit, and the gate driving circuit includes a plurality of cascaded shift register units, wherein a part of the shift register units are located in the first non-display area and are electrically connected to the gate lines in the first special-shaped display area, and another part of the shift register units are located in the third non-display area and / or the fourth non-display area and are electrically connected to the gate lines in the regular display area, and the gate lines are used to provide control signals to the pixel circuits in the display panel.

2. The display panel according to claim 1, wherein: The gate driving circuit includes a scanning driving circuit and / or a light emitting control driving circuit, the shift register unit includes a first shift register unit and / or a second shift register unit, the scanning driving circuit includes a plurality of cascaded first shift register units, the light emitting control driving circuit includes a plurality of cascaded second shift register units, the gate line includes a scanning signal line and / or a light emitting control signal line, the scanning signal line is used to provide a scanning signal to the pixel circuit, and the light emitting control signal line is used to provide a light emitting control signal to the pixel circuit; A portion of the first shift register units is located in the first non-display area and is electrically connected to the scan signal line in the first special-shaped display area, and another portion of the first shift register units is located in the third non-display area and / or the fourth non-display area and is electrically connected to the scan signal line in the regular display area; And / or, a part of the second shift register units are located in the first non-display area and are electrically connected to the light-emitting control signal line in the first special-shaped display area, and another part of the second shift register units are located in the third non-display area and / or the fourth non-display area and are electrically connected to the light-emitting control signal line in the regular display area.

3. The display panel according to claim 2, wherein: The shift register units of the first stage to the xth stage are located in the first non-display area, where x is an integer greater than 1; The second direction includes a first target direction pointing from an edge of the display panel to a center of the display panel or a second target direction pointing from the center of the display panel to an edge of the display panel; Along the first target direction or the second target direction, the shift register units of the first stage to the shift register units of the xth stage are arranged in sequence; The shift register units of the first stage to the xth stage are electrically connected to the first gate line to the xth gate line in the first special-shaped display area respectively, and one shift register unit is connected to one gate line.

4. The display panel according to claim 3, wherein: The gate driving circuit includes the scanning driving circuit and the light emitting control driving circuit, the first shift register unit of the first level to the first shift register unit of the x1th level are located in the first non-display area, the second shift register unit of the first level to the second shift register unit of the x2th level are located in the first non-display area, and x1 and x2 are both integers greater than 1; The first shift register unit of the first stage to the first shift register unit of the x1th stage sequentially arranged along the second direction constitute a first shift register unit group, the second shift register unit of the first stage to the second shift register unit of the x2th stage sequentially arranged along the second direction constitute a second shift register unit group, and the first shift register unit group and the second shift register unit group are arranged along the first direction or the second direction; Alternatively, along the second direction, the first shift register units in the first non-display area and the second shift register units in the first non-display area are arranged alternately.

5. The display panel according to claim 1, wherein: The non-display area includes a first R angle connecting the first non-display area and the third non-display area and a second R angle connecting the first non-display area and the fourth non-display area; The clock signal line in the display panel connects the shift register unit located in the first non-display area and the shift register unit located in the third non-display area via the first R angle, and / or the clock signal line connects the shift register unit located in the first non-display area and the shift register unit located in the fourth non-display area via the second R angle.

6. The display panel according to claim 5, wherein: The first R angle and / or the second R angle is also provided with a negative power supply voltage signal line, and the negative power supply voltage signal line is electrically connected to the cathode of the light emitting element in the display area.

7. The display panel according to claim 1, wherein: The first special-shaped display area is provided with a connecting wire extending along the first direction, and the shift register unit in the first non-display area is electrically connected to the gate line in the first special-shaped display area through the connecting wire.

8. The display panel according to claim 7, wherein: The connection wiring and the gate line in the first special-shaped display area are located in different film layers, and the connection wiring is electrically connected to the gate line in the first special-shaped display area through a via hole.

9. The display panel according to claim 7, wherein: The display area includes a plurality of columns of real sub-pixel units and a plurality of columns of dummy sub-pixel units, one column of real sub-pixel units includes a plurality of real sub-pixel units arranged along the first direction, one column of dummy sub-pixel units includes a plurality of dummy sub-pixel units arranged along the first direction, the real sub-pixel units include pixel circuits and light-emitting elements connected to the pixel circuits, and the dummy sub-pixel units include pixel circuits; The display area is provided with a first dummy signal line extending along the first direction, along the thickness direction of the display panel, the orthographic projection of the first dummy signal line at least partially overlaps with the orthographic projection of the dummy sub-pixel unit, and the connecting line includes the first dummy signal line; Alternatively, the display area includes multiple columns of real sub-pixel units and a first dummy signal line located between two adjacent columns of real sub-pixel units, the first dummy signal line extends along the first direction, a column of real sub-pixel units includes multiple real sub-pixel units arranged along the first direction, and the connecting line includes the first dummy signal line.

10. The display panel according to claim 9, wherein: The first dummy signal line at least includes a first routing portion and a second routing portion located on the same straight line, the shift register unit in the first non-display area is electrically connected to the gate line in the first special-shaped display area through the first routing portion, the first routing portion is not connected to the second routing portion, the second routing portion includes a first conductive routing, the first conductive routing is floating, or the first conductive routing is electrically connected to the dummy sub-pixel unit, or the first conductive routing is electrically connected to a constant potential.

11. The display panel according to claim 7, wherein: Along the thickness direction of the display panel, the display panel includes a substrate and a plurality of metal layers which are stacked, and the connection wiring is located at at least one of the metal layers; The display area includes multiple columns of real sub-pixel units, one column of real sub-pixel units includes multiple real sub-pixel units arranged along the first direction, and along the thickness direction of the display panel, the orthographic projection of the connecting line at least partially overlaps with the orthographic projection of the real sub-pixel unit.

12. The display panel according to claim 11, wherein: The display panel includes a stacked substrate, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, an anode layer and an insulating layer between any two metal layers, and the connecting wire is located in the fifth metal layer.

13. The display panel according to claim 12, wherein: The data signal lines and the positive power supply voltage signal lines in the display panel are located in the third metal layer and / or the fourth metal layer.

14. The display panel according to claim 12, wherein: The connecting routing at least includes a third routing portion and a fourth routing portion located on the same straight line, the shift register unit in the first non-display area is electrically connected to the gate line in the first special-shaped display area through the third routing portion, the third routing portion is not connected to the fourth routing portion, the fourth routing portion includes a second conductive routing, and the second conductive routing is floating or electrically connected to a constant potential.

15. The display panel according to claim 9, wherein: Along the thickness direction of the display panel, the display panel includes a substrate and a plurality of metal layers stacked in layers; The display panel further includes a data signal line and a positive power supply voltage signal line extending along the first direction, and the first dummy signal line and the data signal line and / or the positive power supply voltage signal line are located in the same metal layer.

16. The display panel according to claim 15, wherein: The display panel includes a stacked substrate, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, an anode layer and an insulating layer between any two metal layers, and the first dummy signal line, the data signal line and the positive power supply voltage signal line are located in the third metal layer and / or the fourth metal layer.

17. The display panel according to claim 9, wherein: The display area is further provided with a second dummy signal line extending along the first direction, and the second dummy signal line maintains a constant potential; Along the second direction, the second dummy signal line is between the first dummy signal line and an adjacent column of real sub-pixel units, and the adjacent column of real sub-pixel units is a column of real sub-pixel units adjacent to at least one side of the first dummy signal line.

18. The display panel according to claim 1, wherein: The gate driving circuit at least includes a light emitting control driving circuit.

19. The display panel according to claim 17, wherein: The first dummy signal line includes a dummy positive power supply voltage signal line, and the second dummy signal line includes a dummy data signal line.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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