Three-dimensional memory and manufacturing method therefor, and electronic device

Abstract

The present disclosure provides a three-dimensional memory and a manufacturing method therefor, and an electronic device. The three-dimensional memory of the present disclosure comprises multiple layers of storage unit arrays stacked in a third direction, and a word line. Each layer of storage unit array comprises a first column of storage units and a second column of storage units adjacent to the first column of storage units. The first column of storage units and the second column of storage units are arranged in a first direction. The first column of storage units is connected to a bit line extending in a second direction. The second column of storage units is connected to another bit line extending in the second direction. The storage units each comprise a transistor and a capacitor. The capacitor comprises a first electrode and a second electrode. The transistor is electrically connected to the first electrode. The word line extends in the third direction. The transistor has a channel region only on at least one side of the word line connected thereto in the second direction. The first direction intersects with the second direction. The first direction and the second direction are both perpendicular to the third direction. Each channel region of the first column of storage units or the second column of storage units and the connected bit line are different regions of the same film layer. The film layer is a monocrystalline silicon layer. The bit line region of the film layer comprises a metal silicide.

Description

Three-dimensional memory, manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 31, 2023, with application number 202311118811.7 and invention name “Three-dimensional memory, manufacturing method thereof, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a three-dimensional memory, a manufacturing method thereof, and an electronic device. Background Art

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0004] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] Summary of the Invention

[0006] The following is an overview of the subject matter described in detail in accordance with the embodiments of the present disclosure. This overview is not intended to limit the scope of the claims.

[0007] In some embodiments, a three-dimensional memory is provided, comprising:

[0008] a multi-layer memory cell array stacked along a third direction, each layer of the memory cell array comprising a first column of memory cells and a second column of memory cells, the first column of memory cells and the second column of memory cells being adjacent and arranged along the first direction, the first column of memory cells being connected to a bit line extending along the second direction, and the second column of memory cells being connected to another bit line extending along the second direction;

[0009] The memory cell includes a transistor and a capacitor; the capacitor includes a first electrode and a second electrode, and the transistor is electrically connected to the first electrode;

[0010] word lines, extending along a third direction;

[0011] The transistor has a channel region only on at least one side of the word line connected thereto along the second direction;

[0012] The first direction intersects the second direction and is perpendicular to the third direction;

[0013] Each channel region of the first column of memory cells or the second column of memory cells and the connected bit lines are different regions of the same film layer, the film layer is a single crystal silicon layer, and the bit line region of the film layer contains metal silicide.

[0014] In some embodiments, the transistor has channel regions only on two sides of the word line to which it is connected along the second direction.

[0015] In some embodiments, an isolation portion is further included, wherein a bit line connected to the first column of memory cells and another bit line connected to the second column of memory cells are separated by the isolation portion, and the first column of memory cells and the second column of memory cells are symmetrically distributed relative to the isolation portion in a first direction.

[0016] In some embodiments, the transistor further includes a gate, the gate is part of the corresponding word line, and a gate insulating layer is provided between the gate and the channel region; the transistors stacked in the third direction share a word line.

[0017] In some embodiments, in the third direction, the channel regions of the memory cells stacked in the third direction are spaced apart from each other.

[0018] In some embodiments, the transistor further includes a first source / drain and a second source / drain located on both sides of the word line in the first direction.

[0019] In some embodiments, the first source / drain, the second source / drain, the first electrode and the bit line are different regions of the same film layer, the same film layer is a single crystal silicon layer, and the regions corresponding to the first source / drain and the second source / drain of the film layer are N-type doped regions.

[0020] In some embodiments, the second electrode surrounds the first electrode.

[0021] In some embodiments, the capacitor includes a dielectric layer located between the first electrode and the second electrode, and the dielectric layers of the capacitors of the plurality of storage units are interconnected to form an integrated structure.

[0022] In some embodiments, the second electrodes of the capacitors of the plurality of storage units are interconnected to form an integrated structure.

[0023] In some embodiments, a conductive layer is provided between the plurality of second electrodes, a support portion is provided on a side of the capacitor away from the transistor, and the conductive layer is connected to the support portion.

[0024] In some embodiments, a plurality of second electrodes are electrically connected through the conductive layer, and the second electrodes are made of different materials from the conductive layer.

[0025] In some embodiments, a method for manufacturing a three-dimensional memory is provided, comprising the following steps:

[0026] Alternatingly forming sacrificial layers and semiconductor layers along a third direction, wherein the sacrificial layers are silicon germanium layers grown by epitaxial growth, and the semiconductor layers are single crystal silicon layers grown by epitaxial growth, to form a stacked structure;

[0027] forming a plurality of first extensions extending along a first direction and spaced apart along a second direction and a second extension extending along the second direction in the semiconductor layer, wherein each of the first extensions is divided into a first sub-extension and a second sub-extension by the second extension in the first direction, and the first direction intersects the second direction and is perpendicular to the third direction;

[0028] An isolation region and bit line preset regions located on both sides of the isolation region are provided in the second extension portion;

[0029] In the first sub-extension, a second source / drain preset region, a word line preset region, a first source / drain preset region and a capacitor preset region are sequentially arranged along a first direction on a side of the bit line preset region away from the isolation region;

[0030] forming a support portion on a side of the capacitor preset region away from the first source / drain preset region;

[0031] removing the sacrificial layer in the predetermined area of ​​the capacitor to expose the semiconductor layer in the predetermined area of ​​the capacitor, thereby forming a first electrode of the capacitor;

[0032] forming a bit line comprising metal silicide in the bit line predetermined region;

[0033] forming a word line through hole penetrating the stacked structure in the word line preset area;

[0034] An insulating layer film and a conductive film are sequentially deposited around the inner peripheral wall of the word line through hole to form a gate insulating layer and a word line.

[0035] In some embodiments, the manufacturing method further comprises:

[0036] Depositing a dielectric film around the exposed first electrode to completely cover the first electrode to form a dielectric layer;

[0037] A conductive film is deposited around the dielectric layer and completely covers the dielectric layer to form a second electrode.

[0038] In some embodiments, forming the bit line includes:

[0039] removing the stacked structure in the isolation region to form a trench penetrating the stacked structure;

[0040] The semiconductor layer in the bit line preset area is doped with the formed trench to form the bit line.

[0041] In some embodiments, exemplary embodiments of the present disclosure provide an electronic device comprising any of the three-dimensional memories described above.

[0042] In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0043] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0044] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0045] Summary of the Figures

[0046] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0047] FIG1A is a perspective schematic diagram of a three-dimensional memory provided in accordance with an exemplary embodiment of the present disclosure;

[0048] FIG1B is a schematic cross-sectional view taken along the C1 plane in FIG1A ;

[0049] FIG2A is a perspective schematic diagram of a three-dimensional memory provided in accordance with an exemplary embodiment of the present disclosure;

[0050] FIG2B is a schematic cross-sectional view taken along plane C2 in FIG2A ;

[0051] FIG3A is a perspective schematic diagram of a three-dimensional memory provided in accordance with an exemplary embodiment of the present disclosure;

[0052] FIG3B is a schematic cross-sectional view taken along plane C3 in FIG3A ;

[0053] FIG4A is a perspective schematic diagram of a three-dimensional memory provided in accordance with an exemplary embodiment of the present disclosure;

[0054] FIG4B is a schematic cross-sectional view taken along plane C4 in FIG4A ;

[0055] FIG5A is a perspective schematic diagram of a three-dimensional memory provided in accordance with an exemplary embodiment of the present disclosure;

[0056] FIG5B is a schematic cross-sectional view taken along the C5 plane in FIG5A ;

[0057] FIG6A is a perspective schematic diagram of a three-dimensional memory provided in accordance with an exemplary embodiment of the present disclosure;

[0058] FIG6B is a schematic cross-sectional view taken along plane C6 in FIG6A ;

[0059] FIG7A is a perspective schematic diagram of a three-dimensional memory provided in accordance with an exemplary embodiment of the present disclosure;

[0060] FIG7B is a schematic cross-sectional view taken along the C7 / C8 plane in FIG7A ;

[0061] 8A is a perspective schematic diagram of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present disclosure after forming a stacked structure including a sacrificial layer and a semiconductor layer;

[0062] FIG8B is a vertical cross-sectional view of the structure shown in FIG8A taken along the cross-sectional line BB′;

[0063] FIG9A is a perspective schematic diagram of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present disclosure after forming a stacked structure having a preset pattern;

[0064] FIG9B is a horizontal cross-sectional view of the structure shown in FIG9A taken along the cross-sectional line AA′;

[0065] FIG10A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0066] FIG10B is a horizontal cross-sectional view of the structure shown in FIG10A taken along the cross-sectional line AA′;

[0067] FIG11A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0068] FIG11B is a horizontal cross-sectional view of the structure shown in FIG11A taken along the cross-sectional line AA′;

[0069] FIG12A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0070] FIG12B is a schematic vertical cross-sectional view of the structure shown in FIG12A taken along the cross-sectional line BB′;

[0071] FIG13A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0072] FIG13B is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0073] FIG14A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0074] FIG14B is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0075] FIG14C is a perspective view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present disclosure;

[0076] FIG15A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0077] FIG15B is a perspective view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0078] FIG15C is a perspective view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present disclosure;

[0079] FIG16A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure;

[0080] FIG16B is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present disclosure; and

[0081] FIG16C is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present disclosure.

[0082] Explanation of the accompanying drawings: 1-stacked structure; 10-substrate; 20-sacrificial layer; 30-semiconductor layer; 31-first extension portion; 32-second extension portion; 40-hard mask layer; 50-first source / drain; 60-second source / drain; 61-first electrode; 62-dielectric layer; 63-second electrode; 64-conductive layer; 70-support portion; 80-bit line; 90-word line; 91-gate insulating layer; 92-channel region; 93-gate; 100-isolation region; 200-bit line preset region; 300-second source / drain preset region; 311-first sub-extension portion; 312-second sub-extension portion; 400-word line preset region; 500-first source / drain preset region; 600-capacitor preset region; 700-isolation portion.

[0083] Details

[0084] To make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0085] The embodiments herein can be implemented in a variety of different forms. A person skilled in the art can easily understand that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0086] The sizes and proportional relationships between the various film layers or components in the drawings of this disclosure can be used as a reference in actual processes and are embodiments with good technical effects, but are not limited to such. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing between them can be adjusted according to actual needs. The drawings described in this disclosure are merely schematic diagrams of the structures, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0087] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0088] In this specification, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0089] In the description of the present disclosure, ordinal numbers such as “first” and “second” are provided to avoid confusion among constituent elements, rather than to limit the quantity.

[0090] In this specification, "film" and "layer" can be interchanged. For example, "metal layer" can sometimes be replaced with "metal film".

[0091] In recent years, with the rise of 3D integrated circuits, stacking capacitors and transistors has become a common method for increasing integration. However, the inventors of this disclosure have discovered that because 3D memory devices often employ a gate-around or channel-around structure in their transistors, the manufacturing process is complex and integration is challenging.

[0092] Therefore, an exemplary embodiment of the present disclosure provides a three-dimensional memory, comprising multiple layers of memory cells stacked along a third direction, each layer of memory cells comprising a first column of memory cells extending along a second direction and a second column of memory cells extending along the second direction, the first column of memory cells and the second column of memory cells being adjacent and arranged along the first direction, the multiple memory cells in the first column of memory cells sharing a bit line extending along the second direction, and the multiple memory cells in the second column of memory cells sharing a bit line extending along the second direction; the memory cell comprising a transistor and a capacitor; the capacitor comprising a first electrode and a second electrode, the transistor being electrically connected to the first electrode; a word line extending along the third direction; each of the transistors having a channel region only on at least one side of the word line to which it is connected along the second direction, the first direction intersecting the second direction and both being perpendicular to the third direction.

[0093] In an exemplary embodiment, the transistor has channel regions only on two sides of the word line to which it is connected along the second direction.

[0094] In an exemplary embodiment, an isolation portion is further included, wherein a bit line shared by the first column of memory cells and a bit line shared by the second column of memory cells are separated by the isolation portion, and the first column of memory cells and the second column of memory cells are symmetrical with respect to the isolation portion in the first direction.

[0095] As used in this disclosure, the term "first direction" X is defined as a direction perpendicular to the direction in which the bit lines extend; the term "second direction" Y is defined as a direction parallel to the direction in which the bit lines extend; and the term "third direction" Z is defined as a direction perpendicular to the plane of the substrate, that is, a direction parallel to the direction in which the word lines extend. The plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be shown in Figures 1A to 7B, etc.

[0096] As used in this disclosure, the term "integrated structure" may refer to a microstructural separation between A and B, such as the absence of distinct interfaces such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integral. For example, A and B may be formed from the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0097] As shown in Figures 1A to 7B, a three-dimensional memory may include a multi-layer memory cell array stacked along a third direction. Each layer of the memory cell array includes a first column of memory cells extending along a second direction Y and a second column of memory cells extending along the second direction Y. The first column of memory cells and the second column of memory cells are adjacent and arranged along a first direction X. The plurality of memory cells in the first column of memory cells are connected to a bit line extending along the second direction Y, and the plurality of memory cells in the second column of memory cells are connected to another bit line extending along the second direction Y. Each memory cell may include a transistor and a capacitor. Each of the transistors stacked vertically in the third direction Z is connected to a word line 90 extending along the third direction Z.

[0098] Each channel region of the first column of memory cells or the second column of memory cells and the connected bit lines are an integrally arranged film layer.

[0099] Each channel region of the first column of memory cells or the second column of memory cells and the connected bit lines are different regions of the same film layer, the film layer is a single crystal silicon layer, and the bit line region of the film layer contains metal silicide.

[0100] In an exemplary embodiment, FIG1B shows an isolation portion 700 and two columns of memory cells arranged in a mirror-symmetrical pattern on either side of the isolation portion 700 along a first direction X. Each column of memory cells includes multiple transistors sharing a bit line 80 extending along a second direction Y. The second source / drain 60 of each transistor is connected to the bit line 80. The approximate boundary between the bit line 80 and the second source / drain 60 is schematically shown by the dashed line II-II' in FIG1B. Each transistor may also include a gate 93 and a first source / drain 50 and a second source / drain 60 located on either side of the word line 90 along the first direction X. Each transistor may also include a capacitor. Each capacitor may include a first electrode 61, a second electrode 63 surrounding the first electrode 61, and a dielectric layer 62 located between the first and second electrodes. The first electrode 61 is connected to the first source / drain 50. The approximate boundary between the first electrode 61 and the first source / drain 50 is schematically shown by the dashed line II-I' in FIG1B.

[0101] In an exemplary embodiment, a metal silicide is formed on the surface of the bit line 80 , thereby further reducing the contact resistance of the bit line 80 .

[0102] Figure 1B also shows that the bit line 80 shared by the first column of memory cells and the bit line 80 shared by the second column of memory cells are separated by an isolation portion 700. The first column of memory cells and the second column of memory cells are symmetrical with respect to the isolation portion in the first direction. By making the overall device structure symmetrical, the present disclosure significantly increases the density of transistors per unit area and reduces manufacturing costs.

[0103] 1B also shows that a conductive layer 64 is provided in the space enclosed by the second electrode 63 of the capacitor, and a support portion 70 is provided on a side of the capacitor away from the transistor, and the conductive layer 64 is connected to the support portion 70. The support portion 70 can be used to support the capacitor.

[0104] In an exemplary embodiment, multiple second electrodes 63 are electrically connected through the conductive layer 64, that is, there is a conductive layer 64 between two adjacent second electrodes 63 in the multiple second electrodes 63 in the third direction Z and between two adjacent second electrodes 63 in the multiple second electrodes 63 in the second direction Y and they are electrically connected through the conductive layer 64.

[0105] In an exemplary embodiment, the second electrode and the conductive layer are made of different materials.

[0106] With particular reference to FIG. 1B , FIG. 1B clearly shows that the channel region 92 of each transistor is located only on at least one side of the corresponding word line 90 along the second direction Y. The present disclosure forms a channel region only on at least one side of the word line in the second direction Y, and each transistor does not have a channel region on both sides of the word line 90 to which it is connected along the first direction X. This reduces the difficulty of the etching process and subsequent deposition and filling processes, thereby widening the process window.

[0107] In an exemplary embodiment, the channel region 92 may include a single crystal silicon material.

[0108] FIG1B also shows that each transistor may further include a gate 93 . The gate 93 is a portion of the corresponding word line 90 . A gate insulating layer 91 may be provided between the gate 93 and the channel region 92 .

[0109] 6B , it is clearly shown that in the third direction Z, the channel regions 92 are spaced apart and the gate insulating layer 91 is continuously disposed. The present disclosure improves device stability by arranging the channel regions spaced apart in the direction of word line extension, thereby avoiding the introduction of parasitic MOS and eliminating the need for additional processes to remove the parasitic MOS.

[0110] As used in the present disclosure, the term "spaced arrangement" or "disconnected arrangement" may be physically separated.

[0111] In an exemplary embodiment, as shown in FIG. 13A , the dielectric layers 62 of the capacitors of the memory cells may be connected to each other into an integrated structure.

[0112] In an exemplary embodiment, as shown in FIG. 13B , the second electrodes 63 of the capacitors of the memory cells may be connected to each other in an integrated structure.

[0113] In an exemplary embodiment, the first source / drain 50 , the second source / drain 60 , the first electrode 61 , and the bit line 80 may all be formed of the same material.

[0114] In an exemplary embodiment, the first source / drain 50 and the second source / drain 60 may be formed by doping ions into a single crystal silicon semiconductor material, for example, an N-type Si conductor structure formed by doping Si with ions.

[0115] The first source / drain, the second source / drain, the first electrode and the bit line are different regions of the same film layer, the same film layer is a single crystal silicon layer, and the regions corresponding to the first source / drain and the second source / drain of the film layer are N-type doped regions.

[0116] In an exemplary embodiment, the first source / drain 50 and the second source / drain 60 of the same transistor may be located in the same conductive layer.

[0117] Although the first and second source / drain references are used herein to designate two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as the "first" and / or "second" source / drain regions have a unique meaning. It is intended that only one of the source / drain regions be connected to the bit line and the other be connected to the first electrode of the capacitor.

[0118] In an exemplary embodiment, the first source / drain region 50 and the second source / drain region 60 are independent of each other. In an exemplary embodiment, one of the first source / drain region 50 and the second source / drain region 60 is the source of the transistor, and the other is the drain of the transistor.

[0119] The following further illustrates the technical solution of the present disclosure through the fabrication process of a three-dimensional memory device according to an exemplary embodiment of the present disclosure. The "patterning process" referred to in this exemplary embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this exemplary embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film of a certain material deposited on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire fabrication process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning or photolithography process contains at least one "pattern."

[0120] In an exemplary embodiment, a manufacturing process of a three-dimensional memory, such as a three-dimensional DRAM, may include:

[0121] S100: forming a laminated structure.

[0122] An exemplary step may include providing a substrate 10 , and alternately depositing sacrificial layer films and semiconductor material films on the substrate 10 along a third direction Z to form a stacked structure 1 including a sacrificial layer 20 and a semiconductor layer 30 , as shown in FIG. 8A and FIG. 8B .

[0123] In an exemplary embodiment, an epitaxial growth method may be used to grow a SiGe sacrificial layer thin film and a single crystal silicon semiconductor material thin film.

[0124] In an exemplary embodiment, substrate 10 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In an exemplary embodiment, substrate 10 may be a single crystal silicon substrate.

[0125] In an exemplary embodiment, the sacrificial layer 20 may be made of SiGe, such as a SiGe single crystal material.

[0126] In an exemplary embodiment, the semiconductor layer 30 may be made of a semiconductor material such as silicon, including single crystal silicon.

[0127] In the present disclosure, a single crystal stacked structure may be formed by epitaxially growing a plurality of SiGe single crystal layers and a plurality of single crystal silicon layers on a single crystal silicon substrate.

[0128] 8B may include three sacrificial layers 20 and three semiconductor layers 30. In other exemplary embodiments, the stacked structure may further include more or fewer sacrificial layers 20 and semiconductor layers 30 that are alternately arranged.

[0129] In addition, a hard mask layer 40 may be provided on top of the stacked structure 1 for use in subsequent patterning processes and will be removed after patterning.

[0130] In an exemplary embodiment, the hard mask layer 40 may be formed of an oxide such as silicon dioxide.

[0131] S200: Patterning the stacked structure.

[0132] An exemplary step may include first transferring a preset pattern to a photoresist layer through a photolithography process using a first mask having a preset pattern (also called a first photomask, not shown); then, etching (which may include anisotropic etching and isotropic etching) each sacrificial layer and semiconductor layer of the stacked structure based on the preset pattern, as shown in Figures 9A and 9B.

[0133] 9A and 9B , the predetermined pattern may include four rows of first extensions 31 extending in the first direction X and spaced apart in the second direction Y, and one column of second extensions 32 extending in the second direction Y. The second extensions 32 are perpendicular to the first extensions 31. Both ends of the second extensions 32 in the second direction Y extend beyond the first extensions 31 in the second direction Y. The second extensions 32 divide each row of first extensions 31 into a first sub-extension 311 and a second sub-extension 312. The two sub-extensions 311 and 312 are symmetrical with respect to the second extension 32 in the first direction X.

[0134] 9A and 9B , the second extension portion 32 may include an isolation region 100 and two bit line preset regions 200 on both sides of the isolation region 100 along the first direction X. Within the region of the first sub-extension 311 , on a side of the bit line preset region 200 away from the isolation region 100 , a second source / drain preset region 300 , a word line preset region 400 , a first source / drain preset region 500 , and a capacitor preset region 600 may be sequentially included along the first direction X.

[0135] Similarly, within the area of ​​the second sub-extension 312, on the side of the bit line preset region 200 away from the isolation region 100, along the direction away from the first direction X, a second source / drain preset region 300, a word line preset region 400, a first source / drain preset region 500 and a capacitor preset region 600 can be sequentially included.

[0136] 9A and 9B , a first trench T1 penetrating the stacked structure 1 is formed between two adjacent sub-extensions 311 or 312 in the second direction Y. FIG. 9A and 9B show that the predetermined pattern includes a total of 10 first trenches T1 , and each first trench T1 has the same dimensions in the first direction X and the second direction Y.

[0137] In an exemplary embodiment, the preset pattern shown in FIG. 9A and FIG. 9B is merely an example, however, the preset pattern may also be other shapes, for example, the dimensions of each first trench T1 in the first direction X and the second direction Y are not the same; or more rows of first extensions are included.

[0138] S300: forming a source and a drain.

[0139] Exemplary steps may include performing high-concentration doping in the first source / drain preset region 500 and the second source / drain preset region 300 through ion implantation, plasma implantation, diffusion annealing, etc., thereby forming a conductive region from the semiconductor region, that is, forming the first source / drain 50 and the second source / drain 60.

[0140] S400: forming a support portion.

[0141] An exemplary step may include filling all first trenches T1 formed in the aforementioned steps with insulating material to form an isolation layer 21; photolithography and etching to remove the stacked structure on one side of the capacitor preset area 600 away from the first source / drain preset area 500 to form two support portion preset areas; and depositing insulating material in the two support portion preset areas to form two support portions 70, as shown in Figures 10A and 10B.

[0142] In an exemplary embodiment, the insulating material used for the isolation layer 21 may be the same material as that used for the sacrificial layer 20, such as SiGe. However, in other exemplary embodiments, the material used for the isolation layer 21 may be other insulating materials.

[0143] In an exemplary embodiment, the insulating material for the support portion 70 may be SiN, and the deposition method may be low-temperature atomic layer deposition.

[0144] S500: forming a capacitor preset area.

[0145] An exemplary step may include removing only the isolation layer 21 within the capacitor preset region 600 through photolithography and dry vertical etching, forming a plurality of second trenches T2 that penetrate the stacked structure 1 within the capacitor preset region 600 and terminate at a side of the substrate 10 close to the sacrificial layer 20, exposing the capacitor preset region 600 at each semiconductor layer 30, as shown in Figures 11A and 11B.

[0146] S600 : exposing the first electrode 61 of the capacitor to be formed.

[0147] An exemplary step may include removing the sacrificial layer 20 between adjacent semiconductor layers 30 in the third direction Z by lateral etching with the help of the second trench T2 in the capacitor preset area 600, so that the side walls of the semiconductor layer 30 of each layer in the capacitor preset area 600 are exposed. Due to the supporting effect of the support portion 70, the semiconductor layer 30 will not collapse; at the same time, the side surface of the isolation layer 21 in the transistor area opposite to the support portion 70 is also exposed, as shown in Figures 12A and 12B.

[0148] S700: forming a capacitor.

[0149] Exemplary steps may include doping the exposed semiconductor layer 30 (single crystal silicon) in the capacitor preset area 600 to form a conductive layer, that is, forming the first electrode 61 of the capacitor; depositing a dielectric film around the exposed first electrode 61 to completely cover the first electrode 61 and also depositing a dielectric film completely covering the side of the isolation layer 21 in the transistor area opposite to the support portion 70 to form a dielectric layer 62; depositing a conductive film completely covering the dielectric layer 62 on the dielectric layer 62 to form a second electrode 63. The first electrode 61, the second electrode 63 covering the first electrode 61, and the dielectric layer 62 that acts as an isolation between them constitute a capacitor, as shown in Figures 13A and 13B.

[0150] In an exemplary embodiment, the dielectric film and the conductive film may be deposited by atomic layer deposition (ALD).

[0151] In an exemplary embodiment, dielectric layer 62 may be a high-k dielectric layer, i.e., a dielectric layer with a dielectric constant K ≥ 3.9. Dielectric layer 62 may be made of one of the following materials: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide. In an exemplary embodiment, the dielectric film may be doped with Si or N to improve the dielectric's high-temperature resistance.

[0152] In an exemplary embodiment, the conductive film may be made of a material including, but not limited to, at least one of the following: polysilicon, tungsten, and titanium nitride.

[0153] S800: An exemplary step may include filling the space between the second electrodes of the capacitor in the capacitor preset area 600 with a conductive material using a furnace process and flattening the space so that the space surrounded by the second electrodes 63 of the capacitor has a conductive layer 64; the conductive layer connects the second electrodes together. A hard mask layer is provided on the capacitor preset area 600; dry etching is used to laterally and vertically etch away the sacrificial layer 20 in other areas outside the capacitor preset area 600 to form multiple grooves, so that each semiconductor layer 30 in the non-capacitor preset area is exposed and suspended. The suspended semiconductor layer 30 will not collapse due to the support of the capacitor preset area; atomic layer deposition is used to deposit a layer of insulating material (such as SiO2) in the formed grooves and then spin coating (SOD) is used to deposit insulating material to cover and fill the formed multiple grooves, that is, the sacrificial layer material in the previous stacked structure formation step is replaced with insulating material in the non-capacitor preset area to play an isolation and insulation role, as shown in Figures 14A, 14B and 14C.

[0154] S900: forming a bit line and an isolation portion.

[0155] An exemplary step may include removing the material in the isolation region 100 using a dry etching method under the protection of a hard mask layer, forming a third trench T3 in the isolation region 100 that penetrates the stacked structure and terminates at one side of the upper surface of the substrate 10, wherein the third trench T3 can be used to separate two columns of memory cells; with the help of the third trench T3, doping each semiconductor layer in the bit line preset area 200 by ion implantation to form a plurality of bit lines 80; filling the third trench T3 with an isolation insulating material to form an isolation portion 700, as shown in Figures 15A, 15B and 15C.

[0156] In an exemplary embodiment, the isolation insulating material may be SiN.

[0157] In an exemplary embodiment, the sidewalls of each semiconductor layer exposed by the third trench T3 may be doped using a self-aligned plasma doping process to reduce the bit line resistance.

[0158] In an exemplary embodiment, a layer of metal silicide may be formed on the surface of each bit line 80 by forming silicide, thereby further reducing the contact resistance of the bit line 80 .

[0159] The manufacturing method for forming a bit line according to the embodiment of the present disclosure greatly reduces the process difficulty of manufacturing the bit line.

[0160] S1000: forming a channel region.

[0161] An exemplary step may include forming a word line through hole K penetrating the stacked structure in the word line preset area 400 by dry etching with the help of a hard mask layer; depositing an insulating layer film and a conductive film in sequence around the inner wall of each word line through hole K to form a gate insulating layer 91 and a word line 90 (without the step of depositing a semiconductor material film); forming a channel region 92 in the semiconductor layer 30 in the area on both sides of the word line 90 along the second direction Y, as shown in Figures 16A, 16B and 16C.

[0162] In an exemplary embodiment, the orthographic projection of the word line through hole K on a plane parallel to the substrate 10 may be rectangular, square, circular, etc.

[0163] In an exemplary embodiment, an orthographic projection of the word line through hole K on a plane parallel to the substrate 10 is located within an orthographic projection of the semiconductor layer 30 on a plane parallel to the substrate 10 .

[0164] In an exemplary embodiment, the gate insulating layer 91 may be a high-k dielectric layer, i.e., a dielectric layer with a K value of ≥ 3.9. The high-k dielectric layer may serve as a gate oxide. The gate insulating layer 91 may be made of one or more of silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0165] In an exemplary embodiment, the word line 90 may be made of metal tungsten W or a composite metal of TiN / W, or may be made of ITO.

[0166] When manufacturing transistors, the method of the embodiment of the present disclosure adopts a method for manufacturing channels on both sides of the gate, which only requires vertical etching and filling. This method greatly reduces the difficulty of the etching process and the subsequent filling process, and widens the process window.

[0167] The exemplary embodiments of the present disclosure further provide a method for manufacturing a three-dimensional memory, which may include the following steps:

[0168] S2000: alternately forming sacrificial layers and semiconductor layers along a third direction to form a stacked structure;

[0169] S2100: forming a plurality of first extension portions extending along a first direction and spaced apart along a second direction and a second extension portion extending along the second direction in the semiconductor layer, wherein each of the first extension portions is divided into a first sub-extension portion and a second sub-extension portion by the second extension portion in the first direction, and the first direction intersects the second direction and is perpendicular to the third direction;

[0170] S2200: providing an isolation region and bit line preset regions located on both sides of the isolation region in the second extension portion;

[0171] S2300: in the first sub-extension, sequentially disposing a second source / drain preset region, a word line preset region, a first source / drain preset region, and a capacitor preset region along a first direction on a side of the bit line preset region away from the isolation region;

[0172] S2400: forming a support portion in the capacitor preset region on a side away from the first source / drain preset region;

[0173] S2500: removing the sacrificial layer in the preset area of ​​the capacitor to expose the semiconductor layer in the preset area of ​​the capacitor, thereby forming a first electrode of the capacitor;

[0174] S2600: forming a bit line in the bit line preset area;

[0175] S2700: forming a word line through hole penetrating the stacked structure in the word line preset area;

[0176] S2800: sequentially depositing an insulating film and a conductive film around the inner wall of the word line through hole to form a gate insulating layer and a word line;

[0177] S2900: forming a channel region in a region of the semiconductor layer located on at least one side of the word line along the second direction.

[0178] In an exemplary embodiment, the manufacturing method further comprises:

[0179] Depositing a dielectric film around the exposed first electrode to completely cover the first electrode to form a dielectric layer;

[0180] A conductive film is deposited around the dielectric layer and completely covers the dielectric layer to form a second electrode.

[0181] In an exemplary embodiment, forming a bit line includes:

[0182] removing the stacked structure in the isolation region to form a trench penetrating the stacked structure;

[0183] The semiconductor layer in the bit line preset area is doped with the formed trench to form the bit line.

[0184] The exemplary embodiments of the present disclosure further provide an electronic device, including the three-dimensional memory provided by the exemplary embodiments of the present disclosure, such as a three-dimensional DRAM.

[0185] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0186] Although the embodiments disclosed in the present disclosure are as described above, the above contents are merely examples or implementations adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A three-dimensional memory, comprising: A multi-layer memory cell array stacked along a third direction, each layer of the memory cell array comprising a first column of memory cells and a second column of memory cells, the first column of memory cells and the second column of memory cells being adjacent and arranged along the first direction, the first column of memory cells being connected to a bit line extending along the second direction, and the second column of memory cells being connected to another bit line extending along the second direction; The storage unit includes a transistor and a capacitor; the capacitor includes a first electrode and a second electrode, and the transistor is electrically connected to the first electrode; The word line extends along the third direction; The transistor has a channel region only on at least one side of the word line connected thereto along the second direction; The first direction intersects the second direction and is perpendicular to the third direction; Each channel region of the first column of memory cells or the second column of memory cells and the connected bit lines are different regions of the same film layer, the film layer is a single crystal silicon layer, and the bit line region of the film layer contains metal silicide.

2. The three-dimensional memory according to claim 1, wherein: The transistor has a channel region only on two sides of the word line connected thereto along the second direction.

3. The three-dimensional memory according to claim 1 further comprises an isolation portion, wherein a bit line connected to the first column of memory cells and another bit line connected to the second column of memory cells are separated by the isolation portion, and the first column of memory cells and the second column of memory cells are symmetrically distributed relative to the isolation portion in a first direction.

4. The three-dimensional memory according to claim 1, wherein: The transistor further includes a gate, which is a part of the corresponding word line, and a gate insulating layer is arranged between the gate and the channel region; the transistors stacked in the third direction share a word line.

5. The three-dimensional memory according to claim 4, wherein: In the third direction, the channel regions of the memory cells stacked in the third direction are spaced apart from each other.

6. The three-dimensional memory according to claim 4, wherein: The transistor further includes a first source / drain and a second source / drain located at both sides of the word line in the first direction.

7. The three-dimensional memory according to claim 6, wherein: The first source / drain, the second source / drain, the first electrode and the bit line are different regions of the same film layer, the same film layer is a single crystal silicon layer, and the regions corresponding to the first source / drain and the second source / drain of the film layer are N-type doped regions.

8. The three-dimensional memory according to claim 1, wherein: The second electrode surrounds the first electrode.

9. The three-dimensional memory according to claim 8, wherein: The capacitor includes a dielectric layer between the first electrode and the second electrode, and the dielectric layers of the capacitors of a plurality of storage units are interconnected to form an integrated structure.

10. The three-dimensional memory according to claim 9, wherein: The second electrodes of the capacitors of the plurality of storage units are connected to each other to form an integrated structure.

11. The three-dimensional memory according to claim 1, wherein: A conductive layer is provided between the plurality of second electrodes, a support portion is provided on a side of the capacitor away from the transistor, and the conductive layer is connected to the support portion.

12. The three-dimensional memory according to claim 11, wherein: The plurality of second electrodes are electrically connected via the conductive layer, and the second electrodes and the conductive layer are made of different materials.

13. A method for manufacturing a three-dimensional memory, comprising the following steps: Alternatingly forming sacrificial layers and semiconductor layers along a third direction, wherein the sacrificial layers are silicon germanium layers grown by epitaxial growth, and the semiconductor layers are single crystal silicon layers grown by epitaxial growth, to form a stacked structure; A plurality of first extension portions extending along a first direction and arranged at intervals along a second direction and a second extension portion extending along the second direction are formed in the semiconductor layer, each of the first extension portions is divided into a first sub-extension portion and a second sub-extension portion by the second extension portion in the first direction, and the first direction intersects the second direction and is perpendicular to the third direction; An isolation region and bit line preset regions located on both sides of the isolation region are provided in the second extension portion; In the first sub-extension portion, a second source / drain preset region, a word line preset region, a first source / drain preset region and a capacitor preset region are sequentially arranged along a first direction on a side of the bit line preset region away from the isolation region; Forming a support portion on a side of the capacitor preset region away from the first source / drain preset region; Removing the sacrificial layer in the preset area of ​​the capacitor to expose the semiconductor layer in the preset area of ​​the capacitor to form a first electrode of the capacitor; forming a bit line including metal silicide in the bit line preset region; In the word line preset area, a word line through hole penetrating the stacked structure is formed; An insulating layer film and a conductive film are sequentially deposited around the inner peripheral wall of the word line through hole to form a gate insulating layer and a word line.

14. The manufacturing method according to claim 13, wherein: The manufacturing method further comprises: Depositing a dielectric film around the exposed first electrode and completely covering the first electrode to form a dielectric layer; A conductive film is deposited around the dielectric layer and completely covers the dielectric layer to form a second electrode.

15. The manufacturing method according to claim 13, wherein: Forming the bit line includes: Removing the stacked structure in the isolation region to form a groove penetrating the stacked structure; The semiconductor layer in the predetermined bit line region is doped by means of the formed trench to form the bit line.

16. An electronic device comprising the three-dimensional memory according to any one of claims 1 to 12.

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