Interface communication method and apparatus, and server

Abstract

The present application provides an interface communication method and apparatus, and a server. A server host system comprises a plurality of hardware partitions, and a BMC comprises a plurality of kernel partitions, the kernel partitions being used for managing the hardware partitions corresponding thereto. The method comprises: a kernel partition generates a control instruction for controlling a hardware partition; converting the control instruction into an interface signal conforming to an interface protocol of a first interface of the hardware partition; and sending the interface signal to the first interface by means of a second interface of the kernel partition, the interface type of the first interface being different from that of the second interface. The present application solves the problem of complex BMC chip design in a host system hardware partition scenario.

Description

Interface communication method, device and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on August 28, 2023, with application number 202311090170.9 and application name “Interface Communication Method, Device and Server”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and in particular, to an interface communication method, device, and server. Background Art

[0004] With the rapid development of the semiconductor industry and integrated circuit technology in recent years, processors have become essential computing units in fields such as cloud computing, artificial intelligence, and big data. To enable hardware computing resource sharing and improve the utilization of multi-core processors, virtualization technology is commonly used. This involves creating multiple virtual machines (VMs) based on the processor hardware platform, each running an independent operating system. However, VM-based operating systems generally fail to meet the real-time requirements of services due to the added overhead of VM management. Therefore, operating systems are often run directly on dedicated physical machines. This "bare metal" processor usage significantly reduces service processing latency. In the server industry, hardware partitioning of computing resources, such as the CPU (Central Processing Unit) of a general-purpose host system, has emerged. A single server is partitioned into two or more physical host systems, each independently hosting and providing services. This presents difficulties and challenges in the design of the server's Baseboard Management Controller (BMC), particularly regarding the design of the BMC's Platform Environment Control Interface (PECI) link. To ensure long-term stable and efficient server operation, server systems must possess powerful fault monitoring and management capabilities. Since traditional servers are usually only equipped with one BMC management unit, that is, there is only one PECI controller interface, in the server hardware partition system scenario, there will be a problem that each hardware partition system cannot use the PECI interface independently, which in turn affects the independence of the fault management functions of different partition systems on the same server platform.

[0005] The existing solution involves upgrading the BMC's CPU architecture, which involves redesigning the PECI interface module for the host system's multiple hardware partitioning system. However, this solution presents two challenges: First, upgrading the BMC CPU architecture requires hardware partitioning within the BMC, significantly increasing design complexity and inevitably leading to a significant increase in chip costs. Second, upgrading the BMC CPU architecture consumes significant time in chip design, tape-out, manufacturing, and debugging, severely impacting the application and promotion of hardware partitioning technology in the host system and hindering its rapid adoption.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide an interface communication method, apparatus, and server to at least solve the problem of complex BMC chip design in a host system hardware partitioning scenario in the related art.

[0008] According to one embodiment of the present application, an interface communication method is provided, wherein the server host system includes a hardware partition, the baseboard management controller includes a kernel partition, and the kernel partition is used to manage the hardware partition. The method includes: generating a control instruction to control the hardware partition; converting the control instruction into an interface signal that complies with a predetermined interface protocol, wherein the predetermined interface protocol is an interface protocol of a first interface of the hardware partition; and sending the interface signal to the first interface through the second interface, wherein the interface types of the first interface and the second interface are different.

[0009] In an exemplary embodiment, converting a control instruction into an interface signal that complies with a predetermined interface protocol includes: determining multiple logic bit information corresponding to the control instruction according to the predetermined interface protocol; and generating an interface signal based on the multiple logic bit information, a first timer, and a second timer.

[0010] In an exemplary embodiment, an interface signal is generated based on multiple logical bit information, a first timer and a second timer, including: determining the timing duration of the first timer and the second timer based on the multiple logical bit information; and generating an interface signal through the second interface based on the timing duration.

[0011] In an exemplary embodiment, the timing durations of a first timer and a second timer are determined based on multiple logical bit information, including: obtaining a first duration and a second duration corresponding to each logical bit information, the first duration representing the duration during which the logical bit information is at a high level, the second duration representing the total duration of the logical bit information, and different logical bit information corresponding to different first durations; determining the timing duration of the first timer to be the first duration, and determining the timing duration of the second timer to be the second duration.

[0012] In an exemplary embodiment, an interface signal is generated through the second interface according to the timing duration, including: according to the first duration of the first timer and the second duration of the second timer, and in accordance with the order of multiple logical bit information, a sub-interface signal corresponding to each logical bit information is generated in sequence through the second interface to obtain an interface signal.

[0013] In an exemplary embodiment, according to the first duration of the first timer and the second duration of the second timer, and in accordance with the sorting of multiple logical bit information, a sub-interface signal corresponding to each logical bit information is generated in sequence through the second interface to obtain an interface signal, including: a control step of controlling the first timer and the second timer to start timing, and outputting the first signal through the second interface before the timing duration of the first timer reaches the first duration; an output step of outputting the second signal through the second interface after the timing duration of the first timer reaches the first duration and before the timing duration of the second timer reaches the second duration, to obtain a sub-interface signal composed of the first signal and the second signal; a counting step of performing a timing count when the timing duration of the second timer reaches the second duration; a determination step of determining whether the timing count value is less than the total number of logical bit information, and when the timing count value is less than the total number of logical bit information, performing the control step, the output step and the counting step in sequence according to the sorting until the timing count value is not less than the total number of logical bit information, to obtain an interface signal including multiple sub-interface signals.

[0014] In an exemplary embodiment, the method further includes: before the controlling step, initializing the output of the second interface to a low level state.

[0015] In an exemplary embodiment, the control step includes: controlling the first timer and the second timer to start timing; setting the output of the second interface to a high level state, and outputting a first signal in a high level state through the second interface; when the timing duration of the first timer reaches a first duration, stopping the output of the first signal and setting the output of the second interface to a low level.

[0016] In an exemplary embodiment, when the timing duration of the first timer reaches a first duration, stopping the output of the first signal includes: when the timing duration of the first timer reaches the first duration, triggering a first interrupt to stop the output of the first signal.

[0017] In an exemplary embodiment, the output step includes: when the timing duration of the first timer reaches a first duration, setting the output of the second interface to a low level state, and outputting a second signal in a low level state through the second interface; when the timing duration of the second timer reaches a second duration, stopping the output of the second signal, and setting the output of the second interface to a high level to obtain a sub-interface signal.

[0018] In an exemplary embodiment, when the timing duration of the second timer reaches a second duration, stopping the output of the second signal includes: when the timing duration of the second timer reaches the second duration, triggering a second interrupt to stop the output of the second signal.

[0019] In an exemplary embodiment, the control instruction includes at least one of the following: a first instruction for determining whether a hardware partition exists; a second instruction for obtaining a sensor temperature of the hardware partition; and a third instruction for obtaining register data of the hardware partition.

[0020] In an exemplary embodiment, the data structure of the control instruction includes an address rate field, a target address field, a message rate field, a write length field, and a read length field, wherein the address rate field represents the transmission rate of the address data, the target address field represents the address data of the hardware partition, and the message rate field represents the transmission rate of the message data.

[0021] In an exemplary embodiment, after sending the interface signal to the first interface through the second interface, the method further includes: receiving a response instruction generated by the hardware partition in response to the control instruction, the response instruction including the control instruction and a frame check field.

[0022] In an exemplary embodiment, the first interface includes a PECI interface, and the second interface includes a GPIO (General-Purpose Input / Output) interface.

[0023] In an exemplary embodiment, there are multiple hardware partitions and multiple kernel partitions, one of the multiple kernel partitions includes a third interface, and the other kernel partitions each include a second interface, each hardware partition includes a first interface, and the third interface has the same interface type as the first interface. The method also includes: sending a control instruction to the corresponding first interface through the third interface.

[0024] According to another embodiment of the present application, an interface communication device is provided, wherein the server host system includes a hardware partition, the baseboard management controller includes a kernel partition, the kernel partition is used to manage the hardware partition, and the device includes: a generation unit, configured to generate control instructions for controlling the hardware partition; a conversion unit, configured to convert the control instructions into an interface signal that complies with a predetermined interface protocol, wherein the predetermined interface protocol is an interface protocol of a first interface of the hardware partition; and a first sending unit, configured to send the interface signal to the first interface through the second interface, and the interface types of the first interface and the second interface are different.

[0025] According to another embodiment of the present application, a non-volatile readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0026] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0027] According to another embodiment of the present application, a server is also provided, including: a host system, including multiple hardware partitions, the hardware partitions including a first interface; a BMC, including multiple kernel partitions, the kernel partitions corresponding one-to-one to the hardware partitions, at least some of the kernel partitions including a second interface, the first interface and the second interface having different interface types, wherein the kernel partition is used to generate control instructions for controlling the hardware partitions; converting the control instructions into interface signals that comply with a predetermined interface protocol, wherein the predetermined interface protocol is the interface protocol of the first interface of the hardware partition; and sending the interface signal to the first interface through the second interface.

[0028] In an exemplary embodiment, the core partition is further configured to determine a plurality of logic bit information corresponding to the control instruction according to a predetermined interface protocol; and generate an interface signal according to the plurality of logic bit information, the first timer, and the second timer.

[0029] In an exemplary embodiment, the core partition is further configured to determine the timing durations of the first timer and the second timer according to a plurality of logic bit information; and generate an interface signal through the second interface according to the timing durations.

[0030] In an exemplary embodiment, the kernel partition is also used to obtain a first duration and a second duration corresponding to each logical bit information, where the first duration represents the duration during which the logical bit information is at a high level, and the second duration represents the total duration of the logical bit information. Different logical bit information corresponds to different first durations; the timing duration of the first timer is determined to be the first duration, and the timing duration of the second timer is determined to be the second duration.

[0031] In an exemplary embodiment, the kernel partition is also used to generate a sub-interface signal corresponding to each logical bit information in sequence through the second interface according to the first duration of the first timer and the second duration of the second timer, in accordance with the order of multiple logical bit information, to obtain an interface signal.

[0032] In an exemplary embodiment, one of the multiple kernel partitions includes a third interface, the third interface is of the same interface type as the first interface, all kernel partitions except the one including the third interface include a second interface, and the kernel partition including the third interface is used to send control instructions to the corresponding first interface through the third interface.

[0033] Through the present application, there is no need to implement the hardware logic design of the PECI controller on the BMC chip in advance. The kernel partition only needs to simulate the interface protocol of the first interface through the second interface to generate the interface signal on the BMC chip, thereby achieving the technical effect of simulating the generation of hardware interface signals by software, and thus achieving the purpose of not requiring the chip itself to have the hardware logic design of the relevant hardware interface signals. It can not only reduce the design difficulty of the BMC chip, reduce the design cost and design cycle of the BMC chip, but also achieve the effect of a kernel partition of the BMC independently managing a hardware partition in the host system, and realize the expansion of the communication link between the BMC and the host system, so that the purpose of one BMC chip independently controlling multiple hardware partitions of the host system can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic diagram of a computer terminal according to an embodiment of the present application;

[0035] FIG2 is a flow chart of an interface communication method according to an embodiment of the present application;

[0036] FIG3 is a waveform diagram corresponding to a logic bit according to an embodiment of the present application;

[0037] FIG4 is a schematic diagram of a message transmission format of a response instruction according to an embodiment of the present application;

[0038] FIG5 is a flow chart of generating interface information according to an embodiment of the present application;

[0039] FIG6 is a structural block diagram of an interface communication device according to an embodiment of the present application;

[0040] FIG7 is a schematic diagram of the structure of a server according to an embodiment of the present application.

[0041] The above drawings include the following reference numerals:

[0042] 02. Processor; 04. Memory; 06. Transmission device; 08. Input / output device; 100. Host system; 101. Hardware partition; 102. First interface; 200. BMC; 201. Kernel partition; 202. Second interface; 203. Third interface. DETAILED DESCRIPTION

[0043] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0044] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0045] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking operation on a mobile terminal as an example, FIG1 is a hardware structure block diagram of a mobile terminal of an interface communication method in an embodiment of the present application. As shown in FIG1 , the mobile terminal may include one or more (only one is shown in FIG1 ) processors 02 (the processor 02 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 04 for storing data, wherein the mobile terminal may also include a transmission device 06 and an input and output device 08 for communication functions. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0046] The memory 04 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the interface communication method in the embodiment of the present application. The processor 02 executes various functional applications and data processing by running the computer program stored in the memory 04, that is, implementing the above-mentioned method. The memory 04 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 04 may further include a memory remotely located relative to the processor 02, and these remote memories can be connected to the mobile terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0047] Transmission device 06 is used to receive or transmit data via a network. Optional examples of the aforementioned network may include a wireless network provided by the mobile terminal's communications provider. In one embodiment, transmission device 06 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, transmission device 06 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0048] In this embodiment, an interface communication method is provided. The server host system includes a hardware partition, and the baseboard management controller (BMC) includes a kernel partition. The kernel partition is used to manage the hardware partition. The method is applied to the kernel partition. FIG2 is a flow chart of the interface communication method according to an embodiment of the present application. As shown in FIG2 , the process includes the following steps:

[0049] Step S102, generating a control instruction for controlling the hardware partition;

[0050] In some embodiments, the control instruction includes at least one of the following: a first instruction for determining whether the hardware partition exists; a second instruction for obtaining the sensor temperature of the hardware partition; and a third instruction for obtaining register data of the hardware partition.

[0051] Step S104, converting the control instruction into an interface signal that complies with a predetermined interface protocol, wherein the predetermined interface protocol is the interface protocol of the first interface of the hardware partition;

[0052] In some embodiments, the above interface signal may be a PECI signal, or an interface signal of another protocol type.

[0053] Step S106: Send the interface signal to the first interface via the second interface, where the first interface and the second interface are of different interface types.

[0054] In some embodiments, the first interface may include a PECI interface, and the second interface may include a CPIO interface. For example, the first interface is a PECI interface, and the second interface is a GPIO interface.

[0055] Through the above steps, in the scenario of hardware partitioning of the server host system, the kernel partition of the BMC first generates a control instruction for controlling the hardware partition; then the control instruction is converted to obtain an interface signal that complies with the interface protocol of the first interface of the hardware partition, and finally the obtained interface signal is sent to the first interface via the second interface to realize the control of a hardware partition of the host system. Compared with the related art, in the hardware partitioning scenario of the host system, the BMC chip itself needs to have the hardware logic design of the PECI controller, which leads to the problem of complex BMC chip design. The present application does not need to implement the hardware logic design of the PECI controller on the BMC chip in advance. It only needs the kernel partition to simulate the interface protocol of the first interface through the second interface to generate the interface signal on the BMC chip, thereby achieving the technical effect of simulating the generation of hardware interface signals using software, and thus achieving the purpose of not requiring the chip itself to have the hardware logic design of the relevant hardware interface signal. It can not only reduce the design difficulty of the BMC chip, reduce the design cost and design cycle of the BMC chip, but also realize the effect of a kernel partition of the BMC independently managing a hardware partition in the host system, and realize the expansion of the communication link between the BMC and the host system, so that a BMC chip can achieve the purpose of independently controlling multiple hardware partitions of the host system.

[0056] The execution subject of the above steps may be a terminal, a processor, etc., but is not limited thereto.

[0057] In one exemplary embodiment, converting the control instruction into an interface signal that complies with a predetermined interface protocol includes: determining, according to the predetermined interface protocol, a plurality of logical bit information corresponding to the control instruction; and generating the interface signal based on the plurality of logical bit information, a first timer, and a second timer. In this embodiment, generating the interface signal corresponding to the control instruction according to the predetermined interface protocol further achieves the technical effect of simulating the generation of the interface signal of the first interface using software.

[0058] In order to generate the interface signal corresponding to the above-mentioned control instruction based on multiple logical bit information, the first timer and the second timer, according to some optional embodiments of the present application, the above-mentioned interface signal is generated based on the multiple above-mentioned logical bit information, the first timer and the second timer, including: determining the timing duration of the above-mentioned first timer and the above-mentioned second timer based on the multiple above-mentioned logical bit information; generating the above-mentioned interface signal through the above-mentioned second interface based on the above-mentioned timing duration.

[0059] In some embodiments, the first timer and the second timer may be a timing program in the kernel partition or a register on the kernel partition, wherein the first timer and the second timer may at least provide a timing function.

[0060] In another exemplary embodiment, the timing durations of the first timer and the second timer are determined based on the plurality of the above-mentioned logic bit information, including: obtaining the first duration and the second duration corresponding to each of the above-mentioned logic bit information, the first duration representing the duration during which the above-mentioned logic bit information is at a high level, the second duration representing the total duration of the above-mentioned logic bit information, and the first durations corresponding to different above-mentioned logic bit information are different; determining the timing duration of the above-mentioned first timer to be the above-mentioned first duration, and determining the timing duration of the above-mentioned second timer to be the above-mentioned second duration. In this embodiment, by setting the timing duration of the first timer to the first duration and the timing duration of the second timer to the second duration, it is convenient to subsequently generate logic bit information corresponding to different logic bits according to the timing durations of the first timer and the second timer to obtain interface signals, further achieving the purpose of using the software system to generate interface signals without the need for hardware logic design of the interface signals for the BMC chip, thereby further reducing the design difficulty of the BM chip.

[0061] The first duration is shorter than the second duration.

[0062] In some embodiments, the control instruction is composed of at least one field, and the field is represented by a plurality of logical bits, each of which can be 0 or 1. Each logical bit is converted into the corresponding logical bit information, and the interface signal corresponding to the control instruction is obtained. The logical bit information can be represented by a combination of a high-level signal and a low-level signal. For example, for a logical bit 0, a high-level signal of a first preset duration and a low-level signal of a second preset duration can be used to represent it. For a logical bit 1, a high-level signal of a third preset duration and a low-level signal of a fourth preset duration can be used to represent it. The first preset duration and the third preset duration are different, and the second preset duration and the fourth preset duration are also different.

[0063] Generally speaking, under an interface protocol, the running duration corresponding to each of the multiple logical bit information is the same, that is, the second duration corresponding to each of the logical bit information is the same. Therefore, the sum of the first preset duration and the second preset duration is equal to the sum of the third preset duration and the fourth preset duration.

[0064] In actual application, there is a sequence between multiple logical bit information. In order to further ensure that the interface signal corresponding to the above-mentioned control instruction is obtained more accurately, in another optional embodiment of the present application, the above-mentioned interface signal is generated through the above-mentioned second interface according to the above-mentioned timing duration, including: according to the above-mentioned first duration of the above-mentioned first timer and the second duration of the above-mentioned second timer, according to the sorting of the multiple above-mentioned logical bit information, the sub-interface signal corresponding to each of the above-mentioned logical bit information is generated in sequence through the above-mentioned second interface to obtain the above-mentioned interface signal.

[0065] In some embodiments, the above-mentioned sub-interface signal is actually a waveform signal composed of a high-level signal and a low-level signal, and multiple waveform signals constitute the above-mentioned interface signal.

[0066] In some embodiments, as shown in Figure 3, when the above-mentioned logic bit is 0, the first duration corresponding to the first timer is t0, and when the above-mentioned logic bit is 1, the first duration corresponding to the above-mentioned first timer is t1, t0 is less than t1, and the above-mentioned second duration is tBIT. Generally, t0 is 0.6 to 0.8 times of tBIT, that is, t0 = 0.2 to 0.4tBIT, and t1 is 0.6 to 0.8 times of tBIT, that is, t1 = 0.6 to 0.8tBIT.

[0067] In an exemplary embodiment, according to the first duration of the first timer and the second duration of the second timer, and in accordance with the order of the plurality of logical bit information, sequentially generating, through the second interface, a sub-interface signal corresponding to each piece of the logical bit information, to obtain the interface signal includes:

[0068] A control step of controlling the first timer and the second timer to start timing, and outputting a first signal through the second interface before the timing duration of the first timer reaches the first duration;

[0069] In some embodiments, the first timer and the second timer each contain a decrement counter, the starting value of the first timer is set to the first duration, and the starting value of the second timer is set to the second duration. When the first timer and the second timer start timing, the decrement counter decrements from the starting value to 0, and when it reaches 0, the first timer and the second timer are interrupted, and the starting value of the first timer is reset to the first duration, and the starting value of the second timer is reset to the second duration, and then the decrement counter is restarted. Among them, an interrupt can be understood as a kind of identifier, so an interrupt can also be called an interrupt identifier.

[0070] In some embodiments, the first signal is a high level signal. In this application, in order to convert a logic bit 0 or 1 into a corresponding sub-interface signal, a high level first signal is generated through the second interface before the timing duration of the first timer reaches the first duration.

[0071] an output step of outputting a second signal through the second interface after the timing duration of the first timer reaches the first duration and before the timing duration of the second timer reaches the second duration, to obtain the sub-interface signal consisting of the first signal and the second signal;

[0072] In some embodiments, the second signal is a low-level signal. In the present application, in order to distinguish between logic bits 0 and 1, after the first timer reaches the first time, a low-level second signal is generated through the second interface until the second timer reaches the second time, thereby obtaining sub-interface signals with different waveforms, wherein the waveform signals corresponding to logic bits 0 and 1 have different duty cycles.

[0073] a counting step, executing a timer count when the timing duration of the second timer reaches the second duration;

[0074] In some embodiments, executing a timing count may be to add one to the original timing count value.

[0075] A determination step is performed to determine whether the timing count value is less than the total number of the above-mentioned logical bit information. When the timing count value is less than the total number of the above-mentioned logical bit information, the control step, the output step and the counting step are sequentially executed according to the above-mentioned sorting until the timing count value is not less than the total number of the above-mentioned logical bit information, thereby obtaining the above-mentioned interface signal including multiple above-mentioned sub-interface signals.

[0076] In the above embodiment, the first timer and the second timer are configured in the order of the logic bits and are controlled to start. The first signal and the second signal of the corresponding duration are output according to the timing duration of the first timer and the second timer, thereby realizing the control of the duration of the waveform signal corresponding to the logic bit, and further realizing the simulation of multiple sub-interface signals in sequence by software to obtain the effect of the interface signal.

[0077] The method further includes: before the control step, initializing the timing count value to 0.

[0078] In actual application, before determining the multiple logical bit information corresponding to the control instruction according to the predetermined interface protocol, the method further includes: storing the control instruction consisting of multiple logical bits in an array variable, wherein the data stream length of the array variable is greater than or equal to the number of the logical bits, and each of the logical bits is stored in the array variable in a sorted order; and setting an index variable for the logical bit, wherein the index variable is used to index the logical bit at the corresponding position in the array variable. In this way, when subsequently determining the multiple logical bit information corresponding to the control instruction according to the predetermined interface protocol, the logical bits can be read from the array variable in order according to the sorted order of the logical bits to determine the corresponding logical bit information.

[0079] Then, according to the above-mentioned predetermined interface protocol, multiple logical bit information corresponding to the above-mentioned control instruction is determined, including: an indexing step, indexing the logical bit to be converted from the above-mentioned array variable according to the above-mentioned index variable; a second determination step, according to the above-mentioned predetermined interface protocol, determining the logical bit information corresponding to the logical bit to be converted.

[0080] After setting the index variable of the logic bit and before obtaining the logic bit to be converted from the array variable by indexing according to the index variable, the method further includes: initializing the index variable to 0.

[0081] In the above embodiment, the step of obtaining the first duration and the second duration corresponding to each of the above-mentioned logical bit information serves as the obtaining step, the step of determining the timing duration of the above-mentioned first timer to be the above-mentioned first duration, and the step of determining the timing duration of the above-mentioned second timer to be the above-mentioned second duration serves as the fourth determining step, and the step of sequentially generating the sub-interface signal corresponding to each of the above-mentioned logical bit information through the above-mentioned second interface according to the first duration of the above-mentioned first timer and the second duration of the above-mentioned second timer and in accordance with the sorting of the plurality of above-mentioned logical bit information serves as the generating step. The above-mentioned method may further include: an accumulating step, when the timing duration of the above-mentioned second timer reaches the above-mentioned second duration, adding one to the above-mentioned index variable to obtain an updated index variable; the above-mentioned method also includes: a third determining step, determining whether the updated index variable is less than the total number of the above-mentioned logical bit information, and when the updated index variable is less than the total number of the above-mentioned logical bit information, sequentially executing the indexing step, the second determining step, the obtaining step, the fourth determining step and the generating step until the above-mentioned index variable is not less than the number of the above-mentioned logical bits. That is to say, the above-mentioned logical bits are read from the array variable in sequence through the index variable, and the first duration and second duration corresponding to the read logical bits are obtained to obtain the timing duration of the first timer and the second timer. Finally, the first timer and the second timer are controlled to start timing according to the timing duration, and the sub-interface signals corresponding to the logical bit information are generated in sequence through the second interface, further realizing the generation of interface sub-new numbers in sequence, thereby further ensuring that a more accurate interface signal is obtained.

[0082] Among them, the above-mentioned logical bit sorting refers to the order of the logical bits that constitute the above-mentioned control instructions. For example, the logical bits corresponding to the control instructions are logical bit 1, logical bit 2, logical bit 3,..., logical bit n in order, and the corresponding index variables are index variable 0, index variable 1, index variable 2,..., index variable n-1. Then, through the above-mentioned loop process, the sub-interface signals corresponding to logical bit 1, logical bit 2, logical bit 3,..., logical bit n are generated in turn, that is, sub-interface signal 1, sub-interface signal 2, sub-interface signal 3,..., sub-interface signal n are obtained, and the interface signal is obtained.

[0083] In some embodiments, after obtaining the plurality of sub-interface signals, the method further includes: splicing the plurality of sub-interface signals according to the generation order of the plurality of sub-interface signals to obtain the interface signal.

[0084] In an exemplary embodiment, the method further includes, before the control step, initializing the output of the second interface to a low level. Because the default level is low according to the transmission protocol specification of the predetermined interface protocol, in this embodiment, the output of the second interface is initially set to a low level. When the first timer and the second timer are started, the output is then set high via the second interface to output the high-level first signal.

[0085] In order to further implement simulation of the interface signal of the first interface through software and further avoid upgrading the architecture of the BMC chip or hardware investment, in another optional implementation, the above-mentioned control step includes: controlling the above-mentioned first timer and the above-mentioned second timer to start timing; setting the output of the above-mentioned second interface to a high level state, and outputting the above-mentioned first signal in the high level state through the above-mentioned second interface; when the timing duration of the above-mentioned first timer reaches the above-mentioned first duration, stopping the output of the above-mentioned first signal and setting the output of the above-mentioned second interface to a low level.

[0086] In some embodiments, when the timer reaches the first time duration, stopping the output of the first signal includes: triggering a first interrupt to stop the output of the first signal when the timer reaches the first time duration. By triggering the first interrupt and disabling the first timer, the duration of the high level in the sub-interface signal is controlled, further achieving conversion of different logic bits.

[0087] In some embodiments, the first interrupt may carry the location information of the currently converted logical bit, and the core partition can use this location information to determine the location of the logical bit currently undergoing signal conversion. Of course, the core partition can also determine the location of the logical bit currently undergoing signal conversion by counting the number of times the first interrupt is triggered and the order of the logical bits. In this way, if a fault occurs during the conversion process, after the fault is recovered, the logical bits that have already completed signal conversion processing do not need to be repeatedly converted, thereby improving signal conversion efficiency, avoiding waste of core partition computing resources, and more efficiently performing conversion operations on the logical bits to be converted.

[0088] In order to further realize the simulation of the interface signal of the first interface through software, and further avoid upgrading the architecture of the BMC chip or hardware investment, according to another exemplary embodiment of the present application, the above-mentioned output step includes: when the timing duration of the above-mentioned first timer reaches the above-mentioned first duration, setting the output of the above-mentioned second interface to a low level state, and outputting the above-mentioned second signal in a low level state through the above-mentioned second interface; when the timing duration of the above-mentioned second timer reaches the above-mentioned second duration, stopping the output of the above-mentioned second signal, and setting the output of the above-mentioned second interface to a high level to obtain the above-mentioned sub-interface signal.

[0089] In some embodiments, when the second timer reaches the second duration, stopping the output of the second signal includes: triggering a second interrupt to stop the output of the second signal when the second timer reaches the second duration. By triggering the second interrupt and disabling the second timer, the duration of the sub-interface signal is controlled, further ensuring that each sub-interface signal with a consistent duration can be obtained more accurately.

[0090] In some embodiments, each time the second interrupt is triggered, a timing count is performed, where the timing count represents the number of logic bits that have been converted.

[0091] Furthermore, the second interrupt may carry the location information of the currently converted logical bit, and the core partition may know the location of the logical bit currently undergoing signal conversion through this location information. Of course, the core partition may also determine the location of the logical bit currently undergoing signal conversion by counting the number of times the second interrupt is triggered and the order of the logical bits. The core partition may also determine the location of the logical bit currently undergoing signal conversion through timer counting and the order of the logical bits. In this way, if a fault occurs during the conversion process, after the fault is recovered, the logical bits that have already completed signal conversion processing do not need to be repeatedly converted, thereby improving signal conversion efficiency, avoiding waste of core partition computing resources, and more efficiently implementing the conversion operation of the logical bits to be converted.

[0092] During application, those skilled in the art may flexibly configure the structure of the control instruction. In one optional solution, the data structure of the control instruction includes an address rate field, a target address field, a message rate field, a write length field, and a read length field. The address rate field represents the transmission rate of the address data, the target address field represents the address data of the hardware partition, and the message rate field represents the transmission rate of the message data. The write length field represents the write operation information of the kernel partition, and the read length field represents the read operation information of the kernel partition.

[0093] For example, when the control instruction is the first instruction for determining whether the hardware partition exists, the optional message transmission format of the first instruction is shown in FIG4 , wherein the address rate field is 2 logical bits 0, and the message rate field is 1 logical bit 0. The target address field, write length field, and read length field are all 8 logical bits. The target address field is determined by the hardware design of the hardware partition and is generally 0x30 (0x represents a hexadecimal number). The write length field and the read length field are both 0x00. These fields are all completed by the kernel partition initiating the write operation.

[0094] Furthermore, after sending the interface signal to the first interface via the second interface, the method further includes receiving a response instruction generated by the hardware partition in response to the control instruction, the response instruction including the control instruction and a frame check sequence (FCS). The response instruction generated by the hardware partition in response to the control instruction includes, in addition to the control instruction information, the frame check sequence at the end of the control instruction, which is converted into information recognizable by the second interface, resulting in a field format as shown in FIG4 .

[0095] In an exemplary embodiment, the first interface includes a PECI interface, and the second interface includes a GPIO interface. That is, the kernel partition of the present application simulates a PECI signal via the GPIO interface and sends the PECI signal to the PECI interface of the hardware partition via the GPIO interface, thereby expanding the PECI link between the BMC and the host system. This further enables the BMC kernel partition to independently manage the hardware partitions of the server host system without performing hardware logic design on the BMC chip, further enabling a single BMC chip to independently monitor multiple hardware partitions of the host system.

[0096] In some embodiments, the first interface is a PECI interface, and the second interface is a GPIO interface. Among them, the PECI interface is an interface for information exchange between the BMC and the processor of the host system. As an important interface in the server, the PECI interface is mainly responsible for obtaining the server's CPU temperature, power consumption, and fault status information of key unit modules such as the CPU, UPI (Ultra Path Interconnect) link, memory controller, PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) link, etc., to provide strong protection for the health status monitoring, fault analysis and positioning of the server system. The BMC has many GPIO interfaces, so there is no need to introduce additional hardware overhead when implementing the technical solution of this application.

[0097] In order to further expand the communication link between the BMC chip and the host system, and further realize the effect of a BMC chip monitoring multiple hardware partitions of the host system, according to some other embodiments of the present application, there are multiple hardware partitions, there are multiple kernel partitions, one of the multiple kernel partitions includes a third interface, the other kernel partitions respectively include the second interface, each of the hardware partitions respectively includes the first interface, the third interface is the same as the interface type of the first interface, and the method further includes: sending the control instruction to the corresponding first interface through the third interface. In this embodiment, one of the kernel partitions is connected to the first interface of a hardware partition through the third interface, and the other kernel partitions are connected to the first interfaces of other hardware partitions through the second interface in a one-to-one correspondence. That is to say, the kernel partition of the BMC monitors the hardware partitions one-to-one through the physical link formed by the third interface and the first interface, or through the physical link formed by the second interface and the first interface, further realizing that a BMC management unit independently manages multiple hardware partitions, thereby further ensuring the independence of the fault management functions of different partition systems of the unified server platform.

[0098] In some embodiments, the third interface is also a PECI interface. In related art, a BMC chip has only one PECI interface, meaning that only one PECI link can be established with the host system through this PECI interface. The solution of the present application, in addition to retaining this PECI link, simulates the PECI protocol through multiple GPIO interfaces of the BMC chip, thereby establishing one-to-one PECI links with the PECI interfaces of other hardware partitions of the host system through the GPIO interfaces. This expands the PECI links and enables the BMC kernel partition to monitor hardware partitions on a one-to-one basis.

[0099] In actual application, a first operating system is deployed on the hardware partition, and a second operating system is deployed on the kernel partition. The first operating system includes, but is not limited to, a Linux system, an RTOS (Real Time Operating System), or other self-developed software systems. The second operating system includes, but is not limited to, a Linux system, an RTOS system, or other self-developed software systems.

[0100] In addition, in this application, the BMC is divided into multiple kernel partitions according to the kernel, and each kernel partition deploys one of the above-mentioned second operating systems. The above-mentioned kernel partitions correspond one-to-one with the above-mentioned hardware partitions, that is, one kernel partition performs health status monitoring, remote power on and off, temperature (voltage) collection, and fault analysis and location operations on one hardware partition.

[0101] In order to enable those skilled in the art to more clearly understand the generation process of the interface signal in this application, the following is explained in conjunction with Figure 5, taking the above-mentioned first interface as a PECI interface, the above-mentioned second interface as a GPIO interface, and the above-mentioned control instruction as the above-mentioned first instruction for determining whether the above-mentioned hardware partition exists as an example.

[0102] Among them, according to the PECI related protocols, the PECI interface is divided into Host (host system) devices and Client (guest machine) devices. Each communication is initiated by the Host device, and the Host device obtains corresponding information through different PECI commands. In this application, a kernel partition of the BMC serves as the Host device, and the hardware partition corresponding to the kernel partition in the host system serves as the Client device.

[0103] The message transmission format of the first instruction that the kernel partition of the kernel partition needs to send is shown in Figure 4, and its corresponding data stream is 0000100000 0 00000000 00000000, a total of 27 logical bits, that is, the length of the data stream is 27. The waveform definition of logical bits 0 and 1 in the PECI protocol is shown in Figure 3. In Figure 3, tBIT represents the period of 1 bit (logical bit = 0 or 1), and logical bit 0 and logical bit 1 are distinguished by the duty cycle of the high level in the entire tBIT time, that is: the high level time of logical bit 0 is 0.2~0.4tBIT, represented by t0 here; the high level time of logical bit 1 is 0.6~0.8tBIT, represented by t1 here. When designing the software of this application, t0 (or t1) is timed by the first timer T0, and tBIT is timed by the second timer T1. The interface signal generation process is as follows:

[0104] Step S1: Initialize the first timer T0 and the second timer T1, initialize the GPIO controller, and configure the second interface GPIO output to a low level state;

[0105] Step S2: Cache the data stream of the first instruction into a char array variable, calculate the number of logical bits of the data stream and store it into the variable len, and obtain len=27;

[0106] Step S3: Initialize the index variable index of the logic bit and set it to 0;

[0107] Step S4: Determine whether index is less than len. If so, execute step S5; otherwise, end the entire process.

[0108] Step S5: Determine whether the logic bit Data[index] corresponding to index is equal to 0. If so, configure the timing time of the first timer T0 to t0; otherwise, configure the timing time of the first timer T0 to t1;

[0109] Step S6: Set the timing time of the second timer T1 to tBIT;

[0110] Step S7: When the T0 interrupt is triggered, the second interface GPIO output is set to a low level, and the first timer TO is turned off;

[0111] Step S8: When the T1 interrupt is triggered, the second interface GPIO output is set to a high level, and the second timer T1 is turned off;

[0112] Step S9: Update index=index+1 and return to step S4.

[0113] The above embodiment, based on the dual-timer GPIO simulation method, can realize the expansion and construction of the GPIO interface under each hardware partition system to the PECI type PECI independent link, and realize the independent monitoring capability of a single BMC management unit to multiple hardware partition systems of the host system.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a non-volatile readable storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the above-mentioned methods of each embodiment of the present application.

[0115] In this embodiment, an interface communication device is also provided, which is configured to implement the above-mentioned embodiments and optional implementations. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0116] FIG6 is a block diagram of an interface communication device according to an embodiment of the present application. The server host system includes a hardware partition, and the BMC includes a kernel partition. The kernel partition is used to manage the hardware partition. The device is applied to the kernel partition. As shown in FIG6 , the device includes:

[0117] A generating unit 10 is configured to generate a control instruction for controlling the hardware partition;

[0118] In some embodiments, the control instruction includes at least one of the following: a first instruction for determining whether the hardware partition exists; a second instruction for obtaining the sensor temperature of the hardware partition; and a third instruction for obtaining register data of the hardware partition.

[0119] The conversion unit 20 is configured to convert the control instruction into an interface signal that complies with a predetermined interface protocol, wherein the predetermined interface protocol is the interface protocol of the first interface of the hardware partition;

[0120] In some embodiments, the above interface signal may be a PECI signal, or an interface signal of another protocol type.

[0121] The first sending unit 30 is configured to send the interface signal to the first interface through the second interface, where the first interface and the second interface are of different interface types.

[0122] In some embodiments, the first interface may include a PECI interface, and the second interface may include a GPIO interface. For example, the first interface is a PECI interface, and the second interface is a GPIO interface.

[0123] Through the above scheme, in the scenario of hardware partitioning of the server host system, the kernel partition of the BMC of the above-mentioned generation unit first generates a control instruction for controlling the hardware partition; the control instruction is converted by the conversion unit to obtain an interface signal that complies with the interface protocol of the first interface of the hardware partition, and the obtained interface signal is sent to the first interface via the second interface by the first sending unit to realize control of a hardware partition of the host system. Compared with the related art in which the hardware partitioning scenario of the host system requires the BMC chip itself to have the hardware logic design of the PECI controller, which leads to the problem of complex BMC chip design, the present application does not need to implement the hardware logic design of the PECI controller on the BMC chip in advance. It only needs the kernel partition to simulate the interface protocol of the first interface through the second interface to generate the interface signal on the BMC chip, thereby achieving the technical effect of simulating and generating the hardware interface signal by software, and thus achieving the purpose of not requiring the chip itself to have the hardware logic design of the relevant hardware interface signal. It can not only reduce the design difficulty of the BMC chip, reduce the design cost and design cycle of the BMC chip, but also achieve the effect of a kernel partition of the BMC independently managing a hardware partition in the host system, and realize the expansion of the communication link between the BMC and the host system, so that a BMC chip can achieve the purpose of independently controlling multiple hardware partitions of the host system.

[0124] In one exemplary embodiment, the conversion unit includes: a determination module configured to determine, based on the predetermined interface protocol, a plurality of logic bit information corresponding to the control instruction; and a generation module configured to generate the interface signal based on the plurality of logic bit information, a first timer, and a second timer. In this embodiment, generating the interface signal corresponding to the control instruction based on the predetermined interface protocol further achieves the technical effect of simulating the generation of the interface signal of the first interface using software.

[0125] In order to generate the interface signal corresponding to the above-mentioned control instruction based on multiple logical bit information, the first timer and the second timer, according to some optional embodiments of the present application, the above-mentioned generation module includes: a first determination submodule, which is configured to determine the timing duration of the above-mentioned first timer and the above-mentioned second timer based on the multiple above-mentioned logical bit information; and a generation submodule, which is configured to generate the above-mentioned interface signal through the above-mentioned second interface based on the above-mentioned timing duration.

[0126] In some embodiments, the first timer and the second timer may be a timing program in the kernel partition or a register on the kernel partition, wherein the first timer and the second timer may at least provide a timing function.

[0127] In another exemplary embodiment, the first determination submodule is further used to obtain the first duration and the second duration corresponding to each of the above-mentioned logical bit information, the first duration representing the duration that the above-mentioned logical bit information is at a high level, the second duration representing the total duration of the above-mentioned logical bit information, and the first duration corresponding to different above-mentioned logical bit information is different; the first determination submodule is further used to determine the timing duration of the above-mentioned first timer to be the above-mentioned first duration, and to determine the timing duration of the above-mentioned second timer to be the above-mentioned second duration. In this embodiment, by setting the timing duration of the first timer to the first duration and the timing duration of the second timer to the second duration, it is convenient to subsequently generate the logical bit information corresponding to different logical bits according to the timing durations of the first timer and the second timer to obtain the interface signal, further achieving the purpose of using the software system to generate the interface signal without the need for hardware logic design of the interface signal for the BMC chip, thereby further reducing the design difficulty of the BM chip.

[0128] The first duration is shorter than the second duration.

[0129] In some embodiments, the control instruction is composed of at least one field, and the field is represented by a plurality of logical bits, each of which can be 0 or 1. Each logical bit is converted into the corresponding logical bit information, and the interface signal corresponding to the control instruction is obtained. The logical bit information can be represented by a combination of a high-level signal and a low-level signal. For example, for a logical bit 0, a high-level signal of a first preset duration and a low-level signal of a second preset duration can be used to represent it. For a logical bit 1, a high-level signal of a third preset duration and a low-level signal of a fourth preset duration can be used to represent it. The first preset duration and the third preset duration are different, and the second preset duration and the fourth preset duration are also different.

[0130] Generally speaking, under an interface protocol, the running duration corresponding to each of the multiple logical bit information is the same, that is, the second duration corresponding to each of the logical bit information is the same. Therefore, the sum of the first preset duration and the second preset duration is equal to the sum of the third preset duration and the fourth preset duration.

[0131] In actual application, there is a sequence between multiple logical bit information. In order to further ensure that the interface signal corresponding to the above-mentioned control instruction is obtained more accurately, in another optional embodiment of the present application, the above-mentioned generation sub-module is also used to generate the sub-interface signal corresponding to each of the above-mentioned logical bit information in sequence through the above-mentioned second interface according to the above-mentioned first duration of the above-mentioned first timer and the second duration of the above-mentioned second timer, in accordance with the sorting of the multiple above-mentioned logical bit information, to obtain the above-mentioned interface signal.

[0132] In some embodiments, the above-mentioned sub-interface signal is actually a waveform signal composed of a high-level signal and a low-level signal, and multiple waveform signals constitute the above-mentioned interface signal.

[0133] In some embodiments, as shown in Figure 3, when the above-mentioned logic bit is 0, the first duration corresponding to the first timer is t0, and when the above-mentioned logic bit is 1, the first duration corresponding to the above-mentioned first timer is t1, t0 is less than t1, and the above-mentioned second duration is tBIT. Generally, t0 is 0.6 to 0.8 times of tBIT, that is, t0 = 0.2 to 0.4tBIT, and t1 is 0.6 to 0.8 times of tBIT, that is, t1 = 0.6 to 0.8tBIT.

[0134] In an exemplary embodiment, the generating submodule is further configured to execute:

[0135] A control step of controlling the first timer and the second timer to start timing, and outputting a first signal through the second interface before the timing duration of the first timer reaches the first duration;

[0136] In some embodiments, the first timer and the second timer each contain a decrement counter, the starting value of the first timer is set to the first duration, and the starting value of the second timer is set to the second duration. When the first timer and the second timer start timing, the decrement counter decrements from the starting value to 0, and when it reaches 0, the first timer and the second timer are interrupted, and the starting value of the first timer is reset to the first duration, and the starting value of the second timer is reset to the second duration, and then the decrement counter is restarted. Among them, an interrupt can be understood as a kind of identifier, so an interrupt can also be called an interrupt identifier.

[0137] In some embodiments, the first signal is a high level signal. In this application, in order to convert a logic bit 0 or 1 into a corresponding sub-interface signal, a high level first signal is generated through the second interface before the timing duration of the first timer reaches the first duration.

[0138] an output step of outputting a second signal through the second interface after the timing duration of the first timer reaches the first duration and before the timing duration of the second timer reaches the second duration, to obtain the sub-interface signal consisting of the first signal and the second signal;

[0139] In some embodiments, the second signal is a low-level signal. In the present application, in order to distinguish between logic bits 0 and 1, after the first timer reaches the first time, a low-level second signal is generated through the second interface until the second timer reaches the second time, thereby obtaining sub-interface signals with different waveforms, wherein the waveform signals corresponding to logic bits 0 and 1 have different duty cycles.

[0140] a counting step, executing a timer count when the timing duration of the second timer reaches the second duration;

[0141] In some embodiments, executing a timing count may be to add one to the original timing count value.

[0142] A determination step is performed to determine whether the timing count value is less than the total number of the above-mentioned logical bit information. When the timing count value is less than the total number of the above-mentioned logical bit information, the control step, the output step and the counting step are sequentially executed according to the above-mentioned sorting until the timing count value is not less than the total number of the above-mentioned logical bit information, thereby obtaining the above-mentioned interface signal including multiple above-mentioned sub-interface signals.

[0143] In the above embodiment, the first timer and the second timer are configured in the order of the logic bits and are controlled to start. The first signal and the second signal of the corresponding duration are output according to the timing duration of the first timer and the second timer, thereby realizing the control of the duration of the waveform signal corresponding to the logic bit, and further realizing the simulation of multiple sub-interface signals in sequence by software to obtain the effect of the interface signal.

[0144] The above-mentioned device further includes: a first initialization unit, which is configured to initialize the above-mentioned timing count value to 0 before the above-mentioned control step.

[0145] In actual application, the device further includes: a storage unit configured to store the control instruction consisting of multiple logical bits into an array variable before determining the multiple logical bit information corresponding to the control instruction according to the predetermined interface protocol, wherein the data stream length of the array variable is greater than or equal to the number of the logical bits, and each of the logical bits is stored in the array variable in a sorted order; and a setting unit configured to set an index variable for the logical bit, wherein the index variable is used to index the logical bit at the corresponding position in the array variable. In this way, in the subsequent process of determining the multiple logical bit information corresponding to the control instruction according to the predetermined interface protocol, the logical bits can be read from the array variable in order according to the sorting order of the logical bits to determine the corresponding logical bit information.

[0146] Then, the above-mentioned determination module includes: an indexing submodule, which is set as an indexing step, and obtains the logical bit to be converted from the above-mentioned array variable according to the above-mentioned index variable; a second determination submodule, which is set as a second determination step, and determines the logical bit information corresponding to the logical bit to be converted according to the above-mentioned predetermined interface protocol.

[0147] The apparatus further includes: a second initialization unit configured to initialize the index variable to 0 after setting the index variable of the logic bit and before obtaining the logic bit to be converted from the array variable according to the index variable.

[0148] In the above embodiment, the step of acquiring the first and second durations corresponding to each piece of the logical bit information serves as the acquiring step, the step of determining the timing duration of the first timer to be the first duration, and the step of determining the timing duration of the second timer to be the second duration serves as the fourth determining step, and the step of sequentially generating, through the second interface, a sub-interface signal corresponding to each piece of the logical bit information according to the order of the plurality of pieces of the logical bit information based on the first duration of the first timer and the second duration of the second timer serves as the generating step. The above apparatus may further include: an accumulating unit configured to perform an accumulating step, and when the timing duration of the second timer reaches the second duration, increment the index variable by one to obtain an updated index variable; and a determining unit configured to perform a third determining step, and determine whether the updated index variable is less than the total number of the logical bit information. If the updated index variable is less than the total number of the logical bit information, the indexing step, the second determining step, the acquiring step, the fourth determining step, and the generating step are sequentially performed until the index variable is no less than the number of the logical bits. That is to say, the above-mentioned logical bits are read from the array variable in sequence through the index variable, and the first duration and second duration corresponding to the read logical bits are obtained to obtain the timing duration of the first timer and the second timer. Finally, the first timer and the second timer are controlled to start timing according to the timing duration, and the sub-interface signals corresponding to the logical bit information are generated in sequence through the second interface, further realizing the generation of interface sub-new numbers in sequence, thereby further ensuring that a more accurate interface signal is obtained.

[0149] Among them, the above-mentioned logical bit sorting refers to the order of the logical bits that constitute the above-mentioned control instructions. For example, the logical bits corresponding to the control instructions are logical bit 1, logical bit 2, logical bit 3,..., logical bit n in order, and the corresponding index variables are index variable 0, index variable 1, index variable 2,..., index variable n-1. Then, through the above-mentioned loop process, the sub-interface signals corresponding to logical bit 1, logical bit 2, logical bit 3,..., logical bit n are generated in turn, that is, sub-interface signal 1, sub-interface signal 2, sub-interface signal 3,..., sub-interface signal n are obtained, and the interface signal is obtained.

[0150] In some embodiments, the apparatus further comprises: a splicing unit configured to, after obtaining the plurality of sub-interface signals, splice the plurality of sub-interface signals in the order in which the plurality of sub-interface signals are generated to obtain the interface signal.

[0151] In an exemplary embodiment, the apparatus further includes a third initialization unit configured to initialize the output of the second interface to a low level before the control step. Because the default level is low according to the transmission protocol specification of the predetermined interface protocol, in this embodiment, the output of the second interface is initially set to a low level. When the first timer and the second timer are started, the output is set high via the second interface to output the high-level first signal.

[0152] In order to further simulate the interface signal of the first interface through software and further avoid upgrading the architecture of the BMC chip or hardware investment, in another optional implementation, the above-mentioned generation submodule is also used to control the above-mentioned first timer and the above-mentioned second timer to start timing; the above-mentioned generation submodule is also used to set the output of the above-mentioned second interface to a high level state, and output the above-mentioned first signal in the high level state through the above-mentioned second interface; the above-mentioned generation submodule is also used to stop the output of the above-mentioned first signal when the timing duration of the above-mentioned first timer reaches the above-mentioned first duration, and set the output of the above-mentioned second interface to a low level.

[0153] In some embodiments, the generating submodule is further configured to trigger a first interrupt to stop outputting the first signal when the first timer reaches the first duration. By triggering the first interrupt and disabling the first timer, the duration of the high level in the sub-interface signal is controlled, thereby further enabling conversion between different logic bits.

[0154] In some embodiments, the first interrupt may carry the location information of the currently converted logical bit, and the core partition can use this location information to determine the location of the logical bit currently undergoing signal conversion. Of course, the core partition can also determine the location of the logical bit currently undergoing signal conversion by counting the number of times the first interrupt is triggered and the order of the logical bits. In this way, if a fault occurs during the conversion process, after the fault is recovered, the logical bits that have already completed signal conversion processing do not need to be repeatedly converted, thereby improving signal conversion efficiency, avoiding waste of core partition computing resources, and more efficiently performing conversion operations on the logical bits to be converted.

[0155] In order to further realize the simulation of the interface signal of the first interface through software, and further avoid upgrading the architecture of the BMC chip or hardware investment, according to another exemplary embodiment of the present application, the above-mentioned generation submodule is also used to set the output of the above-mentioned second interface to a low level state when the timing duration of the above-mentioned first timer reaches the above-mentioned first duration, and output the above-mentioned second signal in the low level state through the above-mentioned second interface; the above-mentioned generation submodule is also used to stop the output of the above-mentioned second signal when the timing duration of the above-mentioned second timer reaches the above-mentioned second duration, and set the output of the above-mentioned second interface to a high level to obtain the above-mentioned sub-interface signal.

[0156] In some embodiments, the generation submodule is further configured to trigger a second interrupt to stop outputting the second signal when the second timer reaches the second duration. By triggering the second interrupt and disabling the second timer, the duration of the sub-interface signal is controlled, further ensuring that each sub-interface signal with a consistent duration can be accurately obtained.

[0157] In some embodiments, each time the second interrupt is triggered, a timing count is performed, where the timing count represents the number of logic bits that have been converted.

[0158] Furthermore, the second interrupt may carry the location information of the currently converted logical bit, and the core partition may know the location of the logical bit currently undergoing signal conversion through this location information. Of course, the core partition may also determine the location of the logical bit currently undergoing signal conversion by counting the number of times the second interrupt is triggered and the order of the logical bits. The core partition may also determine the location of the logical bit currently undergoing signal conversion through timer counting and the order of the logical bits. In this way, if a fault occurs during the conversion process, after the fault is recovered, the logical bits that have already completed signal conversion processing do not need to be repeatedly converted, thereby improving signal conversion efficiency, avoiding waste of core partition computing resources, and more efficiently implementing the conversion operation of the logical bits to be converted.

[0159] During application, those skilled in the art may flexibly configure the structure of the control instruction. In one optional solution, the data structure of the control instruction includes an address rate field, a target address field, a message rate field, a write length field, and a read length field. The address rate field represents the transmission rate of the address data, the target address field represents the address data of the hardware partition, and the message rate field represents the transmission rate of the message data. The write length field represents the write operation information of the kernel partition, and the read length field represents the read operation information of the kernel partition.

[0160] For example, when the control instruction is the first instruction for determining whether the hardware partition exists, an optional message transmission format for the first instruction is shown in FIG4 , wherein the address rate field is two logical bits 0, and the message rate field is one logical bit 0. The target address field, write length field, and read length field are all 8 logical bits. The target address field is determined by the hardware design of the hardware partition and is generally 0x30 (0x represents a hexadecimal number). The write length field and the read length field are both 0x00. These fields are all completed by the kernel partition initiating the write operation.

[0161] Furthermore, the apparatus further includes a receiving unit configured to receive a response instruction generated by the hardware partition in response to the control instruction after the interface signal is sent to the first interface via the second interface, the response instruction including the control instruction and a frame check field. The response instruction generated by the hardware partition in response to the control instruction includes, in addition to the control instruction information, the frame check field at the end of the control instruction, which is converted into information recognizable by the second interface, resulting in a field format as shown in FIG4 .

[0162] In an exemplary embodiment, the first interface includes a PECI interface, and the second interface includes a GPIO interface. That is, the kernel partition of the present application simulates a PECI signal via the GPIO interface and sends the PECI signal to the PECI interface of the hardware partition via the GPIO interface, thereby expanding the PECI link between the BMC and the host system. This further enables the BMC kernel partition to independently manage the hardware partitions of the server host system without performing hardware logic design on the BMC chip, further enabling a single BMC chip to independently monitor multiple hardware partitions of the host system.

[0163] In some embodiments, the first interface is a PECI interface, and the second interface is a GPIO interface. The PECI interface is an interface for information exchange between the BMC and the host system's processor. As an important interface in the server, the PECI interface is primarily responsible for obtaining the server's CPU temperature, power consumption, and fault status information of key unit modules such as the CPU, UPI link, memory controller, and PCIe link, providing strong support for server system health status monitoring, fault analysis, and location. The BMC has a relatively large number of GPIO interfaces, so there is no need to introduce additional hardware overhead when implementing the technical solution of this application.

[0164] In order to further expand the communication link between the BMC chip and the host system, and further realize the effect of a BMC chip monitoring multiple hardware partitions of the host system, according to some other embodiments of the present application, there are multiple hardware partitions, there are multiple kernel partitions, one of the multiple kernel partitions includes a third interface, the other kernel partitions respectively include the second interface, each of the hardware partitions respectively includes the first interface, the third interface is the same as the interface type of the first interface, and the device further includes: a second sending unit, which is configured to send the control instruction to the corresponding first interface through the third interface. In this embodiment, one of the kernel partitions is connected to the first interface of a hardware partition through the third interface, and the other kernel partitions are connected to the first interfaces of other hardware partitions through the second interface in a one-to-one correspondence. That is to say, the kernel partition of the BMC monitors the hardware partitions one-to-one through the physical link formed by the third interface and the first interface, or through the physical link formed by the second interface and the first interface, further realizing that a BMC management unit independently manages multiple hardware partitions, thereby further ensuring the independence of the fault management functions of different partition systems of the unified server platform.

[0165] In some embodiments, the third interface is also a PECI interface. In related art, a BMC chip has only one PECI interface, meaning that only one PECI link can be established with the host system through this PECI interface. The solution of the present application, in addition to retaining this PECI link, simulates the PECI protocol through multiple GPIO interfaces of the BMC chip, thereby establishing one-to-one PECI links with the PECI interfaces of other hardware partitions of the host system through the GPIO interfaces. This expands the PECI links and enables the BMC kernel partition to monitor hardware partitions on a one-to-one basis.

[0166] In actual application, a first operating system is deployed on the hardware partition, and a second operating system is deployed on the kernel partition. The first operating system includes, but is not limited to, a Linux system, an RTOS system, or other self-developed software systems. The second operating system includes, but is not limited to, a Linux system, an RTOS system, or other self-developed software systems.

[0167] In addition, in this application, the BMC is divided into multiple kernel partitions according to the kernel, and each kernel partition deploys one of the above-mentioned second operating systems. The above-mentioned kernel partitions correspond one-to-one with the above-mentioned hardware partitions, that is, one kernel partition performs health status monitoring, remote power on and off, temperature (voltage) collection, and fault analysis and location operations on one hardware partition.

[0168] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0169] An embodiment of the present application further provides a non-volatile readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when running.

[0170] In an exemplary embodiment, the non-volatile readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0171] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0172] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0173] An embodiment of the present application also provides a server as shown in Figure 7, including: a host system 100, including multiple hardware partitions 101, the above-mentioned hardware partitions include a first interface 102; a BMC200, including multiple kernel partitions 201, the above-mentioned kernel partitions 201 correspond one-to-one to the above-mentioned hardware partitions 101, at least some of the above-mentioned kernel partitions include a second interface 202, the interface types of the above-mentioned first interface 102 and the above-mentioned second interface 202 are different, wherein the above-mentioned kernel partition 201 is used to generate control instructions for controlling the above-mentioned hardware partition 101; convert the above-mentioned control instructions into interface signals that comply with a predetermined interface protocol, wherein the above-mentioned predetermined interface protocol is the interface protocol of the first interface 102 of the above-mentioned hardware partition 101; and send the above-mentioned interface signal to the above-mentioned first interface 102 through the second interface 202.

[0174] In the above-mentioned server, the host system is divided into multiple independent hardware partitions, and the BMC is divided into multiple independent kernel partitions. The kernel partitions correspond to the hardware partitions one by one. The kernel partition is connected to the first interface of the corresponding hardware partition through the second interface. The kernel partition simulates the interface protocol of the first interface through the second interface to realize the monitoring of the hardware partition. In this way, the present application does not need to implement the hardware logic design of the PECI controller on the BMC chip in advance. It only needs the kernel partition to simulate the interface protocol of the first interface through the second interface to generate the interface signal on the BMC chip, thereby achieving the technical effect of simulating and generating the hardware interface signal using software, and thus achieving the purpose of not requiring the chip itself to have the hardware logic design of the relevant hardware interface signal. It can not only reduce the design difficulty of the BMC chip, reduce the design cost and design cycle of the BMC chip, but also realize the effect of a kernel partition of the BMC independently managing a hardware partition in the host system, realize the expansion of the communication link between the BMC and the host system, so as to achieve the purpose of a BMC chip independently controlling multiple hardware partitions of the host system.

[0175] In addition, in this application, the host system is divided into multiple hardware partitions based on the number of CPU units. Each hardware partition includes one CPU unit and is deployed with a corresponding first operating system. The BMC is divided into multiple kernel partitions based on the number of cores. Each kernel partition is deployed with a second operating system. The kernel partitions correspond one-to-one with the hardware partitions, that is, one kernel partition performs health status monitoring, remote power on and off, temperature (voltage) acquisition, and fault analysis and location operations on one hardware partition.

[0176] In one exemplary embodiment, the core partition is further configured to: determine, based on the predetermined interface protocol, a plurality of logical bit information corresponding to the control instruction; and generate the interface signal based on the plurality of logical bit information, the first timer, and the second timer. In this embodiment, generating the interface signal corresponding to the control instruction based on the predetermined interface protocol further achieves the technical effect of simulating the generation of the interface signal of the first interface using software.

[0177] In order to generate the interface signal corresponding to the above-mentioned control instruction based on multiple logical bit information, the first timer and the second timer, according to some optional embodiments of the present application, the above-mentioned kernel partition is also used to: determine the timing duration of the above-mentioned first timer and the above-mentioned second timer based on the multiple above-mentioned logical bit information; and generate the above-mentioned interface signal through the above-mentioned second interface based on the above-mentioned timing duration.

[0178] In some embodiments, the first timer and the second timer may be a timing program in the kernel partition or a register on the kernel partition, wherein the first timer and the second timer may at least provide a timing function.

[0179] In another exemplary embodiment, the kernel partition is further used to: obtain the first duration and the second duration corresponding to each of the above-mentioned logical bit information, the first duration representing the duration that the above-mentioned logical bit information is at a high level, the second duration representing the total duration of the above-mentioned logical bit information, and the first duration corresponding to different above-mentioned logical bit information is different; determine the timing duration of the above-mentioned first timer to be the above-mentioned first duration, and determine the timing duration of the above-mentioned second timer to be the above-mentioned second duration. In this embodiment, by setting the timing duration of the first timer to the first duration and the timing duration of the second timer to the second duration, it is convenient to subsequently generate the logical bit information corresponding to different logical bits according to the timing durations of the first timer and the second timer to obtain the interface signal, further achieving the purpose of using the software system to generate the interface signal without the need for hardware logic design of the interface signal for the BMC chip, thereby further reducing the design difficulty of the BM chip.

[0180] The first duration is shorter than the second duration.

[0181] In some embodiments, the control instruction is composed of at least one field, and the field is represented by a plurality of logical bits, each of which can be 0 or 1. Each logical bit is converted into the corresponding logical bit information, and the interface signal corresponding to the control instruction is obtained. The logical bit information can be represented by a combination of a high-level signal and a low-level signal. For example, for a logical bit 0, a high-level signal of a first preset duration and a low-level signal of a second preset duration can be used to represent it. For a logical bit 1, a high-level signal of a third preset duration and a low-level signal of a fourth preset duration can be used to represent it. The first preset duration and the third preset duration are different, and the second preset duration and the fourth preset duration are also different.

[0182] Generally speaking, under an interface protocol, the running duration corresponding to each of the multiple logical bit information is the same, that is, the second duration corresponding to each of the logical bit information is the same. Therefore, the sum of the first preset duration and the second preset duration is equal to the sum of the third preset duration and the fourth preset duration.

[0183] In actual application, there is a sequence between multiple logical bit information. In order to further ensure that the interface signal corresponding to the above-mentioned control instruction is obtained more accurately, in another optional embodiment of the present application, the above-mentioned kernel partition is also used to: according to the above-mentioned first duration of the above-mentioned first timer and the second duration of the above-mentioned second timer, according to the sorting of the multiple above-mentioned logical bit information, generate the sub-interface signal corresponding to each of the above-mentioned logical bit information in sequence through the above-mentioned second interface to obtain the above-mentioned interface signal.

[0184] In some embodiments, the above-mentioned sub-interface signal is actually a waveform signal composed of a high-level signal and a low-level signal, and multiple waveform signals constitute the above-mentioned interface signal.

[0185] In some embodiments, as shown in Figure 3, when the above-mentioned logic bit is 0, the first duration corresponding to the first timer is t0, and when the above-mentioned logic bit is 1, the first duration corresponding to the above-mentioned first timer is t1, t0 is less than t1, and the above-mentioned second duration is tBIT. Generally, t0 is 0.6 to 0.8 times of tBIT, that is, t0 = 0.2 to 0.4tBIT, and t1 is 0.6 to 0.8 times of tBIT, that is, t1 = 0.6 to 0.8tBIT.

[0186] In an exemplary embodiment, the kernel partition is further used to:

[0187] A control step of controlling the first timer and the second timer to start timing, and outputting a first signal through the second interface before the timing duration of the first timer reaches the first duration;

[0188] In some embodiments, the first timer and the second timer each contain a decrement counter, the starting value of the first timer is set to the first duration, and the starting value of the second timer is set to the second duration. When the first timer and the second timer start timing, the decrement counter decrements from the starting value to 0, and when it reaches 0, the first timer and the second timer are interrupted, and the starting value of the first timer is reset to the first duration, and the starting value of the second timer is reset to the second duration, and then the decrement counter is restarted. Among them, an interrupt can be understood as a kind of identifier, so an interrupt can also be called an interrupt identifier.

[0189] In some embodiments, the first signal is a high level signal. In this application, in order to convert a logic bit 0 or 1 into a corresponding sub-interface signal, a high level first signal is generated through the second interface before the timing duration of the first timer reaches the first duration.

[0190] an output step of outputting a second signal through the second interface after the timing duration of the first timer reaches the first duration and before the timing duration of the second timer reaches the second duration, to obtain the sub-interface signal consisting of the first signal and the second signal;

[0191] In some embodiments, the second signal is a low-level signal. In the present application, in order to distinguish between logic bits 0 and 1, after the first timer reaches the first time, a low-level second signal is generated through the second interface until the second timer reaches the second time, thereby obtaining sub-interface signals with different waveforms, wherein the waveform signals corresponding to logic bits 0 and 1 have different duty cycles.

[0192] a counting step, executing a timer count when the timing duration of the second timer reaches the second duration;

[0193] In some embodiments, executing a timing count may be to add one to the original timing count value.

[0194] A determination step is performed to determine whether the timing count value is less than the total number of the above-mentioned logical bit information. When the timing count value is less than the total number of the above-mentioned logical bit information, the control step, the output step and the counting step are sequentially executed according to the above-mentioned sorting until the timing count value is not less than the total number of the above-mentioned logical bit information, thereby obtaining the above-mentioned interface signal including multiple above-mentioned sub-interface signals.

[0195] In the above embodiment, the first timer and the second timer are configured in the order of the logic bits and are controlled to start. The first signal and the second signal of the corresponding duration are output according to the timing duration of the first timer and the second timer, thereby realizing the control of the duration of the waveform signal corresponding to the logic bit, and further realizing the simulation of multiple sub-interface signals in sequence by software to obtain the effect of the interface signal.

[0196] The kernel partition is further configured to initialize the timing count value to 0 before the control step.

[0197] In actual application, the kernel partition is further configured to: before determining the plurality of logical bit information corresponding to the control instruction according to the predetermined interface protocol, store the control instruction consisting of the plurality of logical bits in an array variable, wherein the data stream length of the array variable is greater than or equal to the number of the logical bits, and each of the logical bits is stored in the array variable in sorted order; and set an index variable for the logical bit, wherein the index variable is used to index the logical bit at the corresponding position in the array variable. In this way, when subsequently determining the plurality of logical bit information corresponding to the control instruction according to the predetermined interface protocol, the logical bits can be read from the array variable in order according to the sorted order of the logical bits to determine the corresponding logical bit information.

[0198] Then, the above-mentioned kernel partition is also used for: an indexing step, obtaining the logic bit to be converted from the above-mentioned array variable according to the above-mentioned index variable; a second determination step, determining the logic bit information corresponding to the logic bit to be converted according to the above-mentioned predetermined interface protocol.

[0199] The kernel partition is further configured to: after setting the index variable of the logic bit, and before obtaining the logic bit to be converted from the array variable by indexing according to the index variable, initialize the index variable to 0.

[0200] In the above embodiment, the step of obtaining the first duration and the second duration corresponding to each of the above-mentioned logical bit information serves as the obtaining step, the step of determining the timing duration of the above-mentioned first timer to be the above-mentioned first duration and the step of determining the timing duration of the above-mentioned second timer to be the above-mentioned second duration serves as the fourth determining step, and the step of sequentially generating the sub-interface signal corresponding to each of the above-mentioned logical bit information through the above-mentioned second interface according to the first duration of the above-mentioned first timer and the second duration of the above-mentioned second timer and in accordance with the order of the plurality of above-mentioned logical bit information serves as the generating step. The above-mentioned core partition is further used for: an accumulation step, when the timing duration of the above-mentioned second timer reaches the above-mentioned second duration, adding one to the above-mentioned index variable to obtain an updated index variable; the above-mentioned core partition is further used for: a third determining step, determining whether the above-mentioned updated index variable is less than the total number of the above-mentioned logical bit information. When the above-mentioned updated index variable is less than the total number of the above-mentioned logical bit information, the above-mentioned indexing step, the above-mentioned second determining step, the above-mentioned obtaining step, the above-mentioned fourth determining step and the above-mentioned generating step are sequentially performed until the above-mentioned index variable is not less than the number of the above-mentioned logical bits. That is to say, the above-mentioned logical bits are read from the array variable in sequence through the index variable, and the first duration and second duration corresponding to the read logical bits are obtained to obtain the timing duration of the first timer and the second timer. Finally, the first timer and the second timer are controlled to start timing according to the timing duration, and the sub-interface signals corresponding to the logical bit information are generated in sequence through the second interface, further realizing the generation of interface sub-new numbers in sequence, thereby further ensuring that a more accurate interface signal is obtained.

[0201] Among them, the above-mentioned logical bit sorting refers to the order of the logical bits that constitute the above-mentioned control instructions. For example, the logical bits corresponding to the control instructions are logical bit 1, logical bit 2, logical bit 3,..., logical bit n in order, and the corresponding index variables are index variable 0, index variable 1, index variable 2,..., index variable n-1. Then, through the above-mentioned loop process, the sub-interface signals corresponding to logical bit 1, logical bit 2, logical bit 3,..., logical bit n are generated in turn, that is, sub-interface signal 1, sub-interface signal 2, sub-interface signal 3,..., sub-interface signal n are obtained, and the interface signal is obtained.

[0202] In some embodiments, after obtaining the plurality of sub-interface signals, the core partition is further configured to: splice the plurality of sub-interface signals according to the generation order of the plurality of sub-interface signals to obtain the interface signal.

[0203] In an exemplary embodiment, the core partition is further configured to initialize the output of the second interface to a low level before the control step. Because the default level is low according to the transmission protocol specification of the predetermined interface protocol, this embodiment initializes the output of the second interface to a low level. When the first timer and the second timer are started, the output is set high via the second interface to output a high-level first signal.

[0204] In order to further implement the simulation of the interface signal of the first interface through software and further avoid upgrading the architecture of the BMC chip or hardware investment, in another optional implementation, the above-mentioned core partition is also used to: control the above-mentioned first timer and the above-mentioned second timer to start timing; set the output of the above-mentioned second interface to a high level state, and output the above-mentioned first signal in the high level state through the above-mentioned second interface; when the timing duration of the above-mentioned first timer reaches the above-mentioned first duration, stop outputting the above-mentioned first signal and set the output of the above-mentioned second interface to a low level.

[0205] In some embodiments, the core partition is further configured to trigger a first interrupt to stop outputting the first signal when the first timer reaches the first duration. By triggering the first interrupt and disabling the first timer, the duration of the high level in the sub-interface signal is controlled, further enabling conversion between different logic bits.

[0206] In some embodiments, the first interrupt may carry the location information of the currently converted logical bit, and the core partition can use this location information to determine the location of the logical bit currently undergoing signal conversion. Of course, the core partition can also determine the location of the logical bit currently undergoing signal conversion by counting the number of times the first interrupt is triggered and the order of the logical bits. In this way, if a fault occurs during the conversion process, after the fault is recovered, the logical bits that have already completed signal conversion processing do not need to be repeatedly converted, thereby improving signal conversion efficiency, avoiding waste of core partition computing resources, and more efficiently performing conversion operations on the logical bits to be converted.

[0207] In order to further implement the simulation of the interface signal of the first interface through software, and further avoid upgrading the architecture of the BMC chip or hardware investment, according to another exemplary embodiment of the present application, the above-mentioned core partition is also used to: when the timing duration of the above-mentioned first timer reaches the above-mentioned first duration, set the output of the above-mentioned second interface to a low level state, and output the above-mentioned second signal in a low level state through the above-mentioned second interface; when the timing duration of the above-mentioned second timer reaches the above-mentioned second duration, stop the output of the above-mentioned second signal, and set the output of the above-mentioned second interface to a high level to obtain the above-mentioned sub-interface signal.

[0208] In some embodiments, the core partition is further configured to trigger a second interrupt to stop outputting the second signal when the second timer reaches the second duration. By triggering the second interrupt and disabling the second timer, the duration of the sub-interface signal is controlled, further ensuring that each sub-interface signal with a consistent duration can be accurately obtained.

[0209] In some embodiments, each time the second interrupt is triggered, a timing count is performed, where the timing count represents the number of logic bits that have been converted.

[0210] Furthermore, the second interrupt may carry the location information of the currently converted logical bit, and the core partition may know the location of the logical bit currently undergoing signal conversion through this location information. Of course, the core partition may also determine the location of the logical bit currently undergoing signal conversion by counting the number of times the second interrupt is triggered and the order of the logical bits. The core partition may also determine the location of the logical bit currently undergoing signal conversion through timer counting and the order of the logical bits. In this way, if a fault occurs during the conversion process, after the fault is recovered, the logical bits that have already completed signal conversion processing do not need to be repeatedly converted, thereby improving signal conversion efficiency, avoiding waste of core partition computing resources, and more efficiently implementing the conversion operation of the logical bits to be converted.

[0211] During application, those skilled in the art may flexibly configure the structure of the control instruction. In one optional solution, the data structure of the control instruction includes an address rate field, a target address field, a message rate field, a write length field, and a read length field. The address rate field represents the transmission rate of the address data, the target address field represents the address data of the hardware partition, and the message rate field represents the transmission rate of the message data. The write length field represents the write operation information of the kernel partition, and the read length field represents the read operation information of the kernel partition.

[0212] For example, when the control instruction is the first instruction for determining whether the hardware partition exists, an optional message transmission format for the first instruction is shown in FIG4 , wherein the address rate field is two logical bits 0, and the message rate field is one logical bit 0. The target address field, write length field, and read length field are all 8 logical bits. The target address field is determined by the hardware design of the hardware partition and is generally 0x30 (0x represents a hexadecimal number). The write length field and the read length field are both 0x00. These fields are all completed by the kernel partition initiating the write operation.

[0213] Furthermore, the kernel partition is further configured to, after sending the interface signal to the first interface via the second interface, receive a response instruction generated by the hardware partition in response to the control instruction, the response instruction including the control instruction and a frame check field. The response instruction generated by the hardware partition in response to the control instruction includes, in addition to the control instruction information, the frame check field at the end of the control instruction, which is converted into information recognizable by the second interface, resulting in a field format as shown in FIG4 .

[0214] In an exemplary embodiment, the first interface includes a PECI interface, and the second interface includes a GPIO interface. That is, the kernel partition of the present application simulates a PECI signal via the GPIO interface and sends the PECI signal to the PECI interface of the hardware partition via the GPIO interface, thereby expanding the PECI link between the BMC and the host system. This further enables the BMC kernel partition to independently manage the hardware partitions of the server host system without performing hardware logic design on the BMC chip, further enabling a single BMC chip to independently monitor multiple hardware partitions of the host system.

[0215] In some embodiments, the first interface is a PECI interface, and the second interface is a GPIO interface. The PECI interface is an interface for information exchange between the BMC and the host system's processor. As an important interface in the server, the PECI interface is primarily responsible for obtaining the server's CPU temperature, power consumption, and fault status information of key unit modules such as the CPU, UPI link, memory controller, and PCIe link, providing strong support for server system health status monitoring, fault analysis, and location. The BMC has a relatively large number of GPIO interfaces, so there is no need to introduce additional hardware overhead when implementing the technical solution of this application.

[0216] In order to further expand the communication link between the BMC chip and the host system, and further achieve the effect of a BMC chip monitoring multiple hardware partitions of the host system, according to some other embodiments of the present application, as shown in Figure 7, one of the multiple kernel partitions 201 includes a third interface 203, and the other kernel partitions 201 respectively include the second interface 202. Each of the hardware partitions 101 includes the first interface 102. The third interface 203 is the same interface type as the first interface 102. The kernel partition is also used to send the control instruction to the corresponding first interface through the third interface. In this embodiment, one kernel partition is connected to the first interface of a hardware partition through the third interface, and the other kernel partitions are connected to the first interfaces of other hardware partitions through the second interface. That is, the kernel partition of the BMC monitors the hardware partitions one by one through the physical link formed by the third interface and the first interface, or through the physical link formed by the second interface and the first interface, further achieving the independent management of multiple hardware partitions by a BMC management unit, thereby further ensuring the independence of the fault management functions of different partition systems of the unified server platform.

[0217] In some embodiments, the third interface is also a PECI interface. In related art, a BMC chip has only one PECI interface, meaning that only one PECI link can be established with the host system through this PECI interface. The solution of the present application, in addition to retaining this PECI link, simulates the PECI protocol through multiple GPIO interfaces of the BMC chip, thereby establishing one-to-one PECI links with the PECI interfaces of other hardware partitions of the host system through the GPIO interfaces. This expands the PECI links and enables the BMC kernel partition to monitor hardware partitions on a one-to-one basis.

[0218] For optional examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementations, and this embodiment will not be described in detail here.

[0219] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0220] The above are merely optional embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may be subject to various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An interface communication method, characterized in that: The server host system includes a hardware partition, the baseboard management controller includes a kernel partition, and the kernel partition is used to manage the hardware partition. The method includes: generating a control instruction for controlling the hardware partition; Converting the control instruction into an interface signal conforming to a predetermined interface protocol, wherein the predetermined interface protocol is an interface protocol of a first interface of the hardware partition; The interface signal is sent to the first interface through a second interface, and the first interface and the second interface are of different interface types.

2. The method according to claim 1, characterized in that Converting the control instruction into an interface signal conforming to a predetermined interface protocol comprises: Determining, according to the predetermined interface protocol, a plurality of logic bit information corresponding to the control instruction; The interface signal is generated according to the plurality of logic bit information, the first timer and the second timer.

3. The method according to claim 2, characterized in that Generating the interface signal according to the plurality of logic bit information, the first timer and the second timer, comprising: Determine the timing duration of the first timer and the second timer according to the plurality of logic bit information; The interface signal is generated through the second interface according to the timing duration.

4. The method according to claim 3, characterized in that Determining the timing durations of the first timer and the second timer according to the plurality of logic bit information includes: Obtaining a first duration and a second duration corresponding to each of the logic bit information, wherein the first duration represents the duration during which the logic bit information is at a high level, and the second duration represents the total duration of the logic bit information, and different logic bit information corresponds to different first durations; The timing duration of the first timer is determined to be the first duration, and the timing duration of the second timer is determined to be the second duration.

5. The method according to claim 4, characterized in that Generating the interface signal through the second interface according to the timing duration includes: According to the first duration of the first timer and the second duration of the second timer, and in accordance with the order of the plurality of logic bit information, a sub-interface signal corresponding to each logic bit information is sequentially generated through the second interface to obtain the interface signal.

6. The method according to claim 5, characterized in that According to the first duration of the first timer and the second duration of the second timer, and in accordance with the order of the plurality of logic bit information, sequentially generating, through the second interface, a sub-interface signal corresponding to each of the logic bit information, to obtain the interface signal, includes: A control step of controlling the first timer and the second timer to start timing, and outputting a first signal through the second interface before the timing duration of the first timer reaches the first duration; an output step, after the timing duration of the first timer reaches the first duration and before the timing duration of the second timer reaches the second duration, outputting a second signal through the second interface to obtain the sub-interface signal composed of the first signal and the second signal; A counting step, when the timing duration of the second timer reaches the second duration, performing a timing count; A determination step is performed to determine whether the timing count value is less than the total number of the logic bit information. When the timing count value is less than the total number of the logic bit information, the control step, the output step and the counting step are performed in sequence according to the sorting until the timing count value is not less than the total number of the logic bit information, thereby obtaining the interface signal including multiple sub-interface signals.

7. The method according to claim 6, characterized in that The method further comprises: Before the control step, the output of the second interface is initialized to a low level state.

8. The method according to claim 6, characterized in that The control step comprises: Controlling the first timer and the second timer to start timing; Setting the output of the second interface to a high level state, and outputting the first signal in the high level state through the second interface; When the timing duration of the first timer reaches the first duration, the output of the first signal is stopped, and the output of the second interface is set to a low level.

9. The method according to claim 8, characterized in that When the timing duration of the first timer reaches the first duration, stopping the output of the first signal includes: When the timing duration of the first timer reaches the first duration, a first interrupt is triggered to stop outputting the first signal.

10. The method according to claim 6, characterized in that The output step comprises: When the timing duration of the first timer reaches the first duration, setting the output of the second interface to a low level state, and outputting the second signal in a low level state through the second interface; When the timing duration of the second timer reaches the second duration, the output of the second signal is stopped, and the output of the second interface is set to a high level to obtain the sub-interface signal.

11. The method according to claim 8, characterized in that When the timing duration of the second timer reaches the second duration, stopping the output of the second signal includes: When the timing duration of the second timer reaches the second duration, a second interrupt is triggered to stop outputting the second signal.

12. The method according to any one of claims 1 to 11, characterized in that The control instruction includes at least one of the following: A first instruction is used to determine whether the hardware partition exists; A second instruction is used to obtain the sensor temperature of the hardware partition; The third instruction is used to obtain the register data of the hardware partition.

13. The method according to any one of claims 1 to 11, characterized in that The data structure of the control instruction includes an address rate field, a target address field, a message rate field, a write length field and a read length field, wherein the address rate field represents the transmission rate of the address data, the target address field represents the address data of the hardware partition, and the message rate field represents the transmission rate of the message data.

14. The method according to any one of claims 1 to 11, characterized in that After sending the interface signal to the first interface through the second interface, the method further includes: A response instruction generated by the hardware partition in response to the control instruction is received, where the response instruction includes a control instruction and a frame check field.

15. The method according to any one of claims 1 to 11, characterized in that The first interface includes a PECI interface, and the second interface includes a GPI0 interface.

16. The method according to any one of claims 1 to 11, characterized in that There are multiple hardware partitions, there are multiple kernel partitions, one of the multiple kernel partitions includes the third interface, the other kernel partitions respectively include the second interface, each of the hardware partitions includes the first interface, the third interface is the same as the first interface, and the method further includes: The control instruction is sent to the corresponding first interface through the third interface.

17. An interface communication device, characterized in that: The server host system includes a hardware partition, the baseboard management controller includes a kernel partition, and the kernel partition is used to manage the hardware partition. The device includes: A generating unit, configured to generate a control instruction for controlling the hardware partition; a conversion unit, configured to convert the control instruction into an interface signal conforming to a predetermined interface protocol, wherein the predetermined interface protocol is an interface protocol of the first interface of the hardware partition; The first sending unit is configured to send the interface signal to the first interface through a second interface, and the first interface and the second interface are of different interface types.

18. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 16 when executed by a processor.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 16 are implemented.

20. A server, characterized in that: include: A host system, comprising a plurality of hardware partitions, wherein the hardware partitions include a first interface; The BMC includes a plurality of kernel partitions, the kernel partitions correspond to the hardware partitions one by one, at least some of the kernel partitions include a second interface, and the first interface and the second interface have different interface types, The kernel partition is used to generate control instructions for controlling the hardware partition; convert the control instructions into interface signals that comply with a predetermined interface protocol, wherein the predetermined interface protocol is the interface protocol of the first interface of the hardware partition; and send the interface signal to the first interface via the second interface.

21. The server according to claim 20, characterized in that The kernel partition is also used to determine a plurality of logic bit information corresponding to the control instruction according to the predetermined interface protocol; and to generate the interface signal according to the plurality of logic bit information, the first timer and the second timer.

22. The server according to claim 21, characterized in that The core partition is also used to determine the timing duration of the first timer and the second timer according to the plurality of logic bit information; and generate the interface signal through the second interface according to the timing duration.

23. The server according to claim 22, characterized in that The kernel partition is also used to obtain a first duration and a second duration corresponding to each of the logical bit information, wherein the first duration represents the duration during which the logical bit information is at a high level, and the second duration represents the total duration of the logical bit information, and different logical bit information corresponds to different first durations; determine the timing duration of the first timer to be the first duration, and determine the timing duration of the second timer to be the second duration.

24. The server according to claim 23, characterized in that The kernel partition is also used to generate a sub-interface signal corresponding to each logical bit information in sequence through the second interface according to the first duration of the first timer and the second duration of the second timer, in accordance with the order of the multiple logical bit information, to obtain the interface signal.

25. The server according to claim 20, characterized in that One of the multiple kernel partitions includes a third interface, the third interface is the same interface type as the first interface, all of the kernel partitions except those including the third interface include the second interface, and the kernel partition including the third interface is used to send the control instruction to the corresponding first interface through the third interface.

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