Display substrate and display panel

Abstract

The present disclosure provides a display substrate and a display panel. The display substrate comprises a display area and a first frame area. The display substrate comprises: a base substrate; a plurality of first voltage lines and a plurality of second voltage lines, which are arranged on the base substrate in the first frame area, one second voltage line being arranged between two adjacent first voltage lines in a first direction, the plurality of first voltage lines being electrically connected to each other, and the plurality of second voltage lines being electrically connected to each other; and a circuit board arranged on the base substrate in the first frame area, wherein the circuit board is arranged on the sides of the first voltage lines and the second voltage lines away from the display area; and the circuit board is electrically connected to the plurality of first voltage lines and is used for providing first voltage signals for the first voltage lines. The present disclosure has the function of splitting first voltage signals, thus avoiding the risk of burning caused by the high current density of the first voltage signals on first voltage lines on the left side and the right side under conditions of high brightness.

Description

Display substrate and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311088419.2 filed in China on August 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display panel. Background Art

[0004] In the related art, a small number of first voltage lines are used in the lower frame area of ​​a display product. In a high-brightness situation, there is a risk of burns due to the high current density of the first voltage signal on the first voltage line.

[0005] Summary of the Invention

[0006] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising a display area and a first frame area; the display substrate comprises:

[0007] substrate;

[0008] a plurality of first voltage lines and a plurality of second voltage lines provided on the base substrate in the first frame region; a second voltage line provided between two adjacent first voltage lines in the first direction; the plurality of first voltage lines being electrically connected to each other, and the plurality of second voltage lines being electrically connected to each other;

[0009] A circuit board is arranged on the base substrate in the first frame area, and the circuit board is arranged on the side of the first voltage line and the second voltage line away from the display area; the circuit board is electrically connected to the multiple first voltage lines respectively, and is used to provide a first voltage signal to the first voltage line.

[0010] Optionally, the display substrate includes at least three second voltage lines arranged in the first frame area; a first voltage line is arranged between the second voltage lines adjacent to each other in the first direction;

[0011] The circuit board is electrically connected to the at least three second voltage lines respectively, and is used to provide a second voltage signal for the second voltage lines.

[0012] Optionally, the display substrate includes at least three first voltage lines arranged in the first frame area;

[0013] The at least three first voltage lines and the plurality of second voltage lines are sequentially arranged along a first direction.

[0014] Optionally, the display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line and a third first voltage line arranged in sequence along the first direction in the first frame area; or,

[0015] The display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line and a fourth first voltage line arranged in sequence along a first direction in the first frame area.

[0016] Optionally, the first border region includes a bending region and a first region; the first region is located on a side of the bending region close to the display region; the display substrate further includes a first metal layer provided on the base substrate; the display substrate further includes a second voltage connection line formed in the first metal layer, the second voltage connection line extending along a first direction, and the second voltage connection line is provided in the first region;

[0017] The second voltage lines are all connected to the second voltage communication line, so that the plurality of second voltage lines are electrically connected to each other.

[0018] Optionally, the display substrate further includes a first side region and a second side region; the first region includes an arc region;

[0019] The first side area is provided at a first side of the display area, the second side area is provided at a second side of the display area, the first side and the second side are opposite sides, and the arc area is an area of ​​the first area close to the first side area or the second side area;

[0020] The display substrate includes a first voltage line partially disposed in the arc area.

[0021] Optionally, the display substrate further includes a second metal layer disposed on the first metal layer away from the base substrate;

[0022] The display substrate further includes a plurality of second voltage connection lines arranged in the arc region and extending along a second direction; the second voltage connection lines are formed in a second metal layer; the first direction intersects the second direction;

[0023] The second voltage connection line and the second voltage communication line are electrically connected through a via.

[0024] Optionally, the display substrate further includes a first voltage connection line extending along a second direction, and a plurality of first conductive connection portions electrically connected to ends of the first voltage connection line away from the display area; the first voltage connection line and the first conductive connection portions are both disposed in the arc region; the first direction intersects the second direction; and the first voltage connection line and the first conductive connection portions are both formed in the second metal layer;

[0025] The display substrate further includes a first voltage line portion disposed in the arc region, the first voltage line portion being included in a first voltage line; the first voltage line portion extending along a first direction and formed in a first metal layer; an orthographic projection of the first voltage line portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate;

[0026] The first conductive connection portion is electrically connected to the first voltage line portion through a via hole.

[0027] Optionally, the second voltage connection lines and the first conductive connection portions are alternately arranged along a first direction.

[0028] Optionally, the display substrate further includes a plurality of first connecting lines and a plurality of second connecting lines disposed in the arc region, wherein the first connecting lines and the second connecting lines both extend along the second direction and are both formed in the second metal layer;

[0029] The second connecting line is arranged on a side of the first connecting line away from the display area; at least two of the first connecting lines are electrically connected to one of the second connecting lines; the first direction intersects the second direction;

[0030] The second connection line is electrically connected to the second voltage communication line through a via.

[0031] Optionally, the display substrate further includes a plurality of first voltage connection lines arranged in the arc region and extending along the second direction, and a plurality of second conductive connection portions electrically connected to ends of the first voltage connection lines away from the display region;

[0032] The first direction intersects the second direction; the first voltage connection line and the second conductive connection portion are both formed in the second metal layer;

[0033] The display substrate further includes a first voltage line portion disposed in the arc region, the first voltage line portion being included in a first voltage line; the first voltage line portion extending along a first direction, the first voltage line portion being formed in a first metal layer; an orthographic projection of the first voltage line portion on the base substrate at least partially overlapping with an orthographic projection of the second conductive connection portion on the base substrate;

[0034] The second conductive connection portion is electrically connected to the first voltage line portion through a via hole.

[0035] Optionally, the second connecting lines and the second conductive connecting portions are alternately arranged along the first direction;

[0036] The area of ​​the orthographic projection of the second conductive connection portion on the base substrate is greater than or equal to 500 μm 2 Less than or equal to 1200 μm 2 .

[0037] Optionally, the orthographic projection of the second voltage connection line on the base substrate is arranged on a side of the orthographic projection of the first voltage line portion on the base substrate away from the display area.

[0038] Optionally, in the arc region, the first voltage line further includes a second voltage line portion formed in the second metal layer, a third voltage line portion formed in the first metal layer, and a fourth voltage line portion formed in the conductive layer;

[0039] The second voltage line portion is electrically connected to the first voltage line portion through a via hole, and an orthographic projection of the first voltage line portion on the base substrate at least partially overlaps with an orthographic projection of the second voltage line portion on the base substrate;

[0040] The orthographic projection of the third voltage line portion on the base substrate is arranged on a side of the orthographic projection of the first voltage line portion on the base substrate away from the display area;

[0041] The orthographic projection of the fourth voltage line portion on the substrate at least partially overlaps with the orthographic projection of the second voltage line portion on the substrate, and the orthographic projection of the fourth voltage line portion on the substrate at least partially overlaps with the orthographic projection of the third voltage line portion on the substrate, and the fourth voltage line portion is electrically connected to the second voltage line portion and the third voltage line portion respectively, so that the second voltage line portion is electrically connected to the third voltage line portion.

[0042] Optionally, the area of ​​the first region excluding the arc region is a middle region; in the middle region, the first voltage line includes a fifth voltage line portion, a sixth voltage line portion, a seventh voltage line portion, an eighth voltage line portion, and a ninth voltage line portion;

[0043] The fifth voltage line portion, the sixth voltage line portion, the seventh voltage line portion, the eighth voltage line portion, and the ninth voltage line portion all extend along the first direction;

[0044] The fifth voltage line portion and the sixth voltage line portion are formed in the first metal layer, the seventh voltage line portion and the eighth voltage line portion are formed in the second metal layer, and the ninth voltage line portion is formed in the conductive layer;

[0045] The orthographic projection of the seventh voltage line portion on the base substrate, the orthographic projection of the ninth voltage line portion on the base substrate, and the orthographic projection of the second voltage connection line on the base substrate at least partially overlap;

[0046] The ninth voltage line portion, the seventh voltage line portion, the fifth voltage line portion, and the sixth voltage line portion are electrically connected;

[0047] The seventh voltage line portion is electrically connected to the eighth voltage line portion.

[0048] Optionally, a length of the second voltage communication line along the second direction is greater than or equal to 20 μm and less than or equal to 120 μm.

[0049] Optionally, the seventh voltage line portion is electrically connected to the eighth voltage line portion through a via hole, and at the via hole, the seventh voltage line portion is in direct contact with the eighth voltage line portion, and the area of ​​direct contact between the seventh voltage line portion and the eighth voltage line portion is greater than or equal to 40000 μm 2 Less than or equal to 100,000 μm 2 .

[0050] In a second aspect, an embodiment of the present disclosure provides a display panel including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG1 is a layout diagram of a first border region of a display substrate according to at least one embodiment of the present disclosure;

[0052] FIG2A is a layout diagram of the left half of FIG1 ;

[0053] FIG2B is a layout diagram of the first gate metal layer in FIG2A ;

[0054] FIG2C is a layout diagram of the second gate metal layer in FIG2B ;

[0055] FIG2D is a layout diagram of the first source / drain metal layer in FIG2A ;

[0056] FIG2E is a layout diagram of the second source / drain metal layer in FIG1 ;

[0057] FIG2F is a layout diagram of the anode layer in FIG2B ;

[0058] 3 is a layout diagram of a first border region of a display substrate according to at least one embodiment of the present disclosure;

[0059] 4A is a layout diagram of a first border region of a display substrate according to at least one embodiment of the present disclosure;

[0060] 4B is a layout diagram of a first border region of a display substrate according to at least one embodiment of the present disclosure;

[0061] FIG5 is a schematic diagram showing FIG4A with a first dotted frame X1 and a second dotted frame X2 added thereto;

[0062] FIG6 is a layout diagram of the portion within the first dotted box X1 in FIG5 ;

[0063] FIG7 is a layout diagram of the first source / drain metal layer in FIG6 ;

[0064] FIG8 is a layout diagram of the second source / drain metal layer in FIG6 ;

[0065] FIG9 is a layout diagram of the anode layer in FIG6 ;

[0066] FIG10 is a layout diagram of the third region Q3 in FIG6 ;

[0067] FIG11 is a cross-sectional view of AA' in FIG10;

[0068] FIG12 is a BB' cross-sectional view in FIG10;

[0069] 13 is a layout diagram of at least one embodiment of a third area of ​​the display substrate in the first arc area;

[0070] FIG14 is a layout diagram of the first source / drain metal layer in FIG13 ;

[0071] FIG15 is a layout diagram of the second source / drain metal layer in FIG13 ;

[0072] FIG16 is a layout diagram of the anode layer in FIG13;

[0073] FIG17 is a layout diagram of the portion within the second dotted box X2 in FIG5 ;

[0074] FIG18 is a layout diagram of the first source / drain metal layer in FIG17 ;

[0075] FIG19 is a layout diagram of the second source / drain metal layer in FIG17 ;

[0076] FIG20 is a layout diagram of the anode layer in FIG17;

[0077] FIG21 is a cross-sectional view of FIG17 'CC;

[0078] FIG22 is a sectional view DD' in FIG17;

[0079] FIG23 is a layout diagram of a first border region of a display substrate according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0081] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0082] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0083] The display substrate according to the embodiment of the present disclosure includes a display area and a first frame area; the display substrate includes:

[0084] substrate;

[0085] a plurality of first voltage lines and a plurality of second voltage lines provided on the base substrate in the first frame region; a second voltage line provided between two adjacent first voltage lines in the first direction; the plurality of first voltage lines being electrically connected to each other, and the plurality of second voltage lines being electrically connected to each other;

[0086] A circuit board is arranged on the base substrate in the first frame area, and the circuit board is arranged on the side of the first voltage line and the second voltage line away from the display area; the circuit board is electrically connected to the multiple first voltage lines respectively, and is used to provide a first voltage signal to the first voltage line.

[0087] Optionally, the first direction may be a horizontal direction.

[0088] In at least one embodiment of the present disclosure, the display substrate may include a base substrate, a plurality of first voltage lines, a plurality of second voltage lines, and a circuit board.

[0089] In a display product using SIP (VSS In Panel, a low voltage line is set inside the panel) technology, in order to reduce the current density of the first voltage lines on the left and right sides (the first voltage line can be a low voltage line), reduce the voltage drop on the first voltage line, and improve the brightness uniformity, the embodiment of the present disclosure adds a first voltage line in the first frame area of ​​the display substrate, and sets a plurality of first voltage lines electrically connected to each other in the first frame area. The plurality of first voltage lines are respectively electrically connected to the circuit board to receive the first voltage signal provided by the circuit board, and have a shunting effect on the first voltage signal, thereby avoiding the risk of burns caused by the high current density of the first voltage signals on the first voltage lines on the left and right sides under high brightness conditions.

[0090] In a specific implementation, the display substrate may further include gate lines disposed in the display area, and the gate lines extend in a horizontal direction.

[0091] Optionally, the additional first voltage line may be provided in the central area of ​​the first frame area.

[0092] In the first frame area, at least one second voltage line is provided between two adjacent first voltage lines.

[0093] In at least one embodiment of the present disclosure, the display substrate includes at least three second voltage lines arranged in the first frame area; a first voltage line is arranged between the second voltage lines adjacent to each other in the first direction;

[0094] The circuit board is electrically connected to the at least three second voltage lines respectively, and is used to provide a second voltage signal for the second voltage lines.

[0095] In specific implementation, a second voltage line can be added at the center position of the first border area, and a first voltage line can be added on the left and right sides of the second voltage line respectively. The newly added first voltage line and the second voltage line are electrically connected to the circuit board respectively. At least one embodiment of the present disclosure can simultaneously shunt the first voltage signal and the second voltage signal, reduce the load of the first voltage line and the load of the second voltage line, and improve the uniformity of display brightness.

[0096] Optionally, the display substrate includes at least three first voltage lines arranged in the first frame area;

[0097] The at least three first voltage lines and the plurality of second voltage lines are sequentially arranged along a first direction.

[0098] In a specific implementation, the display substrate may include at least three first voltage lines disposed in the frame area, and the at least three first voltage lines and the plurality of second voltage lines are sequentially arranged along a first direction.

[0099] In at least one embodiment of the present disclosure, the display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, and a third first voltage line arranged in sequence along a first direction in the first frame area; or,

[0100] The display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line and a fourth first voltage line arranged in sequence along a first direction in the first frame area.

[0101] In a specific implementation, in the first frame area, the display substrate may include a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, and a third first voltage line sequentially arranged along the horizontal direction;

[0102] The first first voltage line, the second first voltage line, and the third first voltage line are electrically connected to each other, and the first second voltage line and the second second voltage line are electrically connected to each other;

[0103] The first first voltage line, the first second voltage line, the second first voltage line, the second second voltage line and the third first voltage line are electrically connected to the circuit board respectively, and are used to receive voltage signals provided by the circuit board.

[0104] The second first voltage line located in the middle is electrically connected to the circuit board through two ports, respectively, for respectively receiving the first voltage signal provided by the circuit board, so as to further realize the diversion of the first voltage signal.

[0105] In a specific implementation, in the first frame area, the display substrate may include a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line and a fourth first voltage line arranged in sequence along the first direction in the first frame area, the first first voltage line, the second first voltage line, the third first voltage line and the fourth first voltage line are electrically connected to each other, the first second voltage line, the second second voltage line and the third second voltage line are electrically connected to each other, the first first voltage line, the first second voltage line, the second first voltage line, the second second voltage line, the third first voltage line, the third second voltage line and the fourth first voltage line are respectively electrically connected to the circuit board for receiving voltage signals provided by the circuit board.

[0106] Among them, the second second voltage line located in the middle part of the first frame area is electrically connected to the circuit board through two ports, respectively, for respectively receiving the first voltage signal provided by the circuit board, so as to further realize the diversion of the first voltage signal.

[0107] In at least one embodiment of the present disclosure, the first frame area may be a lower frame area.

[0108] FIG1 is a layout diagram of a first border region of a display substrate according to at least one embodiment of the present disclosure.

[0109] In FIG1 , the first voltage line is labeled VSS1 , the first voltage line is labeled VDD1 , the second voltage line is labeled VSS2 , the second voltage line is labeled VDD2 , and the third voltage line is labeled VSS3 .

[0110] The element labeled I0 is a driving integrated circuit, and the element labeled F1 is a flexible circuit board. The flexible circuit board F1 is used to provide a first voltage signal and a second voltage signal.

[0111] In at least one embodiment of the present disclosure, the first voltage line may be a low voltage line, and the second voltage line may be a high voltage line, but the present invention is not limited thereto.

[0112] VSS1, VSS2 and VSS3 are respectively electrically connected to different ports of the flexible circuit board F1, and are used to receive a first voltage signal provided by the flexible circuit board F1;

[0113] VDD1 and VDD2 are electrically connected to different ports of the flexible circuit board F1 respectively, and are used to receive a second voltage signal provided by the flexible circuit board F1.

[0114] FIG. 2A is a layout diagram of the left half of FIG. 1 , wherein X0 is the center line of the lower frame region of the display substrate.

[0115] Figure 2B is a layout diagram of the first gate metal layer in Figure 2A, Figure 2C is a layout diagram of the second gate metal layer in Figure 2B, Figure 2D is a layout diagram of the first source and drain metal layer in Figure 2A, Figure 2E is a layout diagram of the second source and drain metal layer in Figure 1, and Figure 2F is a layout diagram of the anode layer in Figure 2B.

[0116] In FIG. 2B , GA1 is a first GOA (Gate On Array, a gate driving circuit provided on an array substrate) signal line region. GOA signal lines are provided in GA1 .

[0117] In FIG. 2C , the second GOA signal line area is labeled GA2 , and a GOA signal line is provided in GA2 .

[0118] In FIG2D , the area labeled GA3 is a second GOA signal line area, and a GOA signal line is provided in GA3 .

[0119] In FIG. 2D , VSS11 is a first signal line portion included in VSS1 , VDD11 is a first signal line portion included in VDD1 , and VSS21 is a first signal line portion included in VSS2 .

[0120] In FIG. 2E , VSS12 is a second signal line portion included in VSS1 , VDD12 is a second signal line portion included in VDD1 , and VSS22 is a second signal line portion included in VSS2 .

[0121] In FIG. 2F , the pattern labeled Y1 is an anode.

[0122] In at least one embodiment of the present disclosure, the first frame region includes a bending region and a first region; the first region is located on a side of the bending region close to the display region; the display substrate further includes a first metal layer provided on the base substrate;

[0123] The display substrate further includes a second voltage connection line formed on the first metal layer, the second voltage connection line extending along a first direction, and the second voltage connection line is disposed in the first area;

[0124] The second voltage lines are all connected to the second voltage communication line, so that the plurality of second voltage lines are electrically connected to each other.

[0125] In FIG3 , the area labeled Q1 is the first area, the area labeled W1 is the bending area, and the area labeled B1 is the first frame area.

[0126] Optionally, the display substrate further includes a first side region and a second side region; the first region includes an arc region;

[0127] The first side area is provided at a first side of the display area, the second side area is provided at a second side of the display area, the first side and the second side are opposite sides, and the arc area is an area of ​​the first area close to the first side area or the second side area;

[0128] The display substrate includes a first voltage line partially disposed in the arc area.

[0129] In FIG4A , the first side region is labeled C1 , the second side region is labeled C2 , the first arc region is labeled R1 , and the second arc region is labeled R2 .

[0130] In FIG. 4A , a portion of the first voltage line V1 is located in the first arc region R1 .

[0131] In at least one embodiment of the present disclosure, the first side area may be an area arranged on the left side of the display area, and the second side area may be an area arranged on the right side of the display area. A GOA circuit may be arranged in the first side area and / or the second side area.

[0132] In FIG. 4B , the area labeled A0 is the display area.

[0133] In at least one embodiment of the present disclosure, the display substrate further includes a second metal layer disposed on the first metal layer away from the base substrate;

[0134] The display substrate further includes a plurality of second voltage connection lines arranged in the arc region and extending along a second direction; the second voltage connection lines are formed in a second metal layer; the first direction intersects the second direction;

[0135] The second voltage connection line and the second voltage communication line are electrically connected through a via.

[0136] Optionally, the first metal layer may be a first source-drain metal layer, the second metal layer may be a second source-drain metal layer, and the conductive layer may be an anode layer.

[0137] In at least one embodiment of the present disclosure, the first direction may be a horizontal direction, and the second direction may be a vertical direction, but the present invention is not limited thereto.

[0138] FIG5 is a schematic diagram showing FIG4A with a first dotted frame X1 and a second dotted frame X2 added thereto.

[0139] FIG. 6 is a layout diagram of the portion within the first dotted-line frame X1 in FIG. 5 .

[0140] 7 is a layout diagram of the first source-drain metal layer in FIG. 6 , FIG. 8 is a layout diagram of the second source-drain metal layer in FIG. 6 , and FIG. 9 is a layout diagram of the anode layer in FIG. 6 .

[0141] In FIG8 , the second voltage connection line is labeled L02 , and the second voltage connection line L02 extends in a vertical direction. L02 is formed in the second source-drain metal layer;

[0142] In FIG7 , the second voltage connection line is labeled T02 , and the second voltage connection line T02 is formed in the first source-drain metal layer, and the second voltage connection line T02 extends in the horizontal direction;

[0143] The second voltage connection line L02 is electrically connected to the second voltage communication line T02 through a via.

[0144] In at least one embodiment of the present disclosure, the display substrate further includes a first voltage connection line extending along a second direction and a plurality of first conductive connection portions electrically connected to ends of the first voltage connection line away from the display area; the first voltage connection line and the first conductive connection portions are both disposed in the arc region; the first direction intersects the second direction; and the first voltage connection line and the first conductive connection portions are both formed in the second metal layer;

[0145] The display substrate further includes a first voltage line portion disposed in the arc region, the first voltage line portion being included in a first voltage line; the first voltage line portion extending along a first direction and formed in a first metal layer; an orthographic projection of the first voltage line portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate;

[0146] The first conductive connection portion is electrically connected to the first voltage line portion through a via hole.

[0147] As shown in FIG8 , the first voltage connection line is labeled L01 , and the first conductive connection portion is labeled DL1 ;

[0148] The first voltage connection line L01 extends in a vertical direction. The first conductive connection portion DL1 is electrically connected to an end of the first voltage connection line L01 away from the display area. Both L01 and DL1 are formed in the second source / drain metal layer.

[0149] As shown in FIG. 7 , the first voltage line portion L11 is labeled as the first voltage line portion, and the first voltage line portion L11 extends in the horizontal direction.

[0150] As shown in FIG6 to FIG9 , the orthographic projection of the first voltage line portion L11 on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion DL1 on the base substrate;

[0151] L11 and DL1 are electrically connected through a via.

[0152] Optionally, the second voltage connection lines and the first conductive connection portions are alternately arranged along a first direction.

[0153] As shown in FIG. 8 , the second voltage connection lines L02 and the first conductive connection portions DL1 are alternately arranged along the horizontal direction.

[0154] In at least one embodiment of the present disclosure, the orthographic projection of the second voltage connection line on the base substrate is arranged on a side of the orthographic projection of the first voltage line portion on the base substrate away from the display area.

[0155] As shown in FIG6 to FIG9 , the orthographic projection of the second voltage connection line T02 on the base substrate is arranged on a side of the orthographic projection of the first voltage line portion L11 on the base substrate away from the display area.

[0156] In at least one embodiment of the present disclosure, the first voltage lines may be electrically connected to each other through a voltage line portion provided on the anode layer.

[0157] In at least one embodiment of the present disclosure, in the arc region, the first voltage line further includes a second voltage line portion formed in the second metal layer, a third voltage line portion formed in the first metal layer, and a fourth voltage line portion formed in the conductive layer;

[0158] The second voltage line portion is electrically connected to the first voltage line portion through a via hole, and an orthographic projection of the first voltage line portion on the base substrate at least partially overlaps with an orthographic projection of the second voltage line portion on the base substrate;

[0159] The orthographic projection of the third voltage line portion on the base substrate is arranged on a side of the orthographic projection of the first voltage line portion on the base substrate away from the display area;

[0160] The orthographic projection of the fourth voltage line portion on the substrate at least partially overlaps with the orthographic projection of the second voltage line portion on the substrate, and the orthographic projection of the fourth voltage line portion on the substrate at least partially overlaps with the orthographic projection of the third voltage line portion on the substrate, and the fourth voltage line portion is electrically connected to the second voltage line portion and the third voltage line portion respectively, so that the second voltage line portion is electrically connected to the third voltage line portion.

[0161] As shown in FIG6 to FIG9 , in the first arc region, the first voltage line further includes a second voltage line portion L12 formed in the second source / drain metal layer, a third voltage line portion L13 formed in the first source / drain metal layer, and a fourth voltage line portion L14 formed in the conductive layer;

[0162] The second voltage line portion L12 is electrically connected to the first voltage line portion L11 through a via hole, and an orthographic projection of the first voltage line portion L11 on the base substrate at least partially overlaps with an orthographic projection of the second voltage line portion L12 on the base substrate;

[0163] The orthographic projection of the third voltage line portion L13 on the base substrate is arranged on a side of the orthographic projection of the first voltage line portion L11 on the base substrate away from the display area;

[0164] The orthographic projection of the fourth voltage line portion L14 on the substrate at least partially overlaps with the orthographic projection of the second voltage line portion L12 on the substrate, and the orthographic projection of the fourth voltage line portion L14 on the substrate at least partially overlaps with the orthographic projection of the third voltage line portion L13 on the substrate. The fourth voltage line portion L14 is electrically connected to the second voltage line portion L12 and the third voltage line portion L13 respectively, so that the second voltage line portion L12 is electrically connected to the third voltage line portion L13.

[0165] FIG10 is a layout diagram of the third region Q3 in FIG6 .

[0166] FIG11 is a cross-sectional view taken along line AA′ in FIG10 , and FIG12 is a cross-sectional view taken along line BB′ in FIG10 .

[0167] In FIG. 11 and FIG. 12 , the reference numeral 11 is a first source-drain metal layer, the reference numeral 12 is a second source-drain metal layer, the reference numeral J1 is a first insulating layer, and the reference numeral J2 is a second insulating layer.

[0168] Optionally, the first insulating layer J1 may be a passivation layer, and the second insulating layer J2 may be a planarization layer.

[0169] In FIG. 7 , the line labeled VI1 is a first initial voltage line, and the line labeled VI2 is a second initial voltage line. VI1 and VI2 extend in the horizontal direction.

[0170] As shown in FIG6-FIG9, the second voltage connection line L02 crosses the first initial voltage line VI1, the second initial voltage line VI2, the first voltage line portion L11 and is electrically connected to the second voltage communication line T02;

[0171] The first voltage connection line L01 crosses the first initial voltage line VI1 and the second initial voltage line VI2 and is electrically connected to the first conductive connection part DL1. The DL1 formed on the second source-drain metal layer is electrically connected to the first voltage line part L11 formed on the first source-drain metal layer through a via.

[0172] In at least one embodiment of the present disclosure, a double SD layer process is used to implement a scheme for overlapping the first voltage line and the second voltage line in the lower frame area, thereby reducing one mask.

[0173] In at least one embodiment of the present disclosure, the display substrate further includes a plurality of first connecting lines and a plurality of second connecting lines disposed in the arc region, wherein the first connecting lines and the second connecting lines both extend along the second direction and are both formed in the second metal layer;

[0174] The second connecting line is arranged on a side of the first connecting line away from the display area; at least two of the first connecting lines are electrically connected to one of the second connecting lines; the first direction intersects the second direction;

[0175] The second connection line is electrically connected to the second voltage communication line through a via.

[0176] In a specific implementation, the display substrate may include a plurality of first connecting lines and second connecting lines extending in a vertical direction and arranged in an arc area; the first connecting lines and the second connecting lines are both formed in a second source-drain metal layer; the second connecting lines are arranged below the first connecting lines, at least two first connecting lines are electrically connected to one of the second connecting lines, and the second connecting lines are electrically connected to the second voltage connection line through a via.

[0177] In actual operation, the first connecting line may be electrically connected to a signal line disposed in the display area and used to transmit a second voltage signal.

[0178] In at least one embodiment of the present disclosure, the display substrate further includes a plurality of first voltage connection lines disposed in the arc region and extending along the second direction, and a plurality of second conductive connection portions electrically connected to ends of the first voltage connection lines away from the display region;

[0179] The first direction intersects the second direction; the first voltage connection line and the second conductive connection portion are both formed in the second metal layer;

[0180] The display substrate further includes a first voltage line portion disposed in the arc region, the first voltage line portion being included in a first voltage line; the first voltage line portion extending along a first direction, the first voltage line portion being formed in a first metal layer; an orthographic projection of the first voltage line portion on the base substrate at least partially overlapping with an orthographic projection of the second conductive connection portion on the base substrate;

[0181] The second conductive connection portion is electrically connected to the first voltage line portion through a via hole.

[0182] Optionally, the second connecting lines and the second conductive connecting portions are alternately arranged along the first direction;

[0183] The area of ​​the orthographic projection of the second conductive connection portion on the base substrate is greater than or equal to 500 μm 2 Less than or equal to 1200 μm 2 For example, the area of ​​the orthographic projection of the second conductive connection portion on the base substrate may be 800 μm 2 .

[0184] FIG. 13 is a layout diagram of at least one embodiment of a third area of ​​the display substrate within the first arc area.

[0185] 14 is a layout diagram of the first source-drain metal layer in FIG. 13 , FIG. 15 is a layout diagram of the second source-drain metal layer in FIG. 13 , and FIG. 16 is a layout diagram of the anode layer in FIG. 13 .

[0186] In FIG15 , the line labeled LX11 is the first first connection line, the line labeled LX21 is the second first connection line, and the line labeled LX2 is the second connection line;

[0187] LX11, LX21 and LX2 all extend in the vertical direction;

[0188] LX2 is set on the side of LX11 and LX21 away from the display area;

[0189] LX11 and LX21 are electrically connected, and LX2 is electrically connected to LX11 and LX21 respectively.

[0190] In FIG14 , the line labeled T02 is the second voltage connection line;

[0191] As shown in FIG13 to FIG16 , LX2 is electrically connected to T02 through a via.

[0192] In FIG14 , the line labeled VI1 is a first initial voltage line, the line labeled VI2 is a second initial voltage line, and VI1 , VI2 , and T02 all extend in the horizontal direction.

[0193] As shown in FIG15 , the first voltage connection line is labeled L01 , the second conductive connection portion is labeled DL2 , and the second voltage line portion is labeled L12 .

[0194] DL2 is electrically connected to the end of L01 away from the display area;

[0195] L01 and DL2 are both formed in the second source and drain metal layer;

[0196] As shown in FIG14 , the first voltage line portion L11 is marked as L11 and extends in the horizontal direction.

[0197] The orthographic projection of the first voltage line portion L11 on the base substrate at least partially overlaps with the orthographic projection of the second conductive connection portion DL2 on the base substrate;

[0198] The second conductive connection portion DL2 is electrically connected to the first voltage line portion L11 through a via hole.

[0199] As shown in FIG15 , the orthographic projection area of ​​the second conductive connection portion DL2 on the base substrate is greater than or equal to 500 μm 2 Less than or equal to 1200 μm 2 , so as to increase the opening area of ​​the first voltage line segment overlap.

[0200] In FIG. 16 , L14 is a fourth voltage line portion.

[0201] As shown in FIG13 to FIG16 , the second voltage line portion L12 is electrically connected to the first voltage line portion L11 through a via, and the orthographic projection of the first voltage line portion L11 on the base substrate at least partially overlaps with the orthographic projection of the second voltage line portion L12 on the base substrate;

[0202] An orthographic projection of the fourth voltage line portion L14 on the base substrate at least partially overlaps with an orthographic projection of the second voltage line portion L12 on the base substrate, and the fourth voltage line portion L14 is electrically connected to the second voltage line portion L12.

[0203] In at least one embodiment shown in FIG. 13 to FIG. 16 , the overlapping area between each connection line for transmitting the second voltage signal and the first voltage line portion L11 can be reduced.

[0204] In at least one embodiment of the present disclosure, the area of ​​the first region other than the arc region is a middle region; in the middle region, the first voltage line includes a fifth voltage line portion, a sixth voltage line portion, a seventh voltage line portion, an eighth voltage line portion, and a ninth voltage line portion;

[0205] The fifth voltage line portion, the sixth voltage line portion, the seventh voltage line portion, the eighth voltage line portion, and the ninth voltage line portion all extend along the first direction;

[0206] The fifth voltage line portion and the sixth voltage line portion are formed in the first metal layer, the seventh voltage line portion and the eighth voltage line portion are formed in the second metal layer, and the ninth voltage line portion is formed in the conductive layer;

[0207] The orthographic projection of the seventh voltage line portion on the base substrate, the orthographic projection of the ninth voltage line portion on the base substrate, and the orthographic projection of the second voltage connection line on the base substrate at least partially overlap;

[0208] The ninth voltage line portion, the seventh voltage line portion, the fifth voltage line portion, and the sixth voltage line portion are electrically connected;

[0209] The seventh voltage line portion is electrically connected to the eighth voltage line portion.

[0210] At least one embodiment of the present disclosure can complete the connection between the first voltage line and the second voltage line through two source-drain metal layers, thereby reducing the number of masks used.

[0211] Optionally, the length of the second voltage communication line along the second direction is greater than or equal to 20 μm and less than or equal to 120 μm. For example, the length of the second voltage communication line along the second direction may be 80 μm.

[0212] During specific implementation, the line width of the second voltage connection line can be reduced, thereby reducing the overlapping area between the first voltage line and the second voltage line.

[0213] In at least one embodiment of the present disclosure, the seventh voltage line portion is electrically connected to the eighth voltage line portion through a via hole, and at the via hole, the seventh voltage line portion is in direct contact with the eighth voltage line portion, and the area of ​​direct contact between the seventh voltage line portion and the eighth voltage line portion is greater than or equal to 40000 μm 2 Less than or equal to 100,000 μm 2 For example, the area where the seventh voltage line portion directly contacts the eighth voltage line portion may be equal to 52500 μm 2 .

[0214] In the specific implementation, at the via hole, the area of ​​direct contact between the seventh voltage line portion and the eighth voltage line portion is larger, so as to maximize the overlapping area of ​​the first source-drain metal layer and the second source-drain metal layer on the basis of avoiding the organic clearance area inside and outside the DAM (blocking wall).

[0215] FIG. 17 is a layout diagram of the portion within the second dotted-line frame X2 in FIG. 5 .

[0216] FIG18 is a layout diagram of the first source-drain metal layer in FIG17 , FIG19 is a layout diagram of the second source-drain metal layer in FIG17 , and FIG20 is a layout diagram of the anode layer in FIG17 .

[0217] In at least one embodiment of the present disclosure, the area included in the first area except the arc area is the middle area; in FIG4 , the area labeled Z1 is the middle area;

[0218] As shown in FIG17 to FIG20 , in the middle area, the first voltage line includes a fifth voltage line portion L15 , a sixth voltage line portion L16 , a seventh voltage line portion L17 , an eighth voltage line portion L18 , and a ninth voltage line portion L19 ;

[0219] The fifth voltage line portion L15, the sixth voltage line portion L16, the seventh voltage line portion L17, the eighth voltage line portion L18 and the ninth voltage line portion L19 all extend along the first direction;

[0220] The fifth voltage line portion L15 and the sixth voltage line portion L16 are formed in the first source-drain metal layer, the seventh voltage line portion L17 and the eighth voltage line portion L18 are formed in the second source-drain metal layer, and the ninth voltage line portion L19 is formed in the conductive layer;

[0221] The orthographic projection of the seventh voltage line portion L17 on the base substrate, the orthographic projection of the ninth voltage line portion L19 on the base substrate, and the orthographic projection of the second voltage connection line T02 on the base substrate at least partially overlap;

[0222] The ninth voltage line portion L19, the seventh voltage line portion L17, the fifth voltage line portion L15, and the sixth voltage line portion L16 are electrically connected;

[0223] The seventh voltage line portion L17 is electrically connected to the eighth voltage line portion L18.

[0224] In FIG18 , L15 is the fifth voltage line portion, L16 is the sixth voltage line portion, VI1 is the first initial voltage line, VI2 is the second initial voltage line; T02 is the second voltage connection line;

[0225] L15, L16, VI1, VI2 and T02 all extend in the horizontal direction.

[0226] In FIG19 , the seventh voltage line portion is labeled L17 , and the eighth voltage line portion is labeled L18 ;

[0227] In FIG20 , the ninth voltage line portion is labeled L19 .

[0228] As shown in FIG. 18 , the length of the second voltage connection line T02 along the vertical direction may be 80 μm.

[0229] During specific implementation, the line width of the second voltage connection line T02 may be reduced to reduce the overlapping area between the first voltage line and the second voltage line.

[0230] As shown in FIG17 to FIG20, the seventh voltage line portion L17 is electrically connected to the eighth voltage line portion L18 through a via hole. At the via hole, the seventh voltage line portion L17 is in direct contact with the eighth voltage line portion L18. The area of ​​direct contact between the seventh voltage line portion L17 and the eighth voltage line portion L18 can be 52500 μm 2 .

[0231] In the specific implementation, at the via hole, the area of ​​direct contact between the seventh voltage line portion and the eighth voltage line portion is larger, so as to maximize the overlapping area of ​​the first source-drain metal layer and the second source-drain metal layer on the basis of avoiding the organic clearance area inside and outside the DAM (blocking wall).

[0232] FIG21 is a cross-sectional view taken along line CC′ in FIG17 , and FIG22 is a cross-sectional view taken along line DD′ in FIG17 .

[0233] In Figure 21, the number 11 is the first source and drain metal layer, the number 12 is the second source and drain metal layer, the number J1 is the first insulating layer, and the number J2 is the second insulating layer; the number 13 is the anode layer, and the number J3 is the third insulating layer.

[0234] In FIG22 , the element labeled 11 is the first source-drain metal layer, the element labeled 12 is the second source-drain metal layer, the element labeled J1 is the first insulating layer, and the element labeled J2 is the second insulating layer.

[0235] Optionally, the first insulating layer may be a passivation layer, the second insulating layer may be a first planarization layer, and the third insulating layer may be a second planarization layer.

[0236] FIG23 is a layout diagram of a first border region of a display substrate according to at least one embodiment of the present disclosure.

[0237] In FIG23 , the first voltage line is labeled VSS1 , the second voltage line is labeled VSS2 , the third voltage line is labeled VSS3 , and the fourth voltage line is labeled VSS4 .

[0238] The line labeled VDD1 is the first second voltage line, the line labeled VDD2 is the second second voltage line, and the line labeled VDD3 is the third second voltage line.

[0239] In FIG23 , the driving integrated circuit is labeled I0 and the flexible circuit board is labeled F1;

[0240] VSS1, VSS2, VSS3, VSS4, VDD1, VDD2 and VDD3 are respectively electrically connected to different ports of the flexible circuit board F1, and the flexible circuit board F1 is used to provide a first voltage signal for VSS1, VSS2, VSS3 and VSS4, and a second voltage signal for VDD1, VDD2 and VDD3;

[0241] The area labeled CT1 is the first boxed test area, the area labeled CT2 is the second boxed test area, the area labeled CT3 is the third boxed test area, and the area labeled CT4 is the fourth boxed test area.

[0242] In at least one embodiment shown in FIG23 , a second voltage line is added to the center of the display substrate, and a first voltage line is added on either side of the second voltage line at the center. Each of the additional voltage lines is electrically connected to a different port on the flexible circuit board F1. The connection scheme for the first and second voltage lines above the bend region W1 is the same as that shown in FIG1 . At least one embodiment shown in FIG23 of the present disclosure can simultaneously shunt the first and second voltage signals, reducing the load on the first and second voltage lines and improving brightness uniformity.

[0243] FIG24 is a layout diagram of the left half of FIG23.

[0244] Figure 25 is a layout diagram of the first source and drain metal layer in Figure 24, Figure 26 is a layout diagram of the second source and drain metal layer in Figure 24, Figure 27 is a layout diagram of the first gate metal layer in Figure 24, Figure 28 is a layout diagram of the second gate metal layer in Figure 24, and Figure 29 is a layout diagram of the anode layer in Figure 24.

[0245] The display panel described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0246] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a display area and a first frame area; the display substrate comprises: substrate substrate; A plurality of first voltage lines and a plurality of second voltage lines are arranged on the base substrate in the first frame area; A second voltage line is arranged between two first voltage lines adjacent to each other in the first direction; the plurality of first voltage lines are electrically connected to each other, and the plurality of second voltage lines are electrically connected to each other; A circuit board is arranged on the base substrate in the first frame area, and the circuit board is arranged on the side of the first voltage line and the second voltage line away from the display area; the circuit board is electrically connected to the multiple first voltage lines respectively, and is used to provide a first voltage signal for the first voltage line.

2. The display substrate according to claim 1, wherein: The display substrate comprises at least three second voltage lines arranged in the first frame area; a first voltage line is arranged between the second voltage lines adjacent to each other in the first direction; The circuit board is electrically connected to the at least three second voltage lines respectively, and is used to provide a second voltage signal for the second voltage lines.

3. The display substrate according to claim 1 or 2, wherein: The display substrate comprises at least three first voltage lines arranged in the first frame area; The at least three first voltage lines and the plurality of second voltage lines are sequentially arranged along a first direction.

4. The display substrate according to claim 3, wherein: The display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line and a third first voltage line arranged in sequence along a first direction in the first frame area; or, The display substrate includes a first first voltage line, a first second voltage line, a second first voltage line, a second second voltage line, a third first voltage line, a third second voltage line and a fourth first voltage line arranged in sequence along a first direction in the first frame area.

5. The display substrate according to claim 1, wherein: The first frame region includes a bending region and a first region; the first region is located on a side of the bending region close to the display region; the display substrate further includes a first metal layer disposed on the base substrate; the display substrate further includes a second voltage connection line formed on the first metal layer, the second voltage connection line extends along a first direction, and the second voltage connection line is disposed in the first region; The second voltage lines are all connected to the second voltage communication line, so that the plurality of second voltage lines are electrically connected to each other.

6. The display substrate according to claim 5, wherein: The display substrate further comprises a first side region and a second side region; the first region comprises an arc region; The first side area is arranged at a first side of the display area, the second side area is arranged at a second side of the display area, the first side and the second side are opposite sides, and the arc area is an area included in the first area and close to the first side area or the second side area; The display substrate includes a first voltage line partially disposed in the arc region.

7. The display substrate according to claim 6, wherein: The display substrate further comprises a second metal layer disposed at the first metal layer away from the base substrate; The display substrate further comprises a plurality of second voltage connection lines arranged in the arc region and extending along a second direction; the second voltage connection lines are formed in a second metal layer; the first direction intersects with the second direction; The second voltage connection line is electrically connected to the second voltage communication line through a via.

8. The display substrate according to claim 7, wherein: The display substrate further includes a first voltage connection line extending along a second direction, and a plurality of first conductive connection parts electrically connected to an end of the first voltage connection line away from the display area; the first voltage connection line and the first conductive connection part are both arranged in the arc area; the first direction intersects with the second direction; the first voltage connection line and the first conductive connection part are both formed in the second metal layer; The display substrate further includes a first voltage line portion disposed in the arc region, the first voltage line portion being included in a first voltage line; the first voltage line portion extends along a first direction, and the first voltage line portion is formed in a first metal layer; The orthographic projection of the first voltage line portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive connection portion on the base substrate; The first conductive connection portion is electrically connected to the first voltage line portion through a via hole.

9. The display substrate according to claim 8, wherein: The second voltage connection lines and the first conductive connection portions are alternately arranged along a first direction.

10. The display substrate according to claim 6, wherein: The display substrate further includes a plurality of first connection lines and a plurality of second connection lines disposed in the arc region, the first connection lines and the second connection lines both extend along the second direction, and the first connection lines and the second connection lines are both formed in the second metal layer; The second connection line is arranged on a side of the first connection line away from the display area; at least two of the first connection lines are electrically connected to one of the second connection lines; the first direction intersects with the second direction; The second connection line is electrically connected to the second voltage communication line through a via.

11. The display substrate according to claim 10, wherein: The display substrate further comprises a plurality of first voltage connection lines arranged in the arc region and extending along the second direction, and a plurality of second conductive connection parts electrically connected to ends of the first voltage connection lines away from the display region; The first direction intersects with the second direction; the first voltage connection line and the second conductive connection portion are both formed in the second metal layer; The display substrate further includes a first voltage line portion disposed in the arc region, wherein the first voltage line portion is included in a first voltage line; The first voltage line portion extends along a first direction, and the first voltage line portion is formed in a first metal layer; The orthographic projection of the first voltage line portion on the base substrate at least partially overlaps with the orthographic projection of the second conductive connection portion on the base substrate; The second conductive connection portion is electrically connected to the first voltage line portion through a via hole.

12. The display substrate according to claim 11, wherein: The second connecting lines and the second conductive connecting portions are alternately arranged along a first direction; The area of ​​the orthographic projection of the second conductive connection portion on the base substrate is greater than or equal to 500 μm 2 Less than or equal to 1200 μm 2 .

13. The display substrate according to claim 8 or 11, wherein: The orthographic projection of the second voltage connection line on the base substrate is arranged on a side of the orthographic projection of the first voltage line portion on the base substrate away from the display area.

14. The display substrate according to claim 8 or 11, wherein: In the arc region, the first voltage line further includes a second voltage line portion formed in the second metal layer, a third voltage line portion formed in the first metal layer, and a fourth voltage line portion formed in the conductive layer; The second voltage line portion is electrically connected to the first voltage line portion through a via hole, and an orthographic projection of the first voltage line portion on the base substrate at least partially overlaps with an orthographic projection of the second voltage line portion on the base substrate; The orthographic projection of the third voltage line portion on the substrate is arranged at the same position as the first voltage line portion on the substrate. The orthographic projection on the bottom substrate is away from the side of the display area; The orthographic projection of the fourth voltage line portion on the substrate substrate at least partially overlaps with the orthographic projection of the second voltage line portion on the substrate substrate, and the orthographic projection of the fourth voltage line portion on the substrate substrate at least partially overlaps with the orthographic projection of the third voltage line portion on the substrate substrate, and the fourth voltage line portion is electrically connected to the second voltage line portion and the third voltage line portion, respectively, so that the second voltage line portion is electrically connected to the third voltage line portion.

15. The display substrate according to claim 6, wherein: The area of ​​the first area except the arc area is a middle area; in the middle area, the first voltage line includes a fifth voltage line portion, a sixth voltage line portion, a seventh voltage line portion, an eighth voltage line portion, and a ninth voltage line portion; The fifth voltage line portion, the sixth voltage line portion, the seventh voltage line portion, the eighth voltage line portion and the ninth voltage line portion all extend along the first direction; The fifth voltage line portion and the sixth voltage line portion are formed in the first metal layer, the seventh voltage line portion and the eighth voltage line portion are formed in the second metal layer, and the ninth voltage line portion is formed in the conductive layer; The orthographic projection of the seventh voltage line portion on the base substrate, the orthographic projection of the ninth voltage line portion on the base substrate and the orthographic projection of the second voltage connection line on the base substrate at least partially overlap; The ninth voltage line portion, the seventh voltage line portion, the fifth voltage line portion and the sixth voltage line portion are electrically connected; The seventh voltage line portion is electrically connected to the eighth voltage line portion.

16. The display substrate according to claim 15, wherein: A length of the second voltage connection line along the second direction is greater than or equal to 20 μm and less than or equal to 120 μm.

17. The display substrate according to claim 15, wherein: The seventh voltage line portion is electrically connected to the eighth voltage line portion through a via hole, the seventh voltage line portion is in direct contact with the eighth voltage line portion at the via hole, and an area where the seventh voltage line portion is in direct contact with the eighth voltage line portion is greater than or equal to 40000 μm 2 Less than or equal to 100000μm 2 .

18. A display panel comprising the display substrate according to any one of claims 1 to 17.

Images