Encoding method, decoding method, and apparatus

Abstract

The present application relates to the technical field of media, and provides an encoding method, a decoding method, and an apparatus. The encoding method comprises: encoding a plurality of display images and a plurality of CRR images to obtain a code stream; according to first information, authenticating data to be authenticated so as to obtain first treetop abstract data; according to second information, performing signature computing on the first treetop abstract data so as to obtain a digital signature; and encapsulating the digital signature into an authentication data set. The code stream comprises a security parameter set and the authentication data set, the security parameter set comprising the first information and the second information, the first information being used for representing an algorithm used for generating a treetop abstract, and the second information being used for representing an algorithm used for performing digital signing; the first treetop abstract data is treetop abstract data of an encoding end, the first treetop abstract data comprising treetop abstract data of N primary bit streams and / or M CRR slice bit streams, and N and M being positive integers.

Description

Coding and decoding method and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 1, 2023, with application number 202311138721.4 and application name “Encoding and Decoding Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of media technology, and in particular to a coding and decoding method and device. Background Art

[0003] The third-generation Audio and Video Coding Standard 3 (AVS3) proposes a Cross Random Access Point Reference (CRR) encoding and decoding scheme based on library pictures. This scheme obtains library pictures from existing video. A long-term buffer is provided at the system level to store reconstructed library pictures. The reconstructed library pictures at the encoding end are obtained by encoding the library pictures, while the reconstructed library pictures at the decoding end are obtained by decoding the library picture bitstream (i.e., the CRR slice bitstream). When encoding a video sequence, the reconstructed library picture corresponding to the current frame is obtained from the long-term buffer. The reconstructed library picture is used as a reference picture for inter-frame prediction coding of the current frame, thereby obtaining a video bitstream and a library picture bitstream corresponding to each reconstructed library picture used in the encoding. The video bitstream includes a reference picture flag for each frame, indicating whether the reconstructed library picture was used as a reference picture when encoding the frame. The decoder's system layer decodes each knowledge base image bitstream and stores the resulting reconstructed knowledge base image in a long-term buffer. When decoding the current image bitstream, the decoder retrieves the corresponding reconstructed knowledge base image from the long-term buffer and uses the reconstructed knowledge base image as a reference image for inter-frame prediction decoding of the current video bitstream.

[0004] With the rapid development of network video surveillance technology, data security issues are becoming increasingly prominent. Therefore, how to improve the security of the CRR media content transmission process is one of the problems that those skilled in the art need to solve urgently.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a coding and decoding method and apparatus that can improve the security of the CRR media content transmission process. To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, the present application provides a coding method, which includes: performing coding operations on multiple display images and the above-mentioned multiple CRR images to obtain a code stream. Authenticating the data to be authenticated according to the first information to obtain first tree-top summary data. Performing signature calculation on the above-mentioned first tree-top summary data according to the second information to obtain a digital signature. Encapsulating the above-mentioned digital signature into an authentication data set. The above-mentioned code stream includes a security parameter set and an authentication data set, and the above-mentioned security parameter set includes first information and second information. The above-mentioned first information is used to indicate the algorithm used to generate the tree-top summary, and the above-mentioned second information is used to indicate the algorithm used for digital signature. The above-mentioned first tree-top summary data is the tree-top summary data of the encoding end, and the above-mentioned first tree-top summary data includes the tree-top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers.

[0008] It can be seen that the method provided in the embodiment of the present application can perform signature authentication on the main bit stream obtained by display image encoding and / or the slice bit stream obtained by CRR image encoding, so that the receiving end can determine the integrity and authenticity of the transmitted bit stream based on the signature authentication data, thereby improving the security of the CRR media content transmission process.

[0009] In addition, in some online scenarios / offline storage scenarios, the position of the CRR slices may change flexibly, and the authentication operation is strongly related to the position and order of the network abstraction layer. At this time, if the CRR slices are not independently authenticated, it is very likely that the encoding and decoding ends will fail to pass the signature verification. However, using the embodiment of the present application, the CRR bit stream can be authenticated separately, thereby avoiding the problem of the encoding and decoding ends failing to pass the signature verification due to the inability to authenticate the CRR bit stream separately.

[0010] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0011] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag = 0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag = 1 indicates that the current authentication data belongs to a CRR slice, constraining all CRR slices to be authenticated.

[0012] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0013] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which represents the length of the signature data in bytes, and the value should be 0 to 255.

[0014] In a possible implementation, the authentication data set further includes fifth information, where the fifth information is used to indicate a CRR image corresponding to an authentication range of the current authentication data set.

[0015] For example, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to specify which CRR image the authentication range of the current authentication data set belongs to. This parameter can only be parsed when is_crr_flag=1.

[0016] In a possible implementation, the data signature may be encoded, and the encoded data signature may be encapsulated into the authentication data set.

[0017] Exemplarily, the data signature may be Base64 encoded, and the Base64 encoded data signature may be encapsulated into the authentication data set.

[0018] In one possible implementation, the CRR image may be segmented to obtain a plurality of CRR slices; the plurality of CRR slices may be interleaved and arranged between the plurality of display images to obtain a sequence of images to be encoded; and the CRR slices and the display images in the sequence of images to be encoded may be encoded in sequence to obtain the code stream.

[0019] In a possible implementation, the code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

[0020] It should be noted that encoding the display image and the CRR image into the same code stream can reduce the design and deployment cost of the overall encoding and decoding system.

[0021] In a second aspect, the present application provides a decoding method, comprising: obtaining a codestream, the codestream being obtained by encoding multiple display images and multiple CRR images, the codestream including a security parameter set and an authentication data set, the security parameter set including first information and second information, the first information being used to indicate an algorithm used to generate a treetop digest, the second information being used to indicate an algorithm used to generate a digital signature, the authentication data set including a digital signature; decoding the digital signature based on the second information to obtain first treetop digest data, the first treetop digest data being treetop digest data at the encoding end, the first treetop digest data including treetop digest data of N main bitstreams and / or M CRR slice bitstreams, where N and M are positive integers; authenticating authentication data corresponding to the authentication data set based on the first information to obtain second treetop digest data, the second treetop digest data being treetop digest data at the decoding end, the first treetop digest data including treetop digest data of N main bitstreams and / or M CRR slice bitstreams; and verifying the authentication data based on the first treetop digest and the second treetop digest data.

[0022] In a possible implementation, the digital signature may be decoded; and the decoded digital signature may be decoded according to the second information to obtain the first tree-top summary data.

[0023] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0024] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0025] In a third aspect, the present application provides an encoding method, comprising: encoding a plurality of display images and the plurality of CRR images to obtain a bitstream, wherein the bitstream includes a security parameter set, the security parameter set includes a video encryption key, and encrypting the bitstream according to the video encryption key.

[0026] In a possible implementation, the payload data of the code stream may be encrypted according to the video encryption key, where the payload data includes at least one of a sequence parameter set SPS, a picture parameter set PPS, a main bitstream, and a CRR slice bitstream.

[0027] In a fourth aspect, the present application provides a decoding method, which includes: obtaining a code stream, the code stream being obtained by encoding multiple display images and the multiple CRR images, the code stream including a security parameter set, and the security parameter set including a video encryption key; decrypting the code stream according to the video encryption key; and determining a reconstructed image based on the decoded code stream.

[0028] In a possible implementation, the payload data of the code stream may be decrypted according to the video encryption key, where the payload data includes at least one of an SPS, a PPS, a main bit stream, and a CRR slice bit stream.

[0029] In a fifth aspect, the present application provides an encoding device, which includes: an encoding unit and an authentication unit. The encoding unit is used to perform encoding operations on multiple display images and the above-mentioned multiple CRR images to obtain a code stream, the above-mentioned code stream includes a security parameter set and an authentication data set, the above-mentioned security parameter set includes first information and second information, the above-mentioned first information is used to indicate the algorithm used to generate the tree top summary, and the above-mentioned second information is used to indicate the algorithm used for digital signature. The authentication unit is used to authenticate the data to be authenticated according to the above-mentioned first information to obtain first tree top summary data, the above-mentioned first tree top summary data is the tree top summary data of the encoding end, and the above-mentioned first tree top summary data includes the tree top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers. The authentication unit is also used to perform signature calculation on the above-mentioned first tree top summary data according to the above-mentioned second information to obtain a digital signature. The authentication unit is also used to encapsulate the above-mentioned digital signature into the above-mentioned authentication data set.

[0030] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0031] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag = 0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag = 1 indicates that the current authentication data belongs to a CRR slice, constraining all CRR slices to be authenticated.

[0032] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0033] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which represents the length of the signature data in bytes, and the value should be 0 to 255.

[0034] In a possible implementation, the authentication data set further includes fifth information, where the fifth information is used to indicate a CRR image corresponding to an authentication range of the current authentication data set.

[0035] For example, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to specify which CRR image the authentication range of the current authentication data set belongs to. This parameter can only be parsed when is_crr_flag=1.

[0036] In a possible implementation, the authentication unit is specifically configured to: encode the data signature; and encapsulate the encoded data signature into the authentication data set.

[0037] In one possible implementation, the encoding unit is specifically used to: divide the above-mentioned CRR image to obtain multiple CRR slices; interleave the above-mentioned multiple CRR slices between the above-mentioned multiple display images to obtain a sequence of images to be encoded; and sequentially perform encoding operations on the above-mentioned CRR slices and the above-mentioned display images in the above-mentioned sequence of images to be encoded to obtain the above-mentioned code stream.

[0038] In a possible implementation, the code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

[0039] In a sixth aspect, the present application provides a decoding device comprising: a transceiver unit and an authentication unit. The transceiver unit is configured to obtain a bitstream, wherein the bitstream comprises a security parameter set and an authentication data set, wherein the security parameter set comprises first information and second information, wherein the first information is used to indicate an algorithm used to generate a treetop digest, and the second information is used to indicate an algorithm used to generate a digital signature, wherein the authentication data set comprises a digital signature. The authentication unit is configured to decode the digital signature based on the second information to obtain first treetop digest data, wherein the first treetop digest data is treetop digest data for the encoding end, and the first treetop digest data comprises treetop digest data for N main bitstreams and / or M CRR slice bitstreams, where N and M are positive integers. The authentication unit is further configured to authenticate authentication data corresponding to the authentication data set based on the first information to obtain second treetop digest data, wherein the second treetop digest data is treetop digest data for the decoding end, and the first treetop digest data comprises treetop digest data for N main bitstreams and / or M CRR slice bitstreams. The authentication unit is further configured to verify the authentication data according to the first tree-top summary and the second tree-top summary data.

[0040] In a possible implementation, the authentication unit is specifically configured to: decode the digital signature; and decode the decoded digital signature according to the second information to obtain first tree-top summary data.

[0041] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0042] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0043] In a seventh aspect, the present application provides an encoding device comprising: an encoding unit and an encryption unit. The encoding unit is configured to encode multiple display images and the multiple CRR images to generate a bitstream, wherein the bitstream includes a security parameter set, which includes a video encryption key. The encryption unit is configured to encrypt the bitstream based on the video encryption key.

[0044] In one possible implementation, the encryption unit is specifically used to: encrypt the payload data of the above-mentioned code stream according to the above-mentioned video encryption key, and the above-mentioned payload data includes at least one of the sequence parameter set SPS, the picture parameter set PPS, the main bit stream and the CRR slice bit stream.

[0045] In an eighth aspect, the present application provides a decoding device comprising: a transceiver unit, a decryption unit, and a reconstruction unit. The transceiver unit is configured to obtain a bitstream, wherein the bitstream includes a security parameter set, and the security parameter set includes a video encryption key. The decryption unit is configured to decrypt the bitstream based on the video encryption key. The reconstruction unit is configured to determine a reconstructed image based on the decoded bitstream.

[0046] In a possible implementation, the decryption unit is specifically configured to decrypt the payload data of the code stream according to the video encryption key, where the payload data includes at least one of an SPS, a PPS, a main bit stream, and a CRR slice bit stream.

[0047] In the ninth aspect, the present application provides a coding device, comprising: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by one or more processors, the one or more processors implement the method as described in any one of the first aspects.

[0048] In the tenth aspect, the present application provides a decoding device, comprising: one or more processors; a memory for storing one or more computer programs or instructions; when the one or more computer programs or instructions are executed by one or more processors, the one or more processors implement the method as described in any one of the second aspects.

[0049] In an eleventh aspect, embodiments of the present application further provide a chip comprising: an input interface, an output interface, and at least one processor. Optionally, the chip further comprises a memory. The at least one processor is configured to execute code in the memory. When the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation thereof.

[0050] Optionally, the chip may also be an integrated circuit.

[0051] In a twelfth aspect, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, which includes methods for implementing the above-mentioned first aspect or any possible implementation thereof.

[0052] In a thirteenth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method described in the first aspect or any possible implementation thereof.

[0053] In a fourteenth aspect, the present application provides an electronic device comprising: a processing circuit and an interface circuit; wherein the interface circuit is used to couple with a memory outside the encoding and decoding device and provide a communication interface for the processing circuit to access the memory; the processing circuit is used to execute program instructions in the memory to implement the method described in the first aspect or any possible implementation thereof.

[0054] In a specific implementation, the electronic device may be a chip, the input circuit may be an input pin, the output circuit may be an output pin, and the processing circuit may be a transistor, a gate circuit, a trigger, or various logic circuits. The input signal received by the input circuit may be, for example, but not limited to, received and input by a receiver, and the signal output by the output circuit may be, for example, but not limited to, output to and transmitted by a transmitter. The input circuit and the output circuit may be the same circuit, which functions as an input circuit and an output circuit at different times. The embodiments of the present application do not limit the specific implementation of the processor and various circuits.

[0055] In one implementation, the electronic device may be a wireless communication device, that is, a computer device that supports wireless communication functions. Specifically, the wireless communication device may be a terminal such as a smartphone, or a wireless access network device such as a base station. The system chip may also be referred to as a system on chip (SoC), or simply as an SoC chip. The communication chip may include a baseband processing chip and a radio frequency processing chip. The baseband processing chip is sometimes also referred to as a modem or baseband chip. The radio frequency processing chip is sometimes also referred to as a radio frequency transceiver or radio frequency chip. In a physical implementation, some or all of the chips in the communication chip may be integrated inside the SoC chip. For example, the baseband processing chip is integrated into the SoC chip, and the radio frequency processing chip is not integrated with the SoC chip. The interface circuit may be the radio frequency processing chip in the wireless communication device, and the processing circuit may be the baseband processing chip in the wireless communication device.

[0056] In another implementation, the electronic device may be a component of a wireless communication device, such as an integrated circuit product such as a system-on-chip (SoC) or a communication chip. The interface circuit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip or chip system. The processor may also be embodied as a processing circuit or a logic circuit.

[0057] The encoding and decoding device, computer storage medium, computer program product and chip provided in this embodiment are all used to execute the encoding and decoding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the encoding and decoding method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1a is an exemplary block diagram of a decoding system provided in an embodiment of the present application;

[0059] FIG1b is an exemplary block diagram of a video decoding system provided in an embodiment of the present application;

[0060] FIG2 is an exemplary block diagram of a video encoder provided in an embodiment of the present application;

[0061] FIG3 is an exemplary block diagram of a video decoder provided in an embodiment of the present application;

[0062] FIG4 is an exemplary schematic diagram of candidate image blocks provided in an embodiment of the present application;

[0063] FIG5 is an exemplary block diagram of a video decoding device provided in an embodiment of the present application;

[0064] FIG6 is an exemplary block diagram of a device provided in an embodiment of the present application;

[0065] FIG7 is a schematic diagram of a video sequence provided in an embodiment of the present application;

[0066] FIG8 is a schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0067] FIG9 is a schematic diagram of an encoding and decoding process provided by an embodiment of the present application;

[0068] FIG10 is a schematic diagram of a flowchart of a decoding method provided in an embodiment of the present application;

[0069] FIG11 is a schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0070] FIG12 is a schematic diagram of a flow chart of a decoding method provided in an embodiment of the present application;

[0071] FIG13 is a schematic structural diagram of an encoding device provided in an embodiment of the present application;

[0072] FIG14 is a schematic structural diagram of a decoding device provided in an embodiment of the present application;

[0073] FIG15 is a schematic structural diagram of another encoding device provided in an embodiment of the present application;

[0074] FIG16 is a schematic structural diagram of another decoding device provided in an embodiment of the present application;

[0075] FIG17 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0076] FIG18 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0078] The terms "first," "second," and the like in the description, embodiments, claims, and drawings of this application are used solely for descriptive purposes and are not to be construed as indicating or implying relative importance or order. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions, such as, for example, inclusion of a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0079] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0080] Data encoding and decoding includes two parts: data encoding and data decoding. Data encoding is performed on the source side (or commonly referred to as the encoder side), and generally includes processing (e.g., compressing) the original data to reduce the amount of data required to represent the original data (thereby more efficiently storing and / or transmitting). Data decoding is performed on the destination side (or commonly referred to as the decoder side), and generally includes inverse processing relative to the encoder side to reconstruct the original data. The "encoding and decoding" of the data involved in the embodiments of the present application should be understood as the "encoding" or "decoding" of the data. The encoding part and the decoding part are also collectively referred to as encoding and decoding (encoding and decoding, CODEC).

[0081] In the case of lossless data encoding, the original data can be reconstructed, that is, the reconstructed original data has the same quality as the original data (assuming there is no transmission loss or other data loss during storage or transmission). In the case of lossy data encoding, further compression is performed through quantization, etc. to reduce the amount of data required to represent the original data, but the decoder side cannot fully reconstruct the original data, that is, the quality of the reconstructed original data is lower or worse than the quality of the original data.

[0082] The embodiments of the present application can be applied to video data and other data with compression / decompression requirements. The following uses the encoding of video data (referred to as video encoding) as an example to illustrate the embodiments of the present application. Other types of data (such as image data, audio data, integer data, and other data with compression / decompression requirements) can refer to the following description, and the embodiments of the present application will not be repeated here. It should be noted that, compared to video encoding, the encoding process of data such as audio data and integer data does not require data to be divided into blocks, but the data can be directly encoded.

[0083] Video coding generally refers to processing a sequence of images to form a video or video sequence. In the field of video coding, the terms "picture", "frame" or "image" can be used as synonyms.

[0084] Several video coding standards fall under the category of "lossy hybrid video codecs" (i.e., combining spatial and temporal prediction in the pixel domain with 2D transform coding in the transform domain for applying quantization). Each image in a video sequence is typically divided into a set of non-overlapping blocks, which are typically coded at the block level. In other words, the encoder typically processes, i.e., encodes, the video at the block (video block) level, for example, by generating a prediction block through spatial (intra-frame) and temporal (inter-frame) prediction; subtracting the prediction block from the current block (currently processed / to-be-processed block) to obtain a residual block; transforming and quantizing the residual block in the transform domain to reduce the amount of data to be transmitted (compressed), while the decoder applies the inverse of the encoder's processing to the coded or compressed block to reconstruct the current block for representation. Furthermore, the encoder needs to repeat the decoder's processing steps so that the encoder and decoder generate the same predictions (e.g., intra-frame predictions and inter-frame predictions) and / or reconstructed pixels for processing, i.e., encoding, the subsequent block.

[0085] In the following embodiment of the decoding system 10 , the encoder 20 and the decoder 30 are described with reference to FIG. 1 a to FIG. 3 .

[0086] FIG1a is an exemplary block diagram of a decoding system 10 provided in an embodiment of the present application, such as a video decoding system 10 (or simply, decoding system 10) that can utilize the techniques of the embodiments of the present application. The video encoder 20 (or simply, encoder 20) and video decoder 30 (or simply, decoder 30) in the video decoding system 10 represent devices that can be used to perform various techniques according to the various examples described in the embodiments of the present application.

[0087] As shown in FIG. 1 a , a decoding system 10 includes a source device 12 for providing encoded image data 21 such as an encoded image to a destination device 14 for decoding the encoded image data 21 .

[0088] The source device 12 includes an encoder 20 , and optionally, may include an image source 16 , a preprocessor (or preprocessing unit) 18 such as an image preprocessor, and a communication interface (or communication unit) 22 .

[0089] Image source 16 may include or may be any type of image capture device for capturing real-world images, etc., and / or any type of image generation device, such as a computer graphics processor for generating computer-animated images, or any type of device for acquiring and / or providing real-world images, computer-generated images (e.g., screen content, virtual reality (VR) images, and / or any combination thereof (e.g., augmented reality (AR) images). The image source may be any type of memory or storage for storing any of the above images.

[0090] In order to distinguish the processing performed by the pre-processor (or pre-processing unit) 18 , the image (or image data) 17 may also be referred to as a raw image (or raw image data) 17 .

[0091] The preprocessor 18 is configured to receive raw image data 17 and preprocess the raw image data 17 to obtain a preprocessed image (or preprocessed image data) 19. For example, the preprocessing performed by the preprocessor 18 may include cropping, color format conversion (e.g., from RGB to YCbCr), color grading, or denoising. It will be appreciated that the preprocessor 18 may be an optional component.

[0092] The video encoder (or encoder) 20 is used to receive the pre-processed image data 19 and provide encoded image data 21 (which will be further described below with reference to FIG. 2 and the like).

[0093] The communication interface 22 in the source device 12 can be used to receive the encoded image data 21 and send the encoded image data 21 (or any other processed version) to another device such as the destination device 14 or any other device through the communication channel 13 for storage or direct reconstruction.

[0094] The destination device 14 includes a decoder 30 and, in addition or alternatively, may include a communication interface (or communication unit) 28 , a post-processor (or post-processing unit) 32 , and a display device 34 .

[0095] The communication interface 28 in the destination device 14 is used to receive the encoded image data 21 (or any other processed version) directly from the source device 12 or from any other source device such as a storage device, for example, the storage device is a encoded image data storage device, and provide the encoded image data 21 to the decoder 30.

[0096] The communication interface 22 and the communication interface 28 can be used to send or receive encoded image data (or encoded data) 21 through a direct communication link between the source device 12 and the destination device 14, such as a direct wired or wireless connection, or through any type of network, such as a wired network, a wireless network or any combination thereof, any type of private network and public network or any combination thereof.

[0097] For example, the communication interface 22 may be used to encapsulate the encoded image data 21 into a suitable format such as a message, and / or process the encoded image data using any type of transmission coding or processing for transmission over a communication link or network.

[0098] The communication interface 28 corresponds to the communication interface 22 , and can be used, for example, to receive transmission data and process the transmission data using any type of corresponding transmission decoding or processing and / or decapsulation to obtain the encoded image data 21 .

[0099] Both the communication interface 22 and the communication interface 28 can be configured as a unidirectional communication interface as indicated by the arrow pointing from the source device 12 to the corresponding communication channel 13 of the destination device 14 in Figure 1a, or a bidirectional communication interface, and can be used to send and receive messages, etc. to establish a connection, confirm and exchange any other information related to the communication link and / or data transmission such as encoded image data transmission, etc.

[0100] The video decoder (or decoder) 30 is used to receive the encoded image data 21 and provide decoded image data (or decoded image data) 31 (which will be further described below with reference to FIG. 3 and the like).

[0101] The post-processor 32 is configured to post-process the decoded image data 31 (also referred to as reconstructed image data), such as the decoded image, to obtain post-processed image data 33, such as the post-processed image. The post-processing performed by the post-processing unit 32 may include, for example, color format conversion (e.g., from YCbCr to RGB), color grading, cropping, or resampling, or any other processing for generating the decoded image data 31 for display on a display device 34, etc.

[0102] The display device 34 is configured to receive the post-processed image data 33 and display the image to a user or viewer. The display device 34 may be or include any type of display for displaying the reconstructed image, such as an integrated or external display screen or monitor. For example, the display screen may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro-LED display, a liquid crystal on silicon (LCoS) display, a digital light processor (DLP), or any other type of display screen.

[0103] The decoding system 10 also includes a training engine 25, which is used to train the encoder 20 (especially the entropy encoding unit 270 in the encoder 20) or the decoder 30 (especially the entropy decoding unit 304 in the decoder 30) to perform entropy encoding on the image block to be encoded based on the estimated probability distribution. For a detailed description of the training engine 25, please refer to the following method test example.

[0104] Although FIG1a shows source device 12 and destination device 14 as separate devices, device embodiments may also include both source device 12 and destination device 14 or the functions of both source device 12 and destination device 14, that is, both source device 12 or the corresponding functions and destination device 14 or the corresponding functions. In these embodiments, source device 12 or the corresponding functions and destination device 14 or the corresponding functions may be implemented using the same hardware and / or software or through separate hardware and / or software or any combination thereof.

[0105] According to the description, the existence and (accurate) division of different units or functions in the source device 12 and / or the destination device 14 shown in FIG. 1 a may vary depending on actual devices and applications, which is obvious to those skilled in the art.

[0106] Please refer to Figure 1b, which is an exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application. The encoder 20 (e.g., video encoder 20) or the decoder 30 (e.g., video decoder 30), or both, can be implemented by processing circuitry in the video decoding system 40 shown in Figure 1b, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, video encoding-specific processors, or any combination thereof. Please refer to Figures 2 and 3, Figure 2 is an exemplary block diagram of a video encoder provided in an embodiment of the present application, and Figure 3 is an exemplary block diagram of a video decoder provided in an embodiment of the present application. The encoder 20 can be implemented by processing circuitry 46 to include the various modules discussed with reference to the encoder 20 in Figure 2 and / or any other encoder systems or subsystems described herein. The decoder 30 can be implemented by processing circuitry 46 to include the various modules discussed with reference to the decoder 30 in Figure 3 and / or any other decoder systems or subsystems described herein. The processing circuitry 46 described above can be used to perform the various operations discussed below. As shown in Figure 5, if part of the technology is implemented in software, the device can store the software instructions in a suitable non-transitory computer-readable storage medium and use one or more processors to execute the instructions in hardware, thereby performing the technology of the embodiment of the present application. One of the video encoder 20 and the video decoder 30 can be integrated into a single device as part of a combined codec (encoder / decoder, CODEC), as shown in Figure 1b.

[0107] The source device 12 and the destination device 14 may include any of a variety of devices, including any type of handheld or fixed device, such as a notebook computer or laptop, a mobile phone, a smart phone, a tablet or a tablet computer, a camera, a desktop computer, a set-top box, a television, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiving device, a broadcast transmitting device, and a monitoring device, etc., and may not use or use any type of operating system. The source device 12 and the destination device 14 may also be devices in a cloud computing scenario, such as a virtual machine in a cloud computing scenario. In some cases, the source device 12 and the destination device 14 may be equipped with components for wireless communication. Therefore, the source device 12 and the destination device 14 may be wireless communication devices.

[0108] The source device 12 and the destination device 14 may be installed with virtual scene applications (APPs) such as virtual reality (VR), augmented reality (AR), or mixed reality (MR), and may run the VR, AR, or MR applications based on user operations (e.g., click, touch, slide, shake, voice control, etc.). The source device 12 and the destination device 14 may capture images / videos of any objects in the environment through cameras and / or sensors, and then display virtual objects on a display device based on the captured images / videos. The virtual objects may be virtual objects in the VR, AR, or MR scenes (i.e., objects in the virtual environment).

[0109] It should be noted that in the embodiment of the present application, the virtual scene application in the source device 12 and the destination device 14 can be an application built into the source device 12 and the destination device 14 themselves, or it can be an application provided by a third-party service provider and installed by the user. There is no specific limitation on this.

[0110] In addition, the source device 12 and the destination device 14 may be installed with a real-time video transmission application, such as a live broadcast application. The source device 12 and the destination device 14 may capture images / videos through cameras and then display the captured images / videos on a display device.

[0111] In some cases, the video decoding system 10 shown in FIG1a is merely exemplary, and the techniques provided in embodiments of the present application may be applicable to video encoding settings (e.g., video encoding or video decoding) that do not necessarily include any data communication between an encoding device and a decoding device. In other examples, data is retrieved from a local memory, sent over a network, and so on. A video encoding device may encode data and store the data in a memory, and / or a video decoding device may retrieve data from a memory and decode the data. In some examples, encoding and decoding are performed by devices that do not communicate with each other but simply encode data to a memory and / or retrieve and decode data from a memory.

[0112] Please refer to Figure 1b, which is an exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application. As shown in Figure 1b, the video decoding system 40 may include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video encoder / decoder implemented by a processing circuit 46), an antenna 42, one or more processors 43, one or more memory storage devices 44 and / or a display device 45.

[0113] 1b, imaging device 41, antenna 42, processing circuit 46, video encoder 20, video decoder 30, processor 43, memory 44, and / or display device 45 are capable of communicating with one another. In different embodiments, video decoding system 40 may include only video encoder 20 or only video decoder 30.

[0114] In some instances, antenna 42 can be used to transmit or receive an encoded bitstream of video data. Additionally, in some instances, display device 45 can be used to present the video data. Processing circuitry 46 can include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Video decoding system 40 can also include an optional processor 43, which can similarly include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Furthermore, memory storage 44 can be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.). In a non-limiting example, memory storage 44 can be implemented as cache memory. In other instances, processing circuitry 46 can include memory (e.g., cache memory, etc.) for implementing an image buffer, etc.

[0115] In some examples, video encoder 20 implemented by logic circuitry may include an image buffer (e.g., implemented by processing circuitry 46 or memory storage 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include video encoder 20 implemented by processing circuitry 46 to implement the various modules discussed with reference to FIG. 2 and / or any other encoder systems or subsystems described herein. Logic circuitry may be used to perform the various operations discussed herein.

[0116] In some examples, the video decoder 30 may be implemented by processing circuitry 46 in a similar manner to implement the various modules discussed with reference to the video decoder 30 of FIG. 3 and / or any other decoder systems or subsystems described herein. In some examples, the logic circuit implementation of the video decoder 30 may include an image buffer (implemented by processing circuitry 46 or memory storage 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include the video decoder 30 implemented by processing circuitry 46 to implement the various modules discussed with reference to FIG. 3 and / or any other decoder systems or subsystems described herein.

[0117] In some examples, antenna 42 may be used to receive an encoded bitstream of video data. As discussed, the encoded bitstream may include data related to the encoded video frames, indicators, index values, mode selection data, etc., as discussed herein, such as data related to encoding partitions (e.g., transform coefficients or quantized transform coefficients, optional indicators (as discussed), and / or data defining encoding partitions). Video decoding system 40 may also include video decoder 30 coupled to antenna 42 and configured to decode the encoded bitstream. Display device 45 is configured to present the video frames.

[0118] It should be understood that for the examples described herein with reference to video encoder 20, video decoder 30 can be configured to perform the reverse process. With respect to signaling syntax elements, video decoder 30 can be configured to receive and parse such syntax elements and decode the associated video data accordingly. In some examples, video encoder 20 can entropy encode the syntax elements into an encoded video bitstream. In such examples, video decoder 30 can parse such syntax elements and decode the associated video data accordingly.

[0119] For ease of description, the embodiments of the present application are described with reference to the universal video coding (VVC) reference software or the high-efficiency video coding (HEVC) developed by the joint collaboration team on video coding (JCT-VC) of the ITU-T video coding experts group (VCEG) and the ISO / IEC motion picture experts group (MPEG). Those skilled in the art will understand that the embodiments of the present application are not limited to HEVC or VVC.

[0120] Encoders and encoding methods

[0121] As shown in FIG2 , the video encoder 20 includes an input terminal (or input interface) 201, a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy coding unit 270, and an output terminal (or output interface) 272. The mode selection unit 260 may include an inter-frame prediction unit 244, an intra-frame prediction unit 254, and a segmentation unit 262. The inter-frame prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). The video encoder 20 shown in FIG2 may also be referred to as a hybrid video encoder or a video encoder based on a hybrid video codec.

[0122] 2 , the inter-frame prediction unit is a trained target model (also known as a neural network) that processes an input image, image region, or image block to generate a prediction value for the input image block. For example, the neural network for inter-frame prediction receives an input image, image region, or image block and generates a prediction value for the input image, image region, or image block.

[0123] The residual calculation unit 204, the transform processing unit 206, the quantization unit 208, and the mode selection unit 260 constitute the forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, the inter-frame prediction unit 244, and the intra-frame prediction unit 254 constitute the backward signal path of the encoder, where the backward signal path of the encoder 20 corresponds to the signal path of the decoder (see decoder 30 in Figure 3). The inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer 230, the inter-frame prediction unit 244, and the intra-frame prediction unit 254 also constitute the "internal decoder" of the video encoder 20.

[0124] Images and image segmentation (images and blocks)

[0125] Encoder 20 is operable to receive, via input 201 or the like, an image (or image data) 17, for example, an image from a sequence of images forming a video or video sequence. The received image or image data may also be a pre-processed image (or pre-processed image data) 19. For simplicity, the following description uses image 17. Image 17 may also be referred to as a current image or image to be encoded (particularly when distinguishing the current image from other images in video encoding, such as previously encoded and / or decoded images in the same video sequence, i.e., a video sequence that also includes the current image).

[0126] A (digital) image is, or can be considered to be, a two-dimensional array or matrix of pixels with intensity values. The pixels in the array are also referred to as pixels (or pels, short for picture elements). The number of pixels in the array or image in the horizontal and vertical directions (or axes) determines the image size and / or resolution. To represent color, three color components are typically used, meaning that an image can be represented as or include three pixel arrays. In the RBG format or color space, an image includes corresponding arrays of red, green, and blue pixels. However, in video coding, each pixel is typically represented in a luma / chroma format or color space, such as YCbCr, which includes a luma component indicated by Y (sometimes also indicated by L) and two chroma components, indicated by Cb and Cr. The luma component Y represents the brightness or grayscale level intensity (for example, in grayscale images, both are the same), while the two chroma components (abbreviated as chroma) Cb and Cr represent the chroma or color information components. Accordingly, an image in YCbCr format includes a luma pixel array of luma pixel values ​​(Y) and two chroma pixel arrays of chroma values ​​(Cb and Cr). An image in RGB format can be converted or transformed into YCbCr format, and vice versa, a process also known as color conversion or transformation. If the image is black and white, the image may include only a luma pixel array. Accordingly, the image may be, for example, a luma pixel array in monochrome format or a luma pixel array and two corresponding chroma pixel arrays in 4:2:0, 4:2:2, and 4:4:4 color formats.

[0127] In one embodiment, an embodiment of the video encoder 20 may include an image segmentation unit (not shown in FIG. 2 ) for segmenting the image 17 into a plurality of (typically non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macroblocks (H.264 / AVC) or coding tree blocks (CTBs), or coding tree units (CTUs) in the H.265 / HEVC and VVC standards. The segmentation unit may be used to use the same block size for all images in a video sequence and a corresponding grid of defined block sizes, or to vary the block size between images or subsets or groups of images, and to segment each image into corresponding blocks.

[0128] In other embodiments, the video encoder may be configured to directly receive a block 203 of the image 17, for example, one, several or all blocks constituting the image 17. The image block 203 may also be referred to as a current image block or an image block to be encoded.

[0129] Like image 17, image block 203 is also or can be considered to be a two-dimensional array or matrix of pixels having intensity values ​​(pixel values), but image block 203 is smaller than image 17. In other words, block 203 may include one pixel array (e.g., a luminance array in the case of monochrome image 17, or a luminance array or chrominance array in the case of a color image), or three pixel arrays (e.g., one luminance array and two chrominance arrays in the case of a color image 17), or any other number and / or type of arrays depending on the color format used. The number of pixels in the horizontal and vertical directions (or axes) of block 203 defines the size of block 203. Accordingly, a block may be an M×N (M columns×N rows) pixel array, or an M×N transform coefficient array, etc.

[0130] In one embodiment, the video encoder 20 shown in FIG. 2 is configured to encode the image 17 block by block, for example, performing encoding and prediction on each block 203 .

[0131] In one embodiment, the video encoder 20 shown in FIG2 may also be configured to partition and / or encode an image using slices (also referred to as video slices), where an image may be partitioned or encoded using one or more slices (typically non-overlapping). Each slice may include one or more blocks (e.g., coding tree units (CTUs)) or one or more groups of blocks (e.g., tiles in the H.265 / HEVC / VVC standard and bricks in the VVC standard).

[0132] In one embodiment, the video encoder 20 shown in Figure 2 can also be used to segment and / or encode an image using slices / coding block groups (also called video coding block groups) and / or coding blocks (also called video coding blocks), where the image can be segmented or encoded using one or more slices / coding block groups (usually non-overlapping), each slice / coding block group may include one or more blocks (e.g., CTUs) or one or more coding blocks, etc., where each coding block can be in a shape such as a rectangle and may include one or more complete or partial blocks (e.g., CTUs).

[0133] Residual calculation

[0134] The residual calculation unit 204 is used to calculate the residual block 205 (the prediction block 265 is described in detail later) based on the image block (or original block) 203 and the prediction block 265 in the following manner: for example, the pixel value of the prediction block 265 is subtracted from the pixel value of the image block 203 pixel by pixel (pixel by pixel) to obtain the residual block 205 in the pixel domain.

[0135] Transform

[0136] The transform processing unit 206 is configured to perform a discrete cosine transform (DCT) or a discrete sine transform (DST) on the pixel values ​​of the residual block 205 to obtain transform coefficients 207 in the transform domain. The transform coefficients 207 may also be referred to as transform residual coefficients, representing the residual block 205 in the transform domain.

[0137] The transform processing unit 206 may be used to apply an integerized approximation of the DCT / DST, such as the transform specified for H.265 / HEVC. This integerized approximation is typically scaled by a factor compared to the orthogonal DCT transform. In order to maintain the norm of the residual block after the forward and inverse transforms, additional scaling factors are used as part of the transform process. The scaling factors are typically selected based on certain constraints, such as whether the scaling factor is a power of 2 for the shift operation, the bit depth of the transform coefficients, a trade-off between accuracy and implementation cost, etc. For example, a specific scaling factor is specified for the inverse transform on the encoder 20 side by the inverse transform processing unit 212 (and for the corresponding inverse transform on the decoder 30 side by, for example, the inverse transform processing unit 312), and correspondingly, a corresponding scaling factor may be specified for the forward transform on the encoder 20 side by the transform processing unit 206.

[0138] In one embodiment, the video encoder 20 (correspondingly, the transform processing unit 206) may be configured to output transform parameters such as one or more transform types, for example, directly output or output after being encoded or compressed by the entropy coding unit 270, such that the video decoder 30 may receive and use the transform parameters for decoding.

[0139] Quantification

[0140] The quantization unit 208 is configured to quantize the transform coefficients 207 by, for example, scalar quantization or vector quantization to obtain quantized transform coefficients 209 . The quantized transform coefficients 209 may also be referred to as quantized residual coefficients 209 .

[0141] The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, during quantization, an n-bit transform coefficient may be rounded down to an m-bit transform coefficient, where n is greater than m. The degree of quantization may be modified by adjusting a quantization parameter (QP). For example, for scalar quantization, varying degrees of scaling may be applied to achieve finer or coarser quantization. A smaller quantization step size corresponds to finer quantization, while a larger quantization step size corresponds to coarser quantization. The appropriate quantization step size may be indicated by a quantization parameter (QP). For example, the quantization parameter may be an index into a predefined set of appropriate quantization step sizes. For example, a smaller quantization parameter may correspond to fine quantization (a smaller quantization step size), while a larger quantization parameter may correspond to coarse quantization (a larger quantization step size), or vice versa. Quantization may include dividing by the quantization step size, while the corresponding or inverse dequantization performed by the inverse quantization unit 210, etc., may include multiplying by the quantization step size. Embodiments according to some standards, such as HEVC, may be used to determine the quantization step size using the quantization parameter. Generally, the quantization step size may be calculated based on the quantization parameter using a fixed-point approximation of an equation involving division. Additional scaling factors can be introduced for quantization and dequantization to restore the norm of the residual block that may have been modified by the scaling used in the fixed-point approximation of the equations for the quantization step size and quantization parameter. In one exemplary implementation, the scaling of the inverse transform and dequantization can be combined. Alternatively, a custom quantization table can be used and indicated from the encoder to the decoder in the bitstream, etc. Quantization is a lossy operation, where larger quantization step sizes result in greater losses.

[0142] In one embodiment, the video encoder 20 (correspondingly, the quantization unit 208) may be configured to output a quantization parameter (QP), for example, directly or after being encoded or compressed by the entropy coding unit 270, such that the video decoder 30 may receive and use the quantization parameter for decoding.

[0143] Dequantization

[0144] The inverse quantization unit 210 is configured to perform inverse quantization performed by the quantization unit 208 on the quantized coefficients to obtain dequantized coefficients 211. For example, the inverse quantization scheme performed by the quantization unit 208 may be performed according to or using the same quantization step size as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211, and correspond to the transform coefficients 207. However, due to the loss caused by quantization, the dequantized coefficients 211 are generally not identical to the transform coefficients.

[0145] Inverse transform

[0146] The inverse transform processing unit 212 is configured to perform the inverse transform of the transform performed by the transform processing unit 206, such as an inverse discrete cosine transform (DCT) or an inverse discrete sine transform (DST), to obtain a reconstructed residual block 213 (or corresponding dequantized coefficients 213) in the pixel domain. The reconstructed residual block 213 may also be referred to as a transform block 213.

[0147] reconstruction

[0148] The reconstruction unit 214 (e.g., the summer 214) is used to add the transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the pixel domain, for example, by adding the pixel point values ​​of the reconstructed residual block 213 and the pixel point values ​​of the prediction block 265.

[0149] Filtering

[0150] The loop filter unit 220 (or simply "loop filter" 220) is used to filter the reconstructed block 215 to obtain a filter block 221, or generally to filter the reconstructed pixels to obtain filtered pixel values. For example, the loop filter unit is used to smoothly perform pixel conversion or improve video quality. The loop filter unit 220 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination thereof. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process can be a deblocking filter, an SAO filter, and an ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., an adaptive in-loop reshaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process can also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 220 is shown as a loop filter in FIG2 , in other configurations, the loop filter unit 220 can be implemented as a post-loop filter. The filter block 221 can also be referred to as a filter reconstruction block 221.

[0151] In one embodiment, the video encoder 20 (correspondingly, the loop filter unit 220) may be configured to output loop filter parameters (e.g., SAO filter parameters, ALF filter parameters, or LMCS parameters), for example, directly or after being entropy-encoded by the entropy coding unit 270, such that the decoder 30 may receive and use the same or different loop filter parameters for decoding.

[0152] Decoded Image Buffer

[0153] The decoded picture buffer (DPB) 230 may be a reference picture memory that stores reference picture data for use by the video encoder 20 when encoding video data. The DPB 230 may be formed from any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. The decoded picture buffer 230 may be used to store one or more filter blocks 221. The decoded picture buffer 230 may also be used to store other previously filtered blocks of the same current picture or a different picture, such as a previously reconstructed picture, such as a previously reconstructed and filtered block 221, and may provide a complete previously reconstructed, i.e., decoded picture (and corresponding reference blocks and pixels) and / or a partially reconstructed current picture (and corresponding reference blocks and pixels), for example, for inter-frame prediction. The decoded image buffer 230 may also be used to store one or more unfiltered reconstructed blocks 215, or generally to store unfiltered reconstructed pixels, for example, reconstructed blocks 215 that have not been filtered by the loop filtering unit 220, or reconstructed blocks or reconstructed pixels that have not undergone any other processing.

[0154] Mode selection (segmentation and prediction)

[0155] The mode selection unit 260 includes a segmentation unit 262, an inter-frame prediction unit 244, and an intra-frame prediction unit 254, which are configured to receive or obtain original image data, such as an original block 203 (current block 203 of the current image 17) and reconstructed image data, such as filtered and / or unfiltered reconstructed pixels or reconstructed blocks of the same (current) image and / or one or more previously decoded images, from the decoded image buffer 230 or other buffer (e.g., a column buffer, not shown in FIG. 2). The reconstructed image data is used as reference image data required for prediction, such as inter-frame prediction or intra-frame prediction, to obtain a prediction block 265 or a prediction value 265.

[0156] The mode selection unit 260 may be used to determine or select a partitioning for the current block (including no partitioning) and prediction mode (eg, intra-frame or inter-frame prediction mode), generate a corresponding prediction block 265 , and calculate the residual block 205 and reconstruct the reconstruction block 215 .

[0157] In one embodiment, the mode selection unit 260 may be configured to select a segmentation and prediction mode (e.g., from prediction modes supported or available by the mode selection unit 260) that provides the best match or minimum residual (minimum residual means better compression during transmission or storage), or provides minimum signaling overhead (minimum signaling overhead means better compression during transmission or storage), or simultaneously considers or balances both. The mode selection unit 260 may be configured to determine the segmentation and prediction mode based on rate distortion optimization (RDO), i.e., select the prediction mode that provides the minimum rate distortion optimization. Terms such as "best," "lowest," and "optimal" herein do not necessarily refer to "best," "lowest," or "optimal" overall, but may also refer to situations where termination or selection criteria are met, e.g., values ​​exceeding or falling below a threshold or other limit may result in a "suboptimal selection" but reduce complexity and processing time.

[0158] In other words, the partitioning unit 262 may be configured to partition an image in a video sequence into a sequence of coding tree units (CTUs), the CTU 203 being further partitioned into smaller block portions or sub-blocks (again forming blocks), e.g., by iteratively using quad-tree partitioning (QT), binary-tree partitioning (BT), or triple-tree partitioning (TT), or any combination thereof, and for, e.g., performing prediction on each of the block portions or sub-blocks, wherein the mode selection comprises selecting a tree structure for partitioning the block 203 and selecting a prediction mode to be applied to each of the block portions or sub-blocks.

[0159] The segmentation (eg, performed by segmentation unit 262) and prediction processes (eg, performed by inter-prediction unit 244 and intra-prediction unit 254) performed by video encoder 20 are described in detail below.

[0160] segmentation

[0161] The partitioning unit 262 can partition (or divide) an image block (or CTU) 203 into smaller parts, such as square or rectangular blocks. For an image with three pixel arrays, a CTU consists of N×N luminance pixel blocks and two corresponding chrominance pixel blocks. The maximum allowed size of a luminance block in a CTU is specified as 128×128 in the developing Universal Video Coding (VVC) standard, but may be specified to a value other than 128×128, such as 256×256, in the future. The CTUs of an image can be grouped / collected into slices / coding block groups, coding blocks, or bricks. A coding block covers a rectangular area of ​​an image and can be divided into one or more bricks. A brick consists of multiple CTU rows within a coding block. A coding block that is not partitioned into multiple bricks can be called a brick. However, a brick is a true subset of a coding block and is therefore not called a coding block. VVC supports two coding block group modes: raster scan slice / coding block group mode and rectangular slice mode. In raster scan CBG mode, a slice / CBG contains a sequence of CBs from a raster scan of the CBs of an image. In rectangular slice mode, a slice contains multiple bricks of an image that together form a rectangular region of the image. The bricks within a rectangular slice are arranged in the slice's brick raster scan order. These smaller blocks (also called sub-blocks) can be further split into smaller parts. This is also known as tree partitioning or hierarchical tree partitioning, where a root block at, for example, root tree level 0 (hierarchy level 0, depth 0) can be recursively split into two or more blocks at the next lower tree level, such as nodes at tree level 1 (hierarchy level 1, depth 1). These blocks can be further split into two or more blocks at the next lower level, such as nodes at tree level 2 (hierarchy level 2, depth 2), and so on, until the partitioning is completed (because the end criteria are met, such as reaching the maximum tree depth or minimum block size). Blocks that are not further split are also called leaf blocks or leaf nodes of the tree. A tree divided into two parts is called a binary tree (BT), a tree divided into three parts is called a ternary tree (TT), and a tree divided into four parts is called a quadtree (QT).

[0162] For example, a coding tree unit (CTU) may be or include a CTB for luma pixels, two corresponding CTBs for chroma pixels of an image with a three-pixel array, or a CTB for pixels of a monochrome image, or a CTB for pixels of an image encoded using three independent color planes and syntax structures for encoding pixels. Accordingly, a coding tree block (CTB) may be an N×N block of pixels, where N may be set to a value such that a component is divided into CTBs, which is known as partitioning. A coding unit (CU) may be or include a coding block of luma pixels, two corresponding coding blocks for chroma pixels of an image with a three-pixel array, or a coding block of pixels of a monochrome image, or a coding block of pixels of an image encoded using three independent color planes and syntax structures for encoding pixels. Accordingly, a coding block (CB) may be an M×N block of pixels, where M and N may be set to a value such that a CTB is divided into coding blocks, which is known as partitioning.

[0163] For example, in an embodiment, according to HEVC, a coding tree unit (CTU) can be divided into multiple CUs using a quadtree structure represented as a coding tree. A decision is made at the leaf-CU level whether to use inter-frame (temporal) prediction or intra-frame (spatial) prediction to encode an image region. Each leaf-CU can be further divided into one, two, or four PUs according to the PU partition type. The same prediction process is used within a PU, and relevant information is transmitted to the decoder in units of PUs. After applying the prediction process according to the PU partition type to obtain a residual block, the leaf-CU can be divided into transform units (TUs) according to other quadtree structures similar to the coding tree for the CU.

[0164] For example, in an embodiment, according to the latest video coding standard currently under development (called Versatile Video Coding (VVC), a combined quadtree of nested multi-type trees (such as binary trees and ternary trees) is used to divide the segment structure for partitioning the coding tree unit. In the coding tree structure within the coding tree unit, the CU can be square or rectangular. For example, the coding tree unit (CTU) is first partitioned by the quadtree structure. The quadtree leaf nodes are further partitioned by the multi-type tree structure. The multi-type tree structure has four partition types: vertical binary tree partition (SPLIT_BT_VER), horizontal binary tree partition (SPLIT_BT_HOR), vertical ternary tree partition The tree nodes of the multi-type tree are called coding units (CUs), unless the CU is too large for the maximum transform length, in which case such segmentation is used for prediction and transform processing without any other splitting. In most cases, this means that the block sizes of CUs, PUs, and TUs in the coding block structure of the quadtree nested multi-type tree are the same. This exception occurs when the maximum supported transform length is less than the width or height of the color components of the CU. VVC has developed a unique signaling mechanism for the split partitioning information in the coding structure with quadtree nested multi-type trees. In the signaling mechanism, the coding The tree unit (CTU) as the root of the quadtree is first split by the quadtree structure. Then each quadtree leaf node (when large enough) is further split into a multi-type tree structure. In the multi-type tree structure, the first flag (mtt_split_cu_flag) is used to indicate whether the node is further split. When the node is further split, the second flag (mtt_split_cu_vertical_flag) is used to indicate the division direction, and the third flag (mtt_split_cu_binary_flag) is used to indicate whether the division is a binary tree division or a ternary tree division. According to mtt_split_c The values ​​of u_vertical_flag and mtt_split_cu_binary_flag allow the decoder to derive the multi-type tree split mode (MttSplitMode) of the CU based on predefined rules or tables. It should be noted that for certain designs, such as the 64×64 luma block and 32×32 chroma pipeline design in the VVC hardware decoder, TT splitting is not allowed when the width or height of the luma coding block is greater than 64. TT splitting is also not allowed when the width or height of the chroma coding block is greater than 32. The pipeline design divides the image into multiple virtual pipeline data units (VPDUs), each of which is defined as a non-overlapping unit in the image. In the hardware decoder, consecutive VPDUs are processed simultaneously in multiple pipeline stages. In most pipeline stages, the VPDU size is roughly proportional to the buffer size, so it is desirable to keep the VPDU small.In most hardware decoders, the VPDU size can be set to the maximum transform block (TB) size. However, in VVC, the ternary tree (TT) and binary tree (BT) partitioning may increase the VPDU size.

[0165] In addition, it should be noted that when a part of the tree node block exceeds the bottom or the right boundary of the image, the tree node block is forcibly divided until all pixels of each coding CU are located within the image boundary.

[0166] For example, the intra sub-partitions (ISP) tool may vertically or horizontally divide the luma intra prediction block into two or four sub-partitions according to the block size.

[0167] In one example, mode select unit 260 of video encoder 20 may be used to perform any combination of the segmentation techniques described above.

[0168] As described above, the video encoder 20 is configured to determine or select the best or optimal prediction mode from a (predetermined) prediction mode set. The prediction mode set may include, for example, an intra-frame prediction mode and / or an inter-frame prediction mode.

[0169] Intra-frame prediction

[0170] The intra prediction mode set may include 35 different intra prediction modes, for example, non-directional modes like DC (or mean) mode and planar mode, or directional modes as defined in HEVC, or may include 67 different intra prediction modes, for example, non-directional modes like DC (or mean) mode and planar mode, or directional modes as defined in VVC. For example, several traditional angle intra prediction modes are adaptively replaced with wide-angle intra prediction modes for non-square blocks defined in VVC. For another example, in order to avoid the division operation of DC prediction, only the longer side is used to calculate the average value of the non-square block. In addition, the intra prediction result of the planar mode can also be modified using the position dependent intraprediction combination (PDPC) method.

[0171] The intra prediction unit 254 is configured to generate an intra prediction block 265 by reconstructing pixels in adjacent blocks of the same current image according to an intra prediction mode in the intra prediction mode set.

[0172] The intra-frame prediction unit 254 (or generally the mode selection unit 260) is also used to output intra-frame prediction parameters (or generally information indicating the selected intra-frame prediction mode for the block) in the form of syntax elements 266 to the entropy coding unit 270 for inclusion in the encoded image data 21, so that the video decoder 30 can perform operations, such as receiving and using the prediction parameters for decoding.

[0173] The intra prediction modes in HEVC include DC prediction mode, plane prediction mode and 33 angular prediction modes, with a total of 35 candidate prediction modes. The current block can use the pixels of the reconstructed image blocks on the left and above as references for intra prediction. The image blocks in the surrounding area of ​​the current block used for intra prediction of the current block are called reference blocks, and the pixels in the reference blocks are called reference pixels. Among the 35 candidate prediction modes, the DC prediction mode is applicable to areas with flat textures in the current block. All pixels in this area use the average value of the reference pixels in the reference block as prediction; the plane prediction mode is applicable to image blocks with smoothly changing textures. The current block that meets this condition uses the reference pixels in the reference block for bilinear interpolation as the prediction of all pixels in the current block; the angular prediction mode uses the characteristic that the texture of the current block is highly correlated with the texture of the adjacent reconstructed image blocks, and copies the values ​​of the reference pixels in the corresponding reference block along a certain angle as the prediction of all pixels in the current block.

[0174] The HEVC encoder selects an optimal intra-frame prediction mode for the current block from 35 candidate prediction modes and writes this optimal intra-frame prediction mode into the video bitstream. To improve the coding efficiency of intra-frame prediction, the encoder / decoder derives three most probable modes from the optimal intra-frame prediction modes of the reconstructed image blocks in the surrounding area using intra-frame prediction. If the optimal intra-frame prediction mode selected for the current block is one of these three most probable modes, a first index is encoded to indicate that the selected optimal intra-frame prediction mode is one of these three most probable modes; if the selected optimal intra-frame prediction mode is not one of these three most probable modes, a second index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the other 32 modes (other than the aforementioned three most probable modes among the 35 candidate prediction modes). The HEVC standard uses a 5-bit fixed-length code as the aforementioned second index.

[0175] The HEVC encoder derives the three most probable modes by selecting the optimal intra-frame prediction mode of the image block to the left and the image block above the current block and adding them to a set. If these two optimal intra-frame prediction modes are the same, only one is retained in the set. If these two optimal intra-frame prediction modes are the same and both are angular prediction modes, two angular prediction modes adjacent to the angular direction are selected and added to the set. Otherwise, the planar prediction mode, the DC mode, and the vertical prediction mode are selected and added to the set in sequence until the number of modes in the set reaches three.

[0176] After the HEVC decoder performs entropy decoding on the bitstream, it obtains the mode information of the current block, which includes an indicator indicating whether the optimal intra-frame prediction mode of the current block is among the three most probable modes, and the index of the optimal intra-frame prediction mode of the current block among the three most probable modes or the index of the optimal intra-frame prediction mode of the current block among the other 32 modes.

[0177] Inter-frame prediction

[0178] In a possible implementation, the set of inter-prediction modes depends on the available reference picture (i.e., at least part of the previously decoded picture stored in the DBP 230 as mentioned above) and other inter-prediction parameters, e.g., on whether the entire reference picture is used or only a part of the reference picture is used, e.g., a search window area around the area of ​​the current block, to search for the best matching reference block, and / or on whether pixel interpolation such as half-pixel, quarter-pixel and / or 1 / 16 interpolation is performed, for example.

[0179] In addition to the above prediction modes, skip mode and / or direct mode may also be employed.

[0180] For example, in extended merge prediction, the merge candidate list of this mode consists of the following five candidate types in order: spatial MVP from spatially neighboring CUs, temporal MVP from collocated CUs, history-based MVP from the FIFO table, pairwise average MVP, and zero MV. Decoder-side motion vector refinement (DMVR) based on bilateral matching can be used to increase the accuracy of the MV in merge mode. Merge mode with MVD (MMVD) is derived from merge mode with motion vector difference. The MMVD flag is sent immediately after the skip flag and merge flag to specify whether the CU uses MMVD mode. A CU-level adaptive motion vector resolution (AMVR) scheme can be used. AMVR supports encoding the CU's MVD with different precisions. The MVD of the current CU is adaptively selected based on the prediction mode of the current CU. When the CU is encoded in merge mode, the combined inter / intra prediction (CIIP) mode can be applied to the current CU. The CIIP prediction is obtained by weighted averaging the inter and intra prediction signals. For affine motion compensation prediction, the affine motion field of the block is described by the motion information of 2 control points (4 parameters) or 3 control points (6 parameters) motion vectors. Subblock-based temporal motion vector prediction (SbTMVP) is similar to the temporal motion vector prediction (TMVP) in HEVC, but it predicts the motion vector of the sub-CU within the current CU. Bidirectional optical flow (BDOF), formerly known as BIO, is a simplified version that reduces calculations, especially in terms of the number of multiplications and the size of the multipliers. In the triangle partitioning mode, the CU is evenly divided into two triangular parts using diagonal partitioning and anti-diagonal partitioning. In addition, the bidirectional prediction mode is extended based on the simple average to support the weighted average of the two prediction signals.

[0181] The inter-frame prediction unit 244 may include a motion estimation (ME) unit and a motion compensation (MC) unit (both not shown in FIG. 2 ). The motion estimation unit may be configured to receive or obtain an image block 203 (the current image block 203 of the current image 17 ) and a decoded image 231 , or at least one or more previously reconstructed blocks, e.g., reconstructed blocks of one or more other / different previously decoded images 231 , to perform motion estimation. For example, a video sequence may include the current image and the previously decoded image 231 , or in other words, the current image and the previously decoded image 231 may be part of or form a sequence of images forming the video sequence.

[0182] For example, the encoder 20 may be configured to select a reference block from a plurality of reference blocks of the same or different images among a plurality of other images, and provide the reference image (or reference image index) and / or the offset (spatial offset) between the position (x, y coordinates) of the reference block and the position of the current block as an inter-frame prediction parameter to the motion estimation unit. This offset is also referred to as a motion vector (MV).

[0183] The motion compensation unit is configured to obtain, for example, receive, inter-frame prediction parameters and perform inter-frame prediction based on or using the inter-frame prediction parameters to obtain an inter-frame prediction block 246. The motion compensation performed by the motion compensation unit may include extracting or generating a prediction block based on a motion / block vector determined by motion estimation, and may also include performing interpolation with sub-pixel accuracy. Interpolation filtering can generate pixel points of other pixels from pixel points of known pixels, thereby potentially increasing the number of candidate prediction blocks that can be used to encode the image block. Upon receiving a motion vector corresponding to a PU of the current image block, the motion compensation unit may locate the prediction block pointed to by the motion vector in one of the reference picture lists.

[0184] The motion compensation unit may also generate syntax elements associated with blocks and video slices for use by video decoder 30 when decoding image blocks of a video slice. In addition to, or in lieu of, slices and corresponding syntax elements, coding block groups and / or coding blocks and corresponding syntax elements may be generated or used.

[0185] In the process of obtaining a candidate motion vector list in an advanced motion vector prediction (AMVP) mode, motion vectors (MVs) that can be added to the candidate motion vector list as alternatives include MVs of spatially and temporally adjacent image blocks of a current block, wherein the MVs of spatially adjacent image blocks can further include the MVs of a left candidate image block located to the left of the current block and the MVs of an upper candidate image block located above the current block. For example, please refer to FIG. 4 , which is an exemplary schematic diagram of candidate image blocks provided in an embodiment of the present application. As shown in FIG. 4 , the set of left candidate image blocks includes {A0, A1}, the set of upper candidate image blocks includes {B0, B1, B2}, and the set of temporally adjacent candidate image blocks includes {C, T}. All three sets can be added to the candidate motion vector list as alternatives. However, according to existing coding standards, the maximum length of the candidate motion vector list for AMVP is 2. Therefore, it is necessary to determine the MVs of up to two image blocks to be added to the candidate motion vector list from the three sets according to a prescribed order. The order may be to give priority to the set of candidate image blocks {A0, A1} to the left of the current block (consider A0 first, and then consider A1 if A0 is not available), then consider the set of candidate image blocks {B0, B1, B2} above the current block (consider B0 first, and then consider B1 if B0 is not available, and then consider B2 if B1 is not available), and finally consider the set of candidate image blocks {C, T} that are adjacent to the current block in the time domain (consider T first, and then consider C if T is not available).

[0186] After obtaining the candidate motion vector list, the optimal MV is determined from the candidate motion vector list using the rate distortion cost (RD cost), and the candidate motion vector with the smallest RD cost is used as the motion vector predictor (MVP) of the current block. The rate distortion cost is calculated using the following formula:

[0187] J=SAD+λR

[0188] Wherein, J represents RD cost, SAD is the sum of absolute differences (SAD) between the pixel values ​​of the predicted block obtained after motion estimation using the candidate motion vector and the pixel values ​​of the current block, R represents the bit rate, and λ represents the Lagrange multiplier.

[0189] The encoder passes the index of the determined MVP in the candidate motion vector list to the decoder. Furthermore, a motion search can be performed within a neighborhood centered on the MVP to obtain the actual motion vector of the current block. The encoder calculates the motion vector difference (MVD) between the MVP and the actual motion vector and also passes the MVD to the decoder. The decoder parses the index, finds the corresponding MVP in the candidate motion vector list based on the index, parses the MVD, and adds the MVD to the MVP to obtain the actual motion vector of the current block.

[0190] When obtaining the candidate motion information list in merge mode, the motion information that can be added to the candidate motion information list includes the motion information of spatially or temporally adjacent image blocks to the current block. For spatially and temporally adjacent image blocks, refer to Figure 4 . The spatially adjacent candidate motion information in the candidate motion information list comes from five spatially adjacent blocks (A0, A1, B0, B1, and B2). If the spatially adjacent blocks are unavailable or are intra-predicted, their motion information is not added to the candidate motion information list. The temporal candidate motion information for the current block is obtained by scaling the MV of the corresponding block in the reference frame based on the picture order count (POC) of the reference frame and the current frame. The block at position T in the reference frame is first determined to be available. If not, the block at position C is selected. After obtaining the candidate motion information list, the optimal motion information from the candidate motion information list is determined using the RD cost as the motion information for the current block. The encoder transmits the index of the optimal motion information in the candidate motion information list (denoted as the merge index) to the decoder.

[0191] Entropy Coding

[0192] The entropy coding unit 270 is configured to apply an entropy coding algorithm or scheme (e.g., a variable length coding (VLC) scheme, a context adaptive VLC (CALVC) scheme, an arithmetic coding scheme, a binarization algorithm, context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or other entropy coding methods or techniques) to the quantized residual coefficients 209, inter-frame prediction parameters, intra-frame prediction parameters, loop filter parameters, and / or other syntax elements, resulting in coded image data 21 that can be output via an output terminal 272 in the form of a coded bitstream 21, etc., so that the video decoder 30, etc. can receive and use the parameters for decoding. The coded bitstream 21 can be transmitted to the video decoder 30 or stored in a memory for later transmission or retrieval by the video decoder 30.

[0193] Other structural variations of the video encoder 20 may be used to encode the video stream. For example, a non-transform-based encoder 20 may directly quantize the residual signal without a transform processing unit 206 for certain blocks or frames. In another implementation, the encoder 20 may have the quantization unit 208 and the inverse quantization unit 210 combined into a single unit.

[0194] Decoder and decoding method

[0195] As shown in FIG3 , a video decoder 30 is configured to receive coded image data 21 (e.g., coded bitstream 21) encoded by, for example, an encoder 20, and generate a decoded image 331. The coded image data or bitstream includes information used to decode the coded image data, such as data representing image blocks of a coded video slice (and / or coding block group or coding block) and related syntax elements.

[0196] 3 , decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., summer 314), a loop filter 320, a decoded picture buffer (DBP) 330, a mode application unit 360, an inter-prediction unit 344, and an intra-prediction unit 354. Inter-prediction unit 344 may be or include a motion compensation unit. In some examples, video decoder 30 may perform a decoding process that is generally the reverse of the encoding process described with reference to video encoder 100 of FIG. 2 .

[0197] As described above with respect to encoder 20, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, loop filter 220, decoded picture buffer DPB 230, inter-frame prediction unit 344, and intra-frame prediction unit 354 also constitute the "built-in decoder" of video encoder 20. Accordingly, inverse quantization unit 310 may be functionally identical to inverse quantization unit 110, inverse transform processing unit 312 may be functionally identical to inverse transform processing unit 122, reconstruction unit 314 may be functionally identical to reconstruction unit 214, loop filter 320 may be functionally identical to loop filter 220, and decoded picture buffer 330 may be functionally identical to decoded picture buffer 230. Therefore, the explanations of the corresponding units and functions of video encoder 20 apply accordingly to the corresponding units and functions of video decoder 30.

[0198] Entropy decoding

[0199] The entropy decoding unit 304 is configured to parse the bitstream 21 (or generally, the encoded image data 21) and perform entropy decoding on the encoded image data 21 to obtain quantization coefficients 309 and / or decoded coding parameters (not shown in FIG. 3 ), such as any or all of inter-frame prediction parameters (e.g., reference image indices and motion vectors), intra-frame prediction parameters (e.g., intra-frame prediction modes or indices), transform parameters, quantization parameters, loop filter parameters, and / or other syntax elements. The entropy decoding unit 304 may be configured to apply a decoding algorithm or scheme corresponding to the coding scheme of the entropy coding unit 270 of the encoder 20. The entropy decoding unit 304 may also be configured to provide inter-frame prediction parameters, intra-frame prediction parameters, and / or other syntax elements to the mode application unit 360, as well as to provide other parameters to other units of the decoder 30. The video decoder 30 may receive syntax elements at the video slice and / or video block level. In addition to, or in lieu of, slices and corresponding syntax elements, coding block groups and / or coding blocks and corresponding syntax elements may also be received or used.

[0200] Dequantization

[0201] The inverse quantization unit 310 may be configured to receive a quantization parameter (QP) (or generally information related to inverse quantization) and quantization coefficients from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304), and inverse quantize the decoded quantization coefficients 309 based on the quantization parameter to obtain inverse quantization coefficients 311. The inverse quantization coefficients 311 may also be referred to as transform coefficients 311. The inverse quantization process may include using the quantization parameter calculated by the video encoder 20 for each video block in the video slice to determine a degree of quantization, and thus a degree of inverse quantization to be performed.

[0202] Inverse transform

[0203] The inverse transform processing unit 312 may be configured to receive the dequantized coefficients 311, also referred to as transform coefficients 311, and apply a transform to the dequantized coefficients 311 to obtain a reconstructed residual block 213 in the pixel domain. The reconstructed residual block 213 may also be referred to as a transform block 313. The transform may be an inverse transform, such as an inverse DCT, an inverse DST, an inverse integer transform, or a conceptually similar inverse transform process. The inverse transform processing unit 312 may also be configured to receive transform parameters or corresponding information from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304) to determine the transform to be applied to the dequantized coefficients 311.

[0204] reconstruction

[0205] The reconstruction unit 314 (eg, summer 314 ) is configured to add the reconstructed residual block 313 to the prediction block 365 to obtain the reconstructed block 315 in the pixel domain, eg, by adding the pixel values ​​of the reconstructed residual block 313 and the pixel values ​​of the prediction block 365 .

[0206] Filtering

[0207] The loop filter unit 320 (in or after the encoding loop) is used to filter the reconstructed block 315 to obtain a filter block 321, thereby smoothly performing pixel conversion or improving video quality. The loop filter unit 320 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process can be a deblocking filter, an SAO filter, and an ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., an adaptive in-loop reshaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process can also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 320 is shown as a loop filter in Figure 3, in other configurations, the loop filter unit 320 can be implemented as a post-loop filter.

[0208] Decoded Image Buffer

[0209] The decoded video blocks 321 of one picture are then stored in a decoded picture buffer 330 which stores the decoded picture 331 as a reference picture for subsequent motion compensation of other pictures and / or for respective output displays.

[0210] The decoder 30 is used to output the decoded image 311 through the output terminal 312, etc., for display to the user or for the user to view.

[0211] predict

[0212] The inter-frame prediction unit 344 may be functionally identical to the inter-frame prediction unit 244 (particularly the motion compensation unit), and the intra-frame prediction unit 354 may be functionally identical to the inter-frame prediction unit 254 and may determine the partitioning or segmentation and perform prediction based on the segmentation and / or prediction parameters or corresponding information received from the coded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304). The mode application unit 360 may be configured to perform prediction (intra-frame or inter-frame prediction) for each block based on the reconstructed image, block, or corresponding pixel point (filtered or unfiltered), resulting in a prediction block 365.

[0213] When the video slice is encoded as an intra-coded (I) slice, the intra-prediction unit 354 in the mode application unit 360 is configured to generate a prediction block 365 for the image block of the current video slice based on the indicated intra-prediction mode and data from previously decoded blocks of the current image. When the video image is encoded as an inter-coded (i.e., B or P) slice, the inter-prediction unit 344 (e.g., a motion compensation unit) in the mode application unit 360 is configured to generate a prediction block 365 for the video block of the current video slice based on the motion vector and other syntax elements received from the entropy decoding unit 304. For inter-prediction, these prediction blocks can be generated from one of the reference pictures in one of the reference picture lists. Video decoder 30 can construct reference frame list 0 and list 1 using a default construction technique based on the reference pictures stored in DPB 330. The same or similar processes may be applied to embodiments of coding block groups (e.g., video coding block groups) and / or coding blocks (e.g., video coding blocks) in addition to or instead of slices (e.g., video slices), e.g., video may be encoded using I, P, or B coding block groups and / or coding blocks.

[0214] Mode application unit 360 is configured to determine prediction information for video blocks of a current video slice by parsing motion vectors and other syntax elements, and to use the prediction information to generate a prediction block for the current video block being decoded. For example, mode application unit 360 uses received syntax elements to determine a prediction mode (e.g., intra prediction or inter prediction) used to encode the video blocks of the video slice, an inter prediction slice type (e.g., a B slice, a P slice, or a GPB slice), construction information for one or more reference picture lists for the slice, a motion vector for each inter-coded video block in the slice, an inter prediction state for each inter-coded video block in the slice, and other information to decode the video blocks within the current video slice. In addition to or in lieu of slices (e.g., video slices), the same or similar process may be applied to embodiments of coding block groups (e.g., video coding block groups) and / or coding blocks (e.g., video coding blocks), for example, video may be encoded using I, P, or B coding block groups and / or coding blocks.

[0215] In one embodiment, the video encoder 30 of FIG3 may also be configured to partition and / or decode an image using slices (also referred to as video slices), where an image may be partitioned or decoded using one or more (typically non-overlapping) slices. Each slice may include one or more blocks (e.g., CTUs) or one or more groups of blocks (e.g., coding blocks in the H.265 / HEVC / VVC standard and bricks in the VVC standard).

[0216] In one embodiment, the video decoder 30 shown in Figure 3 can also be used to segment and / or decode an image using slices / coding block groups (also called video coding block groups) and / or coding blocks (also called video coding blocks), where the image can be segmented or decoded using one or more slices / coding block groups (usually non-overlapping), each slice / coding block group may include one or more blocks (e.g., CTUs) or one or more coding blocks, etc., where each coding block can be in a shape such as a rectangle and may include one or more complete or partial blocks (e.g., CTUs).

[0217] Other variations of the video decoder 30 may be used to decode the encoded image data 21. For example, the decoder 30 may generate an output video stream without the loop filter unit 320. For example, a non-transform-based decoder 30 may directly inverse quantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames. In another implementation, the video decoder 30 may have the inverse quantization unit 310 and the inverse transform processing unit 312 combined into a single unit.

[0218] It should be understood that the processing result of the current step can be further processed in the encoder 20 and the decoder 30 and then output to the next step. For example, after interpolation filtering, motion vector derivation, or loop filtering, the processing result of interpolation filtering, motion vector derivation, or loop filtering can be further operated on, such as clipping or shifting operations.

[0219] It should be noted that further operations can be performed on the derived motion vector of the current block (including but not limited to control point motion vectors in affine mode, sub-block motion vectors in affine, planar, ATMVP modes, temporal motion vectors, etc.). For example, the value of the motion vector can be limited to a predefined range based on the representation bit of the motion vector. If the representation bit of the motion vector is bitDepth, the range is -2^(bitDepth-1) to 2^(bitDepth-1)-1, where "^" represents a power. For example, if bitDepth is set to 16, the range is -32768 to 32767; if bitDepth is set to 18, the range is -131072 to 131071. For example, the value of the derived motion vector (e.g., the MVs of four 4×4 sub-blocks in an 8×8 block) is limited so that the maximum difference between the integer parts of the above four 4×4 sub-block MVs does not exceed N pixels, for example, not more than 1 pixel. Two methods of limiting motion vectors based on bitDepth are provided here.

[0220] Although the above embodiments primarily describe video coding, it should be noted that embodiments of the decoding system 10, encoder 20, and decoder 30, as well as other embodiments described herein, may also be used for still image processing or coding, i.e., processing or coding a single image in a video codec that is independent of any previous or subsequent images. In general, if image processing is limited to a single image 17, the inter-frame prediction unit 244 (encoder) and the inter-frame prediction unit 344 (decoder) may not be available. All other functionalities (also referred to as tools or techniques) of the video encoder 20 and video decoder 30, such as residual calculation 204 / 304, transform 206, quantization 208, inverse quantization 210 / 310, (inverse) transform 212 / 312, segmentation 262 / 362, intra-frame prediction 254 / 354, and / or loop filtering 220 / 320, entropy coding 270, and entropy decoding 304, may also be used for still image processing.

[0221] Please refer to Figure 5, which is an exemplary block diagram of a video decoding device 500 provided in an embodiment of the present application. Video decoding device 500 is suitable for implementing the disclosed embodiments described herein. In one embodiment, video decoding device 500 can be a decoder, such as the video decoder 30 in Figure 1a, or an encoder, such as the video encoder 20 in Figure 1a.

[0222] Video decoding device 500 includes: an input port 510 (or input port 510) and a receiver unit (Rx) 520 for receiving data; a processor, logic unit, or central processing unit (CPU) 530 for processing data; for example, processor 530 may be a neural network processor 530; a transmitter unit (Tx) 540 and an output port 550 (or output port 550) for transmitting data; and a memory 560 for storing data. Video decoding device 500 may also include optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to input port 510, receiver unit 520, transmitter unit 540, and output port 550 for outputting or transmitting optical or electrical signals.

[0223] The processor 530 is implemented in hardware and software. The processor 530 can be implemented as one or more processor chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs. The processor 530 communicates with the input port 510, the receiving unit 520, the transmitting unit 540, the output port 550, and the memory 560. The processor 530 includes a decoding module 570 (e.g., a neural network-based decoding module 570). The decoding module 570 implements the embodiments disclosed above. For example, the decoding module 570 performs, processes, prepares, or provides various encoding operations. Therefore, the decoding module 570 provides substantial improvements to the functionality of the video decoding device 500 and affects the switching of the video decoding device 500 to different states. Alternatively, the decoding module 570 is implemented by instructions stored in the memory 560 and executed by the processor 530.

[0224] Memory 560 includes one or more disks, tape drives, and solid-state drives and can be used as overflow data storage for storing programs when such programs are selected for execution, and for storing instructions and data read during program execution. Memory 560 can be volatile and / or non-volatile and can be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and / or static random-access memory (SRAM).

[0225] Please refer to FIG. 6 , which is an exemplary block diagram of an apparatus 600 provided in an embodiment of the present application. The apparatus 600 may be used as either or both of the source device 12 and the destination device 14 in FIG. 1 a .

[0226] The processor 602 in the apparatus 600 may be a central processing unit. Alternatively, the processor 602 may be any other type of device or devices, now available or developed in the future, capable of manipulating or processing information. While the disclosed implementations may be implemented using a single processor, such as the processor 602 shown, using more than one processor may provide greater speed and efficiency.

[0227] In one implementation, the memory 604 in the apparatus 600 may be a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device may be used as the memory 604. The memory 604 may include code and data 606 that are accessed by the processor 602 via a bus 612. The memory 604 may also include an operating system 608 and application programs 610, which include at least one program that allows the processor 602 to perform the methods described herein. For example, the application programs 610 may include applications 1 through N, as well as a video decoding application that performs the methods described herein.

[0228] The apparatus 600 may also include one or more output devices, such as a display 618. In one example, the display 618 may be a touch-sensitive display that combines a display with touch-sensitive elements that can be used to sense touch input. The display 618 may be coupled to the processor 602 via the bus 612.

[0229] Although bus 612 in device 600 is described herein as a single bus, bus 612 may include multiple buses. Furthermore, secondary storage may be directly coupled to other components of device 600 or accessed via a network, and may include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Thus, device 600 may have a variety of configurations.

[0230] Before describing the embodiments of the present application, the terms and concepts used in the embodiments of the present application are first explained.

[0231] Reconstructed image: This refers to the lossy image obtained by decoding the encoded image bitstream, which can be displayed and played. It exists on both the encoder and decoder, and the reconstructed image on both ends is identical. On the encoder, the reconstructed image can be used as a reference image for the image to be encoded to perform inter-frame prediction encoding. On the decoder, the reconstructed image can be used as a reference image for the image to be decoded to perform inter-frame prediction decoding.

[0232] RAP: Random access point in video encoding. The encoded video bitstream includes at least one RAP. When random access occurs, the video bitstream before the RAP can be skipped, and the subsequent image bitstream can be decoded from the RAP and the reconstructed video image output by the decoder can be played. From the perspective of video playback, random access can be understood as dragging the progress bar of the player to achieve random jumps of the video when watching on-demand video (or local playback video); or when a black screen occurs due to packet loss when watching live broadcast, the client will access the video stream and continue to play the video when the next RAP arrives. RAP is usually an intra-coded picture (I) frame. The I frame only uses the information within the current frame for predictive coding to eliminate information redundancy in the spatial domain without relying on other frames.

[0233] RAS: A RAS includes all images from one RAP to the next. Images in a RAS are forward-predicted (P) frames or bidirectionally interpolated prediction (B) frames. P and B frames use already coded images for temporal prediction to eliminate temporal redundancy.

[0234] For example, please refer to Figure 7, which is a schematic diagram of a video sequence provided in an embodiment of the present application. Figure 7 shows 11 video frames a1 to a11. Among them, a2, a6 and a10 are I frames and serve as RAP, all video frames between a2 and a6 are P frames and constitute RAS1, and all video frames between a6 and a10 are P frames and constitute RAS2. As can be seen from Figure 7, each P frame needs to be encoded with reference to the previous m video frames, where m is an integer greater than 1. For example, a3 can be encoded with reference to a2, and a4 can be encoded with reference to a2 and / or a3.

[0235] CRR encoding: When encoding a video frame in one RAS, video frames in other RASs other than the RAS can be referenced for encoding.

[0236] In most videos (such as movies or TV shows), many scenes appear alternately, and the scenes shown at different times may be similar. The interval duration between two adjacent similar scenes is usually long. Therefore, two adjacent similar scenes are in the same RAP but with a long interval, or the temporal correlation spans across RAPs. For example, in video standards, the length of the RAS is generally specified as 1 s or 2 s, and the interval duration between two adjacent similar scenes is usually close to the length of the RAS (e.g., 0.7 s) or greater than the length of the RAS (e.g., 3 s). In addition, in video scenarios such as security monitoring, similar scenes usually appear for a long time. Therefore, there are also cases where two similar scenes are in the same RAP but with a long interval, or the temporal correlation spans across RAPs.

[0237] Keystream: In cryptography, a keystream is a stream of characters containing random or pseudorandom characters, which is used to combine with a plaintext data stream to generate an encrypted message (ciphertext).

[0238] Network Abstraction Layer Unit (NALU): In video coding, all encoded data is encapsulated into individual NALUs for transmission. They all have a unified structure. Each NALU contains two parts: the NALU header and the NALU payload (RBSP). The length of the NALU Header is fixed at two bytes, reflecting the content payload of the NALU; the length of the RBSP is an integer number of bytes, carrying the bitstream segment after video coding. Whether it is SPS, PPS, or video coding data, it is encapsulated in the form of NALUs.

[0239] Picture Parameter Set and Sequence Parameter Set (PPS and SPS): They contain all the parameters required for encoding the entire sequence or the entire picture. In principle, in addition to the key parameters describing the characteristics of the encoded sequence, the SPS should also carry the control switches of most encoding tools and the corresponding encoding limit parameters. The scope of the parameters in the SPS is the entire encoded sequence, which means that during the entire video coding process, there is only one SPS, and the parameters therein are not allowed to change; for the PPS, in principle, some tool parameters are allowed to change at the frame level but not frequently, so the picture-level tool control parameters can be further repeated and sent at a lower PPS, which means that the parameters in the PPS are allowed to change according to the changes in picture characteristics. Usually, the scope of the PPS is n pictures (0 < n < all pictures).

[0240] The SPS includes a set of global parameters for the video coding sequence, such as the color space, the size of each frame (width and height), and the encoding profile. The PPS includes coding parameters for at least one frame, such as the quantization matrix and filter parameters. The picture header includes coding parameters for a frame, such as the frame number.

[0241] For example, for SPS, one SPS may be placed before every N CRR slice bitstreams, or one SPS may be placed before the entire bitstream. For PPS, one PPS may be placed before every multiple bitstreams. For picture header, one picture header may be placed before the first CRR slice bitstream, and one slice header or segment header may be placed before the bitstreams of other non-first CRR slices.

[0242] The embodiments of the present application provide a coding and decoding method that can improve the security of the CRR media content transmission process.

[0243] Please refer to FIG8 , which is a flowchart of an encoding method provided in an embodiment of the present application. The method can be applied to an encoder and may include the following steps:

[0244] S801: Perform encoding operations on multiple display images and multiple CRR images to obtain code streams.

[0245] The code stream includes a security parameter set and an authentication data set. The security parameter set includes first information and second information. The first information is used to indicate the algorithm used to generate the top-of-tree summary, and the second information is used to indicate the algorithm used to perform the digital signature.

[0246] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0247] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag = 0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag = 1 indicates that the current authentication data belongs to a CRR slice, constraining all CRR slices to be authenticated.

[0248] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0249] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which represents the length of the signature data in bytes, and the value should be 0 to 255.

[0250] In a possible implementation, the authentication data set further includes fifth information, where the fifth information is used to indicate a CRR image corresponding to an authentication range of the current authentication data set.

[0251] For example, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to specify which CRR image the authentication range of the current authentication data set belongs to. This parameter can only be parsed when is_crr_flag=1.

[0252] Exemplarily, as shown in Table 1, the security parameter set provided in the embodiment of the present application may include the following information.

[0253] Table 1

[0254] Where encryption_flag is equal to 1, which indicates that encryption of picture coding slices, sequence parameter sets, picture parameter sets, or extended data units is supported, that is, the RBSP in the NAL unit may be encrypted. Encryption_flag is equal to 0, which indicates that encryption of RBSP in the NAL unit is not supported.

[0255] When authentication_flag is equal to 1, it indicates that authentication of the entire frame image data content is supported. The NAL units for authentication include the coded slice, as well as the sequence parameter set, picture parameter set, security parameter set, and extended data unit transmitted in the frame. When authentication of the above data content is supported, the coded bitstream must carry absolute time extension information, and the authentication data carried in the coded bitstream should be Base64 encoded. The authentication data is transmitted via a NAL unit with nal_unit_type equal to 10. If the image contains coded slices, sequence parameter sets, picture parameter sets, security parameter sets, extended data units, etc. with authentication_idc equal to 1, the NAL units with authentication_idc equal to 1 in a picture are arranged in decoding order and authenticated to generate the summary data of the picture. When authentication_flag is equal to 0, it indicates that authentication of the picture is not supported, and the coded bitstream should not contain NAL units with nal_unit_type equal to 10.

[0256] If spatial_svc_flag is equal to 1, the base layer image and enhancement layer image of the same frame are authenticated separately, the image parameter set and coding slice of the enhancement layer are authenticated as the enhancement layer, and the sequence parameter set, security parameter set and extended data unit are authenticated together with the image parameter set and coding slice of the base layer as the base layer.

[0257] vek_flag equal to 1 indicates that the video encryption key (VEK) is carried; equal to 0 indicates that the video encryption key (VEK) is not carried.

[0258] iv_flag equal to 1 indicates that the initialization vector (IV) is carried; equal to 0 indicates that the initialization vector (IV) is not carried.

[0259] camera_id is a 20-byte string that indicates the camera ID of the image source.

[0260] vek_encryption_type indicates the algorithm used for key encryption. The specific correspondence is the same as encryption_type.

[0261] evek_length_minus1 is the encrypted key length minus 1, in bytes.

[0262] evek is the encrypted key used for encryption calculations, and its length is evek_length_minus1 plus 1 byte.

[0263] vkek_version length_minus1 is the encryption key version number length minus 1, in bytes.

[0264] vkek_version is the encryption key version number, and its length is vkek_version_length_minus1 plus 1 byte.

[0265] iv_length_minus1 is the initial vector length minus 1, in bytes.

[0266] iv is the initialization vector, used for block encryption, and its length is iv_length_minus1 plus 1 byte.

[0267] encryption_type indicates the encryption algorithm used.

[0268] For example, as shown in Table 2, when encryption_type takes a value of 0, it indicates that the encryption algorithm used is the SM1 algorithm. When encryption_type takes a value of 1, it indicates that the encryption algorithm used is the SM4 algorithm.

[0269] Table 2

[0270] hash_type indicates the algorithm used to generate the tree top digest.

[0271] For example, as shown in Table 3, when the value of hash_type is 0, it indicates that the algorithm used to generate the tree top digest is the SM3 algorithm.

[0272] Table 3

[0273] signature_type indicates the algorithm used to digitally sign the image's summary data.

[0274] Exemplarily, as shown in Table 4, when the value of signature_type is 0, it indicates that the algorithm used to digitally sign the summary data of the image is the SM2 algorithm.

[0275] Table 4

[0276] If hash_discard_p_pictures is equal to 1, authentication is not performed for non-IDR pictures; if it is equal to 0, authentication is performed for non-IDR pictures. If hash_discard_p_pictures is not in the bitstream, its default value is 1. The authentication_idc of each NAL unit in the picture not to be authenticated shall be equal to 0.

[0277] successive_hash_pictures_minus1 plus 1 represents the number of consecutive pictures that are digitally signed in decoding order, and these consecutive pictures are limited to one IDR picture interval. The value of successive_hash_pictures_minus1 should be 0 to 255.

[0278] If successive_hash_pictures_minus1 is greater than 0, a tree-type digest is first generated for the digest data of SuccessiveHashPictures consecutive pictures in decoding order, and then the tree-top digest is digitally signed. For example, the tree-top digest of n pictures is the digest data of the first n-1 pictures and the digest data of the nth picture, arranged in the same way as hash_type.

[0279] camera_idc is a 19-byte string that indicates the certificate identifier of the camera from which the image is obtained.

[0280] For example, as shown in Table 5, the authentication data set provided in the embodiment of the present application may include the following information.

[0281] Table 5

[0282] Among them, is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag = 0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag = 1 indicates that the current authentication data belongs to a CRR slice, constraining all CRR slices to be authenticated.

[0283] crr_picture_index specifies which CRR image the authentication range of the current authentication dataset belongs to. This parameter can be parsed only when is_crr_flag=1.

[0284] frame_num indicates the picture that should contain the authentication data. This picture is the picture whose frame_num is the same as the frame_num of the authentication data immediately preceding the authentication data NAL unit. When successive_hash_pictures_minus1 is equal to 0, frame_num indicates the picture corresponding to the authentication data; when it is greater than 0, frame_num indicates the last of the consecutive SuccessiveHashPictures pictures.

[0285] If spatial_el_flag is 1, it indicates that the authentication data is the enhancement layer signature data. If spactial_el_flag is 0, it indicates that the authentication data is the base layer signature data. If spactial_el_flag does not exist in the codestream, its value is 0 by default.

[0286] authentication_data_length_minus1 plus 1 indicates the length of the signature data in bytes, and the value should be 0 to 255.

[0287] authentication_data[i] is the i-th byte of the signature data.

[0288] For example, please refer to Figure 9, which is a schematic diagram of a coding and decoding process provided by an embodiment of the present application. The encoder encodes multiple display images and multiple CRR images to obtain a code stream and sends the code stream to the decoder. Figure 9 is illustrated by taking three CRC slice bit streams b1 to b3 (n=3) and five main bit streams c1 to c5 as an example. The decoder decodes in sequence according to the order of each bit stream in the encoded image bit stream to obtain five reconstructed display images c1′ to c5′ and a reconstructed CRR image. The five reconstructed display images are used for display, and the reconstructed CRR image is only used as a reference image when decoding the display image bit stream and is not used for display.

[0289] S802: Authenticate the data to be authenticated according to the first information to obtain first tree-top summary data.

[0290] The first tree-top summary data is the tree-top summary data of the encoding end, and the first tree-top summary data includes the tree-top summary data of N main bit streams and / or M CRC slice bit streams, where N and M are positive integers.

[0291] For example, if the first information, that is, hash_type, takes a value of 0, the SM3 algorithm can be used to authenticate the data to be authenticated (NALU data of N main bitstreams and / or M CRC slice bitstreams) to obtain the first tree top summary data. The NALU data includes the NAL Uheader and the RBSP of the NALU.

[0292] S803: Perform signature calculation on the first tree-top summary data according to the second information to obtain a digital signature.

[0293] For example, if the value of signature_type in the second information is 0, the SM2 algorithm may be used to perform signature calculation on the first tree-top summary data to obtain a digital signature (ie, video authentication data).

[0294] S804: Encapsulate the digital signature into the authentication data set.

[0295] In a possible implementation, the data signature may be encoded and the encoded data signature may be encapsulated into the authentication data set.

[0296] For example, the data signature can be Base64-encoded and encapsulated into the authentication data set as an independent NALU type. The authentication data set is constrained to have all relevant data of the most recent CRR image (the SPS, PPS, and CRR slice stream of the CRR image), or all relevant data of the N previous display images (the SPS, PPS, and corresponding display image stream of the display image).

[0297] Please refer to FIG10 , which is a flowchart of a decoding method provided in an embodiment of the present application. The method can be applied to a decoder and may include the following steps:

[0298] S1001. Obtain code stream.

[0299] Among them, the above-mentioned code stream is obtained by encoding multiple display images and the multiple CRR images. The above-mentioned code stream includes a security parameter set and an authentication data set. The above-mentioned security parameter set includes first information and second information. The above-mentioned first information is used to indicate the algorithm used to generate the tree top summary, and the above-mentioned second information is used to indicate the algorithm used for digital signature. The above-mentioned authentication data set includes a digital signature.

[0300] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0301] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0302] S1002: Decode the digital signature according to the second information to obtain first tree-top summary data.

[0303] The first tree-top summary data is the tree-top summary data of the encoding end, and the first tree-top summary data includes the tree-top summary data of N main bit streams and / or M CRC slice bit streams, where N and M are positive integers.

[0304] In a possible implementation, the digital signature may be decoded; and the decoded digital signature may be decoded according to the second information to obtain the first tree-top summary data.

[0305] S1003: Authenticate the authentication data corresponding to the authentication data set according to the first information to obtain second tree-top summary data.

[0306] The second tree-top summary data is the tree-top summary data of the decoding end, and the first tree-top summary data includes the tree-top summary data of N main bit streams and / or M CRC slice bit streams.

[0307] S1004: Verify the authentication data according to the first treetop summary and the second treetop summary data.

[0308] Exemplarily, when the first tree-top summary data and the second tree-top summary data are consistent, it can be determined that the authentication data is complete and authentic (ie, the authentication data has not been tampered with).

[0309] As another example, when the first tree-top summary data and the second tree-top summary data are inconsistent, it can be determined that the authentication data is incomplete or untrue (ie, the authentication data may be tampered with).

[0310] Please refer to FIG11, which is a flowchart of an encoding method provided in an embodiment of the present application. The method can be applied to an encoder and may include the following process:

[0311] S1101 . Perform encoding operations on multiple display images and multiple CRR images to obtain a code stream.

[0312] The above-mentioned code stream includes a security parameter set, and the above-mentioned security parameter set includes a video encryption key.

[0313] S1102: Encrypt the code stream according to the video encryption key.

[0314] In a possible implementation, the payload data of the code stream may be encrypted according to a video encryption key.

[0315] The payload data includes at least one of a sequence parameter set SPS, a picture parameter set PPS, a main bit stream, and a CRC slice bit stream.

[0316] For example, the encoder periodically randomly generates a 16-byte video encryption key (VEK). The payload data to be encrypted is then read from the bitstream. The encoder randomly generates a 16-byte initialization vector (IV). The currently used video encryption key (VEK) and initialization vector (IV) are encrypted using the source's video key encryption key (VKEK), and the corresponding ciphertext is encapsulated into the NALU of the security parameter set. The video encryption key (VEK) and initialization vector (IV) are used in output-feedback (OFB) mode of the agreed-upon block cipher algorithm to generate a keystream using the video encryption key (VEK) and initialization vector (IV). The stream key is bit-aligned with the coded slice RBSP data to be encrypted, and then an XOR operation is performed to obtain the encrypted coded slice RBSP data. The encrypted RBSP data is encapsulated into a VCL_NALU, and the encryption_idc of the NALU is set to 1. If a new video encryption key (VEK) is activated or a new initialization vector (IV) is used, the encapsulated security extension information (NAL) should be re-encoded and pre-encrypted before the currently encrypted output VLC_NAL.

[0317] Optionally, when this RBSP is the first coded slice data at the beginning of a group of pictures (GOP) and a new video encryption key (VEK) is available, the current video encryption key (VEK) can be invalidated and a new video encryption key (VEK) can be activated; otherwise, the current video encryption key (VEK) can continue to be used.

[0318] Please refer to FIG12 , which is a flowchart of a decoding method provided in an embodiment of the present application. The method can be applied to a decoder and may include the following steps:

[0319] S1201: Obtain code stream.

[0320] The code stream is obtained by encoding multiple display images and the multiple CRR images, and the code stream includes a security parameter set, which includes a video encryption key.

[0321] S1202: Decrypt the code stream according to the video encryption key.

[0322] In a possible implementation, the payload data of the code stream may be decrypted according to the video encryption key.

[0323] The payload data includes at least one of an SPS, a PPS, a main bit stream and a CRC slice bit stream.

[0324] For example, the ciphertext of the initial vector (IV) and the video encryption key (VEK) can be obtained from the security parameter set NAL, denoted as E(VEK), and E(VEK) can be decrypted with the video key encryption key (VKEK) to obtain the video encryption key (VEK). Read the coded slice RBSP data to be decrypted. Use the OFB mode of the agreed block encryption algorithm to generate a key stream using the video encryption key (VEK) and the initial vector (IV). The stream key is bit-aligned with the coded slice RBSP data to be decrypted, and an XOR operation is performed to obtain the decrypted coded slice RBSP data.

[0325] Optionally, when this RBSP is the first coded slice data at the beginning of a group of pictures (GOP) and a new video encryption key (VEK) is available, the current video encryption key (VEK) can be invalidated and a new video encryption key (VEK) can be activated; otherwise, the current video encryption key (VEK) can continue to be used.

[0326] S1203: Determine a reconstructed image according to the decoded code stream.

[0327] The following will introduce a coding and decoding device for executing the above coding and decoding method with reference to FIG13 to FIG16.

[0328] It is understandable that, in order to implement the above functions, the encoding device includes hardware and / or software modules that perform the corresponding functions. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0329] In the embodiment of the present application, the encoding device can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. In actual implementation, other division methods can be used.

[0330] In the case of dividing the functional modules according to the corresponding functions, Figure 13 shows a possible composition diagram of the encoding device involved in the above embodiment. As shown in Figure 13, the encoding device 1300 may include: an encoding unit 1301 and an authentication unit 1302.

[0331] The encoding unit 1301 is used to perform encoding operations on multiple display images and the above-mentioned multiple CRR images to obtain a code stream, where the above-mentioned code stream includes a security parameter set and an authentication data set. The above-mentioned security parameter set includes first information and second information. The above-mentioned first information is used to indicate the algorithm used for generating the tree top summary, and the above-mentioned second information is used to indicate the algorithm used for digital signature.

[0332] The authentication unit 1302 is configured to authenticate the data to be authenticated based on the first information to obtain first tree-top summary data, where the first tree-top summary data is the tree-top summary data of the encoding end and includes tree-top summary data of N main bitstreams and / or M CRC slice bitstreams, where N and M are positive integers.

[0333] The authentication unit 1302 is further configured to perform signature calculation on the first tree-top summary data according to the second information to obtain a digital signature. The authentication unit is further configured to encapsulate the digital signature into the authentication data set.

[0334] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0335] Exemplarily, the third information may be is_crr_flag. is_crr_flag indicates whether the current authentication data set belongs to a CRR image. is_crr_flag = 0 indicates that the current authentication data belongs to the main bitstream; is_crr_flag = 1 indicates that the current authentication data belongs to a CRR slice, constraining all CRR slices to be authenticated.

[0336] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0337] Exemplarily, the fourth information may be authentication_data_length_minus1+1, which represents the length of the signature data in bytes, and the value should be 0 to 255.

[0338] In a possible implementation, the authentication data set further includes fifth information, where the fifth information is used to indicate a CRR image corresponding to an authentication range of the current authentication data set.

[0339] For example, the fifth information may be crr_picture_index. crr_picture_index is used to indicate the CRR image corresponding to the authentication range of the current authentication data set, that is, to specify which CRR image the authentication range of the current authentication data set belongs to. This parameter can only be parsed when is_crr_flag=1.

[0340] In a possible implementation, the authentication unit 1302 is specifically configured to: encode the data signature; and encapsulate the encoded data signature into the authentication data set.

[0341] In one possible implementation, the encoding unit 1301 is specifically used to: divide the above-mentioned CRR image to obtain multiple CRR slices; interleave the above-mentioned multiple CRR slices between the above-mentioned multiple display images to obtain an image sequence to be encoded; and sequentially perform encoding operations on the above-mentioned CRR slices and the above-mentioned display images in the above-mentioned image sequence to be encoded to obtain the above-mentioned code stream.

[0342] In a possible implementation, the code stream includes multiple CRC slice bit streams and multiple main bit streams in an interleaved order.

[0343] In the embodiments of the present application, the decoding device can be divided into functional modules according to the above-mentioned method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into a processing module. The above-mentioned integrated modules can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical functional division. In actual implementation, other division methods may be used.

[0344] In the case of dividing the functional modules according to their respective functions, FIG14 shows a possible composition diagram of the decoding device involved in the above embodiment. As shown in FIG14 , the decoding device 1400 may include: a transceiver unit 1401 and an authentication unit 1402 .

[0345] The transceiver unit 1401 is used to obtain a code stream, where the code stream includes a security parameter set and an authentication data set. The security parameter set includes first information and second information. The first information is used to indicate the algorithm used to generate the top-of-tree digest, and the second information is used to indicate the algorithm used to perform the digital signature. The authentication data set includes a digital signature.

[0346] The authentication unit 1402 is configured to decode the digital signature according to the second information to obtain first tree-top summary data, where the first tree-top summary data is tree-top summary data at the encoding end and includes tree-top summary data of N main bit streams and / or M CRC slice bit streams, where N and M are positive integers.

[0347] The authentication unit 1402 is further configured to authenticate the authentication data corresponding to the authentication data set according to the first information to obtain second tree-top summary data, where the second tree-top summary data is the tree-top summary data of the decoding end, and the first tree-top summary data includes the tree-top summary data of the N main bitstreams and / or the M CRC slice bitstreams.

[0348] The authentication unit 1402 is further configured to verify the authentication data according to the first tree-top summary and the second tree-top summary data.

[0349] In a possible implementation, the authentication unit 1402 is specifically configured to: decode the digital signature; and decode the decoded digital signature according to the second information to obtain first tree-top summary data.

[0350] In a possible implementation, the authentication data set further includes third information, and the third information is used to indicate whether the authentication data belongs to a CRR slice.

[0351] In a possible implementation, the authentication data set further includes fourth information, where the fourth information is used to indicate the number of authenticated image streams.

[0352] In the case of dividing the functional modules according to the corresponding functions, Figure 15 shows another possible composition diagram of the encoding device involved in the above embodiment. As shown in Figure 15, the encoding device 1500 may include: an encoding unit 1501 and an encryption unit 1502.

[0353] The encoding unit 1501 is configured to perform an encoding operation on the multiple display images and the multiple CRR images to obtain a code stream, where the code stream includes a security parameter set, and the security parameter set includes a video encryption key.

[0354] The encryption unit 1502 is configured to encrypt the code stream according to the video encryption key.

[0355] In one possible implementation, the encryption unit 1502 is specifically used to encrypt the payload data of the above-mentioned code stream according to the above-mentioned video encryption key, where the above-mentioned payload data includes at least one of the sequence parameter set SPS, the picture parameter set PPS, the main bit stream and the CRC slice bit stream.

[0356] In the case of dividing the functional modules according to the corresponding functions, Figure 16 shows another possible composition diagram of the decoding device involved in the above embodiment. As shown in Figure 16, the decoding device 1600 may include: a transceiver unit 1601, a decryption unit 1602 and a reconstruction unit 1603.

[0357] The transceiver unit 1601 is configured to obtain a bitstream, where the bitstream includes a security parameter set, and the security parameter set includes a video encryption key.

[0358] The decryption unit 1602 is configured to decrypt the code stream according to the video encryption key.

[0359] The reconstruction unit 1603 is configured to determine a reconstructed image according to the decoded code stream.

[0360] In a possible implementation, the decryption unit 1602 is specifically configured to decrypt the payload data of the code stream according to the video encryption key, where the payload data includes at least one of the SPS, PPS, main bit stream, and CRC slice bit stream.

[0361] An embodiment of the present application also provides an encoding device, which includes: at least one processor, when the at least one processor executes program code or instructions, implements the above-mentioned related method steps to implement the encoding method in the above-mentioned embodiment.

[0362] Optionally, the apparatus may further include at least one memory configured to store the program code or instruction.

[0363] An embodiment of the present application also provides a decoding device, which includes: at least one processor, when the at least one processor executes program code or instructions, implements the above-mentioned related method steps to implement the decoding method in the above embodiment.

[0364] Optionally, the apparatus may further include at least one memory configured to store the program code or instruction.

[0365] An embodiment of the present application also provides a computer storage medium, which stores computer instructions. When the computer instructions are executed on an encoding device, the encoding device executes the above-mentioned related method steps to implement the encoding and decoding method in the above-mentioned embodiment.

[0366] The embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the encoding and decoding method in the above-mentioned embodiment.

[0367] The present application also provides a coding and decoding device, which can be a chip, integrated circuit, component, or module. Specifically, the device may include a connected processor and a memory for storing instructions, or the device may include at least one processor for retrieving instructions from an external memory. When the device is running, the processor may execute the instructions to cause the chip to perform the coding and decoding methods described in the above method embodiments.

[0368] 17 shows a schematic structural diagram of a chip 1700. The chip 1700 includes one or more processors 1701 and an interface circuit 1702. Optionally, the chip 1700 may further include a bus 1703.

[0369] The processor 1701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above encoding and decoding method can be completed by a hardware integrated logic circuit in the processor 1701 or by software instructions.

[0370] Optionally, the processor 1701 may be a general-purpose processor, a digital signal processing (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The methods and steps disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor.

[0371] The interface circuit 1702 can be used to send or receive data, instructions or information. The processor 1701 can use the data, instructions or other information received by the interface circuit 1702 to process it, and can send the processing completion information through the interface circuit 1702.

[0372] Optionally, the chip also includes a memory, which may include a read-only memory and a random access memory, and provides operating instructions and data to the processor. Part of the memory may also include a non-volatile random access memory (NVRAM).

[0373] Optionally, the memory stores an executable software module or a data structure, and the processor can perform corresponding operations by calling an operation instruction stored in the memory (the operation instruction may be stored in an operating system).

[0374] Optionally, the chip can be used in the encoding device or DOP involved in the embodiments of the present application. Optionally, the interface circuit 1702 can be used to output the execution result of the processor 1701. Regarding the encoding and decoding methods provided in one or more embodiments of the present application, reference can be made to the aforementioned embodiments and will not be repeated here.

[0375] It should be noted that the corresponding functions of the processor 1701 and the interface circuit 1702 can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.

[0376] FIG18 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 1800 can be a device or a chip or functional module in the device. As shown in FIG18 , the electronic device 1800 includes a processor 1801 , a transceiver 1802 , and a communication line 1803 .

[0377] The processor 1801 is used to execute any step of the method provided in the embodiment of the present application, and when executing processes such as receiving a coded image bit stream, the transceiver 1802 and the communication line 1803 may be selectively called to complete the corresponding operation.

[0378] Furthermore, the electronic device 1800 may further include a memory 1804 . The processor 1801 , the memory 1804 and the transceiver 1802 may be connected via a communication line 1803 .

[0379] Transceiver 1802 is used to communicate with other devices or other communication networks, such as Ethernet, radio access networks (RAN), wireless local area networks (WLAN), etc. Transceiver 1802 can be a module, circuit, transceiver, or any device capable of implementing communication.

[0380] The transceiver 1802 is mainly used for transmitting and receiving bit streams, etc., and may include a transmitter and a receiver for transmitting and receiving bit streams, etc., respectively; operations other than transmitting and receiving bit streams, etc. are implemented by the processor, such as enabling at least one target channel in the channel group of the chip, etc.

[0381] The communication line 1803 is used to transmit information between the various components included in the electronic device 1800.

[0382] In one design, the processor can be considered as the logic circuit and the transceiver as the interface circuit.

[0383] The memory 1804 is used to store instructions, where the instructions may be computer programs.

[0384] It should be noted that memory 1804 can exist independently of processor 1801 or can be integrated with processor 1801. Memory 1804 can be used to store instructions, program code, or data. Memory 1804 can be located within or outside electronic device 1800, without limitation. Processor 1801 is configured to execute instructions stored in memory 1804 to implement the methods provided in the above embodiments of this application.

[0385] In one example, processor 1801 may include one or more processors, such as processor 0 and processor 1 in FIG. 18 .

[0386] As an optional implementation, the electronic device 1800 includes multiple processors. For example, in addition to the processor 1801 in FIG. 18 , it may also include a processor 1807 .

[0387] As an optional implementation, the electronic device 1800 further includes an output device 1805 and an input device 1806. For example, the input device 1806 is a keyboard, a mouse, a microphone, or a joystick, and the output device 1805 is a display screen, a speaker, or the like.

[0388] It should be pointed out that the electronic device 1800 can be a chip system or a device with a similar structure as shown in Figure 18. Among them, the chip system can be composed of chips, or it can include chips and other discrete devices. The actions, terms, etc. involved in the various embodiments of this application can refer to each other without limitation. The message names or parameter names in the messages exchanged between the various devices in the embodiments of this application are only an example. Other names can also be used in the specific implementation without limitation. In addition, the component structure shown in Figure 18 does not constitute a limitation on the electronic device 1800. In addition to the components shown in Figure 18, the electronic device 1800 may include more or fewer components than those shown in Figure 18, or combine certain components, or arrange the components differently.

[0389] The processor and transceiver described in this application can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0390] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes computer program code. When the computer program code runs on a computer, it enables the computer to execute any of the methods described in the embodiments of the present application.

[0391] The present application also provides a computer-readable storage medium. All or part of the processes in the above-mentioned method embodiments can be completed by a computer or a device with encoding and decoding capabilities executing a computer program or instruction to control the relevant hardware. The computer program or the group of instructions can be stored in the above-mentioned computer-readable storage medium. When executed, the computer program or the group of instructions can include the processes of the above-mentioned method embodiments. The computer-readable storage medium can be the internal storage unit of the control terminal of any of the above-mentioned embodiments, such as the hard disk or memory of the control terminal. The above-mentioned computer-readable storage medium can also be an external storage device of the above-mentioned control terminal, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the above-mentioned control terminal. Furthermore, the above-mentioned computer-readable storage medium can also include both the internal storage unit of the above-mentioned control terminal and an external storage device. The above-mentioned computer-readable storage medium is used to store the above-mentioned computer program or instruction and other programs and data required by the above-mentioned control terminal. The above-mentioned computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0392] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0393] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0394] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0395] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0396] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0397] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0398] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A coding method, characterized in that: The method comprises: Performing encoding operations on multiple display images and multiple reference images to obtain a code stream, wherein the code stream includes a security parameter set and an authentication data set, wherein the security parameter set includes first information and second information, wherein the first information is used to indicate an algorithm used for authentication, and the second information is used to indicate an algorithm used for digital signature; Authenticate the data to be authenticated according to the first information to obtain first tree top summary data, where the first tree top summary data is tree top summary data of the encoding end, and the first tree top summary data includes tree top summary data of N main bit streams and / or M CRR slice bit streams, where N and M are positive integers; Performing signature calculation on the first tree top summary data according to the second information to obtain a digital signature; The digital signature is encapsulated into the authentication data set.

2. The method according to claim 1, characterized in that: The authentication data set also includes third information, and the third information is used to indicate whether the authentication data belongs to the CRR slice.

3. The method according to claim 1 or 2, characterized in that: The authentication data set also includes fourth information, and the fourth information is used to indicate the length of the signature data.

4. The method according to any one of claims 1 to 3, characterized in that The authentication data set also includes fifth information, and the fifth information is used to indicate a reference image corresponding to an authentication range of the specified current authentication data set.

5. The method according to any one of claims 1 to 4, characterized in that The code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

6. The method according to any one of claims 1 to 5, characterized in that The reference image includes a CRR image.

7. A decoding method, characterized in that: The method comprises: Acquire a code stream, wherein the code stream is obtained by encoding the plurality of display images and the plurality of knowledge images, the code stream comprising a security parameter set, authentication data and a digital signature, the security parameter set comprising first information and second information, the first information being used to indicate an algorithm used for authentication, and the second information being used to indicate an algorithm for digitally signing summary data of the image; Decoding the digital signature according to the second information to obtain first summary data, wherein the first summary data includes summary data of N display images and / or summary data of M knowledge images, where N and M are positive integers; Authenticating the authentication data according to the first information to obtain second summary data, the second summary data including summary data of N display images and / or summary data of M knowledge images; The authentication data is verified according to the first digest data and the second digest data.

8. The method according to claim 7, characterized in that The code stream further includes third information, and the third information is used to indicate whether the authentication data belongs to a knowledge image.

9. The method according to claim 7 or 8, characterized in that: The code stream also includes fourth information, and the fourth information is used to indicate the length of the signature data.

10. The method according to any one of claims 7 to 9, characterized in that The code stream further includes fifth information, and the fifth information is used to indicate the knowledge image corresponding to the authentication scope of the authentication data.

11. The method according to any one of claims 7 to 10, characterized in that The code stream includes a plurality of CRR slice bit streams and a plurality of main bit streams in an interleaved order.

12. The method according to any one of claims 7 to 11, characterized in that The reference image includes a CRR image.

13. A coding method, characterized in that: The method comprises: Performing encoding operation on multiple display images and the multiple reference images to obtain a code stream, wherein the code stream includes a security parameter set, and the security parameter set includes a video encryption key; The code stream is encrypted according to the video encryption key.

14. A decoding method, characterized in that: The method comprises: Acquire a bitstream, wherein the bitstream is obtained by encoding a plurality of display images and a plurality of reference images, wherein the bitstream includes a security parameter set, and the security parameter set includes a video encryption key; Decrypting the bitstream according to the video encryption key; The reconstructed image is determined according to the decoded bitstream.

15. A coding device, characterized in that: Comprising modules for executing the method as claimed in any one of claims 1 to 6.

16. A decoding device, characterized in that: Comprising means for executing the method as claimed in any one of claims 7 to 12.

17. A coding device, characterized in that: The device comprises a processor coupled to a memory, wherein the memory is used to store instructions. When the instructions are executed by the processor, the device performs the method according to any one of claims 1 to 6 or 13.

18. A decoding device, characterized in that: The device comprises a processor coupled to a memory, wherein the memory is used to store instructions. When the instructions are executed by the processor, the device performs the method according to any one of claims 7 to 12 or 14.

19. A computer-readable storage medium for storing a computer program, characterized in that: When the computer program is executed, the method according to any one of claims 1 to 14 is performed.

20. A computer program product, comprising instructions, characterized in that: When the instructions are executed, the method according to any one of claims 1 to 14 is performed.

21. A chip comprising at least one processor and a memory, characterized in that: The at least one processor executes a program or instruction stored in the memory, so that the information processing device implements the method according to any one of claims 1 to 14.

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