Translation lookaside buffer invalidation method, data processing apparatus, and readable medium

Abstract

Provided in the present disclosure is a translation lookaside buffer invalidation method. The method comprises: a first data processing apparatus in a first processing core sending invalidation operation information to a miscellaneous node, wherein the invalidation operation information at least comprises invalidation operation information which has not been defined in an ARM instruction set and has been defined in a non-ARM instruction set, and the miscellaneous node notifies a second data processing apparatus in a second processing core to execute a translation lookaside buffer invalidation operation on the basis of the invalidation operation information. Further provided in the present disclosure are a data processing apparatus and a readable medium.

Description

Page table cache invalidation method, data processing device and readable medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202311085596.5 filed on August 25, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to the field of computer technology, and in particular to a page table cache invalidation method, a data processing device, and a readable medium. Background Art

[0004] In a SoC (System on Chip) consisting of a single processor, processor cluster, graphics processor, memory controller, etc., the CHI (Coherent Hub Interface) bus is one of the most commonly used interconnect bus protocols. It is highly flexible and scalable, and can meet different performance, power consumption, and area requirements.

[0005] The CHI architecture provides a comprehensive DVM (Distributed Virtual Memory) processing flow, enabling efficient virtual memory management. However, the supported TLBI (Translation Lookaside Buffer Invalidate, TLBI) request types are limited to the ARM (Advanced RISC Machine) instruction set. Specifically, the various transactions defined by the CHI protocol are strongly related to the ARM instruction set, and the CHI protocol does not provide a corresponding processing solution for TLBI operations not supported by the ARM instruction set. For example, the CHI protocol does not support ASID (Address Space Identifier)-related TLBI operations at EL (Exception Level) 3. However, some instruction sets, such as the RISC-V instruction set, support ASID-related TLBI operations in M-mode (EL3). This leads to compatibility issues when implementing the CHI protocol in SoCs that include non-ARM instruction set CPUs.

[0006] Summary of the Invention

[0007] The present disclosure provides a page table cache invalidation method, a data processing device, and a readable medium.

[0008] In a first aspect, an embodiment of the present disclosure provides a page table cache invalidation method, which is applied to a first data processing device in a first processing core, and the method includes: sending invalidation operation information to a miscellaneous node, so that the miscellaneous node notifies a second data processing device in a second processing core to perform a page table cache invalidation operation according to the invalidation operation information; wherein the invalidation operation information at least includes invalidation operation information that is not defined in the ARM instruction set and is defined in a non-ARM instruction set.

[0009] On the other hand, an embodiment of the present disclosure also provides a data processing device, comprising: one or more execution units; a storage device on which one or more programs are stored; when the one or more programs are executed by the one or more execution units, the one or more execution units implement the page table cache invalidation method as described above; one or more I / O interfaces, connected between the execution unit and the storage device, configured to implement information interaction between the execution unit and the storage device.

[0010] On the other hand, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein when the program is executed, the page table cache invalidation method as described above is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a first schematic diagram of a page table cache invalidation process executed by a first data processing device according to an embodiment of the present disclosure;

[0012] FIG2 is a schematic diagram of a process of sending invalid operation information to miscellaneous nodes according to an embodiment of the present disclosure;

[0013] FIG3 is a second schematic diagram of a page table cache invalidation process executed by the first data processing device according to an embodiment of the present disclosure;

[0014] FIG4 is a schematic diagram of a page table cache invalidation process according to a specific example of the present disclosure;

[0015] FIG5 is a first schematic diagram of a page table cache invalidation process executed by a second data processing device according to an embodiment of the present disclosure;

[0016] FIG6 is a second schematic diagram of a page table cache invalidation process executed by the second data processing device according to an embodiment of the present disclosure;

[0017] FIG7 is a schematic structural diagram of a data processing device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0019] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof is not excluded.

[0021] The embodiments described herein may be described with reference to plan views and / or cross-sectional views, with the aid of idealized schematic diagrams of the present disclosure. Thus, the example illustrations may be modified based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions of the elements, but are not intended to be limiting.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0023] To achieve efficient virtual memory management, the CHI protocol provides DVMOp (Distributed Virtual Memory operations), which includes the TLB maintenance instruction TLBI. The TLBI instruction can invalidate the page table at different granularities, thereby efficiently managing the virtual memory space of different processes, making the physical memory invisible to the application and achieving isolation between software and hardware.

[0024] TLBI operations are performed only according to EL, VA (Virtual Address) and ASID. That is, invalid operation information may include EL information, ASID information and VA information. The TLBI operations currently supported by the CHI protocol are shown in Tables 1 and 2 below:

[0025] Table 1

[0026] Table 1 shows the TLBI operations corresponding to ARM instructions associated with invalid operation information at the first exception level (EL1). As shown in Table 1, when both the ASID and VA are invalid, the ARM instruction set's "TLBI ALLE1" instruction causes all RNs (Request Nodes) in EL1 to execute the TLBI operation. When the ASID is invalid but the VA is valid, the ARM instruction set's "TLBI VAAE1" instruction causes the RNs in EL1 that match the VA to execute the TLBI operation. When the ASID is valid but the VA is invalid, the ARM instruction set's "TLBI ASIDE1" instruction causes the RNs in EL1 that match the ASID to execute the TLBI operation. When both the ASID and VA are valid, the ARM instruction set's "TLBI VAE1" instruction causes the RNs in EL1 that match both the ASID and VA to execute the TLBI operation.

[0027] Table 2

[0028] Table 2 shows the TLBI operations corresponding to ARM instructions related to invalid operation information at the third exception level (EL3). As shown in Table 2, when both the ASID and VA are invalid, the "TLBI ALLE3" instruction in the ARM instruction set causes all RNs in EL3 to perform the TLBI operation. When the ASID is invalid but the VA is valid, the "TLBI VAE3" instruction in the ARM instruction set causes the RNs in EL3 that match the VA to perform the TLBI operation. When the ASID is valid but the VA is invalid, or when both the ASID and VA are valid, the ARM instruction set does not have a corresponding operation instruction. This means that the ARM instruction set does not define the corresponding operation, does not support the corresponding TLBI operation, and the CHI protocol does not provide a corresponding handling solution.

[0029] As can be seen from Table 1 and Table 2, the current CHI protocol does not support ASID-related TLBI operations in EL3. However, some non-RAM instruction sets, such as the RISC-V instruction set, support ASID-related TLBI operations in M-mode (EL3). This leads to compatibility issues when the CHI protocol is implemented in a SoC that includes a non-ARM instruction set CPU.

[0030] In order to solve the above problems, an embodiment of the present disclosure provides a page table cache invalidation method, which is applied to a first data processing device in a first processing core. The first data processing device may be a request node (Request Node, also referred to as an RN node). It should be noted that, in some embodiments, different data processing devices may be located in different processing cores of the same CPU. In some embodiments, the request node represents a processor core, and in some scenarios it also represents a processor cluster (cluster), in which case there are multiple processor cores in one request node. Therefore, the first data processing device provided in an embodiment of the present disclosure and the second data processing device described below may be different request nodes, such as different processor cores (cores) in the same cluster, or different processor cores in different clusters. As shown in Figure 1, the page table cache invalidation method includes the following steps S11.

[0031] Step S11, sending invalid operation information to the miscellaneous node, so that the miscellaneous node notifies the second data processing device in the second processing core to perform a page table cache invalidation operation according to the invalid operation information; wherein the invalid operation information at least includes invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set.

[0032] The first data processing device in the first processing core sends invalid operation information to a miscellaneous node (MN) in the bus. The miscellaneous node forwards the invalid operation information to other data processing devices in other processing cores in the same CPU, so that the other data processing devices perform TLBI operations based on the invalid operation information. The invalid operation information is invalid operation information that is not defined in the ARM instruction set but defined in a non-ARM instruction set. Exemplarily, the invalid operation information is invalid operation information defined in the RISC-V instruction set but not in the ARM instruction set, i.e., information such as the information in Table 2 for valid ASID and invalid VA in EL3, and information for valid ASID and VA. In this way, the CHI protocol is extended, the ARM instruction set is supplemented and improved, and the compatibility issue of system-on-chips containing CPUs with non-ARM instruction sets is resolved.

[0033] The embodiment of the present disclosure provides a page table cache invalidation method, in which a first data processing device in a first processing core sends invalid operation information to a miscellaneous node, where the invalid operation information at least includes invalid operation information that is not defined in the ARM instruction set and defined in a non-ARM instruction set, and the miscellaneous node notifies a second data processing device in a second processing core to perform a page table cache invalidation operation according to the invalid operation information; the embodiment of the present disclosure extends the CHI protocol, supplements the page table cache invalidation operation supported by the CHI protocol, can support a full range of TLBI operations, decouples the CHI protocol from the instruction set used by the processing core, and makes the CHI protocol compatible with more instruction sets, can solve the compatibility problem of the system-on-chip of the CPU containing the non-ARM instruction set, and improves scalability and applicability.

[0034] In some embodiments, the non-ARM instruction set may be a RISC-V instruction set.

[0035] In some embodiments, the invalid operation information that is not defined in the ARM instruction set and is defined in a non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information. The first invalid operation information may include EL information and ASID information, and the second invalid operation information may include VA information, wherein the EL information may be third exception level information (EL3). That is, the invalid operation information that is not defined in the ARM instruction set and is defined in a non-ARM instruction set includes EL3 information and ASID information, or EL3 information, ASID information, and VA information.

[0036] Taking the RISC-V instruction set as an example, the RISC-V instruction set provides the Sfence.VAM and Hfence.VVAM instructions for TLB maintenance operations. The Sfence.VAM instruction supports operations in S-mode (corresponding to EL1 of the ARM architecture) and M-mode (corresponding to EL3 of the ARM architecture). The above two instructions also have operations for ASID and VA. The mapping relationship between TLBI operations between the RISC-V instruction set and the ARM instruction set is shown in Table 3:

[0037] Table 3

[0038] As shown in Table 3, the invalid operation information includes not only invalid operation information that is not defined in the ARM instruction set but defined in the non-ARM instruction set, but also invalid operation information defined in both the ARM instruction set and the non-ARM instruction set. That is, the invalid operation information also includes third invalid operation information, or third invalid operation information and fourth invalid operation information. The third invalid operation information includes EL information, and the fourth invalid operation information includes VA information; wherein the third invalid operation information is the first exception level information or the third exception level information. That is, the invalid operation information also includes EL information (EL1 information or EL3 information), or the invalid operation information also includes EL information (EL1 information or EL3 information) and VA information. In addition, as shown in Table 3, the EL information in the first invalid operation information can also be EL1 information, that is, the first invalid operation information can also be EL1 information and ASID information.

[0039] As can be seen from Table 3, the current CHI protocol does not support ASID-related TLBI operations under EL3. After the CHI protocol is extended according to the embodiments of the present disclosure, for example, the Sfence VAM ASID M instruction and the Sfence VAM VAA M instruction in the RISC-V instruction set can also be correctly processed in the CHI protocol.

[0040] In some embodiments, as shown in FIG2 , the sending of invalid operation information to the miscellaneous node (ie, step S11 ) includes the following steps S111 and S112 .

[0041] In step S111, a distributed virtual memory operation request message is sent to the miscellaneous node, where the distributed virtual memory operation request message carries first invalid operation information.

[0042] The first data processing device in the first processing core carries first invalid operation information (i.e., EL information and ASID information) in a distributed virtual memory operation request message (DVMOp) sent to the miscellaneous node, so that the miscellaneous node informs the other data processing devices in other processing cores of the CPU to which the first data processing device belongs of the first invalid operation information.

[0043] In step S112, when the invalid operation information includes the second invalid operation information, after receiving the data packet identifier response message returned by the miscellaneous node, the target data and the second invalid operation information are sent to the miscellaneous node.

[0044] After receiving the DVMOp message, the miscellaneous node returns a Data Packet Identifier Response message (DBIDResp) to the first data processing device. If the invalid operation information also includes second invalid operation information, the first data processing device sends the second invalid operation information along with the target data (NCBWrData) to the miscellaneous node, so that the miscellaneous node can notify other data processing devices in other processing cores of the CPU to which the first data processing device belongs of the second invalid operation information. The target data is the unprocessed data to be processed by the first data processing device.

[0045] It should be noted that the miscellaneous node can broadcast the invalid operation information (first invalid operation information, or first invalid operation information and second invalid operation information) in the distributed virtual memory operation snoop response message (SnpDVMOp) and pass it to the second data processing device in the second processing core.

[0046] When the invalid operation information is the third invalid operation information, or the third invalid operation information and the fourth invalid operation information, the first data processing device in the first processing core carries the third invalid operation information (i.e., EL1 information or EL3 information) in a distributed virtual memory operation request message (DVMOp) sent to the miscellaneous node. When the invalid operation information also includes the fourth invalid operation information, the first data processing device in the first processing core sends the target data (NCBWrData) and the fourth invalid operation information (AV information) to the miscellaneous node after receiving the data packet identifier response message (DBIDResp) returned by the miscellaneous node.

[0047] In some embodiments, as shown in FIG3 , after sending the target data and the second invalidation operation information to the miscellaneous node (ie, step S112 ), the page table cache invalidation method may further include the following step S113 .

[0048] Step S113: receiving a completion response message sent by the miscellaneous node. The completion response message is sent by the second data processing device after the miscellaneous node is instructed to do so after completing the page table cache invalidation operation.

[0049] After receiving the invalid operation information sent by the miscellaneous node, the second data processing device in the second processing core performs a TLBI operation according to the invalid operation information and returns a distributed virtual memory operation snoop response message (SnpResp_I) to the miscellaneous node. After receiving the distributed virtual memory operation snoop response message, the miscellaneous node returns a completion response message (Comp) to the first data processing device in the first processing core to inform the first data processing device that the second data processing device has completed the corresponding TLBI operation.

[0050] To clearly illustrate the solution of the embodiment of the present disclosure, the following detailed description of the page table cache invalidation process is provided through a specific example in conjunction with Figure 4. As shown in Figure 4, RN-F0 is the first data processing device within processing core 0, and RN-F1 is the second data processing device within processing core 1. The page table cache invalidation process includes the following steps 1-6.

[0051] In step 1, RN-F0 initiates a DVMOp request message to the MN in the bus. The DVMOp request message carries EL information and ASID information, which are carried in the address payload of the DVMOp request message.

[0052] In step 2, after receiving the DVMOp request message, the MN returns a DBIDResp response message to the RN-F0.

[0053] In step 3, after receiving the DBIDResp response message, RN-F0 carries the VA information in NCBWrData and sends it to MN.

[0054] In step 4, after receiving the NCBWrData message carrying the VA information, the MN broadcasts the SnpDVMOp message corresponding to the TLBI operation. The SnpDVMOp message is split into two parts, namely the SnpDVMOp_P1 message and the SnpDVMOp_P2 message. The SnpDVMOp_P1 message and the SnpDVMOp_P2 message carry the EL information, ASID information, and VA information.

[0055] In step 5, after receiving the SnpDVMOp_P1 message and the SnpDVMOp_P2 message, RN-F1 performs corresponding TLBI operations and returns a SnpResp_I response message to the MN.

[0056] In step 6, after receiving the snpresp_I response message returned by RN-F1, MN returns a Comp response message to RN-F0, completing the processing flow of the entire transaction.

[0057] As can be seen from the above steps 1-6, it is only necessary to modify the information carried by the DVMOp message and the message carrying NCBWrData to implement the ASID-related TLBI operation under EL3. Its processing flow can directly reuse the current CHI protocol's processing flow for conventional TLBI.

[0058] The disclosed embodiments, based on the CHI protocol, extend the TLBI operations in the distributed virtual memory operations supported by the CHI protocol, making the CHI protocol compatible with a wider range of instruction set architectures. The disclosed embodiments are applicable to all SOC systems built on the CHI protocol that need to maintain virtual memory.

[0059] The embodiment of the present disclosure further provides a page table cache invalidation method, which is applied to a second data processing device in a second processing core. As shown in FIG5 , the page table cache invalidation method includes the following steps S21 and S22 .

[0060] In step S21, invalid operation information sent by the miscellaneous node is received; wherein the invalid operation message is sent by the first data processing device in the first processing core to the miscellaneous node, and the invalid operation information at least includes invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set.

[0061] In some embodiments, the non-ARM instruction set includes the RISC-V instruction set.

[0062] In some embodiments, receiving the invalid operation information from the miscellaneous node includes receiving a distributed virtual memory operation snoop message broadcast by the miscellaneous node, the distributed virtual memory operation snoop message carrying the invalid operation information. In other words, the miscellaneous node may broadcast the invalid operation information in a distributed virtual memory operation snoop response message (SnpDVMOp) to the second data processing device in the second processing core.

[0063] In step S22, a page table cache invalidation operation is performed according to the invalidation operation information.

[0064] After receiving the invalid operation information sent by the miscellaneous node, the second data processing device in the second processing core performs the TLBI operation according to the invalid operation information.

[0065] The page table cache invalidation method provided by the embodiment of the present disclosure is as follows: after receiving invalid operation information sent by the miscellaneous node, the second data processing device in the second processing core performs a page table cache invalidation operation according to the invalid operation information, and the invalid operation information at least includes invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set; the embodiment of the present disclosure extends the CHI protocol, supplements the page table cache invalidation operation supported by the CHI protocol, and can support a full range of TLBI operations, decoupling the CHI protocol from the instruction set used by the processing core, so that the CHI protocol can be compatible with more instruction sets, can solve the compatibility problem of the on-chip system of the CPU containing the non-ARM instruction set, and improve scalability and applicability.

[0066] In some embodiments, the invalid operation information that is not defined in the ARM instruction set but defined in a non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information, the first invalid operation information includes exception level EL information and ASID information, and the second invalid operation information includes VA information; wherein the EL information is third exception level information or first exception level information. In other words, the invalid operation information that is not defined in the ARM instruction set but defined in a non-ARM instruction set includes EL3 information and ASID information, or EL3 information, ASID information, and VA information.

[0067] It should be noted that, as shown in Table 3, the invalid operation information may also include third invalid operation information, or third invalid operation information and fourth invalid operation information, where the third invalid operation information includes EL information and the fourth invalid operation information includes VA information. The third invalid operation information is the first abnormality level information or the third abnormality level information. That is, the invalid operation information also includes EL information (EL1 information or EL3 information), or the invalid operation information also includes EL information (EL1 information or EL3 information) and VA information. Furthermore, as shown in Table 3, the EL information in the first invalid operation information may also be EL1 information, that is, the first invalid operation information may also include EL1 information and ASID information.

[0068] In some embodiments, as shown in FIG6 , after performing the page table cache invalidation operation according to the invalidation operation information (ie, step S22 ), the page table cache invalidation method may further include the following step S23 .

[0069] Step S23: Return the distributed virtual memory operation snoop response message to the miscellaneous node, so that the miscellaneous node can send a completion response message to the first data processing device.

[0070] After the second data processing device in the second processing core performs the TLBI operation according to the invalid operation information, it returns a distributed virtual memory operation snoop response message (SnpResp_I) to the miscellaneous node. After receiving the distributed virtual memory operation snoop response message, the miscellaneous node returns a completion response message (Comp) to the first data processing device in the first processing core to inform the first data processing device that the second data processing device has completed the corresponding TLBI operation.

[0071] The present disclosure also provides a data processing device, as shown in FIG7 , which includes: at least one execution unit 701; a memory 702 on which at least one program is stored, and when the at least one program is executed by the at least one execution unit, the at least one execution unit implements the page table cache invalidation method provided in the aforementioned embodiments; and at least one I / O interface 703, connected between the execution unit and the memory, and configured to implement information exchange between the execution unit and the memory. The execution unit 701, the memory 702, and the I / O interface can together constitute a processor, such as a central processing unit (CPU), or a core of a processor.

[0072] Among them, the execution unit 701 is a device with data processing capabilities; the memory 702 is a device with data storage capabilities, which includes but is not limited to random access memory (RAM, more specifically such as SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) 703 is connected between the execution unit 701 and the memory 702, and can realize information interaction between the execution unit 701 and the memory 702, which includes but is not limited to a data bus (Bus), etc.

[0073] In some embodiments, the execution unit 701 , the memory 702 , and the I / O interface 703 are connected to each other via a bus, and further connected to other components of the computing device.

[0074] An embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein when the computer program is executed, the page table cache invalidation method provided in the aforementioned embodiments is implemented.

[0075] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, and the functional modules / units in the device can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0076] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A page table cache invalidation method, the method being applied to a first data processing device in a first processing core and comprising: Sending invalid operation information to a miscellaneous node so that the miscellaneous node notifies a second data processing device in a second processing core to perform a page table cache invalidation operation according to the invalid operation information; wherein the invalid operation information at least includes invalid operation information that is not defined in an ARM instruction set and is defined in a non-ARM instruction set.

2. The method of claim 1, wherein: The invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information, the first invalid operation information includes exception level EL information and address space identifier ASID information, the second invalid operation information includes virtual address VA information; wherein the EL information is third exception level information.

3. The method of claim 2, wherein: The sending of invalid operation information to the miscellaneous node includes: Sending a distributed virtual memory operation request message to a miscellaneous node, wherein the distributed virtual memory operation request message carries the first invalid operation information; In a case where the invalid operation information includes the second invalid operation information, after receiving the data packet identifier response message returned by the miscellaneous node, the target data and the second invalid operation information are sent to the miscellaneous node.

4. The method of claim 3, wherein: After sending the target data and the second invalid operation information to the miscellaneous node, the method further includes: A completion response message sent by the miscellaneous node is received, where the second data processing device instructs the miscellaneous node to send the completion response message after completing the page table cache invalidation operation.

5. The method according to any one of claims 1 to 4, wherein: The non-ARM instruction set includes the RISC-V instruction set.

6. A page table cache invalidation method, the method being applied to a second data processing device in a second processing core, and comprising: Receiving invalid operation information sent by a miscellaneous node; wherein the invalid operation message is sent to the miscellaneous node by a first data processing device in a first processing core, and the invalid operation information at least includes invalid operation information that is not defined in an ARM instruction set and is defined in a non-ARM instruction set; A page table cache invalidation operation is performed according to the invalidation operation information.

7. The method of claim 6, wherein: The invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information, the first invalid operation information includes exception level EL information and address space identifier ASID information, and the second invalid operation information includes virtual address VA information; wherein the EL information is third exception level information or first exception level information.

8. The method of claim 6, wherein: The receiving of invalid operation information sent by the miscellaneous node includes: A distributed virtual memory operation snooping message broadcasted by a miscellaneous node is received, wherein the distributed virtual memory operation snooping message carries the invalid operation information.

9. The method of claim 6, wherein: After performing the page table cache invalidation operation according to the invalidation operation information, the method further includes: A distributed virtual memory operation snoop response message is returned to the miscellaneous node, so that the miscellaneous node can send a completion response message to the first data processing device.

10. The method according to any one of claims 6 to 9, wherein: The non-ARM instruction set includes the RISC-V instruction set.

11. A data processing device, comprising: one or more execution units; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more execution units, the one or more execution units implement the page table cache invalidation method according to any one of claims 1 to 5, or the page table cache invalidation method according to any one of claims 6 to 10; One or more I / O interfaces are connected between the execution unit and the storage device and are configured to implement information exchange between the execution unit and the storage device.

12. A computer readable medium having a computer program stored thereon, wherein: When the program is executed, the page table cache invalidation method according to any one of claims 1 to 5 is implemented, or the page table cache invalidation method according to any one of claims 6 to 10 is implemented.

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