Semiconductor device

Abstract

The present invention provides a semiconductor device with a fast operating speed. A first insulator is disposed on a substrate, a second insulator is disposed on the first insulator, an oxide semiconductor is disposed on the first insulator and covers the second insulator, a first conductor and a second conductor are disposed on the oxide semiconductor, a third insulator is disposed on the first and second conductors and has an opening overlapping an area between the first and second conductors, a fourth insulator is disposed in the opening, overlapping the oxide semiconductor, a third conductor is disposed on the fourth insulator in the opening, the sides of the first insulator coincide or substantially coincide with the sides of the oxide semiconductor, the sides of the first conductor, and the sides of second conductor in a plan view, the film thickness of the first insulator is greater than the film thickness of the fourth insulator, and the height of the second insulator is greater than the width of the second insulator in a cross-sectional view in the channel width direction.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with high operation speed.Another object of one embodiment of the present invention is to provide a memory device with low power consumption.Another object of one embodiment of the present invention is to provide a novel memory device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, first to fourth insulators, and first to third conductors, wherein the first insulator is disposed over a substrate, the second insulator is disposed over the first insulator, the oxide semiconductor is disposed over the first insulator and covers the second insulator, the first conductor and the second conductor are disposed over the oxide semiconductor, a third insulator is disposed over the first conductor and the second conductor and has an opening overlapping with a region between the first conductor and the second conductor, a fourth insulator is disposed in the opening to overlap the oxide semiconductor, and the third conductor is disposed on the fourth insulator in the opening, a side surface of the first insulator coincides or substantially coincides with a side surface of the oxide semiconductor, a side surface of the first conductor, and a side surface of the second conductor in a plan view, the thickness of the first insulator is thicker than the thickness of the fourth insulator, and the height of the second insulator is greater than a width of the second insulator in a cross-sectional view in a channel width direction.

[0013] In the above, it is preferable that a side surface of a portion of the third insulator coincides or substantially coincides with a side surface of the first conductor and a side surface of the second conductor in a plan view.

[0014] In the above, it is preferable that the fifth insulator is provided, the first conductor and the second conductor each have a first layer and a second layer on the first layer, the fifth insulator is disposed in an opening of the third insulator and contacts the top surface of the first layer of the first conductor, the side surface of the second layer of the first conductor, the top surface of the first layer of the second conductor, and the side surface of the second layer of the second conductor, the fifth insulator has an opening overlapping with the region between the first layer of the first conductor and the first layer of the second conductor, and the shortest distance between the first layer of the first conductor and the first layer of the second conductor is shorter than the shortest distance between the second layer of the first conductor and the second layer of the second conductor.

[0015] In the above, it is preferable that a side surface of a portion of the third insulator coincides or substantially coincides with a side surface of the second layer of the first conductor and a side surface of the second layer of the second conductor in a plan view.

[0016] In the above, the second insulator may have a metal oxide containing indium, gallium, and zinc, and the proportion of gallium in the second insulator may be higher than the proportion of indium.

[0017] In the above, the second insulator may include gallium oxide.

[0018] In the above, the second insulator may include silicon nitride, and the fifth insulator may include silicon nitride.

[0019] In the above, the first layer of the first conductor and the first layer of the second conductor preferably contain tantalum nitride.

[0020] In the above, the lower surface of the third conductor preferably has a portion located lower than the lower surface of the oxide semiconductor.

[0021] In the above, it is preferable that the oxide semiconductor contains indium, and that bright spots arranged in layers in a direction parallel to a surface on which the oxide semiconductor is formed are observed in cross-sectional observation of the oxide semiconductor using a transmission electron microscope.

[0022] In the above, it is preferable that the oxide semiconductor contains indium, the oxide semiconductor has a first region, a second region in contact with the first region, and a third region in contact with the second region, and that, in cross-sectional observation of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a surface on which the oxide semiconductor is formed are observed in each of the first region, the second region, and the third region.

[0023] In the above, it is preferable that the second region contains zinc, the second region has crystals, and c-axes of the crystals are approximately parallel to a normal to a surface on which the oxide semiconductor is formed.

[0024] In the above, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0025] According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to another embodiment of the present invention, a novel semiconductor device can be provided. According to another embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to another embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0026] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with a high operating speed can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel memory device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 6A to 6C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 7A to 7C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 8A to 8C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 10A to 10D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. FIGS. 11A to 11D are cross-sectional views illustrating an example of an oxide semiconductor. FIG. 12A is a plan view illustrating an example of a semiconductor device. FIGS. 12B to 12D are cross-sectional views illustrating an example of a semiconductor device. FIG. 13A is a plan view illustrating an example of a semiconductor device. FIGS. 13B to 13D are cross-sectional views illustrating an example of a semiconductor device. FIG. 14A is a plan view illustrating an example of a semiconductor device. 14B to 14D are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. FIGS. 15B to 15D are cross-sectional views showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIGS. 17A to 17C are cross-sectional views showing an example of a semiconductor device. FIGS. 18A and 18B are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 19B to 19D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 20A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 20B to 20D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 21A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 21B to 21D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 22A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 22B to 22D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 23A is a plan view showing an example of a method for manufacturing a semiconductor device. 23B to 23D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.FIG. 24A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 24B to 24D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 25A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 25B to 25D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 26A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 26B to 26D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 27B to 27D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 28B to 28D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 29A and 29B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 30 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 31A to 31H are diagrams illustrating a circuit structural example of a memory cell. FIGS. 32A and 32B are perspective views illustrating a structural example of a semiconductor device. FIG. 33 is a block diagram illustrating a CPU. FIG. 34 is a block diagram illustrating a CPU. FIGS. 35A and 35B are perspective views of a semiconductor device. FIGS. 36A and 36B are perspective views of a semiconductor device. FIGS. 37A and 37B are diagrams illustrating the hierarchy of a memory device in a semiconductor device. FIGS. 38A and 38B are diagrams showing an example of electronic equipment, and FIGS. 38C to 38E are diagrams showing an example of a mainframe computer. FIG. 39 is a diagram showing an example of space equipment. FIG. 40 is a diagram showing an example of a storage system applicable to a data center. FIGS. 41A and 41B are cross-sectional STEM images related to this example. FIG. 42 is a graph showing the electrical characteristics of a transistor related to this example.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In order to make the invention easier to understand, particularly in plan views (also called "top views") and perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0033] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0034] The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0035] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0036] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0037] Furthermore, in the drawings used in this specification and the like, the sidewall of the insulator at the opening portion of the insulator is shown as being perpendicular or approximately perpendicular to the substrate surface or the surface on which the insulator is formed, but it may be tapered.

[0038] In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0039] In this specification, the term "having the same or substantially the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a manufacturing process for a memory device, a planarization process (typically a process using chemical mechanical polishing (CMP)) may expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process are configured to have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or substantially the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to the reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or substantially the same height."

[0040] In this specification, "side surfaces that match or approximately match" or "side edges that match or approximately match" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the terms "side surfaces that match or approximately match" or "side edges that match or approximately match" are also used.

[0041] In this specification, the phrase "the planar shapes are identical or approximately identical" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be disposed inside the lower layer, or the upper layer may be disposed outside the lower layer. In these cases, the phrase "the planar shapes are identical or approximately identical" may also be used. Furthermore, when the planar shapes are identical or approximately identical, it can also be said that the edges are aligned or approximately aligned, or that the side edges are aligned or approximately aligned.

[0042] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0043] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor layer and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1A to 29B.

[0044] 1A to 1D are plan views and cross-sectional views of a semiconductor device including a transistor 200 over a substrate (not shown).

[0045] FIG. 1A is a plan view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1C is a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by the dashed-dotted line A5-A6 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. The dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 1A, some elements are omitted and shown transparently for clarity. 2A shows an enlarged view of the vicinity of the conductor 260 in FIG. 1D. FIG. 2B shows an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1B. FIG. 8A shows an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1C. Note that in this specification and the like, a cross section in the channel width direction does not necessarily include the channel formation region of a transistor. The cross section in the channel width direction may also include a cross section parallel to the cross section in the channel width direction including the channel formation region. For example, a cross section of a portion indicated by the dashed dotted line A3-A4 in FIG. 1C is referred to as a cross section in the channel width direction.

[0046] The semiconductor device of this embodiment has an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an insulator 225 on the insulator 224, an oxide semiconductor 230 on the insulators 224 and 225, a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. Furthermore, an insulator 255 is provided between the insulator 222, the conductor 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 275, and the insulator 280 and the insulator 250. Note that hereinafter, the conductors 242a and 242b may be collectively referred to as the conductors 242.

[0047] An insulator 275 is provided over the conductor 242 and the insulator 222, and an insulator 280 is provided over the insulator 275. An opening 201 is provided in the insulator 280 and the insulator 275. The side surfaces of the insulator 280 and the insulator 275 function as sidewalls of the opening 201. The side surfaces of the conductor 242a1, the conductor 242a2, the conductor 242b1, and the conductor 242b2 can also be considered as sidewalls of the opening 201. The insulators 250, 255, and 260 are disposed inside the opening 201. The insulators 224, 225, and part of the oxide semiconductor 230 are also disposed inside the opening 201. The opening 201 reaches the oxide semiconductor 230 and the insulator 222, and the insulator 250 is in contact with the oxide semiconductor 230 and the insulator 222 within the opening 201.

[0048] Here, an opening is formed in the bottom surface of the insulator 255, and the opening overlaps with a region between the conductor 242a1 and the conductor 242b1. In a cross-sectional view in the channel width direction (see FIG. 1B ), the insulator 224, the insulator 225, and the oxide semiconductor 230 are arranged in the opening of the insulator 255. The insulator 255 is provided along the sidewall and the bottom surface of the opening 201; therefore, the insulator 255 can also be considered as part of the sidewall and the bottom surface of the opening 201.

[0049] An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 215 is provided under the insulator 216.

[0050] An insulator 241a is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240a is provided in contact with the side surface of the insulator 241a. The lower surface of the conductor 240a is in contact with the upper surface of the conductor 242a. An insulator 241b is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240b is provided in contact with the side surface of the insulator 241b. The lower surface of the conductor 240b is in contact with the upper surface of the conductor 242b. Note that hereinafter, the conductors 240a and 240b may be collectively referred to as the conductor 240. The insulators 241a and 241b may be collectively referred to as the insulator 241.

[0051] The oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200.

[0052] The conductor 242a has a region that functions as one of the source electrode and the drain electrode of the transistor 200. The conductor 240a functions as a plug connected to the conductor 242a. The conductor 242b has a region that functions as the other of the source electrode and the drain electrode of the transistor 200. The conductor 240b functions as a plug connected to the conductor 242b.

[0053] The conductor 242a has a stacked structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a stacked structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 in contact with the oxide semiconductor 230 are preferably conductors that are resistant to oxidation, such as metal nitrides. This can prevent the conductors 242a and 242b from being excessively oxidized by oxygen contained in the oxide semiconductor 230. Furthermore, the conductors 242a2 and 242b2 are preferably conductors such as metal layers that have higher conductivity than the conductors 242a1 and 242b1. This allows the conductors 242a and 242b to function as wirings or electrodes with high conductivity. In this manner, a semiconductor device can be provided in which the conductors 242a and 242b functioning as wirings or electrodes are provided in contact with the top surface of the oxide semiconductor 230 functioning as an active layer.

[0054] As shown in FIG. 2A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance D2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance D1 between the conductor 242a2 and the conductor 242b2. Here, the distance D1 refers to the shortest distance between the opposing side surfaces of the conductor 242a2 and the conductor 242b2. Furthermore, the distance D2 refers to the shortest distance between the opposing side surfaces of the conductor 242a1 and the conductor 242b1. This configuration makes it possible to further shorten the distance between the source and drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. In this way, miniaturization of the semiconductor device allows for the provision of a semiconductor device with high operating speed.

[0055] The opening 201 overlaps with a region between the conductor 242a2 and the conductor 242b2. Parts of the conductors 242a1 and 242b1 can also be considered to be formed so as to protrude into the opening 201. Therefore, the insulator 255 is in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 within the opening 201. The insulator 250 is in contact with the top surface of the insulator 222 and the top surface of the oxide semiconductor 230 in the region between the conductor 242a1 and the conductor 242b1.

[0056] The insulator 255 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and has the function of protecting the conductors 242a2 and 242b2. As will be described in detail later, after separating the conductors 242a1 and 242b1, it is preferable to perform heat treatment in an oxygen-containing atmosphere before forming the insulator 250. In this case, since the insulator 255 is formed in contact with the side surfaces of the conductors 242a2 and 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented.

[0057] The oxide semiconductor 230 is formed to cover the insulator 225. As shown in FIGS. 2B and 8A , the insulator 225 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. Therefore, the insulator 225 can also be said to have a fin-like shape. Here, the aspect ratio of the insulator 225 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the insulator 225 in the A1-A2 direction (which can also be referred to as the width L of the insulator 225) to the length H of the insulator 225 in a direction perpendicular to the surface on which the insulator 225 is formed (for example, the insulator 224) (which can also be referred to as the height H of the insulator 225). The aspect ratio of the insulator 225 is preferably as large as possible without causing the insulator 225 to collapse during the manufacturing process of the transistor 200. The height H of the insulator 225 is preferably larger than the width L of the insulator 225.

[0058] The oxide semiconductor 230 and the conductor 242 are provided to cover the insulator 225 having a high aspect ratio. In the vicinity of the channel formation region of the transistor 200, the oxide semiconductor 230 is provided so as to be folded in half with the insulator 225 sandwiched therebetween, as shown in FIG. 2B . As a result, in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided facing each other with the insulator 250 sandwiched between them at the upper part of the insulator 225, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224. That is, the upper part of the oxide semiconductor 230, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224 each function as a channel formation region. Therefore, the channel width of the transistor 200 is increased by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 compared to when the insulator 225 is not provided.

[0059] The increased channel width as described above can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by providing the oxide semiconductor 230 to cover the insulator 225, the channel width can be increased without excessively increasing the area occupied by the transistor 200. This enables miniaturization or high integration of the semiconductor device. Furthermore, the memory capacity of a memory device using the semiconductor device can be increased. Furthermore, the above structure increases the area where the conductor 260 and the oxide semiconductor 230 face each other, so that the transistor 200 can be normally-off by controlling the threshold voltage.

[0060] Furthermore, as shown in FIG. 2B , it is preferable that the thickness t1 of the insulator 224 in the opening 201 is thicker than the thickness t2 of the insulator 250. With this configuration, the lower surface (which can also be referred to as the lower end or bottom edge) of the conductor 260 located in a region of the opening 201 that does not overlap with the oxide semiconductor 230 is located lower than the lower surface (which can also be referred to as the lower end or bottom edge) of the oxide semiconductor 230. Therefore, a sufficient electric field can be applied from the conductor 260 to the region from the upper end to the bottom end of the oxide semiconductor 230. This can reduce leakage current between the source electrode and the drain electrode via the bottom edge of the oxide semiconductor 230. Furthermore, poor characteristics of the transistor, such as normally-on state, due to the leakage current can be suppressed. That is, the electrical characteristics of the transistor 200 can be improved.

[0061] [Oxide Semiconductor Layer] Here, an oxide semiconductor layer that can be used for the oxide semiconductor 230 will be described. The oxide semiconductor layer contains a metal oxide.

[0062] Note that it is preferable that hydrogen in the oxide semiconductor layer be reduced as much as possible. Hydrogen in the oxide semiconductor layer is generated by oxygen vacancies (V Ｏ ) and V Ｏ Defects with hydrogen in the Ｏ Since a gate electrode formed in the oxide semiconductor layer is a gate insulating film, the transistor characteristics (e.g., drain current (Id)-gate voltage (Vg) characteristics of the transistor at an initial stage or Id-Vg characteristics in a long-term reliability test) may be deteriorated. Therefore, a material that releases little hydrogen is preferably used as a material surrounding the oxide semiconductor layer, for example, as a material used for an insulator in contact with the oxide semiconductor layer. Examples of such a material that releases little hydrogen include silicon nitride, silicon nitride oxide, aluminum oxide, and hafnium oxide. This can prevent hydrogen from entering the oxide semiconductor layer. In particular, using silicon nitride for at least one of the insulators in contact with the oxide semiconductor layer can improve the reliability of the transistor. Note that a material that releases little hydrogen may have a function of capturing or fixing (also referred to as gettering) hydrogen inside the insulator.

[0063] When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0064] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure.

[0065] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0066] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a crystal structure different from either a single-crystal structure or a polycrystalline structure. In particular, the oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure.

[0067] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the a-b plane without any clear grain boundaries. When a cross section of an oxide semiconductor layer having the CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0068] In addition, a structure in which metal atoms in each of the multiple microcrystals are arranged in layers parallel or approximately parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the surface on which the metal atoms are formed, is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the multiple microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0069] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0070] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the a-b plane, so a highly reliable semiconductor device can be realized. Furthermore, because there are fewer crystal grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor using an oxide semiconductor layer can be suppressed or the initial characteristics (particularly on-state current) of the transistor can be improved, making the transistor suitable for high-speed operation.

[0071] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0072] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0073] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of the surface of the oxide semiconductor layer.

[0074] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0075] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0076] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0077] A method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0078] An example of the observation range of the TEM in creating a Voronoi diagram is a rectangular region of 50 nm in length and 50 nm in width, although the observation range is not limited to this.

[0079] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0080] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0081] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not limited. The oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0082] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Note that element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0083] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0084] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. The metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0085] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0086] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0087] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0088] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0089] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0090] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0091] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide using two types of film formation methods.

[0092] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. At this time, a sputtering method can be used as a deposition method, thereby forming a metal oxide having high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or another deposition method may be used.

[0093] Here, when a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface on which the metal oxide is to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface on which the metal oxide is to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, etc., which are described as the first film formation method, and then providing a metal oxide formed using the first film formation method as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface on which the metal oxide is to be formed can be suppressed. Furthermore, impurities contained in the surface on which the metal oxide is to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0094] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method for growing a thin film whose crystalline structure reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed.The wet method is also one of the film formation methods that causes little damage to the surface on which the film is formed.An example of a wet method is a spray coating method.

[0095] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0096] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0097] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of upper and lower oxide semiconductor layers (the first layer and the third layer) can be increased by using the second layer (i.e., the CAAC) having high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming oxide semiconductor layers with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0098] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0099] An example of a method for manufacturing the oxide semiconductor 30 will be described below with reference to FIGS. 10A to 10D.

[0100] First, a layer 29 is formed. The layer 29 corresponds to an insulating film or a conductive film included in the semiconductor device. For example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used as the layer 29. Alternatively, for example, a conductive film that functions as an electrode of the semiconductor device can be used as the layer 29. The layer 29 does not need to be crystalline. In other words, the layer 29 may have an amorphous structure. Furthermore, when the layer 29 is crystalline, it may have a crystal structure that has low lattice matching with the metal oxide included in the oxide semiconductor 30.

[0101] Next, an oxide semiconductor 30a is formed on the layer 29 (FIG. 10A).

[0102] In a manufacturing method of one embodiment of the present invention, the oxide semiconductor 30b is formed by a sputtering method, as described later. When a metal oxide film is formed by a sputtering method, a mixed layer (also called alloying) of components of the metal oxide film to be formed and components of a layer on which the film is to be formed may be formed due to sputtering particles emitted from a target or the like, or energy imparted to the substrate by the sputtering particles or the like. There is a concern that alloying may inhibit crystallization of the oxide semiconductor layer thereover. Furthermore, when alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. There is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor.

[0103] Therefore, before forming the oxide semiconductor 30b, the oxide semiconductor 30a is formed in advance using a film formation method that causes minimal damage to the surface on which the oxide semiconductor 30b is to be formed. This suppresses alloying of the components contained in the oxide semiconductor 30 with the components contained in the layer 29, and makes it possible to reduce the thickness of the alloyed region or to make the alloyed region thin enough that it is not observable. Here, the oxide semiconductor 30a is formed using the ALD method.

[0104] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0105] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Because the ALD method can deposit atoms layer by layer, it has the following advantages: it is possible to form an ultrathin film; it is possible to form a film on a surface with a high aspect ratio or large steps; it is possible to form a film with few defects such as pinholes; it is possible to form a film with excellent coverage; and it is possible to form a film at a low temperature. By using the ALD method as a film formation method for the oxide semiconductor 30a and the oxide semiconductor 30c (described later), the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio.

[0106] Furthermore, the PEALD method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods.

[0107] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 30a by ALD will be described.

[0108] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of layer 29. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer in which indium and oxygen are combined.

[0109] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0110] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer in which element M and oxygen are bonded. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0111] By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 30a on the layer 29 by the ALD method.

[0112] The substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0113] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the chamber, and then discharge excess precursor, reaction products, etc. from the chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the chamber, and then discharge excess reactant, reaction products, etc. from the chamber.

[0114] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0115] When the oxide semiconductor 30a is formed using the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed.

[0116] Next, an In-M-Zn oxide is formed as an oxide semiconductor 30b on the oxide semiconductor 30a by sputtering (FIG. 10B). The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure.

[0117] When the oxide semiconductor 30b is formed by sputtering, a mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. During the formation of the oxide semiconductor 30b, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 31. In a subsequent heat treatment step, the mixed layer 31 or the minute crystalline regions formed in the mixed layer 31 may act as nuclei, causing at least a portion of the oxide semiconductor 30a to crystallize.

[0118] Sputtering methods include RF sputtering, which uses a high-frequency power supply as a sputtering power supply; DC sputtering, which uses a direct-current power supply; and pulsed DC sputtering, which changes the voltage applied to an electrode in a pulsed manner. DC sputtering can be suitably used to form a metal conductive film and can improve productivity due to its high film formation rate. Pulsed DC sputtering can be suitably used to form a metal conductive film and a semiconductor film. RF sputtering can be suitably used to form an insulating film. Compounds such as oxides, nitrides, and carbides can be formed by reactive sputtering using a reactive gas. The metal oxide used for the oxide semiconductor layer of one embodiment of the present invention can be formed by a method appropriately selected from these methods depending on the conductivity of the sputtering target and the like.

[0119] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0120] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0121] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0122] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

[0123] In forming the oxide semiconductor 30b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, increasing the substrate temperature (stage temperature) during metal oxide formation may result in the formation of a metal oxide with high crystallinity. In forming the oxide semiconductor 30b by sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0124] Here, a model for forming a CAAC structure using a sputtering method will be described. First, microcrystals are formed during sputtering film formation. The microcrystals may be formed by energy imparted to the substrate by sputtered particles (sometimes referred to as atomic particles) or gas particles. Alternatively, planar or pellet-shaped sputtered particles (sometimes referred to as nanoclusters) that peel off from the sputtering target and deposit on the surface to be formed may become the microcrystals. Next, sputtered particles are adsorbed to the ends of the microcrystals, causing the microcrystals to grow laterally (in a direction substantially parallel to the surface to be formed). As the microcrystals grow laterally, adjacent microcrystals connect with each other, eliminating the ends of the microcrystals. Once the ends of the microcrystals are eliminated, sputtered particles are adsorbed onto the microcrystals, causing the microcrystals to grow vertically (in a direction substantially perpendicular to the surface to be formed). Sputtered particles are adsorbed to the ends of the vertically grown microcrystals, causing the microcrystals to grow laterally. In this way, the CAAC structure is formed by the microcrystals repeatedly growing in the lateral and vertical directions. That is, the CAAC structure is formed by the growth of microcrystals contained in an oxide semiconductor, using the microcrystals as nuclei or seeds.

[0125] Note that a CAAC structure is difficult to form in an oxide semiconductor containing impurities such as silicon, carbon, or water. Therefore, the oxide semiconductor 30b is preferably formed using a deposition method that is less likely to introduce impurities. Sputtering is suitable for forming the oxide semiconductor 30b because it can form an oxide semiconductor with a low impurity concentration by using a sputtering target with a reduced impurity concentration and a deposition gas with a reduced impurity amount.

[0126] Next, the oxide semiconductor 30c is formed on the oxide semiconductor 30b (FIG. 10C). Here, the oxide semiconductor 30c is formed by the ALD method. For the formation of the oxide semiconductor 30c by the ALD method, the method for forming the oxide semiconductor 30a can be referred to.

[0127] When an oxide semiconductor 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor 30b having a CAAC structure by using an ALD method, the oxide semiconductor 30c may grow epitaxially around the oxide semiconductor 30b as a nucleus. Therefore, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 30c.

[0128] The oxide semiconductor 30c can be used, for example, as a layer in contact with a gate insulating layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0129] Furthermore, by forming the oxide semiconductor 30c using the ALD method, damage to the oxide semiconductor 30b is reduced, and the oxide semiconductor 30 as a whole can have high crystallinity.

[0130] By using the ALD method, which has high coverage, as a method for forming the oxide semiconductors 30a and 30c, the oxide semiconductor layer as a whole can have coverage. Furthermore, by forming the oxide semiconductor 30b with high crystallinity using a sputtering method, the crystallinity of the upper and lower oxide semiconductor layers (the oxide semiconductors 30a and 30c) can be improved by epitaxial growth from the oxide semiconductor 30b. This allows the crystallinity of the oxide semiconductor 30 to be improved throughout the entire layer. Therefore, the oxide semiconductor 30 can have both high coverage and high crystallinity.

[0131] Next, a heat treatment step may be carried out.

[0132] The heat treatment may be performed at a temperature of, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the heat treatment may be performed at 400° C.±25° C. (375° C. to 425° C.). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When a rapid thermal annealing (RTA) apparatus is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 30b with the oxide semiconductor 30c (in other words, crystal molecules formed by the ALD method).

[0133] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0134] The heat treatment step may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c. Furthermore, if the region is formed only below the oxide semiconductor 30c after the ALD deposition, the heat treatment step may cause the region to expand upward ( FIG. 10D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 30c.

[0135] Furthermore, the heat treatment process may further repair the oxide semiconductor 30b by the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method) filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor 30b.

[0136] Furthermore, it is preferable that at least a portion of the oxide semiconductor 30a is converted into CAAC by this heat treatment step ( FIG. 10D ). It is expected that the CAAC conversion is facilitated by the mixed layer 31 formed in the oxide semiconductor 30a during the deposition of the oxide semiconductor 30b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 30a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 29.

[0137] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 30a, the CAAC can be formed up to the vicinity of the layer 29 regardless of the material or crystallinity of the layer 29. For example, even if the layer 29 has an amorphous structure, the oxide semiconductor 30a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0138] After the oxide semiconductor 30c is formed, a microwave plasma treatment may be performed.

[0139] Here, microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves, for example. Furthermore, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0140] It is preferable to reduce the impurity concentration in the oxide semiconductor 30 by performing microwave plasma treatment in an atmosphere containing oxygen. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0141] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or more and 1000 Pa or less, and more preferably being 300 Pa or more and 700 Pa or less. The microwave plasma treatment is preferably carried out in a heated state. The substrate temperature is preferably set to be room temperature (e.g., 25°C) or more and 500°C or less, preferably 100°C or more and 500°C or less, more preferably 200°C or more and 500°C or less, even more preferably 300°C or more and 500°C or less, and even more preferably 400°C or more and 500°C or less. For example, the temperature can be set to be 400°C or more and 450°C or less.

[0142] Alternatively, after the microwave plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The heat treatment temperature is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0143] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave plasma treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can act on the oxide semiconductor layer. The V in the oxide semiconductor layer can be formed by the action of the plasma, microwaves, or the like. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. ＯH can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, oxygen vacancies formed in the oxide semiconductor layer can be further reduced by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the oxide semiconductor layer.

[0144] Oxygen to be implanted into the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that the oxygen to be implanted into the oxide semiconductor layer may be in one or more of the above forms, and is particularly preferably an oxygen radical.

[0145] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0146] Note that one or both of the heat treatment and the microwave plasma treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0147] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0148] By using the oxide semiconductor layer having the CAAC structure formed by the above two types of film formation methods in a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small subthreshold swing value (also referred to as S value), a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized. Here, the S value refers to the amount of change in gate voltage in a subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0149] In the oxide semiconductor 30, it is preferable that a region having a CAAC structure is widely present throughout the entire layer including the oxide semiconductor 30a and the oxide semiconductor 30c. FIG. 11A shows the crystallization of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c. The crystals in the region having the CAAC structure in the oxide semiconductor 30a are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The crystals in the region having the CAAC structure in the oxide semiconductor 30c are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The oxide semiconductor 30 can sometimes be expressed as a single layer with no clearly observed interface. The oxide semiconductor 30 can sometimes be expressed as a single layer.

[0150] The regions having the CAAC structure in the oxide semiconductors 30a, 30b, and 30c can be observed as bright spots aligned parallel to the surface on which they are formed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axes of the CAAC structures in the oxide semiconductors 30a, 30b, and 30c are each substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0151] Furthermore, there are cases where a portion of the oxide semiconductor 30a or the oxide semiconductor 30c is not crystallized. The example shown in Fig. 11B shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a is not crystallized. Fig. 11C shows a state in which the vicinity of the surface in the oxide semiconductor 30c is not crystallized. Fig. 11D shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a and the vicinity of the surface of the oxide semiconductor 30c are not crystallized.

[0152] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor 30, the boundaries between the stacked oxide semiconductors 30a, 30b, and 30c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0153] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small. This allows the oxide semiconductor 30a or the oxide semiconductor 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 30b. In this case, for example, when a cross section of the oxide semiconductor 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0154] As long as the lattice mismatch between the crystal of the oxide semiconductor 30b and the crystal of the oxide semiconductor 30a or the oxide semiconductor 30c is small, the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c is not particularly limited. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0155] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0156] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the film thickness of the oxide semiconductor 30 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, and further preferably 5 nm to 12 nm.

[0157] The thickness of the oxide semiconductor 30b is preferably, for example, 200 nm or less. When the oxide semiconductor 30b has a layered structure, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0158] Alternatively, if the oxide semiconductor 30b can function as a crystal nucleus, the oxide semiconductor 30b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 30b exist discretely.

[0159] The thickness of the oxide semiconductor 30a and the oxide semiconductor 30c is, for example, preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm.

[0160] The thickness of the region where the component contained in the oxide semiconductor 30 and the component contained in the layer 29 are alloyed is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 10A and 10B show an example in which no alloy region is formed between the layer 29 and the oxide semiconductor 30a.

[0161] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0162] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 30a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 30a contains In) that is the main component of the oxide semiconductor 30a but is not the main component of the layer that will become the surface (here, layer 29) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 30a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 30a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0163] For example, when a silicon oxide layer is used as the layer 29 and an SIMS analysis is performed on the oxide semiconductor 30 formed on the layer 29, the interface is defined as a depth at which the silicon concentration is 50% of the maximum concentration of the layer 29, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 0.5 nm and the interface is defined as thickness t_s. The thickness t_s is preferably 3 nm or less, and more preferably 2 nm or less.

[0164] By reducing the thickness of the alloyed region, it is possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor 30 that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, substantially perpendicularly from the formation surface.

[0165] The oxide semiconductor 30a has a region located, for example, at a distance of 0 to 3 nm from the top surface of the layer 29. The oxide semiconductor 30c is located, for example, at a distance of 0 to 3 nm from the top surface of the oxide semiconductor 30b. The oxide semiconductors 30a, 30b, and 30c have, for example, approximately the same thickness. Alternatively, the oxide semiconductors 30a, 30b, and 30c may have different thicknesses.

[0166] Although the oxide semiconductor 30 has a three-layer structure of the oxide semiconductors 30a to 30c in the above description, the present invention is not limited to this. The oxide semiconductor 30 may have a two-layer structure or a stacked structure of four or more layers.

[0167] When the oxide semiconductor 30 has a two-layer structure, the oxide semiconductor 30 can have a configuration in which an oxide semiconductor 30a and an oxide semiconductor 30b are stacked in this order. This configuration suppresses alloying of the components contained in the oxide semiconductor 30 with the components contained in the layer 29, and makes it possible to reduce the thickness of the alloyed region or to make the alloyed region thin enough that it cannot be observed. Alternatively, the oxide semiconductor 30 can have a configuration in which an oxide semiconductor 30b and an oxide semiconductor 30c are stacked in this order.

[0168] Alternatively, when the oxide semiconductor 30 has a five-layer structure, the oxide semiconductor 30 can have a structure in which a first oxide semiconductor, a second oxide semiconductor, a third oxide semiconductor, a fourth oxide semiconductor, and a fifth oxide semiconductor are stacked in this order. For example, the first oxide semiconductor, the third oxide semiconductor, and the fifth oxide semiconductor are preferably formed by the second film formation method, more preferably by an ALD method. The second oxide semiconductor and the fourth oxide semiconductor are preferably formed by the first film formation method, more preferably by a sputtering method. With such a structure, even if the third oxide semiconductor has a composition that makes it difficult to form a CAAC structure, crystal growth can be promoted from one or both of the second oxide semiconductor and the fourth oxide semiconductor, thereby improving the crystallinity of the third oxide semiconductor.

[0169] When the oxide semiconductor 30 has a stacked structure of two or more layers, typically a stacked structure of two to five layers, it is preferable to deposit each layer successively without exposing it to the atmosphere. For example, each layer may be deposited successively using a multi-chamber deposition apparatus. This allows the oxide semiconductor 30 to be deposited while suppressing impurities that may be mixed into each layer.

[0170] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0171] The CAAC structure of an oxide semiconductor layer can sometimes be evaluated from a map showing crystal orientation. For example, in a region having the CAAC structure, it is observed that crystals are c-axis oriented.

[0172] A map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing FFT processing on each region within the cross-sectional TEM image to create an FFT pattern, and calculating the crystal axis direction of each region. Specifically, for example, two spots of high intensity are observed in the FFT pattern of a region having layered crystalline portions. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0173] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing the crystal orientation.

[0174] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0175] Furthermore, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image may be, for example, a region with a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0176] In the oxide semiconductor layer of one embodiment of the present invention, for example, the percentage of regions in which the difference between the direction of the crystal axis of each region and the direction perpendicular to the surface on which the layer is formed is within 20° can be defined as the c-axis orientation rate. In this case, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0177] The c-axis orientation rates of the region where the oxide semiconductor 30a is formed, the region where the oxide semiconductor 30b is formed, and the region where the oxide semiconductor 30c is formed are defined as Rc1, Rc2, and Rc3, respectively. For example, the c-axis orientation rate can be defined as the percentage of regions where the difference between the direction perpendicular to the formation surface and the crystal axis direction of each region is within 20°. In this case, Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0178] [Composition of Oxide Semiconductor Layer] The oxide semiconductor 30a preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30c preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30a may have the same composition as the oxide semiconductor 30c. Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may have different compositions.

[0179] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 30b preferably contains, in addition to zinc, the element M. By containing the element M in the oxide semiconductor 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Specifically, the oxide semiconductor 30b may be a metal oxide having an In:M:Zn = 1:1:1 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:1.2 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:0.5 atomic ratio or a composition thereabout, an In:M:Zn = 1:1:2 atomic ratio or a composition thereabout, an In:M:Zn = 4:2:3 atomic ratio or a composition thereabout, an In:M:Zn = 1:3:2 atomic ratio or a composition thereabout, or an In:M:Zn = 1:3:4 atomic ratio or a composition thereabout. Note that, in this specification, a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, tin, yttrium, and aluminum as the element M.

[0180] The oxide semiconductor 30b may not contain the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0181] The oxide semiconductor 30a and the oxide semiconductor 30c can be made of a metal oxide that can be used for the oxide semiconductor 230b described above. The oxide semiconductor 30a and the oxide semiconductor 30c can be made of a metal oxide having a high proportion of In. It is particularly preferable that the oxide semiconductor 30a and the oxide semiconductor 30c be made of a metal oxide having a higher proportion of In than the oxide semiconductor 30b. The oxide semiconductor 30a and the oxide semiconductor 30c can be formed by, for example, an ALD method. It is particularly preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-current and frequency characteristics can be increased.

[0182] An oxide semiconductor with a high In content tends to be polycrystalline. Using a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. In the oxide semiconductor layer of one embodiment of the present invention, the crystal orientation of the oxide semiconductor 30b can be reflected in the oxide semiconductors 30a and 30c with a high In content. Therefore, even when a metal oxide with a high In content is used for the oxide semiconductors 30a and 30c, polycrystallization can be suppressed.

[0183] Alternatively, the oxide semiconductors 30a and 30c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition with an atomic ratio of In:Zn=1:1 or a ratio therebetween, an atomic ratio of In:Zn=2:1 or a ratio therebetween, or an atomic ratio of In:Zn=4:1 or a ratio therebetween. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductors 30a and 30c may contain a trace amount of the element M. Specifically, they may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a ratio therebetween, an atomic ratio of In:Ga:Zn=2:0.1:1 or a ratio therebetween, an atomic ratio of In:Sn:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a ratio therebetween.

[0184] Alternatively, metal oxides with a high Ga content may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with a higher Ga content than the oxide semiconductor 30b may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, metal oxides with an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or metal oxides with an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout are preferably used for the oxide semiconductors 30a and 30c, respectively. Increasing the Ga content may result in the band gaps of the oxide semiconductors 30a and 30c being larger than those of the oxide semiconductor 30b. As a result, the oxide semiconductor 30b is sandwiched between the oxide semiconductors 30a and 30c, which have larger band gaps, allowing the oxide semiconductor 30b to function primarily as a current path (channel). Furthermore, the trap levels at and near the interface of the oxide semiconductor 30b can be reduced. This allows a buried channel transistor in which the channel is located away from the insulating layer interface to be realized. Furthermore, the influence of interface states that may be formed on the back channel side is reduced, which can suppress light degradation of the transistor (e.g., negative bias light degradation) and improve the reliability of the transistor.

[0185] Alternatively, one of the oxide semiconductors 30a and 30c may be a metal oxide having a higher proportion of In than the oxide semiconductor 30b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor 30b.

[0186] The oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may each have a plurality of layers each having the above-described composition stacked together. For example, the oxide semiconductor 30c may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0187] The oxide semiconductor 30a and the oxide semiconductor 30c may be made of a metal oxide having the same composition as the oxide semiconductor 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0188] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 30a and 30c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs with the oxide semiconductor 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 30a and 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductors 30a and 30c and the oxide semiconductor 30b.

[0189] The composition of the metal oxide used in the oxide semiconductor 30 can be analyzed by, for example, EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0190] [Impurities in Oxide Semiconductor] The influence of each impurity in an oxide semiconductor will be described below. The impurities contained in an oxide semiconductor can be quantified using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0191] It is preferable that the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H may be formed, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region, V Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0192] Therefore, reducing the impurity concentration in an oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 1 atomic % or less than 0.1 atomic % may be referred to as an impurity.

[0193] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0194] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0195] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0196] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0197] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0198] The average thickness of the oxide semiconductor 30 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and even more preferably 10 nm or less.

[0199] The oxide semiconductor 30a is an oxide semiconductor layer formed on a surface to be formed. The thickness of the oxide semiconductor 30a is preferably 0.5 nm or more and 3 nm or less.

[0200] In addition, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to see that metal atoms of the metal oxide are arranged in a layered manner in a region having a CAAC structure. In this case, for example, the metal atoms are arranged in a direction parallel to or approximately parallel to a surface on which the metal oxide is formed.

[0201] The oxide semiconductor 30, which is an AG CAAC, can be used as the oxide semiconductor 230 of the transistor 200. For example, as shown in FIG. 2B , the oxide semiconductor 230 can have a structure including an oxide semiconductor 230a, an oxide semiconductor 230b in contact with the top surface of the oxide semiconductor 230a, and an oxide semiconductor 230c in contact with the top surface of the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c.

[0202] Here, the insulators 224 and 225 correspond to the layer 29. That is, the surfaces on which the oxide semiconductor 230 is formed are the top surface of the insulator 224, the top surface of the insulator 225, and the side surface of the insulator 225. During the manufacturing process, one surface of the oxide semiconductor 230a is in contact with the insulators 224 and 225, and the other surface of the oxide semiconductor 230b. One surface of the oxide semiconductor 230b is in contact with the oxide semiconductor 230a and the other surface of the oxide semiconductor 230c. One surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b and the other surface of the oxide semiconductor 230c is in contact with the insulator 250.

[0203] As described above, in a cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel to or approximately parallel to the formation surface. In other words, in a cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using a TEM image, it is confirmed that, in a portion where the oxide semiconductor 230 is in contact with the top surface of the insulator 224 or the top surface of the insulator 225, metal atoms are arranged in layers parallel to or approximately parallel to the top surface of the insulator 224 or the top surface of the insulator 225. It can also be said that, in some cases, in a portion where the oxide semiconductor 230 is in contact with the top surface of the insulator 224 or the top surface of the insulator 225, metal atoms are arranged in layers parallel to or approximately parallel to the substrate surface. Furthermore, in a portion where the oxide semiconductor 230 is in contact with the side surface of the insulator 225, it is confirmed that metal atoms are arranged in layers parallel to or approximately parallel to the side surface of the insulator 225. Here, the side surface of the insulator 225 may be formed perpendicular or substantially perpendicular to the substrate surface (which may also be referred to as the surface of the insulator 222). Therefore, it may be possible to say that, in the portion where the oxide semiconductor 230 contacts the side surface of the insulator 225, metal atoms are arranged in layers in a direction perpendicular or substantially perpendicular to the substrate surface. It may also be possible to say that the c-axis of the AG CAAC is substantially parallel to the normal direction of the surface on which the oxide semiconductor 230 is formed.

[0204] In this manner, by using the oxide semiconductor 230, which is AG CAAC, for the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0205] A channel formation region and a source region and a drain region sandwiching the channel formation region in the transistor 200 are formed in the oxide semiconductor 230. At least part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0206] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0207] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0208] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0209] Note that when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0210] To stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0211] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide semiconductor 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0212] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H may be formed, and electrons serving as carriers may be generated. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0213] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V ＯH can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0214] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0215] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress reduction in the hydrogen concentration in the source and drain regions.

[0216] The insulator 250 in contact with the channel formation region of the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0217] 2A , the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, the insulator 250a and the insulator 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0218] Examples of insulators that have the function of capturing or fixing hydrogen include metal oxides with an amorphous structure. For the insulators 250a and 250c, it is preferable to use, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0219] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulators 250a and 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulators 250a and 250c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0220] For the insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0221] In this embodiment, an aluminum oxide film is used as the insulator 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively captured and fixed.

[0222] In this embodiment, hafnium oxide is used as the insulator 250c. By providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0223] Next, it is preferable to use a thermally stable insulator such as silicon oxide or silicon oxynitride for the insulator 250b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0224] The silicon oxide film used as the insulator 250b is preferably formed using a PEALD method.

[0225] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250d, the insulator 250c, and the insulator 275.

[0226] In this specification and the like, a barrier insulator refers to an insulator with barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. Furthermore, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0227] Examples of the oxygen barrier insulator include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, and 275 each preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen barrier insulators.

[0228] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0229] The insulator 250a is provided in contact with the top surface and side surface of the oxide semiconductor 230 and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide semiconductor 230 during heat treatment or the like. Thus, oxygen vacancies can be reduced in the oxide semiconductor 230.

[0230] Furthermore, the insulator 250a prevents excessive oxygen from being supplied from the insulator 280 to the oxide semiconductor 230, and enables an appropriate amount of oxygen to be supplied to the oxide semiconductor 230. Therefore, excessive oxidation of the source and drain regions can be suppressed, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0231] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and can therefore be suitably used as the insulator 250a.

[0232] The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260 and between the insulator 280 and the conductor 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. Furthermore, oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0233] The insulator 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230.

[0234] The insulator 275 also preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. The insulator 275 is provided in contact with the side surface of the conductor 242, the side surface of the oxide semiconductor 230, and the top surface of the insulator 222. This structure can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, an increase in resistivity due to oxidation of the conductor 242 caused by the oxygen contained in the insulator 280 can be prevented. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, silicon nitride is preferably used as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0235] A barrier insulator against hydrogen is preferably provided near each of the source and drain regions in order to suppress a decrease in the hydrogen concentrations in the source and drain regions of the oxide semiconductor 230. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0236] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0237] Furthermore, because the insulator 275 forms the sidewall of the opening 201, regions of the source and drain regions in the oxide semiconductor 230 that overlap with the opening 201 (which can also be referred to as regions of the source and drain regions in the oxide semiconductor 230 that overlap with the conductors 242a1 and 242b1 but do not overlap with the conductors 242a2 and 242b2) are exposed from the insulator 275. In contrast, the insulator 255 covering these regions of the oxide semiconductor 230 is preferably made of a barrier insulator against hydrogen (for example, silicon nitride). In this way, regions of the source and drain regions of the oxide semiconductor 230 that are not covered with the insulator 275 can also be covered with the insulator 255 that functions as a barrier insulator against hydrogen.

[0238] By providing the insulators 275 and 255 as described above, it is possible to suppress the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentrations in the source and drain regions, thereby making the source and drain regions n-type.

[0239] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0240] The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d, together with the conductor 260, are provided in the opening formed in the insulator 280. To miniaturize the transistor 200, the thicknesses of the insulators 250a to 250d are preferably small. The thicknesses of the insulators 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulators 250a to 250d may have a region with the above thickness at least in part.

[0241] Furthermore, the thickness of the silicon oxide film used as the insulator 250b is preferably 0.7 nm or more and 3 nm or less.

[0242] To thin the film thicknesses of the insulators 250a to 250d as described above, it is preferable to deposit the insulators by an ALD method. Furthermore, to provide the insulators 250a to 250d in openings in the insulator 280 and the like, it is preferable to deposit the insulators by an ALD method. Examples of ALD methods include thermal ALD (thermal ALD), which uses only thermal energy to cause a reaction between a precursor and a reactant, and plasma-enhanced ALD (PEALD), which uses a plasma-excited reactant. The PEALD method may be preferable because it uses plasma, which enables film deposition at a lower temperature.

[0243] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280 and the side ends of the conductors 242a and 242b, etc., with a thin film thickness as described above.

[0244] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using SIMS, XPS, or Auger Electron Spectroscopy (AES).

[0245] Although the above description has been given of a structure in which the insulator 250 has a four-layer structure of the insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0246] For example, as shown in Fig. 6A, the insulator 250 may have a three-layer structure. In this case, it is preferable that the insulator 250 has a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In other words, this is a structure in which the insulator 250d is removed from the structure shown in Fig. 2A.

[0247] It is preferable to use the ALD process two or more times in forming the insulator 250. For example, the insulator 250 preferably has a stacked structure of multiple insulating films, and two or more of the multiple insulating films are preferably formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulator 250. Furthermore, it is possible to increase productivity by continuously forming two or more different films, for example, two or more insulating films, using the ALD process.

[0248] In addition to the above structure, it is preferable to have a structure that suppresses hydrogen from being mixed into the transistor 200 or the like. For example, it is preferable to provide an insulator that has a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, or the insulator 221. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0249] It is preferable that one or more of the insulators 283, 282, 222, and 221 function as barrier insulators that suppress diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or more of the insulators 283, 282, 222, and 221 suppress diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0250] The insulators 283, 282, 222, and 221 each preferably have an insulator that functions to suppress the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulators 283 and 221 are preferably made of silicon nitride, which has a high hydrogen barrier property. Furthermore, for example, the insulator 282 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulator 222 is preferably made of hafnium oxide, which is a high-dielectric-constant (high-k) material and has a high ability to capture or fix hydrogen.

[0251] At least one of the insulators 221 and 222 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulator 221 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 222 can have a stacked structure of hafnium oxide and silicon oxide.

[0252] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200 and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200 and the like. Furthermore, hydrogen contained in the insulator 280, the insulator 250, and the like can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, the provision of the insulators 282 and 283 can prevent oxygen contained in the insulator 280 and the like from diffusing upward from the transistor 200 and the like. Furthermore, the provision of the insulators 222 and 221 can prevent oxygen contained in the oxide semiconductor 230 and the like from diffusing downward from the transistor 200 and the like. Thus, by surrounding the transistor 200 from above and below with insulators that have a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen into the oxide semiconductor can be prevented. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0253] Furthermore, it is preferable to use silicon nitride or the like, which has a higher hydrogen barrier property, for the insulators 275 and 250d. It is also preferable to use aluminum oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250a. It is also preferable to use hafnium oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250c.

[0254] The insulator 225 is formed in contact with the upper surface of the insulator 224. As shown in FIGS. 2B and 8A , the insulator 225 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. The height H of the insulator 225 is preferably greater than the width L of the insulator 225. The height H of the insulator 225 may be 1 to 20 times, preferably 1.3 to 15 times, and more preferably 1.5 to 10 times the width L of the insulator 225. For example, the width L may be 5 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 8 nm to 30 nm. For example, the height H may be 30 nm to 300 nm, preferably 50 nm to 150 nm.

[0255] 2B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the insulator 225 and the top surface of the insulator 224 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0256] The upper portion of the insulator 225 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the oxide semiconductor 230 and the conductor 242 near the upper portion of the insulator 225.

[0257] The oxide semiconductor 230 and the conductor 242 are provided to cover the insulator 225 having such a high aspect ratio. In the vicinity of the channel formation region of the transistor 200, the oxide semiconductor 230 is provided so as to be folded in half with the insulator 225 sandwiched therebetween, as shown in FIG. 2B , and the insulator 250 and the conductor 260 are further provided to cover the oxide semiconductor 230. As a result, the channel width of the transistor 200 is increased by the side surface on the A1 side and the side surface on the A2 side of the insulator 225.

[0258] By increasing the channel width as described above, the on-state current, field-effect mobility, frequency characteristics, and the like of the transistor 200 can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by providing the insulator 225, the channel width can be increased without increasing the area occupied by the transistor 200. This enables miniaturization or high integration of the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0259] The bottom surface of the insulator 224 is in contact with the insulator 222, and the top surface is in contact with the insulator 225 and the oxide semiconductor 230. The planar shape of the insulator 224 is similar to that of the oxide semiconductor 230, and the insulator 224 overlaps with the oxide semiconductor 230 in a planar view. That is, the side surface of the insulator 224 coincides with or substantially coincides with the side surface of the oxide semiconductor 230 in a planar view. Furthermore, at least part of the insulator 224 overlaps with the conductor 242a (the conductor 242a1 and the conductor 242a2) and the conductor 242b (the conductor 242b1 and the conductor 242b2) in a planar view. In other words, at least a portion of the side surface of the insulator 224 coincides or substantially coincides with the side surfaces of the conductor 242a (conductor 242a1 and conductor 242a2) and the conductor 242b (conductor 242b1 and conductor 242b2) in a plan view.

[0260] 2B , it is preferable that the thickness t1 of the insulator 224 in the opening 201 is thicker than the thickness t2 of the insulator 250. With this configuration, the bottom surface of the conductor 260 (conductor 260 a) located in the opening 201 can be positioned lower than the bottom surface of the oxide semiconductor 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0261] By disposing the bottom surface of the conductor 260 below the bottom surface of the oxide semiconductor 230, a gate electric field can be applied sufficiently from the top end to the bottom end of the oxide semiconductor 230. In other words, the entire oxide semiconductor 230 is electrically surrounded by the electric field of the conductor 260 in the opening of the insulator 280 or the like, and can function as a channel formation region. This configuration prevents the bottom end of the oxide semiconductor 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistor behavior, that are caused by the parasitic channel. In other words, the electrical characteristics of the transistor 200 can be improved.

[0262] Furthermore, as described above, the oxide semiconductor 230 functions as a channel formation region from the top end to the bottom end, whereby the channel width can be increased, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200.

[0263] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0264] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a gate all around (GAA) structure or a lateral gate all around (LGAA) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, which is expected to improve the on-state current or the field-effect mobility of the transistor.

[0265] In one embodiment of the present invention, the oxide semiconductor 230 has a CAAC structure and covers the fin-shaped insulator 225. The CAAC structure is formed so that the a-b plane is parallel or approximately parallel to the channel length direction. With this structure, a current path flowing from one of the source and drain of the transistor to the other can be parallel to the a-b plane of the CAAC structure. In other words, an oxide semiconductor having a CAAC structure and covering the fin-shaped insulator 225 has a conduction path equivalent to that of a two-dimensional semiconductor material. By using such an oxide semiconductor for a semiconductor layer of a transistor, a device having a two-dimensional conduction path can be manufactured.

[0266] The insulators 225 and 224 may be formed using an insulating material that can be used for the insulator 222, the insulator 275, the insulator 280, the insulator 250, and the like. Because the insulators 225 and 224 are in contact with the oxide semiconductor 230, as described above, an insulating material that releases little hydrogen is preferably used. Examples of insulating materials that release little hydrogen include silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). This can prevent hydrogen from entering the oxide semiconductor 230. In particular, using silicon nitride for at least one of the insulators 225 and 224 can improve the reliability of the transistor. The insulators 225 and 224 preferably function as barrier insulators against hydrogen and preferably have the property of preventing hydrogen from diffusing into the insulators or the function of capturing or fixing hydrogen inside the insulators. Therefore, the insulators 225 and 224 can also be made of the insulating material that functions as a barrier insulator against hydrogen as described above.

[0267] For example, silicon nitride can be used for the insulators 225 and 224. In this case, the region of the insulator 224 that does not overlap with the insulator 225 may be thinner than the region of the insulator 224 that overlaps with the insulator 225. Alternatively, hafnium silicate can be used for the insulator 225, and silicon nitride can be provided for the insulator 224. With such a configuration, the insulator 224 can suppress the diffusion of hydrogen from below, and the insulator 225 can capture or fix hydrogen in the region surrounded by the insulators 224 and 250. This allows the hydrogen concentration in the region surrounded by the insulators 224 and 250 to be reduced.

[0268] Here, the insulator 225 does not necessarily have to be insulating in the strict sense, and a semiconductor with a wide band gap and high insulating properties may be used as the insulator 225. For example, a metal oxide material having lower conductivity than the oxide semiconductor 230b or a wider band gap than the oxide semiconductor 230b can be used as the insulator 225. Such a metal oxide material is preferably a metal oxide containing a large amount of gallium. The proportion of gallium in the insulator 225 is preferably higher than the proportion of gallium in the oxide semiconductor 230b. Here, the proportions of gallium and indium are compared in atomic percentage. For example, gallium oxide may be used for the insulator 225. Alternatively, a metal oxide containing indium, gallium, and zinc may be used as such a metal oxide material. In this case, the proportion of gallium in the insulator 225 is preferably higher than the proportion of indium. For example, a metal oxide having a composition of In:Ga:Zn=1:3:2 (atomic ratio) or a composition close to that ratio can be used as the insulator 225.

[0269] The insulator 225 preferably contains a Group 13 element (also referred to as a Group III element), such as gallium or indium, in common with the oxide semiconductor 230b. By having a high insulating property and containing a metal element common to the metal element contained in the oxide semiconductor 230, trap levels at the interface with the oxide semiconductor 230 and in the vicinity thereof can be reduced. For example, compared to when a silicon-based insulating material is used for the insulator 225, when the above-mentioned metal oxide material is used for the insulator 225, trap levels at the interface between the insulator 225 and the oxide semiconductor 230 and in the vicinity thereof can be reduced. This can reduce leakage current at the interface between the oxide semiconductor 230b and the insulator 225. Furthermore, the influence of interface states that may be formed on the back channel side of the oxide semiconductor 230 is reduced, which can suppress photodegradation (e.g., negative bias light photodegradation) of the transistor and improve the reliability of the transistor.

[0270] 2B shows an example in which the oxide semiconductor 230 has a three-layer structure, but the present invention is not limited thereto. The oxide semiconductor 230 may have a two-layer structure or a four-layer or more layer structure. For example, when the oxide semiconductor 230 has a two-layer structure, the oxide semiconductor 230 may have a two-layer structure of an oxide semiconductor 230b and an oxide semiconductor 230c on the oxide semiconductor 230b, as shown in FIG. 3A. By forming the oxide semiconductor 230 into a two-layer structure and reducing its thickness, the amounts of impurities such as hydrogen and excess oxygen contained in the oxide semiconductor 230 can be reduced, thereby improving the reliability of the transistor 200.

[0271] Furthermore, even if the thickness of the oxide semiconductor 230 is thin as described above, by providing the oxide semiconductor 230 so as to cover the insulator 225 having a high aspect ratio, the oxide semiconductor 230 can be supported by the insulator 225. This allows the oxide semiconductor 230 to be formed so as to extend upward relative to the substrate without being tilted. Therefore, the channel width of the oxide semiconductor 230 can be increased without increasing the occupation area.

[0272] In particular, by using a metal oxide with high insulating properties for the insulator 225 as described above, trap states at and in the vicinity of the interface between the oxide semiconductor 230b and the insulator 225 can be reduced without providing the oxide semiconductor 230a. This can reduce leakage current at the interface between the oxide semiconductor 230b and the insulator 225. Furthermore, the influence of interface states that may be formed on the back channel side of the oxide semiconductor 230b can be reduced, thereby improving the reliability of the transistor 200.

[0273] Although the above example shows the case where the insulator 224 is provided under the insulator 225, the present invention is not limited to this. As shown in FIG. 3B , a configuration without the insulator 224 is also possible. In this case, the insulator 225 and the oxide semiconductor 230 are formed in contact with the upper surface of the insulator 222. When the oxide semiconductor 230 is processed into an island shape or when the opening 201 is formed, part of the upper surface of the insulator 222 may be removed. As a result, as shown in FIG. 3B , a region of the upper surface of the insulator 222 that overlaps with the oxide semiconductor 230 may be higher than a region of the upper surface of the insulator 222 that does not overlap with the oxide semiconductor 230.

[0274] In addition, although the above describes an example in which the side surface of the insulator 225 is located more inward than the side surface of the insulator 224, the present invention is not limited to this. As shown in Fig. 4A, the side surfaces of the insulator 225 and the insulator 224 can also be formed to be flush with each other. Here, a configuration can be adopted in which the lower end of the side surface of the insulator 225 and the upper end of the side surface of the insulator 224 coincide or approximately coincide with each other.

[0275] Although the above example shows the oxide semiconductor 230 covering the insulator 225, the present invention is not limited thereto. As shown in FIG. 4B , the oxide semiconductor 230 may be provided in a sidewall shape in contact with the side surface of the insulator 225. For example, when the conductor 242a1 and the conductor 242b1 are separated, the oxide semiconductor 230 may be removed from a portion in contact with the top surface of the insulator 225 and a portion in contact with the top surface of the insulator 222, and the oxide semiconductor 230 may remain in a portion in contact with the side surface of the insulator 225. Even when the oxide semiconductor 230 has the above structure, the channel width of the transistor 200 can be made sufficiently large by increasing the height H of the insulator 225.

[0276] 5A , a protective layer 227 may be provided to cover the insulators 224 and 225. The protective layer 227 is preferably made of a metal oxide material that can be used for the oxide semiconductor 230. It is more preferable to use a metal oxide material that can be used for the oxide semiconductor 230a or the insulator 225. For example, the protective layer 227 can be made of a single layer or a stack of gallium oxide, zinc oxide, or the like. For example, the protective layer 227 can be made of a metal oxide containing indium, gallium, and zinc. In this case, the proportion of gallium in the protective layer 227 is preferably higher than the proportion of indium. Here, the proportions of gallium and indium are compared in atomic percent. For example, the protective layer 227 can be made of a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close to that.

[0277] In this manner, by using a metal oxide with high insulating properties for the protective layer 227, trap states at the interface between the oxide semiconductor 230 and the insulator 225 and in the vicinity thereof can be reduced. This can reduce leakage current at the interface between the oxide semiconductor 230 and the insulator 225. Furthermore, the influence of interface states that may be formed on the back channel side of the oxide semiconductor 230 can be reduced, thereby improving the reliability of the transistor 200. When the protective layer 227 is formed, the oxide semiconductor 230a need not be provided.

[0278] The protective layer 227 can be thinner than the oxide semiconductor 230, for example, 0.1 nm to 1 nm in thickness. The planar shape of the protective layer 227 is similar to that of the oxide semiconductor 230, and the protective layer 227 overlaps with the oxide semiconductor 230 in plan view.

[0279] The protective layer 227 covers the insulators 225 and 224, thereby preventing impurities such as hydrogen contained in the insulators 225 and 224 from diffusing into the oxide semiconductor 230. This allows the AG CAAC to be formed even in layers below the oxide semiconductor 230 (for example, the oxide semiconductor 230a shown in FIG. 5A ). Because the protective layer 227 is provided, an insulating material such as silicon oxide or silicon nitride can be used for one or both of the insulators 225 and 224. In this case, it is preferable to perform heat treatment or the like on the insulators 225 and 224 to sufficiently reduce impurities such as hydrogen contained in the insulators 224 and 225.

[0280] Although the above describes an example in which a metal oxide material is used for the protective layer 227, the present invention is not limited to this. The protective layer 227 may be configured to use an insulating material that can be used for the insulator 275, etc. It is preferable to use a barrier insulator against hydrogen for the protective layer 227, for example, silicon nitride for the protective layer 227. Using silicon nitride for the protective layer 227 can further reduce the diffusion of impurity components such as hydrogen contained in the insulators 225 and 224. Therefore, an insulating material that is relatively permeable to hydrogen, such as silicon oxide, can also be used for one or both of the insulators 225 and 224.

[0281] 5B, the insulator 224 can have a structure including an insulator 224a and an insulator 224b on the insulator 224a, and the insulator 225 can have a structure including an insulator 225a and an insulator 225b on the insulator 225a. Here, the insulators 224a and 225a can be made of the above-mentioned insulating material that releases little hydrogen, such as silicon nitride.

[0282] The insulator 225b may be made of an insulating material that functions as a hard mask during etching of the insulator 225a. For example, when silicon nitride is used for the insulator 225a, aluminum oxide may be used for the insulator 225b. In this case, the thickness of the insulator 225b may be thinner than that of the insulator 225a.

[0283] The insulator 224b may be made of an insulating material that functions as an etching stopper when the insulator 225a is etched. For example, if silicon nitride is used for the insulator 225a, aluminum oxide may be used for the insulator 224b. In this case, the thickness of the insulator 224b may be thinner than that of the insulator 224a.

[0284] Alternatively, the insulator 224b may be made of silicon nitride, which has a high hydrogen barrier property. If the insulator 224b can sufficiently suppress the diffusion of impurity components such as hydrogen contained in the insulator 224a, the insulator 224a may be made of an insulating material, such as silicon oxide, that is relatively permeable to hydrogen.

[0285] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0286] The conductor 242a and the conductor 242b are spaced apart from each other through the opening 201 and are in contact with the oxide semiconductor 230. As shown in FIG. 8A and other drawings, the conductor 242 is provided to cover the insulator 225 having a high aspect ratio.

[0287] 8A , the oxide semiconductor 230 and the conductor 242a are provided near the source or drain of the transistor 200 so as to be folded in half with the insulator 225 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductor 242a is in contact with the oxide semiconductor 230 at the top of the insulator 225, the side surface on the A3 side, the side surface on the A4 side, and near the insulator 224. Therefore, compared to when the insulator 225 is not provided, the contact area between the conductor 242a and the oxide semiconductor 230 is increased by the side surface on the A3 side and the side surface on the A4 side of the insulator 225. Note that while FIGS. 8A and 1C show the vicinity of the conductor 242a, the same applies to the conductor 242b. That is, the contact area between the conductor 242b and the oxide semiconductor 230 is increased, similar to the contact area between the conductor 242a and the oxide semiconductor 230 described above.

[0288] By increasing the contact area between the conductor 242 and the oxide semiconductor 230 as described above, the contact resistance between the conductor 242 and the oxide semiconductor 230 can be reduced without significantly increasing the area occupied by the transistor 200. Therefore, the on-state current, frequency characteristics, and the like of the transistor 200 can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also enables miniaturization or high integration of the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0289] As shown in FIGS. 1D and 2A , the conductor 242a and the conductor 242b preferably have a two-layer structure. The conductor 242a is a stacked film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b is a stacked film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the layer in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1). This can suppress a decrease in the conductivity of the conductor 242a and the conductor 242b. Furthermore, it can suppress the extraction of oxygen from the oxide semiconductor 230, which can result in the formation of an excessive amount of oxygen vacancies. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1) because the hydrogen concentration in the oxide semiconductor 230 can be reduced.

[0290] For the conductor 242a1 and the conductor 242b1, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0291] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse into the conductor 242a1 or the conductor 242b1. In particular, when a nitride containing tantalum is used for the conductor 242a1 and the conductor 242b1, hydrogen contained in the oxide semiconductor 230 or the like is likely to diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a1 or the conductor 242b1.

[0292] Furthermore, the conductors 242a2 and 242b2 preferably have higher conductivity than the conductors 242a1 and 242b1. For example, the film thickness of the conductors 242a2 and 242b2 is preferably greater than the film thickness of the conductors 242a1 and 242b1. Conductive materials containing, for example, tungsten, copper, or aluminum as a main component can be used for the conductors 242a2 and 242b2. The above structure can reduce the resistance of the conductors 242a2 and 242b2. This can increase the on-current of the transistor 200 and improve the operating speed of the semiconductor device according to this embodiment.

[0293] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0294] With the above structure, the top surface of the oxide semiconductor 230 is exposed in the region between the conductor 242a1 and the conductor 242b1, and the insulator 250 is in contact with this region. Here, as shown in FIG. 6B , the top surface of the oxide semiconductor 230 in this region may be lower than the other regions. That is, in the oxide semiconductor 230, the top surface of the region between the conductor 242a1 and the conductor 242b1 may be lower than the top surface of the region overlapping with the conductor 242a1 or the conductor 242b1. In this case, the film thickness of the oxide semiconductor 230 in contact with the top surface of the insulator 225 may be thinner than the film thickness of the oxide semiconductor 230 in contact with the side surface of the insulator 225. Furthermore, the portion of the oxide semiconductor 230 in contact with the top surface of the insulator 225, or a portion thereof, may be removed, and a portion of the insulator 225 may be in contact with the insulator 250.

[0295] To prevent a decrease in the conductivity of the conductor 242a and the conductor 242b, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide semiconductor 230. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide semiconductor 230. Furthermore, a decrease in the conductivity of the conductor 242a and the conductor 242b can be prevented.

[0296] 1B and 1D , the insulator 255 is disposed in an opening 201 formed in the insulator 280 or the like, and is in contact with the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222. The insulator 255 is also in contact with part of the side surface of the conductor 242a1 and part of the side surface of the conductor 242b1. In other words, the opening can be said to be formed in the insulator 255 so as to expose the island-shaped oxide semiconductor 230 in the opening 201. In addition, the insulator 250 is in contact with the oxide semiconductor 230, the insulator 224, and the insulator 222 in the region where the opening is formed in the insulator 255. Note that in FIG. 1B , the insulator 255 has an opening only near the oxide semiconductor 230, but the present invention is not limited to this. The insulator 255 only needs to have an opening in at least a region sandwiched between the conductor 242a1 and the conductor 242b1 of the oxide semiconductor 230. Therefore, for example, the insulator 255 may have almost no region in contact with the insulator 222 and may be formed in a sidewall shape in the opening formed in the insulator 280.

[0297] The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Because the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 be an inorganic insulator that is resistant to oxidation. Furthermore, because the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 255 be an inorganic insulator that is resistant to oxidation of the conductor 242a2 and the conductor 242b2. Therefore, it is preferable that the insulator 255 be made of an insulating material that can be used for the insulator 250d, which has oxygen barrier properties. For example, silicon nitride can be used as the insulator 255.

[0298] By using such an insulator 255, the conductors 242a2 and 242b2 are not excessively oxidized even if heat treatment is performed in an oxygen-containing atmosphere after dividing the conductors 242a1 and 242b1 and before forming the insulator 250. For example, the thickness of the oxide film on the side surfaces of the conductors 242a2 and 242b2 near the conductor 260 can be set to 0.5 nm or more and 5 nm or less, preferably 0.5 nm or more and 3 nm or less, and more preferably 0.5 nm or more and 2 nm or less.

[0299] The insulator 255 is preferably thicker than any one of the insulators 250a to 250d. The thickness of the insulator 255 is preferably 1 nm to 20 nm, more preferably 1 nm to 15 nm, and even more preferably 3 nm to 10 nm; for example, the thickness can be approximately 5 nm. By setting the insulator 255 to the above thickness, the distance between the conductor 260 and the conductor 242a or 242b can be increased, and parasitic capacitance can be reduced. Note that the insulator 255 only needs to have a region with the above thickness in at least a portion. Furthermore, since the insulator 255 is provided in the opening formed in the insulator 280, it is preferable to form the insulator 255 by an ALD method or the like, which has good coverage.

[0300] Furthermore, the insulator 255 may have a stacked structure of two or more layers using the inorganic insulator that is resistant to oxidation. When the insulator 255 has a stacked structure of two or more layers, at least one layer must be made of the inorganic insulator that is resistant to oxidation. For example, the insulator 255 may have a two-layer structure of a silicon nitride film and a silicon oxide film on the silicon nitride film.

[0301] Furthermore, the insulator 255 functions as part of a mask when dividing the transistor 200 into the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 2A , in a cross-sectional view of the transistor 200, the side edges of the insulator 255 preferably coincide or substantially coincide with the side edges of the conductor 242a1 and the conductor 242b1.

[0302] Here, the portion of the conductor 242a1 on whose upper surface the insulator 255 is formed protrudes more toward the conductor 260 than the conductor 242a2. Similarly, the portion of the conductor 242b1 on whose upper surface the insulator 255 is formed protrudes more toward the conductor 260 than the conductor 242b2. As shown in FIG. 2A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance D2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance D1 between the conductor 242a2 and the conductor 242b2.

[0303] The distance D2 between the conductor 242a1 and the conductor 242b1 is preferably small because it affects the channel length of the transistor 200. For example, the distance D2 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more. For example, the distance D2 is more preferably approximately 2 nm or more and 20 nm or less. This configuration makes it possible to further shorten the distance between the source and drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. In this way, miniaturization of the semiconductor device can provide a semiconductor device with improved operating speed.

[0304] 2A , the opposing side surfaces of the conductor 242a1 and the conductor 242b1 are substantially perpendicular to the top surface of the oxide semiconductor 230, but the present invention is not limited to this. For example, as shown in FIG. 7A , the opposing side surfaces of the conductor 242a1 and the conductor 242b1 may have a tapered shape. With such a shape, the distance between the conductor 260 and the oxide semiconductor 230 is reduced near the side ends of the conductor 242a1 and the conductor 242b1, and therefore a gate electric field can be effectively applied to the oxide semiconductor 230.

[0305] 7B, the opposing side surfaces of the conductors 242a1 and 242b1 may be tapered, and the opposing side surfaces of the conductors 242a2 and 242b2 may also be tapered. Also, as shown in FIG. 7C, the taper angles of the conductors 242a1 and 242b1 may be more acute than the taper angles of the conductors 242a2 and 242b2.

[0306] Although the above example shows a two-layer stacked structure of the conductors 242a and 242b, the present invention is not limited to this. The conductors 242a and 242b can also be a single-layer structure or a stacked structure of three or more layers. For example, as shown in FIG. 6C , the conductors 242a and 242b can be a single-layer structure. In this case, the conductors 242a and 242b can be made of a conductive material that can be used for the conductors 242a1 and 242b1. In this case, as shown in FIG. 6C , the insulator 255 can be omitted, and the insulators 280 and 275 can be in contact with the insulator 250.

[0307] 1B and 1D , the conductor 260 is disposed in the opening 201 formed in the insulator 280 and the insulator 275. The conductor 260 is disposed in the opening 201 so as to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. Furthermore, as shown in FIG. 2A , part of the conductor 260 overlaps with part of the conductor 242a1 and part of the conductor 242b1 with the insulator 255 interposed therebetween. Furthermore, the top surface of the conductor 260 is disposed so as to be flush or substantially flush with the top of the insulator 255, the top of the insulator 250, and the top surface of the insulator 280.

[0308] In the opening 201 in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening 201 may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may have a tapered shape. By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0309] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 1A and 1B. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0310] Part of the conductor 260 is folded in half with the insulator 225 sandwiched therebetween. As a result, as shown in FIG. 2B , in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are arranged to face each other with the insulator 250 sandwiched therebetween at the upper part of the oxide semiconductor 230, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224. That is, the upper part of the oxide semiconductor 230, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224 each function as a channel formation region. Therefore, the channel width of the transistor 200 is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 than when the insulator 225 is not provided.

[0311] In Figure 1D and other figures, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0312] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0313] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0314] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0315] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill the opening 201 formed in the insulator 280 or the like. Here, the side surface of the insulator 280 in the opening 201 coincides with or substantially coincides with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Therefore, the conductor 260 can be arranged to overlap the region between the conductor 242a2 and the conductor 242b2 without alignment.

[0316] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0317] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0318] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0319] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0320] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0321] Conductor 240a and conductor 240b are formed in openings of insulators 275, 280, 282, and 283, respectively. The lower surface of conductor 240a contacts the upper surface of conductor 242a, and the lower surface of conductor 240b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.

[0322] The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may also have a layered structure in which a first conductor is provided in contact with the side surface of the insulator 241 and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor. Here, the first conductor corresponds to the conductor 240a1 shown in FIG. 8A, and the second conductor corresponds to the conductor 240a2 shown in FIG. 8A.

[0323] Furthermore, when the conductor 240 has a layered structure, the first conductor disposed near the insulators 283, 282, 280, and 275 is preferably made of a conductive material that has a function of suppressing permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulator 283 can be prevented from entering the oxide semiconductor 230 through the conductors 240a and 240b.

[0324] The insulators 241a and 241b are formed in contact with the inner walls of the openings of the insulators 275, 280, 282, and 283, respectively. The inner side surface of the insulator 241a contacts the conductor 240a, and the inner side surface of the insulator 241b contacts the conductor 240b.

[0325] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Providing the insulator 241 can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide semiconductor 230 through the conductor 240a and the conductor 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0326] When the insulator 241 has a layered structure as shown in Figure 1D, it is preferable that the first insulator in contact with the inner wall of the opening, such as insulator 280, and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0327] For example, the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD. This configuration can suppress oxidation of the conductor 240 and further reduce hydrogen contamination of the conductor 240.

[0328] Although the above describes a configuration in which the insulator 241 has a two-layer stacked structure, the present invention is not limited to this. For example, the insulator 241 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, although the above describes a configuration in which the conductor 240 has a two-layer stacked structure, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers.

[0329] 8A and other figures show a configuration in which the conductor 240a is mainly in contact with the upper surface of the conductor 242a2, but the present invention is not limited to this. The conductor 240a may also cover the side surfaces of the conductor 242a2, the conductor 242a1, the oxide semiconductor 230, and the insulator 224. This configuration can increase the contact area between the conductor 240a and the conductor 242a. While the above description is directed to the conductor 240a, the same applies to the conductor 240b.

[0330] As described above, by increasing the contact area between the conductor 240 and the conductor 242, the contact resistance between the conductor 240 and the conductor 242 can be reduced. This allows the on-state current, frequency characteristics, and the like of the transistor 200 to be improved without significantly increasing the area occupied by the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0331] Note that, as shown in FIG. 1A , the shape of the opening through which the conductor 240 and the insulator 241 are provided is rectangular in plan view, but is not limited thereto. For example, the opening may be circular, approximately circular such as elliptical, polygonal such as rectangular, or polygonal such as rectangular with rounded corners in plan view. As shown in FIG. 1C , the opening is formed to overlap the oxide semiconductor 230 and the insulator 225. However, this is not limiting and the opening may be formed to overlap at least the conductor 242 a or the conductor 242 b. For example, as shown in FIG. 8B , a part of the opening (which can also be referred to as a part of the conductor 240) can overlap the insulator 225, and another part of the opening (which can also be referred to as the other part of the conductor 240) can be configured not to overlap the insulator 225. By configuring the conductor 240 so that a part of the conductor 240 overlaps the insulator 225, the margin for arranging the conductor 240 can be increased. Also, for example, as shown in FIG. 8C, the opening and the conductor 240 can be provided in an area that does not overlap with the insulator 225.

[0332] 1D , 8B , and 8C , the conductor 240a and the conductor 240b are arranged symmetrically with respect to the conductor 260, but the present invention is not limited to this. For example, as shown in FIG. 9A , in a cross-sectional view in the channel length direction, the conductor 240a may be arranged so that part of the conductor 240a overlaps with the insulator 225 and the conductor 240b does not overlap with the oxide semiconductor 230. Further, as shown in FIG. 9B , in a cross-sectional view in the channel length direction, the conductor 240a may be arranged so that the entire or almost the entire conductor 240a overlaps with the insulator 225 and the conductor 240b does not overlap with the oxide semiconductor 230.

[0333] 12A to 12D , the semiconductor device of this embodiment may have a structure in which a conductor 205 is provided under an insulator 221. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulators 222, 221, 224, and 225 each have a region that functions as a second gate insulator of the transistor 200. Here, FIGS. 12A to 12D correspond to FIGS. 1A to 1D , and therefore the above description can be referred to for detailed configurations.

[0334] In the transistor 200, the conductor 205 is arranged to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided to be embedded in an opening formed in the insulator 216. Furthermore, the conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 12A and 12B . With such a structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0335] 12B and 12D, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 coincides with or approximately coincides with the height of the upper surface of the insulator 216.

[0336] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0337] By using a conductive material that can reduce hydrogen diffusion for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 via the insulator 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0338] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0339] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. Furthermore, when the transistor 200 is an n-channel transistor, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0340] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore, diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0341] Although the above describes a layered structure of conductor 205a and conductor 205b, the present invention is not limited to this, and conductor 205 may have a single-layer structure or a layered structure of three or more layers. For example, when conductor 205 has a three-layer layered structure, the layered structure of conductor 205a and conductor 205b may further include a conductor made of the same material as conductor 205a provided on conductor 205b. In this case, the conductor may be formed so that the top surface of conductor 205b is lower than the top of conductor 205a, and the conductor fills the recess formed by conductor 205a and conductor 205b.

[0342] 1A to 1D , the insulator 224 is provided only in a region overlapping with the oxide semiconductor 230, but the present invention is not limited to this. For example, as shown in FIGS. 13A to 13D , the insulator 224 may be provided not only in a region overlapping with the oxide semiconductor 230 but also outside the opening 201. Here, FIGS. 13A to 13D correspond to FIGS. 1A to 1D , respectively, and therefore the above description can be referred to for detailed configurations.

[0343] In the semiconductor device of one embodiment of the present invention, the shape of the insulator 224 in a plan view may be made to match or substantially match the shape of the oxide semiconductor 230 in a plan view at least in the opening 201. In other words, the opening 201 preferably reaches the oxide semiconductor 230 and the insulator 222 in the vicinity of the oxide semiconductor 230. In this case, the insulator 224 is provided between the insulator 222 and the insulator 275, as shown in FIGS.

[0344] 1A to 1D , the transistor 200 includes one insulator 225, but the present invention is not limited thereto and may include a plurality of insulators 225. For example, as shown in FIGS. 14A to 14D , the insulators 225_1 and 225_2 may be arranged in the A1-A2 direction, and the oxide semiconductor 230 may be provided to cover the insulators 225_1 and 225_2. Here, FIGS. 14A to 14D correspond to FIGS. 1A to 1D , respectively, and therefore the above description can be referred to for detailed configurations.

[0345] 14B , the structure including the insulators 225_1 and 225_2 can increase the area where the oxide semiconductor 230 and the conductor 260 face each other across the insulator 250, compared to the case where only one insulator 225 is provided. This can increase the channel width per unit area. Furthermore, as shown in FIG. 14C , the structure including the insulators 225_1 and 225_2 can increase the contact area between the oxide semiconductor 230 and the conductor 242a2 (conductor 242b2) compared to the case where only one insulator 225 is provided. This can reduce the contact resistance between the oxide semiconductor 230 and the conductor 242a2 (conductor 242b2).

[0346] In the above description, the insulators 225 (insulators 225_1 and 225_2) have a linear shape extending in the A5-A6 direction, but the present invention is not limited to this. For example, the planar shape of the insulator 225 may be a circumferential shape (which may also be called a frame shape, annular shape, doughnut shape, or closed curve shape) in which both ends coincide or approximately coincide. For example, the insulators 225_1 and 225_2 shown in FIG. 14A may have a shape in which both ends are connected.

[0347] 1A to 1D, respectively. The semiconductor device shown in Figures 15A to 15D differs from the semiconductor device shown in Figures 1A to 1D in that insulators 271a and 271b are provided, insulator 255 is provided in a sidewall shape on the side wall of opening 201, and insulator 224 is not provided. Note that in Figure 15C, to make the structure of insulator 271a easier to see, dashed dotted line A3-A4 is drawn at a position that does not overlap with conductor 240a, unlike in Figure 1C.

[0348] The insulator 271a is provided in contact with the upper surface of the conductor 242a2 and coincides or substantially coincides with the conductor 242a2 in a planar view. Similarly, the insulator 271b is provided in contact with the upper surface of the conductor 242b2 and coincides or substantially coincides with the conductor 242b2 in a planar view. The upper surfaces of the insulators 271a and 271b contact the insulator 275. An opening is also formed in the insulator 271a, and the side surface of the insulator 271a contacts the insulator 241a through the opening. Similarly, an opening is also formed in the insulator 271b, and the side surface of the insulator 271b contacts the insulator 241b through the opening. Furthermore, in a planar view, the side end of the insulator 271a on the opening 201 side and the side end of the insulator 271b on the opening 201 side contact the insulator 255.

[0349] 15A to 15D , the insulators 271a and 271b can be made of an insulating material that can be used for the insulators 275 and 250, and it is preferable to use an insulating material that can be used for the insulator 275. For example, silicon nitride can be used for the insulators 271a and 271b. Note that in the example shown in FIGS. 15A to 15D , the insulators 271a and 271b may have a stacked structure of two or more layers. For example, when the insulators 271a and 271b have a two-layer stacked structure, silicon nitride can be used for the lower layer and silicon oxide can be used for the upper layer.

[0350] 15A to 15D, it is preferable to deposit insulating films to be the insulators 271a and 271b successively after depositing conductive films to be the conductors 242a2 and 242b2. With this structure, the conductors 242a2 and 242b2 can be protected by the insulators 271a and 271b during the manufacturing process of the semiconductor device. Therefore, the yield of the semiconductor device can be improved.

[0351] 15A to 15D, the insulator 255 is formed in a sidewall shape in contact with the side wall of the opening 201. Therefore, as shown in FIGS. 15B and 15C, the side surface of the insulator 255 contacts the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. Furthermore, the bottom surface of the insulator 255 contacts the top surface of the insulator 222, the top surface of the conductor 242a1, and the top surface of the conductor 242b1. With this configuration, the film thickness of the insulator 255 is equal to or approximately equal to the length of the protruding portion of the conductor 242a1 and the length of the protruding portion of the conductor 242b1.

[0352] The insulator 255 having the above-described configuration can be formed in a self-aligned manner by forming an insulating film that will become the insulator 255 after the opening 201 is formed and then anisotropically etching the insulating film. This allows the insulator 255 to be formed inside the opening 201 without forming a separate mask, thereby improving the productivity of the semiconductor device.

[0353] 15A to 15D , the insulator 224 is not provided, and therefore the insulator 225 and the oxide semiconductor 230 are in contact with the top surface of the insulator 222. However, this is not limiting, and the insulator 224 can also be provided between the insulator 225 and the oxide semiconductor 230 and the insulator 222.

[0354] 16A, the transistor 200, the capacitor 460, and the transistor 310 formed on a silicon substrate can function as a 2T (transistor) 1C (capacitor) memory cell. As shown in FIG. 16A, a layer including the transistor 200 and the capacitor 460 can be provided over a layer including the transistor 310. FIG. 17A shows a cross-sectional view of the transistor 200 in the channel width direction, FIG. 17B shows a cross-sectional view of the capacitor 460 in the channel width direction, and FIG. 17C shows a cross-sectional view of the transistor 310 in the channel width direction.

[0355] The transistor 310 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0356] As shown in FIG. 17C , the transistor 310 has a semiconductor region 313 (a part of the substrate 311) where a channel is formed, which has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0357] Note that the transistor 310 illustrated in FIG. 16A is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0358] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0359] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0360] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0361] The transistor 200 and the capacitor 460 are provided over the insulator 326. Here, the transistor 200 shown in FIG. 1D is used as the transistor 200. The structures of the transistor 200 and the layer in which the transistor 200 is formed are the same as those described above and are indicated by the same hatching patterns and symbols. For detailed structures, refer to the above description. Note that an insulator 285 is formed over the insulator 283, and a conductor 413 electrically connected to the conductor 240a is formed over the insulator 285. The insulator 285 can be formed using an insulating material that can be used for the insulator 216. The conductor 413 can be formed using a conductive material that can be used for the conductor 242.

[0362] The capacitor 460 includes an insulator 425 over the insulator 224, an oxide semiconductor 230 covering the insulator 425, a conductor 242b1 over the oxide semiconductor 230, an insulator 455 over the conductor 242b1, an insulator 454 over the insulator 455, and a conductor 456 over the insulator 454. The insulators 455, 454, and 456 are provided in openings 202 formed in the insulators 280, 275, and the like. As shown in FIGS. 16A , 17A , and 17B , the oxide semiconductor 230 and the conductor 242b1 are also used in the transistor 200. The opening 202 can be formed in the same process as the opening 201. The insulator 425 has a similar structure to the insulator 225 and can be formed in the same process. The insulator 455 has a similar structure to the insulator 255 and can be formed in the same process. The insulator 454 has a structure similar to that of the insulator 250 and can be formed in the same process. The conductor 456 has a structure similar to that of the conductor 260 and can be formed in the same process. Note that the conductor 260 can be provided in an extended state as described above and can function as a wiring. The conductor 456 can also be provided in an extended state and can function as a wiring.

[0363] Here, the capacitor 460 includes a conductor 242b1 functioning as a first electrode, a conductor 456 functioning as a second electrode, and an insulator 455 and an insulator 454 functioning as dielectrics. That is, the capacitor 460 includes a metal-insulator-metal (MIM) capacitor.

[0364] The capacitor 460 has a structure similar to that of the transistor 200 and can be formed in the same layer as the transistor 200 in parallel. However, the capacitor 460 differs from the transistor 200 in that the conductor 242b1 and the insulator 455 overlap with the conductor 456 and the insulator 454. For example, as shown in FIG. 17A , an opening is formed in part of the insulator 255 in the opening 201, and the opening overlaps with part of the oxide semiconductor 230. In addition, in a region where the opening in the insulator 255 overlaps with the oxide semiconductor 230, the conductor 242b1 is not formed on the oxide semiconductor 230. In contrast, as shown in FIG. 17B , no opening is formed in the insulator 455 in the opening 202, and the oxide semiconductor 230 is covered with the insulator 455. In addition, in the opening 202, the conductor 242b1 is in contact with the top surface of the oxide semiconductor 230, and the insulator 455 is in contact with the top surface of the conductor 242b1.

[0365] 17B , the insulator 425 of the capacitor 460 has a structure with a high aspect ratio, similar to the insulator 225. Therefore, the area where the conductor 242b1, the insulator 455, the insulator 454, and the conductor 456, which are provided along the top surface and side surface of the insulator 425, face each other can be increased. This allows the capacitance to be increased without significantly increasing the area occupied by the capacitor 460.

[0366] The conductor 458 is preferably provided in openings formed in the insulators 215, 216, 221, 222, and 224. The conductor 458 can have a structure similar to that of the conductor 240, for example. The top surface of the conductor 458 is in contact with the bottom surface of the oxide semiconductor 230 and can be electrically connected to the conductor 330. Note that although only one conductor 458 is shown in FIG. 16A , this is not a limitation, and two or more conductors may be used to electrically connect the conductor 242b1 and the conductor 330. Furthermore, a structure in which the conductor 242b1 and part of the oxide semiconductor 230 are embedded in the openings formed in the insulators 215, 216, 221, 222, and 224 may be used. The top surface of the conductor 458 does not necessarily have to be in contact with the bottom surface of the oxide semiconductor 230. For example, the upper surface of the conductor 458 can be exposed from the upper surface of the insulator 285, and a conductor similar to the conductor 240 can be provided in contact with the upper surface of the conductor 242b2, and the conductor and the conductor 458 can be electrically connected via wiring.

[0367] With the above structure, one of the source and drain of the transistor 200, one electrode of the capacitor 460, and the gate of the transistor 310 are electrically connected to form a 2T1C memory cell. Note that a 1T1C memory cell can also be formed by using a structure without the transistor 310. Furthermore, a 2T0C memory cell can also be formed by using a structure without the capacitor 460.

[0368] Here, the transistor 310 is preferably provided so as to overlap with at least one of the transistor 200 and the capacitor 460. For example, the transistor 310 may overlap with the transistor 200. With such a structure, the area occupied by the memory cell can be reduced.

[0369] 16A illustrates a structure in which the transistor 200 includes the insulator 225 and the capacitor 460 includes the insulator 425, but the present invention is not limited to this. For example, as illustrated in FIG. 16B , a structure in which the insulator 250, the conductor 260, the insulator 455, the insulator 454, and the conductor 456 are formed over the insulator 225 and the oxide semiconductor 230 without providing the insulator 425 may be used. That is, the transistor 200 and the capacitor 460 may share the insulator 225. This eliminates the need to separate the insulator 225 between the transistor 200 and the capacitor 460, thereby reducing the area occupied by the transistor 200 and the capacitor 460.

[0370] 16A illustrates a structure in which the transistor 310 is formed on a silicon substrate, but the present invention is not limited to this. For example, as shown in FIG. 18A, the above-described transistor 200 may be replaced by two transistors (hereinafter referred to as transistors 200a and 200b) having the same structure. Here, the transistors 200a and 200b are formed in the same layer and arranged so that their channel length directions intersect with each other. Note that the transistors 200a and 200b have the same structure as the transistor 200, and therefore the components are indicated by the same hatched patterns and symbols. For detailed structure, please refer to the above description.

[0371] 18A , the capacitor 400 is provided over the insulator 285. The capacitor 400 includes a conductor 410 over the insulator 285, an insulator 430 over the conductor 410, and a conductor 420 over the insulator 430. The conductor 240b, the insulator 241b, the conductor 240c, and the insulator 241c are provided in contact with the bottom surface of the conductor 410. The conductor 240c and the insulator 241c are formed so as to be embedded in the openings of the insulators 282, 283, and 285, and have the same structure as the conductor 240b and the insulator 241c. The bottom surface of the conductor 240c is in contact with the top surface of the conductor 260 of the transistor 200b. With this structure, one of the source and drain of the transistor 200a, one electrode of the capacitor 400, and the gate of the transistor 200b are electrically connected to each other.

[0372] The capacitor 400 includes a conductor 410 functioning as a first electrode, a conductor 420 functioning as a second electrode, and an insulator 430 functioning as a dielectric. That is, the capacitor 400 forms an MIM capacitor.

[0373] The conductor 410 and the conductor 420 may be made of a conductive material that can be used for the conductor 260. For example, tungsten can be used for the conductor 410 and the conductor 420. Here, by using a structure in which the conductor 420 covers the conductor 410, the side surface of the conductor 410 can function as the capacitor 400. This allows the capacitance of the capacitor 400 to be increased. The conductor 413 can be formed simultaneously with the conductor 410.

[0374] Although the conductors 410, 413, and 420 each have a single-layer structure, they are not limited to this structure and may have a stacked structure of two or more layers. For example, a stacked structure of a conductor having barrier properties and a conductor with high conductivity may be used. For example, a stacked structure of titanium nitride and tungsten on titanium nitride may be used.

[0375] The insulator 430 of the capacitor 400 is preferably made of a high-dielectric-constant (high-k) material. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials makes it possible to thicken the insulator 430 to suppress leakage current and ensure sufficient capacitance of the capacitor 400. Furthermore, since the insulator 430 is formed to cover the conductor 410, it is preferable to form the insulator 430 using a film formation method with good coverage, such as an ALD method or a CVD method.

[0376] The insulator 430 may also have a layered structure. It is preferable to use a layered structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-dielectric-constant (high-k) material. Materials with a high dielectric strength (materials with a low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. The insulator 430 may have a layered structure of aluminum oxide, a high-dielectric-constant (high-k) material, and silicon oxide with a high dielectric strength on the aluminum oxide.

[0377] For example, the insulator 430 can be an insulator stacked in this order: zirconium oxide, aluminum oxide, and zirconium oxide. For example, the insulator 430 can be an insulator stacked in this order: zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. For example, the insulator 430 can be an insulator stacked in this order: hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By stacking insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown of the capacitor 400 can be suppressed.

[0378] Furthermore, a material that can have ferroelectricity may be used as the insulator 430. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. Ferroelectric materials include hafnium ... (here, element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0379] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0380] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0381] Although the above description has been given with reference to metal oxides and metal nitrides, the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0382] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulator 430 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0383] 18A, the shape of the capacitor 400 is a planar type, but the shape of the capacitor 400 in the memory device described in this embodiment is not limited to this. For example, the shape of the capacitor 400 may be a cylinder or a pillar.

[0384] An insulator 487 is provided to cover the capacitor 400, and an insulator 488 is provided to cover the insulator 487. The insulator 487 is preferably an insulator that has a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulator 487. The insulator 488 is preferably an insulator that has a function of suppressing diffusion of hydrogen. For example, silicon nitride, which has a higher hydrogen barrier property, may be used for the insulator 488.

[0385] 18A shows a structure in which the transistors 200a and 200b are provided in the same layer, but the present invention is not limited to this. For example, as shown in FIG. 18B, a structure in which a layer 401a including the transistor 200a is stacked on a layer 401b including the transistor 200b may be used. Note that the layers 401a and 401b have the same structure as the layers from the insulator 215 to the insulator 285 shown in FIG. 18A.

[0386] 18B , the conductor 240c and the insulator 241c may be formed in openings provided in the insulators 282 to 285 of the layer 401b and the insulators 215 to 285 of the layer 401a. With this structure, the conductor 410 of the capacitor 400 and the conductor 260 of the transistor 200b can be electrically connected. Note that the conductor 410 and the conductor 260 of the transistor 200b do not need to be connected only by the conductor 240c. Two or more conductors may be used to electrically connect the conductor 410 and the conductor 260 of the transistor 200b.

[0387] Here, the transistor 200b is preferably provided so as to overlap with at least one of the transistor 200a and the capacitor 400. For example, the oxide semiconductor 230 of the transistor 200b is preferably provided so as to overlap with at least one of the oxide semiconductor 230 of the transistor 200a and the conductor 410 of the capacitor 400. With such a structure, the area occupied by the memory cell can be reduced.

[0388] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0389] <<Substrate>> Examples of substrates for forming transistors include insulating substrates, semiconductor substrates, and conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0390] <<Insulators>> Examples of insulators that can be used for at least one of the insulators 215, 216, 221, 222, 224, 225, 241, 250, 255, 271a, 271b, 275, 280, 282, 283, 285, 315, 320, 322, 324, 326, 425, 430, 454, 455, 487, and 488 include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0391] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select a material depending on the function of the insulator.

[0392] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0393] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0394] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0395] The insulator functioning as the gate insulator preferably has a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0396] <<Conductor>> As a conductor that can be used for at least one of the conductors 205, 240, 242, 260, conductor 316, conductor 328, conductor 330, conductor 410, conductor 413, conductor 420, conductor 456, and conductor 458, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. Examples of conductors include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0397] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0398] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0399] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0400] 1A to 1D , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[0401] A in each figure shows a plan view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Note that some elements are omitted from the plan view A in each figure for clarity.

[0402] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0403] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used for film formation using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used for forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0404] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. They can also be further classified into metal CVD (MCVD) and MOCVD, depending on the source gas used.

[0405] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0406] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0407] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0408] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0409] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0410] First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see FIGS. 19A to 19D ). As described above, the insulator 215 can be formed using an insulator similar to one or more of the insulators 282 and 283. The insulator 215 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. Sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0411] Next, the insulator 216 is deposited over the insulator 215. The insulator 216 is preferably deposited by a sputtering method. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0412] The insulators 215 and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen content and reduces the amount of hydrogen mixed into the films between film formation steps.

[0413] 12A to 12D can be formed by forming an opening in the insulator 216 that reaches the insulator 215 and forming the conductor 205 in the opening. The conductor 205 can be formed by depositing a conductive film that can be used for the conductor 205 so as to fill the opening and removing part of the conductive film by CMP treatment.

[0414] Next, an insulator 221 is formed on the insulator 216 (see FIGS. 19A to 19D).

[0415] The insulator 221 may be any of the above insulators that have barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method.

[0416] Next, an insulator 222 is formed on the insulator 221 (see FIGS. 19A to 19D).

[0417] The insulator 222 is preferably an insulator containing one or both of an oxide of aluminum and hafnium. As the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the transistor through the insulator 222, and thus oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0418] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by a thermal ALD method.

[0419] In this embodiment, silicon nitride is deposited as the insulator 221 by a PEALD method, and hafnium oxide is deposited as the insulator 222 by a thermal ALD method. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 221 in this manner, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has a function of capturing or fixing hydrogen, for the insulator 222, hydrogen contained in the oxide semiconductor 230 can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0420] Next, an insulating film 224f is formed on the insulator 222 (see FIGS. 19A to 19D). The insulating film 224f is an insulating film that will become the insulator 224 in a later process. Therefore, any of the insulating materials that can be used for the insulator 224 described above may be used. The insulating film 224f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0421] In this embodiment, the insulating film 224f is a stacked film of a silicon oxide film and an aluminum oxide film on the silicon oxide film. For example, the silicon oxide film can be formed by sputtering, and the aluminum oxide film can be formed by thermal ALD. With this configuration, the insulator 224 can have a stacked structure of an insulator 224a containing silicon oxide and an insulator 224b containing aluminum oxide, as shown in FIG. 5B .

[0422] Next, an insulating film is formed over the insulating film 224f and etched to form the insulator 225 (see FIGS. 19A to 19D). The insulator 225 may be formed using any of the insulating materials that emit little hydrogen and can be used for the insulator 225. The insulating film that becomes the insulator 225 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0423] In this embodiment, the insulating film is a stacked film of a silicon nitride film and an aluminum oxide film on the silicon nitride film. For example, the silicon nitride film can be formed by sputtering, and the aluminum oxide film can be formed by thermal ALD. This structure allows the insulator 225 to have a stacked structure of an insulator 225a containing silicon nitride and an insulator 225b containing aluminum oxide, as shown in FIG. 5B . This stacked structure allows the aluminum oxide layer to function as a hard mask in the etching process of the silicon nitride layer of the insulator 225. This allows the side surface of the insulator 225 to be perpendicular or approximately perpendicular to the top surface of the insulating film 224f. This structure enables a reduction in area and high density when providing multiple transistors.

[0424] Furthermore, without being limited to the above, a highly insulating metal oxide material may be used as the insulating film that becomes the insulator 225. For example, gallium oxide can be deposited as the insulating film by sputtering or ALD. Furthermore, for example, In—Ga—Zn oxide, in which the proportion of gallium is higher than the proportion of indium, can be deposited as the insulating film by sputtering or ALD. For example, In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2 can be deposited as the insulating film.

[0425] When forming a metal oxide film containing multiple metal elements, such as In—Ga—Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not necessarily match.

[0426] The insulator 225 may be processed into an island shape by lithography. For this processing, a dry etching method or a wet etching method can be used. The dry etching method is suitable for fine processing.

[0427] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, or insulator to be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0428] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0429] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. For example, in the above example, an aluminum oxide film on the silicon nitride film functions as the hard mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. The silicon nitride film may be etched after removing the resist mask, or may be etched while the resist mask is left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the silicon nitride film. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0430] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as masks can improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0431] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing hydrocarbon gas or hydrogen gas but not containing halogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0432] A capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. A capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. The DF-CCP etching apparatus may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus. The etching apparatus can be appropriately configured according to the object to be etched. In the above-mentioned dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thereby enabling highly anisotropic etching.

[0433] Furthermore, by using a material that is difficult to etch, such as aluminum oxide, for the upper layer of the insulating film 224f, the insulating film 224f can function as an etching stopper when the insulator 225 is etched.

[0434] Note that although the above description shows a structure in which one insulator 225 is provided in the transistor 200, the present invention is not limited to this. A structure in which two or more insulators 225 are provided separately can also be used. For example, by providing the insulator 225_1 and the insulator 225_2, the transistor 200 having the structure shown in FIGS. 14A to 14D can be formed.

[0435] Next, an oxide semiconductor film 230f that will become the oxide semiconductor 230 is formed to cover the insulator 225 (see FIGS. 20A to 20D ). The oxide semiconductor film 230f is a metal oxide film that will become the oxide semiconductor 230 in a later step, and any of the above-described metal oxide films can be used. The oxide semiconductor film 230f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0436] Since the oxide semiconductor film 230f is formed along the insulator 225, it is preferable that the oxide semiconductor film 230f has good coverage. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method or the like, which has good coverage. Furthermore, since it is preferable that the oxide semiconductor 230 has a high aspect ratio, it is preferable that the oxide semiconductor film 230f have a thin film thickness. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method, which allows for adjustment of the film thickness to a thin film thickness. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed in contact with the top surface and side surface of the insulator 225.

[0437] Here, the oxide semiconductor film 230f is preferably formed by the same method as that used to form the oxide semiconductor film 30 described above.

[0438] For example, when the oxide semiconductor 230 has a three-layer structure including oxide semiconductors 230a to 230c as shown in FIG. 2B and other figures, films to be the oxide semiconductors 230a to 230c may be deposited by ALD, and a film to be the oxide semiconductor 230b may be deposited by sputtering. Specifically, the film to be the oxide semiconductor 230a can be deposited to have a composition of In:Zn=2:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230a. The film to be the oxide semiconductor 230b can be deposited using an oxide target having a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout. Alternatively, the film to be the oxide semiconductor 230c can be deposited to have a composition of In:Zn=2:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230c.

[0439] Note that the compositions of the oxide semiconductors 230a to 230c are not limited to the above. For example, the film to be the oxide semiconductor 230a can be formed to have a composition of In:Ga:Zn = 1:1:1 (atomic ratio) or a composition close to that. The film to be the oxide semiconductor 230b can be formed using an oxide target having a composition of In:Ga:Zn = 1:1:1.2 (atomic ratio) or a composition close to that. The film to be the oxide semiconductor 230c can be formed to have a composition of In:Ga:Zn = 1:1:1 (atomic ratio) or a composition close to that.

[0440] The three-layer structure of the oxide semiconductors 230a to 230c is not limited to the above structure. For example, the oxide semiconductors 230a to 230c may be formed by an ALD method. In this structure, the oxide semiconductors 230a to 230c can be successively formed using a single manufacturing apparatus without using a sputtering method, thereby reducing manufacturing costs. After the oxide semiconductors 230a, 230b, and 230c are formed, microwave treatment may be performed on each of them. The microwave treatment can reduce impurities such as hydrogen contained in the oxide semiconductor 230 and improve the crystallinity of the oxide semiconductor 230.

[0441] Although the oxide semiconductor film 230f has a three-layer structure in the above description, the present invention is not limited thereto and may have a single-layer, two-layer, or four or more-layer structure. For example, the oxide semiconductor film 230f may have a two-layer structure including a film that becomes the oxide semiconductor 230b and a film that becomes the oxide semiconductor 230c. In this case, the insulator 225 preferably uses the metal oxide having high insulating properties. This structure can reduce trap levels at and near the interface between the insulator 225 and the oxide semiconductor 230b. This structure can improve the reliability of the transistor 200.

[0442] Next, heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230f does not become polycrystallized. The heat treatment of the oxide semiconductor film 230f may be performed by the same method as the heat treatment of the oxide semiconductor 30 described above.

[0443] For example, the heat treatment can be carried out at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0444] By forming the oxide semiconductor 230 using the above method and then performing heat treatment, the oxide semiconductor 230 can be converted into an AG CAAC. As a result, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0445] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0446] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f and the like as much as possible. Note that highly purified gas can also be used in the heat treatment before and after this step.

[0447] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor film 230f, reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0448] Furthermore, by performing heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, and oxygen vacancies in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0449] Furthermore, by performing heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the oxide semiconductor film 230f diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentration in each oxide semiconductor film 230f decreases. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0450] In particular, the oxide semiconductor film 230f (later the oxide semiconductor 230) functions as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f in which the hydrogen concentration is reduced has high reliability, which is preferable.

[0451] Note that it is preferable to perform a treatment for increasing the crystallinity of the oxide semiconductor film 230f during or after the formation of the oxide semiconductor film 230f. Examples of the treatment for increasing the crystallinity of the oxide semiconductor film 230f include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0452] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor film 230f multiple times during the formation of the oxide semiconductor film 230f. For example, when the oxide semiconductor film 230f is formed by an ALD method, it is preferable to perform a microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity after each oxide semiconductor film 230f having a thickness within a predetermined range, which can improve productivity. Specifically, it is preferable to form a first oxide semiconductor film having a thickness of 1 nm to 10 nm as the oxide semiconductor film 230f, perform the first microwave plasma treatment, and then form a second oxide semiconductor film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the methods for forming the first oxide semiconductor film and the second oxide semiconductor film are not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor film by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed into the first oxide semiconductor film and the second oxide semiconductor film. This is particularly suitable when the elements contained in the layers constituting the formation surface inhibit crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Although a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is illustrated here, the present invention is not limited to this. The oxide semiconductor film 230f can be formed as a single layer or a stacked structure of three or more layers.

[0453] Furthermore, treatment for increasing the crystallinity of the oxide semiconductor film 230f may be performed after the oxide semiconductor film 230f is formed. Specifically, this treatment may be performed directly on the formed oxide semiconductor film 230f, or may be performed via another film, such as an insulating film, formed on the oxide semiconductor film 230f. For example, microwave plasma treatment may be performed after the oxide semiconductor film 230f is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like) may be formed after the oxide semiconductor film 230f is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor film 230f via the insulating film.

[0454] Note that the above-described treatment for increasing the crystallinity of the oxide semiconductor film 230f can also serve as treatment for removing impurities contained in the oxide semiconductor film 230f. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor film 230f can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor film 230f in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor film 230f can be reduced.

[0455] When the treatment for increasing the crystallinity of the oxide semiconductor film 230f is performed, the substrate temperature is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0456] By increasing the crystallinity of the oxide semiconductor film 230f, a highly reliable transistor can be realized.

[0457] Next, a conductive film 242_1f is formed over the oxide semiconductor film 230f, and a conductive film 242_2f is formed over the conductive film 242_1f (see FIGS. 20A to 20D ). The conductive film 242_1f is a conductive film that will become the conductors 242a1 and 242b1, and the conductive film 242_2f is a conductive film that will become the conductors 242a2 and 242b2. A conductive material that can be used for the conductors 242a1 and 242b1 may be used for the conductive film 242_1f, and a conductive material that can be used for the conductors 242a2 and 242b2 may be used for the conductive film 242_2f. Hereinafter, the conductive films 242_1f and 242_2f may be collectively referred to as conductive films 242f.

[0458] The conductive films 242_1f and 242_2f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, tantalum nitride may be formed as the conductive film 242_1f by a sputtering method. Furthermore, tungsten may be formed as the conductive film 242_2f by a sputtering method. By forming the conductive film 242f to cover the oxide semiconductor film 230f, the contact area between the oxide semiconductor film 230f and the conductors 242a and 242b can be increased without increasing the area occupied by the oxide semiconductor film 230f. This can improve the on-state current and frequency characteristics of the transistor 200.

[0459] Note that an insulating film to be the insulators 271a and 271b may be further formed over the conductive film 242_2f. For example, as the insulating film, a silicon nitride film may be formed by a sputtering method, and a silicon oxide film may be further formed thereover by a sputtering method. By providing such an insulating film, the transistor 200 shown in FIGS. 15A to 15D can be formed.

[0460] Although the above description shows a structure in which the oxide semiconductor film 230f is provided in contact with the insulator 225 and the insulating film 224f, the present invention is not limited to this. As shown in FIG. 29A , a structure in which a protective layer 227 is formed in contact with the insulator 225 and the insulating film 224f may also be used. The protective layer 227 may be formed using any of the above-described metal oxide materials. The thickness of the protective layer 227 is preferably thinner than that of the oxide semiconductor film 230f.

[0461] The protective layer 227 can be formed by a CVD method, an MBE method, a PLD method, or an ALD method. The ALD method, which has good coverage, is preferable because the protective layer 227 can be formed to cover the top surface and side surfaces of the insulator 225. The protective layer 227 can be formed using, for example, gallium oxide or zinc oxide by a thermal ALD method.

[0462] In this manner, the oxide semiconductor film 230f, the conductive film 242_1f, and the conductive film 242_2f are formed with the insulator 225 and the insulating film 224f covered with the protective layer 227 (see FIG. 29B ). Furthermore, the protective layer 227 is processed into an island shape together with the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242_1f, and the conductive film 242_2f in a process described later. With this configuration, the transistor 200 shown in FIG. 5A can be formed. Because the protective layer 227 is provided between the insulator 225 and the oxide semiconductor film 230f, even a layer below the oxide semiconductor film 230f (for example, the oxide semiconductor 230a shown in FIG. 5A ) can be subjected to AG CAAC.

[0463] Next, the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242_1f, and the conductive film 242_2f are processed into island shapes by lithography to form the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 (see FIGS. 21A to 21D ). At this time, the insulator 222 is exposed in a region that does not overlap with the conductor 242_1 and the conductor 242_2.

[0464] For the above processing, a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for fine processing. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. The insulating film 224f, the oxide semiconductor film 230f, the conductive film 242_1f, and the conductive film 242_2f may be processed under different conditions. When the above processing is performed, a hard mask may be provided over the conductive film 242_2f.

[0465] Here, the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 are preferably processed collectively into an island shape. In this case, the side edges of the conductor 242_1 and the conductor 242_2 preferably coincide with or substantially coincide with the side edges of the oxide semiconductor 230. Furthermore, the side edges of the insulator 224 preferably coincide with or substantially coincide with the side edges of the oxide semiconductor 230. Such a structure can reduce the number of steps required to manufacture a semiconductor device according to one embodiment of the present invention. Therefore, a highly productive method for manufacturing a semiconductor device can be provided.

[0466] By processing the insulator 224 into an island shape as described above, the bottom surface of the conductor 260 can be located below the bottom surface of the oxide semiconductor 230 in the transistor 200. This allows a sufficient electric field to be applied from the conductor 260 to the entire oxide semiconductor 230. Therefore, the electrical characteristics of the transistor 200 can be improved.

[0467] The side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 may be perpendicular or approximately perpendicular to the top surface of the insulator 222. With such a structure, a reduction in area and high density can be achieved when a plurality of transistors are provided.

[0468] However, the present invention is not limited to the above, and the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 may be tapered. The taper angle of the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 may be, for example, greater than or equal to 60° and less than 90°. Tapering the side surfaces in this manner improves coverage with the insulator 275 and the like in subsequent steps, and reduces defects such as voids.

[0469] 3B , a configuration without the insulator 224 is also possible. In this case, when the oxide semiconductor 230 is processed into an island shape, part of the upper surface of the insulator 222 may be removed. As a result, as shown in FIG. 3B , a region of the upper surface of the insulator 222 that overlaps with the oxide semiconductor 230 may become higher than a region of the upper surface of the insulator 222 that does not overlap with the oxide semiconductor 230.

[0470] Next, an insulator 275 is formed to cover the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2, and then an insulator 280 is formed over the insulator 275 (see FIGS. 22A to 22D ). The insulators 275 and 280 may be any of the above-described insulators.

[0471] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0472] As the insulator 280, it is preferable to form an insulator with a flat upper surface by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulator 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulator 280.

[0473] The insulators 275 and 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0474] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulator 275. Alternatively, it is preferable to form an aluminum oxide film by a sputtering method and then form a silicon nitride film thereon by a PEALD method as the insulator 275. By using the above structure for the insulator 275, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0475] In this manner, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275 having a function of suppressing oxygen diffusion. This can suppress direct diffusion of oxygen from the insulator 280 or the like to the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 in a later step.

[0476] The insulator 280 is preferably formed using silicon oxide by a sputtering method. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 and the like can be removed, and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be further reduced. The heat treatment can be performed under the above-described heat treatment conditions.

[0477] Next, the conductor 242_2, the insulator 275, and the insulator 280 are processed by lithography to form an opening 201 that reaches the conductor 242_1 and the insulator 222 (see FIGS. 23A to 23D ). Here, the conductor 242_2 is divided to form the conductor 242a2 and the conductor 242b2. The opening 201 is formed so that at least a portion of the opening 201 overlaps with the oxide semiconductor 230. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening 201 is D1, which corresponds to the distance D1 between the conductor 242a2 and the conductor 242b2. That is, the width D1 of the opening 201 is greater than the distance D2 between the conductor 242a1 and the conductor 242b1.

[0478] The lithography method can be any of the above-mentioned methods. In order to finely process the openings in the insulator 280, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0479] The above processing is preferably performed using a dry etching method. Dry etching is capable of anisotropic etching and is therefore suitable for forming openings 201 with a high aspect ratio. Note that the above description can be referred to for the conditions for the dry etching method and the dry etching apparatus.

[0480] 21A to 21D show the steps of forming the insulator 224. However, the insulating film 224f can also be processed to form the insulator 224 in the steps of FIGS. 23A to 23D . In this case, the insulating film 224f is further etched after the insulator 275 is etched. As a result, a region of the insulator 224 that does not overlap with the oxide semiconductor 230 in the opening 201 is removed, and an opening reaching the insulator 222 is formed. With this structure, the transistor 200 having the structure shown in FIGS. 13A to 13D can be formed.

[0481] Next, an insulating film 255A is formed to cover the insulator 280, the conductor 242_1, and the insulator 222 (see FIGS. 24A to 24D ). The insulating film 255A is an insulating film that will become the insulator 255 in a later process, and any of the above-described insulators can be used. The insulating film 255A can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0482] Since the insulating film 255A is formed along the opening 201, it is preferable that the insulating film 255A has good coverage. Therefore, it is preferable that the insulating film 255A be formed using an ALD method or the like that has good coverage. For example, it is preferable that the insulating film 255A be formed of silicon nitride using the PEALD method.

[0483] Next, the conductor 242_1 and the insulating film 255A are processed by lithography in the opening 201 to form an opening that reaches the oxide semiconductor 230 (see FIGS. 25A to 25D ). Here, an insulator 255 having an opening is formed from the insulating film 255A, and the conductor 242_1 is divided to form the conductor 242a1 and the conductor 242b1. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is D2, which corresponds to the distance D2 between the conductor 242a1 and the conductor 242b1. Because the opening is formed inside the opening formed in the insulator 280, the distance D2 between the conductor 242a1 and the conductor 242b1 is shorter than the distance D1 between the conductor 242a2 and the conductor 242b2.

[0484] The lithography method can be any of the above-described methods, as appropriate. In order to finely process the openings in the insulator 255, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0485] 25A and 25D , the insulator 255 has an opening formed therein so as to expose the island-shaped oxide semiconductor 230, but the present invention is not limited to this. In this step, it is sufficient that the conductor 242a1 and the conductor 242b1 are separated from each other by a distance D2. Therefore, for example, an opening substantially similar to the opening 201 may be formed in the insulator 255, except for the portions that contact the top surfaces of the conductors 242a1 and 242b1. However, in this case, the insulator 255 may be formed in a sidewall shape in contact with the sidewall of the opening 201.

[0486] The above processing is preferably performed using a dry etching method. Dry etching is capable of anisotropic etching and is therefore suitable for performing fine processing such as opening the insulator 255 in the opening 201. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus.

[0487] Although the above describes an example in which lithography is used to process the insulator 255, the present invention is not limited to this. For example, the insulator 255 may be anisotropically etched without using a mask. This allows the insulator 255 to be formed in a sidewall shape in contact with the sidewall of the opening 201, as shown in FIGS. 15A to 15D .

[0488] 4B , a portion of the oxide semiconductor 230 in contact with the upper portion of the insulator 225 is removed, and a portion of the oxide semiconductor 230 in contact with the side surface of the insulator 225 remains, forming a sidewall-shaped oxide semiconductor 230.

[0489] In this manner, the conductors 242a2 and 242b2 having a distance D1 between them and the conductors 242a1 and 242b1 having a distance D2 between them can be formed. With this structure, the distance between the source and drain of the transistor 200 can be shortened, thereby improving the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device.

[0490] 16A and 16B can be manufactured in parallel. In this case, when the conductor 242a1 and the conductor 242b1 of the transistor 200 are formed, the capacitor 460 does not need to be subjected to the etching treatment, and the oxide semiconductor 230 may be covered with the conductor 242b1 in the region where the capacitor 460 is to be formed. In this way, the capacitor 460 including the conductor 242b1, the insulator 454, and the conductor 456 can be manufactured in parallel with the transistor 200.

[0491] Note that ashing treatment using oxygen plasma may be performed after processing the conductor 242_1 and after processing the conductor 242_2. By performing such oxygen plasma treatment, impurities generated during the etching treatment and diffused into the oxide semiconductor 230 and the like can be removed. Examples of the impurities include those originating from components contained in a workpiece of the etching treatment and components contained in a gas used in the etching treatment. Examples of the impurities include chlorine, fluorine, tantalum, silicon, and hafnium. When chlorine gas is used in the etching treatment, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove chlorine attached to the oxide semiconductor 230. Removing the impurities attached to the oxide semiconductor 230 in this manner can improve the electrical characteristics and reliability of the transistor.

[0492] Furthermore, a cleaning treatment may be performed to remove impurities and the like attached to the surface of the oxide semiconductor 230 during the etching process. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (also referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate. Note that the cleaning treatment may deepen the grooves in some cases.

[0493] Wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water. Wet cleaning may also be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water. Wet cleaning may also be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0494] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0495] Note that the ultrasonic cleaning is preferably performed at a frequency of 200 kHz or higher, more preferably 900 kHz or higher, because damage to the oxide semiconductor 230 and the like can be reduced by using such a frequency.

[0496] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0497] In this embodiment, wet cleaning is performed using diluted ammonia water as the cleaning treatment. By performing the cleaning treatment, impurities attached to the surface of the oxide semiconductor 230 or diffused into the oxide semiconductor 230 can be removed. Furthermore, the crystallinity of the oxide semiconductor 230 can be improved.

[0498] It is preferable to perform heat treatment after the etching or cleaning. The temperature of the heat treatment is 100° C. to 650° C., preferably 250° C. to 600° C., more preferably 300° C. to 550° C., and still more preferably 350° C. to 400° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment is preferably performed in an atmosphere containing oxygen. For example, the heat treatment is preferably performed at 350° C. for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the oxide semiconductor 230, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide semiconductor 230. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor 230, converting the hydrogen into H ２ As a result, hydrogen remaining in the oxide semiconductor 230 is recombined with the oxygen vacancies to form V Ｏ The formation of H can be suppressed. Therefore, the electrical characteristics of the transistor including the oxide semiconductor 230 can be improved, and reliability can be improved. Furthermore, variation in the electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the heat treatment may be performed under reduced pressure. Alternatively, heat treatment may be performed in an oxygen atmosphere and then successively in a nitrogen atmosphere without exposure to the air. Furthermore, the heat treatment can also serve as the heat treatment for the oxide semiconductor film 230f described above. Therefore, the heat treatment may cause growth of a crystalline region in the oxide semiconductor 230.

[0499] Note that when heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide semiconductor 230, the sheet resistance of a region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0500] As described above, the insulator 255, which has an inorganic insulator that is resistant to oxidation, is provided in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. This prevents the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment, even if the conductors 242a2 and 242b2 are made of a tungsten film that is relatively easily oxidized.

[0501] Note that part of the top surface of the oxide semiconductor 230 in a region between the conductor 242a1 and the conductor 242b1 might be removed by the processing of the conductor 242_1 or a subsequent cleaning treatment, etc. As a result, in the oxide semiconductor 230, the top surface of the region between the conductor 242a1 and the conductor 242b1 might be lower than the top surface of a region overlapping with the conductor 242a1 or the conductor 242b1, as shown in FIG.

[0502] Next, an insulating film 250A to be the insulator 250 is formed along the side surface and bottom surface of the opening 201 formed in the insulator 280 or the like (see FIGS. 26A to 26D ). Here, the insulating film 250A is in contact with the insulator 255, the conductor 242a, the conductor 242b, the insulator 222, and the oxide semiconductor 230.

[0503] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250A is preferably formed using an ALD method. Like the insulator 250 described above, the insulating film 250A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening, allowing the insulating film 250A to be formed with good coverage on the opening.

[0504] When the insulating film 250A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using HCl, HCl, or the like as an oxidizing agent, hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0505] The insulator 250 can have a layered structure as shown in FIG. 2 and the like. For example, as shown in FIG. 2A, the insulator 250 can have a layered structure of insulators 250a to 250d. In this case, aluminum oxide can be deposited as the insulator 250a by a thermal ALD method, silicon oxide can be deposited as the insulator 250b by a PEALD method, hafnium oxide can be deposited as the insulator 250c by a thermal ALD method, and silicon nitride can be deposited as the insulator 250d by a PEALD method.

[0506] Furthermore, after the insulating film 250A or any of the insulators constituting the insulating film 250A is formed, it is preferable to perform microwave plasma treatment in an atmosphere containing oxygen. Here, the microwave plasma treatment may refer to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. In this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0507] In the microwave plasma treatment, it is preferable to use a microwave plasma treatment apparatus having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave plasma treatment apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. The use of high-density plasma allows high-density oxygen radicals to be generated. Furthermore, the power of the power supply that applies microwaves to the microwave plasma treatment apparatus is preferably 1000 W to 10,000 W, more preferably 2000 W to 5,000 W. The microwave plasma treatment apparatus may also have a power supply that applies RF to the substrate side. Furthermore, applying RF to the substrate side allows oxygen ions generated by the high-density plasma to be efficiently introduced into the oxide semiconductor 230.

[0508] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0509] Furthermore, for example, the microwave plasma treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２+Ar)) is set to 10% or more and 30% or less. By performing microwave plasma treatment in an atmosphere containing oxygen in this manner, the carrier concentration in the oxide semiconductor 230 can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave plasma treatment, an excessive reduction in the carrier concentration in the oxide semiconductor 230 can be prevented.

[0510] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to a region between the conductor 242 a and the conductor 242 b of the oxide semiconductor 230. The action of the plasma, microwaves, or the like can reduce the V in the region. Ｏ The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when using the structure shown in FIG. 2A or the like, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing or fixing hydrogen as the insulator 250a. With such a structure, hydrogen generated by microwave plasma treatment can be captured or fixed in the insulating film 250A. In this way, V included in the channel formation region can be removed. Ｏ As a result, oxygen vacancies in the channel formation region and V Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0511] The oxygen implanted into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0512] Furthermore, the microwave plasma treatment can also remove impurities such as carbon from the oxide semiconductor 230. Removal of carbon, which is an impurity in the oxide semiconductor 230, can improve the crystallinity of the oxide semiconductor 230. This enables the oxide semiconductor 230 to become a CAAC-OS. In particular, when the oxide semiconductor 230 is formed by an ALD method, carbon contained in a precursor might be taken into the oxide semiconductor 230; therefore, it is preferable to remove carbon by microwave plasma treatment.

[0513] Meanwhile, the oxide semiconductor 230 has a region overlapping with either the conductor 242a or the conductor 242b. The region can function as a source region or a drain region. Here, the conductor 242a and the conductor 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, and the like when microwave plasma treatment is performed in an oxygen-containing atmosphere. Therefore, the conductor 242a and the conductor 242b preferably have a function of shielding electromagnetic waves of 300 MHz to 300 GHz, for example, 2.4 GHz to 2.5 GHz.

[0514] The conductors 242a and 242b shield the oxide semiconductor 230 from microwaves, high-frequency waves such as RF, oxygen plasma, and the like, and therefore these effects do not reach a region of the oxide semiconductor 230 that overlaps with either the conductor 242a or the conductor 242b. As a result, the microwave plasma treatment can reduce V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0515] Here, an insulator 255 having a barrier property against oxygen is provided in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, thereby making it possible to prevent an oxide film from being formed on the side surfaces of the conductor 242a2 and the conductor 242b2 by microwave plasma processing.

[0516] In this manner, oxygen vacancies and V ＯBy removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low-resistance region state) before the microwave plasma treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0517] Furthermore, by performing microwave plasma treatment to modify the film quality of the insulator 250, diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide semiconductor 230, the oxide semiconductor 230, and the like can be suppressed by post-processing such as deposition of a conductive film that becomes the conductor 260 or post-treatment such as heat treatment. In this way, improving the film quality of the insulator 250 can improve the reliability of the transistor.

[0518] When the insulator 250 has a stacked structure of insulators 250a to 250d, microwave plasma treatment is preferably performed after the formation of the insulator 250b. Furthermore, microwave plasma treatment may be performed again after the formation of the insulator 250c. In this manner, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more). The microwave plasma treatment may also serve as the heat treatment of the oxide semiconductor film 230f. Therefore, the microwave plasma treatment may cause the growth of a crystalline region in the oxide semiconductor 230.

[0519] After the microwave plasma treatment, heat treatment may be performed while the reduced pressure state is maintained. By performing such treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing heat treatment while the reduced pressure state is maintained after the microwave plasma treatment may be repeated multiple times. By repeatedly performing the heat treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be more efficiently removed. Note that the heat treatment temperature...

Claims

an oxide semiconductor, first to fourth insulators, and first to third conductors; the first insulator is disposed on a substrate; the second insulator is disposed on the first insulator; the oxide semiconductor is disposed on the first insulator and covers the second insulator; the first conductor and the second conductor are disposed on the oxide semiconductor; the third insulator is disposed on the first conductor and the second conductor and has an opening overlapping a region between the first conductor and the second conductor; the fourth insulator is disposed in the opening and overlies the oxide semiconductor; the third conductor is disposed in the opening and on the fourth insulator; a side surface of the first insulator coincides or substantially coincides with a side surface of the oxide semiconductor, a side surface of the first conductor, and a side surface of the second conductor in a plan view; The first insulator has a thickness greater than the fourth insulator, In a cross-sectional view in a channel width direction, a height of the second insulator is greater than a width of the second insulator. Semiconductor device. 　 In claim 1, a side surface of a portion of the third insulator coincides or substantially coincides with a side surface of the first conductor and a side surface of the second conductor in a plan view; Semiconductor device. 　 In claim 1, the second insulator comprises a metal oxide containing indium, gallium, and zinc; In the second insulator, the proportion of gallium is higher than the proportion of indium. Semiconductor device. 　 In claim 1, the second insulator comprises gallium oxide; Semiconductor device. 　 In claim 1, the second insulator comprises silicon nitride; Semiconductor device. 　 In claim 1, a lower surface of the third conductor has a portion located lower than a lower surface of the oxide semiconductor; Semiconductor device. 　 In claim 1, a fifth insulator; each of the first conductor and the second conductor has a first layer and a second layer on the first layer; the fifth insulator is disposed in the opening of the third insulator and contacts a top surface of the first layer of the first conductor, a side surface of the second layer of the first conductor, a top surface of the first layer of the second conductor, and a side surface of the second layer of the second conductor; the fifth insulator has an opening overlapping a region between the first layer of the first conductor and the first layer of the second conductor; a shortest distance between a first layer of the first conductor and a first layer of the second conductor is smaller than a shortest distance between a second layer of the first conductor and a second layer of the second conductor; Semiconductor device. 　 In claim 7, a side surface of a portion of the third insulator coincides or substantially coincides with a side surface of the second layer of the first conductor and a side surface of the second layer of the second conductor in a plan view; Semiconductor device. In claim 7, the fifth insulator comprises silicon nitride; Semiconductor device. 　 In claim 7, the second insulator comprises a metal oxide containing indium, gallium, and zinc; In the second insulator, the proportion of gallium is higher than the proportion of indium. Semiconductor device. 　 In claim 7, the second insulator comprises gallium oxide; Semiconductor device. 　 In claim 7, the second insulator comprises silicon nitride; Semiconductor device. 　 In claim 7, the first layer of the first conductor and the first layer of the second conductor comprise tantalum nitride; Semiconductor device. 　 In claim 7, a lower surface of the third conductor has a portion located lower than a lower surface of the oxide semiconductor; Semiconductor device. 　 In any one of claims 1 to 14, the oxide semiconductor contains indium; In a cross-sectional observation of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction parallel to a surface on which the oxide semiconductor is formed are confirmed. Semiconductor device. 　 In any one of claims 1 to 14, the oxide semiconductor contains indium; the oxide semiconductor has a first region, a second region in contact with the first region, and a third region in contact with the second region; In a cross-sectional observation of the oxide semiconductor using a transmission electron microscope, bright points arranged in layers in a direction parallel to a surface on which the oxide semiconductor is formed are confirmed in each of the first region, the second region, and the third region. Semiconductor device. 　 In claim 16, the second region comprises zinc; the second region has crystals; a c-axis of the crystal is approximately parallel to a normal direction of a surface on which the oxide semiconductor is formed. Semiconductor device. 　 In claim 16, a content of indium in the first region is higher than a content of indium in the second region; The indium content in the third region is higher than the indium content in the second region. Semiconductor device.

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