Imaging device

Abstract

This imaging device comprises: a first semiconductor substrate having a first surface; a second semiconductor substrate having a second surface and a third surface on the opposite side from the second surface, the second semiconductor substrate being layered on the first semiconductor substrate so that the second surface and the first surface face each other; a first photoelectric conversion unit positioned on or above the third surface of the second semiconductor substrate, the first photoelectric conversion unit converting light into electric charges; and a through electrode penetrating the second semiconductor substrate. The first semiconductor substrate is electrically connected to the first photoelectric conversion unit via the through electrode and includes a first impurity region for accumulating the electric charges.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] Charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors are widely used in digital cameras, etc. As an imaging device using such an image sensor, a stacked imaging device has been proposed, which has a structure in which a photoelectric conversion unit having a photoelectric conversion layer is disposed above a semiconductor substrate.

[0003] For example, Patent Document 1 discloses an imaging device that includes a photoelectric conversion unit arranged above a semiconductor substrate, a signal detection circuit arranged on the underside of the semiconductor substrate, and a through electrode that connects the photoelectric conversion unit and the signal detection circuit and penetrates the semiconductor substrate.

[0004] International Publication No. WO 2020 / 158515 International Publication No. WO 2012 / 147302 International Publication No. WO 2020 / 189169

[0005] There is a demand for smaller imaging devices and lower noise.

[0006] Therefore, the present disclosure provides an imaging device that can be made smaller and has lower noise.

[0007] An imaging device according to one aspect of the present disclosure includes a first semiconductor substrate having a first surface, a second semiconductor substrate having a second surface and a third surface opposite to the second surface and stacked on the first semiconductor substrate such that the second surface and the first surface face each other, a first photoelectric conversion unit located on or above the third surface of the second semiconductor substrate and converting light into electric charges, and a through electrode penetrating the second semiconductor substrate, wherein the first semiconductor substrate includes a first impurity region electrically connected to the first photoelectric conversion unit via the through electrode and storing the electric charges.

[0008] According to the present disclosure, it is possible to provide an imaging device that can be made smaller and has lower noise.

[0009] FIG. 1 is a diagram showing a configuration of an imaging device according to Embodiment 1. FIG. 2 is a diagram showing a circuit configuration of a pixel according to Embodiment 1. FIG. 3 is a schematic cross-sectional view of a device structure of a pixel according to Embodiment 1. FIG. 4A is a plan view showing an internal layout of a pixel according to Embodiment 1. FIG. 4B is another plan view showing the internal layout of a pixel according to Embodiment 1. FIG. 5 is a cross-sectional view showing an example of an arrangement of peripheral circuits in an imaging device according to Embodiment 1. FIG. 6 is a cross-sectional view showing another example of an arrangement of peripheral circuits in an imaging device according to Embodiment 1. FIG. 7 is a schematic cross-sectional view of a device structure of a pixel according to a modification of Embodiment 1. FIG. 8A is a plan view showing an internal layout of a pixel according to a modification of Embodiment 1. FIG. 8B is another plan view showing an internal layout of a pixel according to a modification of Embodiment 1. FIG. 9 is a diagram showing a circuit configuration of a pixel according to Embodiment 2. FIG. 10 is a schematic cross-sectional view of a device structure of a pixel according to Embodiment 2. FIG. 11A is a plan view showing an internal layout of a pixel according to Embodiment 2. FIG. 11B is another plan view showing an internal layout of a pixel according to Embodiment 2. FIG. 11C is yet another plan view showing an internal layout of a pixel according to Embodiment 2. FIG. 12 is a diagram showing a circuit configuration of a pixel according to embodiment 3. FIG. 13 is a schematic cross-sectional view of a device structure of a pixel according to embodiment 3. FIG. 14A is a plan view showing an internal layout of a pixel according to embodiment 3. FIG. 14B is another plan view showing an internal layout of a pixel according to embodiment 3. FIG. 15 is a diagram showing a circuit configuration of a pixel according to embodiment 4. FIG. 16 is a schematic cross-sectional view of a device structure of a pixel according to embodiment 4. FIG. 17A is a plan view showing an internal layout of a pixel according to embodiment 4. FIG. 17B is another plan view showing an internal layout of a pixel according to embodiment 4. FIG. 17C is yet another plan view showing an internal layout of a pixel according to embodiment 4. FIG. 18 is a diagram showing a circuit configuration of a pixel according to embodiment 5. FIG. 19 is a schematic cross-sectional view of a device structure of a pixel according to embodiment 5. FIG. 20A is a plan view showing an internal layout of a pixel according to embodiment 5. FIG. 20B is another plan view showing an internal layout of a pixel according to embodiment 5. FIG. 20C is yet another plan view showing an internal layout of a pixel according to embodiment 5.Fig. 21 is a diagram showing a circuit configuration of a pixel according to embodiment 6. Fig. 22 is a schematic cross-sectional view of a device structure of a pixel according to embodiment 6. Fig. 23 is a diagram showing a circuit configuration of a pixel according to modified example 1 of embodiment 6. Fig. 24 is a schematic cross-sectional view of a device structure of a pixel according to modified example 1 of embodiment 6. Fig. 25 is a diagram showing a circuit configuration of a pixel according to modified example 2 of embodiment 6. Fig. 26 is a diagram showing a circuit configuration of a pixel according to modified example 3 of embodiment 6.

[0010] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, an example of an imaging device according to the present disclosure will be described below.

[0011] For example, an imaging device according to a first aspect of the present disclosure includes a first semiconductor substrate having a first surface, a second semiconductor substrate having a second surface and a third surface opposite to the second surface and stacked on the first semiconductor substrate such that the second surface and the first surface face each other, a first photoelectric conversion unit located on or above the third surface of the second semiconductor substrate and converting light into electric charges, and a through electrode penetrating the second semiconductor substrate, wherein the first semiconductor substrate includes a first impurity region electrically connected to the first photoelectric conversion unit via the through electrode and storing the electric charges.

[0012] As a result, for example, by distributing transistors across the first semiconductor substrate and the second semiconductor substrate, the imaging device can be made smaller. Furthermore, because the first impurity region that accumulates the charge converted by the first photoelectric conversion unit is included in the first semiconductor substrate that is farther from the first photoelectric conversion unit than the second semiconductor substrate, charge generation caused by light not absorbed by the first photoelectric conversion unit entering the first impurity region is suppressed. Therefore, noise caused by charge generation unrelated to photoelectric conversion by the first photoelectric conversion unit is suppressed, thereby enabling the imaging device to have low noise.

[0013] Furthermore, since the first surface and the second surface face each other, even when a first transistor is disposed on the first surface and a second transistor is disposed on the second surface and the first transistor and the second transistor are connected by a wiring structure, there is no need to form wiring that penetrates the second semiconductor substrate, making it possible to easily form an imaging device and also increasing the degree of freedom in the layout of the wiring structure.

[0014] In this specification, being able to reduce the size of an imaging device means being able to reduce the area of ​​a semiconductor substrate in a plan view.

[0015] Also, for example, an imaging device according to a second aspect of the present disclosure may be the imaging device according to the first aspect, further including a plurality of transistors located on the second surface.

[0016] Also, for example, an imaging device according to a third aspect of the present disclosure is an imaging device according to the second aspect, and in the imaging device according to the third aspect, the plurality of transistors may include a first transistor having a gate electrically connected to the first photoelectric conversion unit via the through electrode.

[0017] As a result, a first transistor having a gate to which the voltage of the first impurity region is applied is arranged on a second semiconductor substrate different from a first semiconductor substrate including a first impurity region that accumulates electric charges, so that the imaging device can be made smaller even when a signal based on the accumulated electric charges is read out using the first transistor.

[0018] Also, for example, an imaging device according to a fourth aspect of the present disclosure is the imaging device according to the third aspect, and in the imaging device according to the fourth aspect, the second semiconductor substrate may include a second impurity region of a first conductivity type that functions as a source or drain of the first transistor, and the first impurity region may be an impurity region of a second conductivity type different from the first conductivity type.

[0019] This allows the conductivity types of the first impurity region and the second impurity region that functions as the source or drain of the first transistor to be selected according to the desired characteristics.

[0020] Also, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to the fourth aspect, and in the imaging device according to the fifth aspect, the first conductivity type may be n-type, and the second conductivity type may be p-type.

[0021] This allows the first transistor to use electrons as carriers, thereby improving the driving capability of the first transistor.

[0022] Furthermore, for example, an imaging device according to a sixth aspect of the present disclosure may be an imaging device according to any one of the first to fifth aspects, and in the imaging device according to the sixth aspect, the first photoelectric conversion unit may include a first electrode electrically connected to the first impurity region, a second electrode opposite the first electrode, and a photoelectric conversion layer located between the first electrode and the second electrode.

[0023] This allows the light receiving area of ​​the photoelectric conversion section to be increased, thereby improving sensitivity and reducing noise in the imaging device.

[0024] Also, for example, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to any one of the first to sixth aspects, and in the imaging device according to the seventh aspect, the second semiconductor substrate may include a second photoelectric conversion unit that converts light into electric charges.

[0025] This allows the amount of information that can be obtained by the imaging device to be increased by converting light of different wavelengths into electric charges using the first photoelectric conversion unit and the second photoelectric conversion unit.

[0026] Also, for example, an imaging device according to an eighth aspect of the present disclosure may be the imaging device according to the seventh aspect, and in the imaging device according to the eighth aspect, the second photoelectric conversion unit may be arranged at a position where light that has passed through the first photoelectric conversion unit is incident.

[0027] This allows the light receiving areas of the first photoelectric conversion unit and the second photoelectric conversion unit to be increased.

[0028] Furthermore, for example, an imaging device according to a ninth aspect of the present disclosure may be an imaging device according to any one of the first aspect and the sixth to eighth aspects, and may further include a first transistor located on the first surface, including a gate electrically connected to the first photoelectric conversion unit via the through electrode.

[0029] As a result, a first transistor having a gate to which the voltage of the first impurity region is applied is arranged on a first semiconductor substrate including a first impurity region that accumulates electric charge, thereby making it possible to secure space on the second semiconductor substrate for arranging transistors for other circuits provided in the imaging device.

[0030] Also, for example, an imaging device according to a tenth aspect of the present disclosure may be an imaging device according to any one of the first to ninth aspects, and may further include a plurality of pixels and a peripheral circuit electrically connected to the plurality of pixels, each of the plurality of pixels may include the first photoelectric conversion unit, the through electrode, and the first impurity region, and at least a portion of the peripheral circuit may be located on the first surface of the first semiconductor substrate or the second surface of the second semiconductor substrate.

[0031] This makes it possible to electrically connect the plurality of pixels to the peripheral circuitry without providing wiring that penetrates the first semiconductor substrate and wiring that penetrates the second semiconductor substrate.

[0032] Also, for example, an imaging device according to an eleventh aspect of the present disclosure may be an imaging device according to any one of the first to tenth aspects, and may further include a wiring layer located between the first surface and the second surface and overlapping the first impurity region in a planar view.

[0033] This further suppresses the generation of charges due to light that is not absorbed by the first photoelectric conversion portion being incident on the first impurity region.

[0034] Furthermore, for example, an imaging device according to a twelfth aspect of the present disclosure may be an imaging device according to any one of the first to eighth aspects, and may include a second transistor that includes the first impurity region as one of a source and a drain and is located on the first surface.

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components not recited in independent claims are described as optional components. In each drawing, components having substantially the same functions are designated by common reference symbols, and redundant descriptions may be omitted or simplified.

[0036] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from the actual objects. In other words, each drawing is a schematic diagram and is not necessarily an accurate depiction. Therefore, for example, the scales of the drawings do not necessarily match.

[0037] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or coincident, terms indicating the shape of elements, such as circular or rectangular, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0038] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Similarly, the "upper surface" and "lower surface" of each component refer to the light-receiving side of the imaging device as the "upper surface" and the side opposite the light-receiving side as the "lower surface." Note that the terms "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" apply not only to cases where two components are arranged with a gap between them and another component is present between them, but also to cases where two components are arranged closely together and in contact with each other. In this specification, the term "plan view" refers to a view from a direction perpendicular to the semiconductor substrate (in other words, the thickness direction of the semiconductor substrate).

[0039] In this specification and the drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In the following embodiments, the Z-axis direction corresponds to the thickness direction of the semiconductor substrate and the stacking direction of the semiconductor substrate. The negative side of the Z-axis corresponds to the "downward" direction, and the positive side of the Z-axis corresponds to the "upward" direction.

[0040] In this specification, when a transistor is disposed on a certain surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are disposed with the certain surface sandwiched therebetween.

[0041] In this specification, not only visible light but also invisible light such as ultraviolet light and near-infrared light will be referred to as "light" for convenience.

[0042] First Embodiment An imaging device according to a first embodiment will be described.

[0043] [Overall Configuration] First, the overall configuration of the imaging device according to this embodiment will be described.

[0044] Fig. 1 is a diagram showing the configuration of an imaging device according to the present embodiment. As shown in Fig. 1, the imaging device 100A according to the present embodiment includes a plurality of pixels 10A formed on a plurality of stacked semiconductor substrates, and a peripheral circuit 40. Each pixel 10A includes a photoelectric conversion unit 12 arranged above the plurality of stacked semiconductor substrates.

[0045] In the example shown in FIG. 1 , pixels 10A are arranged in a matrix of m rows and n columns. Here, m and n are integers greater than or equal to 2. The pixels 10A are arranged, for example, two-dimensionally to form an imaging region R1. As described above, each pixel 10A includes a photoelectric conversion unit 12 arranged above multiple semiconductor substrates. Therefore, the imaging region R1 is defined as the region of the multiple semiconductor substrates that is covered by the photoelectric conversion units 12. Note that in FIG. 1 , the photoelectric conversion units 12 of each pixel 10A are shown spatially separated from one another for ease of explanation, but the photoelectric conversion units 12 of multiple pixels 10A may be arranged without any gaps between them.

[0046] The number and arrangement of the pixels 10A are not limited to the example shown in the figure. For example, the number of pixels 10A included in the imaging device 100A may be one. Also, in this example, the center of each pixel 10A is located on a lattice point of a square lattice, but the pixels 10A do not have to be arranged in this manner. For example, multiple pixels 10A may be arranged so that each center is located on a lattice point of a triangular lattice, hexagonal lattice, or the like. Furthermore, if the pixels 10A are arranged one-dimensionally, the imaging device 100A can be used as a line sensor.

[0047] In the configuration illustrated in FIG. 1 , the peripheral circuit 40 includes a vertical scanning circuit 46 and a horizontal signal readout circuit 48. The vertical scanning circuit 46, also called a row scanning circuit, is connected to address signal lines 34 provided for each row of the pixels 10A. In FIG. 1 , only the address signal lines 34 provided for each row of the pixels 10A are connected to the vertical scanning circuit 46, but other signal lines (described below) connected to the pixels 10A may also be connected. The horizontal signal readout circuit 48, also called a column scanning circuit, is connected to vertical signal lines 35 provided for each column of the pixels 10A. In other words, the vertical signal lines 35 are provided for each column of the pixels 10A. The horizontal signal readout circuit 48 sequentially reads out signals from each pixel 10A via the vertical signal lines 35.

[0048] As schematically shown in FIG. 1 , the vertical scanning circuit 46 and the horizontal signal readout circuit 48 are arranged in a peripheral region R2 outside the imaging region R1. The peripheral circuit 40 is electrically connected to the multiple pixels 10A and is a circuit for driving each pixel 10A and acquiring signals from each pixel 10A. The peripheral circuit 40 may further include a load circuit, a signal processing circuit, an output circuit, a control circuit, and a power supply for supplying a predetermined voltage to each pixel 10A. The circuit elements constituting the peripheral circuit 40 are arranged, for example, on at least one of the multiple semiconductor substrates on which the pixels 10A are formed. However, at least a portion of the peripheral circuit 40 may be arranged on a semiconductor substrate other than the multiple semiconductor substrates on which the pixels 10A are formed. In other words, at least a portion of the peripheral circuit 40 does not have to be arranged in the peripheral region R2.

[0049] [Pixel Configuration] Next, the configuration of the pixel 10A of the imaging device 100A according to this embodiment will be described.

[0050] First, the circuit configuration of the pixel 10A according to the present embodiment will be described. Fig. 2 is a diagram showing the circuit configuration of the pixel 10A according to the present embodiment. Each of the plurality of pixels 10A has, for example, the circuit configuration shown in Fig. 2.

[0051] The photoelectric conversion unit 12 of the pixel 10A generates positive and negative charges in response to incident light. That is, the photoelectric conversion unit 12 converts light into electric charges. The positive and negative charges are typically hole-electron pairs. The photoelectric conversion unit 12 is an example of a first photoelectric conversion unit. The photoelectric conversion unit 12 of each pixel 10A is connected to an accumulation control line 39, and a predetermined second voltage V2 is applied to the accumulation control line 39 during operation of the imaging device 100A. By applying the predetermined second voltage V2 to the accumulation control line 39, one of the positive and negative charges generated by photoelectric conversion can be selectively accumulated in the charge accumulation region as a signal charge. In the following description, unless otherwise specified, a case will be illustrated in which the positive charge, i.e., the hole, of the positive and negative charges generated by photoelectric conversion is used as the signal charge.

[0052] The pixel 10A includes a signal detection circuit electrically connected to the photoelectric conversion unit 12 and configured to detect a signal based on the charge generated by the photoelectric conversion unit 12. In the configuration illustrated in FIG. 2 , the signal detection circuit includes an amplifier transistor 22, an address transistor 24, and a reset transistor 26. The amplifier transistor 22 is also referred to as a readout transistor. The address transistor 24 is also referred to as a row selection transistor. As will be described in detail later with reference to the drawings, the amplifier transistor 22, the address transistor 24, and the reset transistor 26 are, for example, field effect transistors (FETs) formed on a first semiconductor substrate 60 or a second semiconductor substrate 70 that supports the photoelectric conversion unit 12. Specifically, the reset transistor 26 is formed on the first semiconductor substrate 60 of the first pixel layer 1, and the amplifier transistor 22 and the address transistor 24 are formed on the second semiconductor substrate 70 of the second pixel layer 2. 2, an N-channel MOSFET (Metal Oxide Semiconductor FET) is used for each of the amplifier transistor 22, reset transistor 26, and address transistor 24. Which of the two diffusion regions of the FET corresponds to the source and drain is determined by the polarity of the FET and the level of the potential at that time. Therefore, which is the source and drain can vary depending on the operating state of the FET.

[0053] 2 , the gate of the amplification transistor 22 is electrically connected to the photoelectric conversion unit 12. Charges generated by the photoelectric conversion unit 12 are accumulated as signal charges in a charge accumulation node FD between the photoelectric conversion unit 12 and the amplification transistor 22. In other words, the charge accumulation node FD functions as at least a part of a charge accumulation region that accumulates signal charges, and the potential of the charge accumulation node FD corresponds to the amount of signal charge accumulated in the charge accumulation region. The charge accumulation node FD includes wiring that connects the photoelectric conversion unit 12, the amplification transistor 22, and the reset transistor 26.

[0054] One of the source and drain of the amplification transistor 22 is connected to a power supply wiring 32 that supplies a predetermined power supply voltage VDD to each pixel 10A when the imaging device 100A is in operation. The power supply voltage VDD is, for example, about 3.3 V, but is not limited to this. The amplification transistor 22 outputs a signal voltage SIG that corresponds to the amount of signal charge generated by the photoelectric conversion unit 12. The other of the source and drain of the amplification transistor 22 is connected to one of the source and drain of the address transistor 24.

[0055] 1 (not shown in FIG. 2 ) is connected to the other of the source and drain of the address transistor 24. Each of the vertical signal lines 35 is connected to, for example, a load circuit that forms a source follower circuit together with the amplifier transistor 22, and a column signal processing circuit.

[0056] An address signal line 34 is connected to the gate of the address transistor 24. One address signal line 34 is provided for each row of pixels 10A. The address signal line 34 is connected to a vertical scanning circuit 46, which applies a row selection signal SEL to the address signal line 34 to control the on / off of the address transistor 24. This causes the row to be readout to be scanned in the vertical direction (i.e., the column direction), thereby selecting the row to be readout. By controlling the on / off of the address transistor 24 via the address signal line 34, the vertical scanning circuit 46 can read out the output of the amplifier transistor 22 of the selected pixel 10A to the corresponding vertical signal line 35. The location of the address transistor 24 is not limited to the example shown in FIG. 2 , and may be between one of the source and drain of the amplifier transistor 22 and the power supply wiring 32.

[0057] The signal voltage SIG from the pixel 10A, which is output to the vertical signal line 35 via the address transistor 24, undergoes, for example, noise suppression signal processing and analog-to-digital conversion in a column signal processing circuit, and is then input to the horizontal signal readout circuit 48.

[0058] One of the source and drain of the reset transistor 26 is connected to the charge storage node FD. A reset signal line 36, which is connected to the vertical scanning circuit 46, is connected to the gate of the reset transistor 26. Like the address signal lines 34, the reset signal line 36 is provided for each row of pixels 10A. The vertical scanning circuit 46 applies a reset signal RS, which controls the on / off of the reset transistor 26, to the gate of the reset transistor 26 via the reset signal line 36. When the reset transistor 26 is turned on, the potential of the charge storage node FD is reset.

[0059] 2 , the other of the source and drain of the reset transistor 26 is connected to a reset voltage line 31 that supplies a first voltage V1, which is a predetermined reset voltage, to each pixel 10A when the pixel 10A is reset. That is, in this example, the first voltage V1 is supplied to the charge storage node FD as a reset voltage that initializes the charge generated in the photoelectric conversion unit 12. The reset voltage line 31 is connected, for example, to a voltage supply circuit (not shown) that supplies the first voltage V1. Note that the other of the source and drain of the reset transistor 26 is not limited to being connected to the reset voltage line 31, and may be connected to a feedback line connected to the output of a feedback amplifier, as in Patent Document 2, for example.

[0060] Next, the device structure of the pixel 10A according to the present embodiment will be described. FIG. 3 is a schematic cross-sectional view of the device structure of the pixel 10A according to the present embodiment. FIG. 4A is a plan view showing the layout within the pixel 10A according to the present embodiment. FIG. 4B is another plan view showing the layout within the pixel 10A according to the present embodiment. FIG. 3 is a cross-sectional view of the pixel 10A cut along line III-III in FIGS. 4A and 4B. Each of the multiple pixels 10A has the device structure shown in FIGS. 3, 4A, and 4B, for example. FIGS. 3, 4A, and 4B show the device structure corresponding to one pixel 10A.

[0061] FIG. 4A schematically illustrates the arrangement of each element formed on the second semiconductor substrate 70 shown in FIG. 3 when viewed from below. Specifically, FIG. 4A illustrates the arrangement of the amplifier transistor 22, address transistor 24, and through-electrode pt included in the pixel 10A on the second semiconductor substrate 70. Also, in FIG. 4A, the outline of the wiring 82b is indicated by a dashed line. FIG. 4B schematically illustrates the arrangement of each element formed on the first semiconductor substrate 60 shown in FIG. 3 when viewed from above. Specifically, FIG. 4B illustrates the arrangement of the reset transistor 26 included in the pixel 10A. Also, in FIG. 4B, the outline of the wiring 81a is indicated by a dashed line. Also, FIGS. 4A and 4B illustrate the arrangement of contact plugs connected to each transistor. For ease of viewing, each configuration shown in the plan view is shaded in the same manner as each configuration shown in the cross section of FIG. 3. In the plan views described below, the same hatching as that of the respective configurations in the corresponding cross-sectional views is used. Also, in Fig. 3, for ease of viewing, the hatching indicating the cross section of insulating regions such as the interlayer insulating layer 90 is omitted. This also applies to the cross-sectional views described below.

[0062] As schematically shown in FIG. 3 , the pixel 10A generally includes a first pixel layer 1, a second pixel layer 2, and a photoelectric conversion unit 12, which are stacked in this order from top to bottom. The pixel 10A also includes a wiring structure 80 and a through-electrode pt. In FIG. 3 , the through-electrode pt is indicated by a dashed line because it is not visible in the cross section. The first pixel layer 1 includes a first semiconductor substrate 60 and an interlayer insulating layer 90. The second pixel layer 2 includes a second semiconductor substrate 70 and an interlayer insulating layer 91. The second semiconductor substrate 70 is disposed above the first semiconductor substrate 60, and the photoelectric conversion unit 12 is disposed above the second semiconductor substrate 70. The first semiconductor substrate 60 and the second semiconductor substrate 70 correspond to the multiple semiconductor substrates stacked on top of each other on which the multiple pixels 10A described in FIG. 1 are formed.

[0063] The wiring structure 80 is disposed in interlayer insulating layers 90 and 91 formed between the first semiconductor substrate 60 and the second semiconductor substrate 70. The interlayer insulating layers 90 and 91 each have a stacked structure of multiple insulating layers. The wiring structure 80 also includes multiple wiring layers and multiple plugs and / or vias disposed between these wiring layers. Each of the multiple wiring layers includes at least one wiring. The number of insulating layers in the interlayer insulating layers 90 and 91 and the number of wiring layers in the wiring structure 80 can be set arbitrarily. The first semiconductor substrate 60, the second semiconductor substrate 70, and the interlayer insulating layers 90 and 91 are, for example, continuously formed over at least the entire imaging region R1 and are shared by multiple pixels 10A.

[0064] The first pixel layer 1 and the second pixel layer 2 are bonded at a bonding surface 3. At the bonding surface 3, the insulating materials of the interlayer insulating layers 90 and 91 and the metal wirings of the wiring structure 80 (wires 81a and 82a in the example shown in FIG. 3) form a metal-dielectric hybrid junction. The bonding surface 3 is formed continuously over at least the entire imaging region R1, for example.

[0065] The first semiconductor substrate 60 has a first surface s1. The first surface s1 is a surface perpendicular to the thickness direction of the first semiconductor substrate 60 and is the top surface of the first semiconductor substrate 60. In the present embodiment, a plurality of transistors including the reset transistor 26 of each pixel 10A are arranged on the first surface s1.

[0066] The second semiconductor substrate 70 has a second surface s2 and a third surface s3 opposite to the second surface s2. The second surface s2 and the third surface s3 are surfaces perpendicular to the thickness direction of the second semiconductor substrate 70. The second surface s2 is the bottom surface of the second semiconductor substrate 70, and the third surface s3 is the top surface of the second semiconductor substrate 70. In the present embodiment, the multiple transistors arranged on the second surface s2 include the amplification transistor 22 and the address transistor 24 of each pixel 10A.

[0067] The second semiconductor substrate 70 is stacked on the first semiconductor substrate 60 so that the second surface s2 of the second semiconductor substrate 70 and the first surface s1 of the first semiconductor substrate 60 face each other. That is, the surface of the first semiconductor substrate 60 facing the second semiconductor substrate 70 is the first surface s1, and the surface of the second semiconductor substrate 70 facing the first semiconductor substrate 60 is the second surface s2. The first surface s1 and the second surface s2 face each other with interlayer insulating layers 90 and 91 sandwiched therebetween. Therefore, the multiple wiring layers and multiple plugs in the wiring structure 80 are located between the first surface s1 and the second surface s2. The photoelectric conversion unit 12 is located on the third surface s3 side of the second semiconductor substrate 70 and faces the first semiconductor substrate 60 across the second semiconductor substrate 70.

[0068] The interlayer insulating layer 90 is stacked on the first surface s1 of the first semiconductor substrate 60 via an insulating layer 51. The interlayer insulating layer 91 is stacked on the second surface s2 of the second semiconductor substrate 70 via an insulating layer 52. A bonding surface 3 is formed between the interlayer insulating layer 90 and the interlayer insulating layer 91.

[0069] The first semiconductor substrate 60 is a semiconductor substrate including at least a p-type semiconductor layer 63p. In the example shown in FIG. 3 , the first semiconductor substrate 60 includes a support substrate 61p and one or more semiconductor layers formed on the support substrate 61p. Here, a p-type silicon (Si) substrate is exemplified as the support substrate 61p. The first semiconductor substrate 60 includes a p-type semiconductor layer 62p on the support substrate 61p and a p-type semiconductor layer 63p on the p-type semiconductor layer 62p. A portion of the p-type semiconductor layer 63p is located on the first surface s1. Specifically, the upper surface of the p-type semiconductor layer 63p, i.e., the surface facing the second semiconductor substrate 70, constitutes at least a portion of the first surface s1. The p-type semiconductor layer 63p is located highest among the semiconductor layers included in the first semiconductor substrate 60, i.e., the semiconductor layer closest to the second semiconductor substrate 70. The p-type semiconductor layers 62p and 63p are semiconductor layers containing p-type impurities. In this specification, when holes are used as signal charges, p-type is an example of the second conductivity type. Each of the p-type semiconductor layers 62p and 63p is formed, for example, by ion implantation of impurities into a semiconductor layer formed by epitaxial growth.

[0070] The first semiconductor substrate 60 further includes n-type diffusion regions 64n and 65n. The n-type diffusion regions 64n and 65n are located in the p-type semiconductor layer 63p, more specifically, on the first surface s1 side of the p-type semiconductor layer 63p. The n-type diffusion regions 64n and 65n are impurity diffusion regions containing n-type impurities provided in the p-type semiconductor layer 63p. The n-type diffusion regions 64n and 65n are formed by injecting impurities into the p-type semiconductor layer 63p from the first surface s1 side. The impurity diffusion regions may also be simply referred to as impurity regions. In this specification, when holes are used as signal charges, n-type is an example of a first conductivity type.

[0071] The n-type diffusion region 64n is an example of a first impurity region electrically connected to the photoelectric conversion unit 12 via the through electrode pt, and functions as a charge accumulation region that temporarily accumulates signal charges generated by the photoelectric conversion unit 12. Also, in FIGS. 3 and 4B , the n-type diffusion region 64n is the source region or drain region of the reset transistor 26, and is a charge accumulation region. When the reset transistor 26 is turned on, it initializes the charge in the n-type diffusion region 64n and resets the potential of the n-type diffusion region 64n to the first voltage V1. That is, the n-type diffusion region 64n is configured so that the potential of the n-type diffusion region 64n is reset to the first voltage V1.

[0072] 3 and 4B , a reset transistor 26 is disposed on the first surface s1 of the first semiconductor substrate 60. The reset transistor 26 includes n-type diffusion regions 64n and 65n, an insulating layer 51 formed on the first surface s1 of the first semiconductor substrate 60, and a gate electrode 26e on the insulating layer 51. The reset transistor 26 includes the n-type diffusion region 64n as one of the source and drain, which accumulates the charge converted by the photoelectric conversion unit 12, and the n-type diffusion region 65n as the other of the source and drain. The reset transistor 26 also includes the gate electrode 26e on the insulating layer 51 as its gate. The reset transistor 26 includes the n-type diffusion region 64n as one of the source and drain, and is an example of a second transistor disposed on the first surface s1.

[0073] 3 and 4B, the first semiconductor substrate 60 includes an isolation region in the p-type semiconductor layer 63p. The isolation region is disposed between adjacent pixels 10A and electrically isolates the reset transistors 26 therebetween. The isolation region is provided, for example, around the reset transistor 26 in a plan view. The isolation region may be formed by implantation isolation in which impurities such as p-type impurities are implanted, or by shallow trench isolation (STI).

[0074] The second semiconductor substrate 70 is disposed between the first semiconductor substrate 60 and the photoelectric conversion unit 12. The second semiconductor substrate 70 includes at least a p-type semiconductor layer 71p. A portion of the p-type semiconductor layer 71p is located on the second surface s2. Specifically, the lower surface of the p-type semiconductor layer 71p, i.e., the surface on the first semiconductor substrate 60 side, constitutes at least a portion of the second surface s2. The second semiconductor substrate 70 may include two or more semiconductor layers. When the second semiconductor substrate 70 includes two or more semiconductor layers, the p-type semiconductor layer 71p is located lowest among the semiconductor layers included in the second semiconductor substrate 70, i.e., the semiconductor layer closest to the first semiconductor substrate 60.

[0075] The second semiconductor substrate 70 further includes n-type diffusion regions 72an, 72bn, and 72cn. The n-type diffusion regions 72an, 72bn, and 72cn are located in the p-type semiconductor layer 71p, more specifically, on the second surface s2 side of the p-type semiconductor layer 71p. The n-type diffusion regions 72an, 72bn, and 72cn are impurity diffusion regions containing n-type impurities provided in the p-type semiconductor layer 71p. The n-type diffusion regions 72an, 72bn, and 72cn are formed by implanting impurities into the p-type semiconductor layer 71p from the second surface s2 side.

[0076] As shown in FIGS. 3 and 4A, the amplifier transistor 22 and the address transistor 24 are disposed on the second surface s2 of the second semiconductor substrate 70.

[0077] The amplifier transistor 22 includes n-type diffusion regions 72an and 72bn, a portion of the insulating layer 52, and a gate electrode 22e on the insulating layer 52. The amplifier transistor 22 includes the n-type diffusion region 72an as one of the source and drain, and the n-type diffusion region 72bn as the other of the source and drain. The amplifier transistor 22 also includes the gate electrode 22e on the insulating layer 52 as its gate. The amplifier transistor 22 has a gate electrically connected to the photoelectric conversion unit 12 via a through electrode pt and is an example of a first transistor disposed on the second surface s2. The n-type diffusion region 72an is an example of a second impurity region that functions as the source or drain of the amplifier transistor 22, which is an example of a first transistor disposed on the second surface s2.

[0078] The address transistor 24 includes n-type diffusion regions 72bn and 72cn, a portion of the insulating layer 52, and a gate electrode 24e on the insulating layer 52. In the example shown in Figures 3 and 4A, the address transistor 24 shares the n-type diffusion region 72bn with the amplifier transistor 22, thereby being electrically connected to the amplifier transistor 22. The address transistor 24 includes the n-type diffusion region 72bn as one of the source and drain, and the n-type diffusion region 72cn as the other of the source and drain. The address transistor 24 also includes the gate electrode 24e on the insulating layer 52 as its gate.

[0079] The amplifier transistor 22 and the address transistor 24 formed on the second semiconductor substrate 70 may be transistors having a three-dimensional structure such as Fin-FETs, thereby improving the driving capabilities of the amplifier transistor 22 and the address transistor 24.

[0080] 3 and 4A, the second semiconductor substrate 70 includes an isolation region in the p-type semiconductor layer 71p. The isolation region is disposed between adjacent pixels 10A and electrically isolates pairs of amplifier transistors 22 and address transistors 24 between them. The isolation region is provided, for example, around the pair of amplifier transistors 22 and address transistors 24 in a plan view. The isolation region may be formed by implantation isolation in which impurities such as p-type impurities are implanted, or by shallow trench isolation (STI).

[0081] The gate electrodes 22e, 24e and 26e are formed of, for example, polysilicon doped with impurities such as n-type impurities.

[0082] As shown in FIG. 3 , the photoelectric conversion unit 12 is disposed on an insulating layer 53 on the third surface s3 of the second semiconductor substrate 70. The photoelectric conversion unit 12 includes a pixel electrode 12a formed on the insulating layer 53, a transparent electrode 12c facing the pixel electrode 12a, and a photoelectric conversion layer 12b located between the pixel electrode 12a and the transparent electrode 12c. The pixel electrode 12a is an example of a first electrode, and the transparent electrode 12c is an example of a second electrode. The photoelectric conversion layer 12b of the photoelectric conversion unit 12 is formed from an organic material or an inorganic material such as amorphous silicon. It receives incident light through the transparent electrode 12c and generates positive and negative charges through photoelectric conversion. The photoelectric conversion layer 12b is, for example, continuously formed across multiple pixels 10A. In other words, the photoelectric conversion layer 12b is shared by multiple pixels 10A. The photoelectric conversion layer 12b may also include a layer composed of an organic material and a layer composed of an inorganic material. The photoelectric conversion layer 12b may be provided separately for each pixel 10A.

[0083] The transparent electrode 12c is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. The transparent electrode 12c is typically formed continuously across multiple pixels 10A, similar to the photoelectric conversion layer 12b. That is, the transparent electrode 12c is shared by multiple pixels 10A. In other words, the photoelectric conversion unit 12 provided for each pixel 10A includes a different portion of the transparent electrode 12c for each pixel 10A. The transparent electrode 12c may be provided separately for each pixel 10A.

[0084] Although not shown in FIG. 3 , the transparent electrode 12c is connected to the aforementioned accumulation control line 39. During operation of the imaging device 100A, the potential of the accumulation control line 39 is controlled to make the potential of the transparent electrode 12c different from the potential of the pixel electrode 12a, thereby allowing the pixel electrode 12a to collect signal charges generated by photoelectric conversion. For example, the potential of the accumulation control line 39 is controlled so that the potential of the transparent electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, during operation of the imaging device 100A, a second voltage V2 different from the first voltage V1 is applied to the transparent electrode 12c via the accumulation control line 39. In other words, the transparent electrode 12c is configured to be applied with the second voltage V2. For example, the accumulation control line 39 is connected to a voltage supply circuit (not shown) that supplies the second voltage V2. The second voltage V2 is, for example, a positive voltage of approximately 10 V. As a result, of the hole-electron pairs generated in the photoelectric conversion layer 12b, the holes can be collected as signal charges by the pixel electrode 12a. The n-type diffusion region 64n is electrically connected to the pixel electrode 12a via the wiring structure 80 and the through electrode pt, and the signal charges collected by the pixel electrode 12a are accumulated in the n-type diffusion region 64n via the wiring structure 80 and the through electrode pt. When electrons are used as signal charges, a second voltage V2 is applied to the transparent electrode 12c such that the potential of the transparent electrode 12c is lower than the potential of the pixel electrode 12a.

[0085] The pixel electrode 12a is an electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to make it conductive. The pixel electrode 12a is spatially separated from the pixel electrodes 12a of other adjacent pixels 10A, and is thereby electrically isolated from the pixel electrodes 12a of other pixels 10A.

[0086] 3, the pixel 10A is provided with an insulating layer 51 covering the first surface s1, an insulating layer 52 covering the second surface s2, and an insulating layer 53 covering the third surface s3. The insulating layers 51, 52, and 53 are, for example, silicon oxide films. At least one of the insulating layers 51, 52, and 53 may have a stacked structure including multiple insulating films.

[0087] The through-electrodes pt penetrate the second semiconductor substrate 70 and the insulating layers 52 and 53, and electrically connect the photoelectric conversion unit 12 and the wiring structure 80. Specifically, the through-electrodes pt connect the pixel electrodes 12a and the wiring 82b. Although not shown in the figure, an insulating film such as a silicon oxide film is formed around the through-electrodes pt in the second semiconductor substrate 70, and the through-electrodes pt are not in contact with the second semiconductor substrate 70. The through-electrodes pt are formed, for example, from a metal such as copper or tungsten, polysilicon doped with impurities, or a metal compound such as a metal nitride or metal oxide.

[0088] In the example shown in FIG. 3 , the pixel 10A includes silicide layers 22s, 24s, 73a, 73b, and 73c. ​​The silicide layers 22s, 24s, 73a, 73b, and 73c are formed of metal silicide. The silicide layers 22s and 24s are disposed on the gate electrode 22e and the gate electrode 24e, respectively. The silicide layers 73a, 73b, and 73c are disposed on the n-type diffusion region 72an, the n-type diffusion region 72bn, and the n-type diffusion region 72cn, respectively. The wiring structure 80 is connected to the gate electrode 22e via the silicide layer 22s and to the gate electrode 24e via the silicide layer 24s. The wiring structure 80 is connected to the n-type diffusion region 72an via the silicide layer 73a and to the n-type diffusion region 72cn via the silicide layer 73c. This allows for low resistance in the connection between the wiring structure 80 and the amplifier transistor 22 and the address transistor 24. Note that the pixel 10A does not necessarily have to include the silicide layers 22s, 24s, 73a, 73b, and 73c.

[0089] The wiring structure 80 includes contact plugs cp1, cp2, and cp5 formed in an interlayer insulating layer 90, and contact plugs cp3, cp4, cp6, and cp7 formed in an interlayer insulating layer 91.

[0090] The contact plugs cp1 and cp2 are connected to the n-type diffusion regions 64n and 65n, respectively, through the insulating layer 51. The contact plug cp5 is connected to the gate electrode 26e.

[0091] Contact plugs cp3 and cp4 penetrate the insulating layer 52 and are connected to silicide layers 73a and 73c, respectively. A silicide layer 73a is disposed between the contact plug cp3 and the n-type diffusion region 72an, and the contact plug cp3 is electrically connected to the n-type diffusion region 72an via the silicide layer 73a. A silicide layer 73c is disposed between the contact plug cp4 and the n-type diffusion region 72cn, and the contact plug cp4 is electrically connected to the n-type diffusion region 72cn via the silicide layer 73c. ​​Contact plugs cp6 and cp7 are connected to silicide layers 22s and 24s, respectively. A silicide layer 22s is disposed between the contact plug cp6 and the gate electrode 22e, and the contact plug cp6 is electrically connected to the gate electrode 22e via the silicide layer 22s. A silicide layer 24s is disposed between the contact plug cp7 and the gate electrode 24e, and the contact plug cp7 is electrically connected to the gate electrode 24e via the silicide layer 24s.

[0092] The contact plugs cp1 and cp2 are formed of, for example, polysilicon doped with impurities such as n-type impurities. The contact plugs cp3, cp4, cp5, cp6, and cp7 are formed of, for example, a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide.

[0093] The wiring structure 80 includes connection structures 81 and 82 connected to each other at the junction surface 3. The connection structures 81 and 82 are part of the charge storage node FD. Each of the connection structures 81 and 82 is composed of a plurality of wirings and a plurality of plugs formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. The connection structure 81 is disposed in the interlayer insulating layer 90 and connected to the contact plug cp1. That is, the connection structure 81 connects the contact plug cp1 and the connection structure 82. The connection structure 82 is disposed in the interlayer insulating layer 91 and connected to the contact plug cp6 and the through-electrode pt. That is, the connection structure 82 connects the contact plug cp6, the through-electrode pt, and the connection structure 81. The n-type diffusion region 64n and the gate electrode 22e of the amplification transistor 22 are electrically connected to each other via the contact plugs cp1 and cp6, the connection structures 81 and 82, and the silicide layer 22s. The n-type diffusion region 64n and the pixel electrode 12a of the photoelectric conversion unit 12 are electrically connected to each other via a contact plug cp1, connection structures 81 and 82, and a through-electrode pt. The connection structure 82 includes a wiring 82b connected to the contact plug cp6 and the through-electrode pt. The gate electrode 22e and the pixel electrode 12a are electrically connected to each other via the silicide layer 22s, the contact plug cp6, the wiring 82b, and the through-electrode pt. The wiring 82b is included in, for example, the wiring layer in the wiring structure 80 that is closest to the gate electrode 22e.

[0094] The connection structure 81 includes a wiring 81a, and the connection structure 82 includes a wiring 82a. The wiring 81a and the wiring 82a are bonded at a bonding surface 3. Each of the wirings 81a and 82a is at least a part of one of a plurality of wiring layers and overlaps the n-type diffusion region 64n in a planar view. In the example shown in FIG. 4B , the wiring 81a is larger than the n-type diffusion region 64n in a planar view and completely covers the n-type diffusion region 64n. The wiring 82a is, for example, in the same position and size as the wiring 81a in a planar view.

[0095] The wiring structure 80 may also include, as part thereof, the above-mentioned vertical signal line 35, address signal line 34, power supply wiring 32, reset signal line 36, and reset voltage line 31. The vertical signal line 35, address signal line 34, power supply wiring 32, reset signal line 36, and reset voltage line 31 are connected to the n-type diffusion region 72cn, gate electrode 24e, n-type diffusion region 72an, gate electrode 26e, and n-type diffusion region 65n via contact plugs cp4, cp7, cp3, cp5, and cp2, respectively.

[0096] The connection structures 81 and 82, contact plugs cp1 and cp6, through electrode pt, pixel electrode 12a of the photoelectric conversion unit 12, gate electrode 22e of the amplifying transistor 22, silicide layer 22s, and n-type diffusion region 64n function as a charge storage region that stores signal charges generated by the photoelectric conversion unit 12.

[0097] In the example shown in FIG. 3 , the pixel 10A further includes a shield electrode 13, a protective film 14, a color filter 15, and a microlens 16. The shield electrode 13 is disposed between the pixel electrodes 12a of adjacent pixels 10A, and suppresses electrical coupling between adjacent pixels 10A by applying a predetermined voltage. The protective film 14 is disposed above the photoelectric conversion unit 12. The protective film 14 is an insulating film that protects the photoelectric conversion unit 12. The color filter 15 is disposed above the protective film 14. The color filter 15 is formed, for example, as an on-chip color filter by patterning. The color filter 15 is formed, for example, as a material such as a photosensitive resin in which a dye or pigment is dispersed. The microlens 16 is disposed above the color filter 15 and has a light-collecting function that collects light on the photoelectric conversion unit 12. The microlens 16 is formed, for example, as an on-chip microlens. The microlens 16 is formed, for example, as a material such as an ultraviolet-sensitive material.

[0098] The device structure of the pixel 10A in the imaging device 100A described above can be manufactured using, for example, a general semiconductor manufacturing process.

[0099] Specifically, first, a first semiconductor substrate 60 is prepared, and a reset transistor 26 is formed on a first surface s1 of the first semiconductor substrate 60. Furthermore, an interlayer insulating layer 90 and a part of a wiring structure 80 are formed on the first surface s1 side of the first semiconductor substrate 60, thereby forming a first pixel layer 1. Next, a second semiconductor substrate 70 is prepared, and an amplifier transistor 22 and an address transistor 24 are formed on a second surface s2 of the second semiconductor substrate 70. Furthermore, an interlayer insulating layer 91 and the remaining part of the wiring structure 80 are formed on the second surface s2 side of the second semiconductor substrate 70, thereby forming a second pixel layer 2. A silicide process may be used to form the second pixel layer 2.

[0100] Next, the first pixel layer 1 and the second pixel layer 2 are stacked so that the first surface s1 and the second surface s2 face each other, and the first pixel layer 1 and the second pixel layer 2 are bonded at the bonding surface 3. That is, the first pixel layer 1 and the second pixel layer 2 are stacked and bonded so that the interlayer insulating layers 90 and 91 are sandwiched between the first semiconductor substrate 60 and the second semiconductor substrate 70. Then, after forming the insulating layer 53 and the through-electrode pt, the photoelectric conversion unit 12 and the shield electrode 13 are formed on the third surface s3 side of the second semiconductor substrate 70. Finally, the device structure of the pixel 10A can be formed by forming the protective film 14, the color filter 15, and the microlens 16 on the photoelectric conversion unit 12.

[0101] As described above, the imaging device 100A according to the present embodiment includes a first semiconductor substrate 60 having a first surface s1 on which the reset transistor 26 is arranged, a second semiconductor substrate 70 having a second surface s2 on which the amplification transistor 22 is arranged and a third surface s3 opposite the second surface s2, a photoelectric conversion unit 12, and a through-electrode pt penetrating the second semiconductor substrate 70. The first semiconductor substrate 60 and the second semiconductor substrate 70 are stacked such that the first surface s1 and the second surface s2 face each other. The photoelectric conversion unit 12 is located on the third surface s3 side of the second semiconductor substrate 70. The first semiconductor substrate 60 is electrically connected to the photoelectric conversion unit 12 via the through-electrode pt and includes an n-type diffusion region 64n that accumulates electric charges converted by the photoelectric conversion unit 12.

[0102] This allows transistors necessary for driving the imaging device 100A, which are included in circuits that detect signals of the charges converted by the photoelectric conversion unit 12, to be distributed across the first semiconductor substrate 60 and the second semiconductor substrate 70, thereby reducing the size of the imaging device 100A. Furthermore, the n-type diffusion region 64n that accumulates the charges converted by the photoelectric conversion unit 12 is included in the first semiconductor substrate 60, which is farther from the photoelectric conversion unit 12 than the second semiconductor substrate 70, so that charge generation caused by light not absorbed by the photoelectric conversion unit 12 being incident on the n-type diffusion region 64n is suppressed. Therefore, noise caused by charge generation unrelated to photoelectric conversion by the photoelectric conversion unit 12 is suppressed, thereby reducing noise in the imaging device 100A.

[0103] Furthermore, because the first surface s1 and the second surface s2 face each other, even when a transistor arranged on the first surface s1 and a transistor arranged on the second surface s2 are connected by a wiring structure 80, there is no need to form an electrode that penetrates the second semiconductor substrate 70, making it easy to form the imaging device 100A. This also increases the flexibility of the layout of the wiring structure 80. Furthermore, because the first surface s1 and the second surface s2 face each other, the connection structures 81 and 82 that connect the amplification transistor 22 and the reset transistor 26 and function as charge storage regions that store the electric charge converted by the photoelectric conversion unit 12 can be shortened. This reduces the parasitic capacitance between the connection structures 81 and 82 between adjacent pixels 10A. As a result, the capacitance of the charge storage region can be reduced, which increases the change in potential due to the accumulation of signal charge and increases the conversion gain of the charge storage region. Therefore, the signal corresponding to the electric charge generated by photoelectric conversion can be increased, reducing the influence of noise, thereby achieving low noise in the imaging device 100A.

[0104] [Layout of Peripheral Circuits] Next, the layout of the peripheral circuits 40 of the image pickup device 100A according to this embodiment will be described.

[0105] FIG. 5 is a cross-sectional view showing an example of the arrangement of the peripheral circuit 40 in the image pickup device 100A according to the present embodiment.

[0106] As shown in FIG. 5 , at least a portion of the peripheral circuit 40 is disposed on the first surface s1 of the first semiconductor substrate 60 and the second surface s2 of the second semiconductor substrate 70 in the peripheral region R2. In the example shown in FIG. 5 , transistors included in the peripheral circuit 40 are formed on each of the first surface s1 and the second surface s2. In this manner, by disposing at least a portion of the peripheral circuit 40 on the first surface s1 of the first semiconductor substrate 60 and the second surface s2 of the second semiconductor substrate 70, it is possible to connect the multiple pixels 10A to at least a portion of the peripheral circuit 40 without using electrodes that penetrate the first semiconductor substrate 60 and / or the second semiconductor substrate 70. Note that as long as at least a portion of the peripheral circuit 40 is disposed on the first surface s1 or the second surface s2, a portion of the peripheral circuit 40 may be disposed in a location other than the first surface s1 or the second surface s2.

[0107] 5 , the first semiconductor substrate 60 further includes, in the peripheral region R2, an n-type semiconductor layer 111n on the p-type semiconductor layer 62p, an n-type semiconductor layer 112n on the n-type semiconductor layer 111n, and a p-type semiconductor layer 113p located in a region different from the n-type semiconductor layer 112n on the n-type semiconductor layer 111n. In the peripheral region R2, a contact plug cp8 serving as a p-well contact and a contact plug cp9 serving as an n-well contact are provided on the first surface s1. In the example shown in FIG. 5 , a voltage is applied to the p-type semiconductor layer 63p via the contact plug cp8, and a voltage is applied to the n-type semiconductor layer 112n via the contact plug cp9. In the peripheral region R2, pad electrodes p1, p2, and p3 are provided on the third surface s3 side of the second semiconductor substrate 70. 5, the pad electrodes p1, p2, and p3 are electrodes for supplying a voltage to the first semiconductor substrate 60, but may also be pad electrodes for supplying a voltage to the peripheral circuit 40. Furthermore, a pad electrode electrically connected to the second semiconductor substrate 70 may be provided in the peripheral region R2.

[0108] 5, at least a portion of the peripheral circuit 40 is disposed on the first surface s1 of the first semiconductor substrate 60 and the second surface s2 of the second semiconductor substrate 70, but this is not limiting. Fig. 6 is a cross-sectional view showing another example of the arrangement of the peripheral circuit 40 in the image pickup device 100A according to the present embodiment.

[0109] As shown in FIG. 6 , the imaging device 100A may further include a peripheral circuit layer 4. The peripheral circuit layer 4 includes a third semiconductor substrate 120 and an interlayer insulating layer 92. In the example shown in FIG. 6 , the first semiconductor substrate 60 does not include a support substrate 61p or a p-type semiconductor layer 62p. The first semiconductor substrate 60 is stacked on the third semiconductor substrate 120 so that a fifth surface s5, which is the upper surface of the third semiconductor substrate 120, and a fourth surface s4, which is opposite the first surface s1 of the first semiconductor substrate 60, face each other via the interlayer insulating layer 92. A plurality of transistors included in the peripheral circuit 40 are disposed on the fifth surface s5 of the third semiconductor substrate 120. That is, at least a portion of the peripheral circuit 40 is disposed on the fifth surface s5 of the third semiconductor substrate 120. By providing at least a portion of the peripheral circuit 40 on the third semiconductor substrate 120, on which the first semiconductor substrate 60 and the second semiconductor substrate 70 are stacked, the imaging device 100A can be miniaturized.

[0110] 6 , the third semiconductor substrate 120 includes a p-type semiconductor layer 122p on the support substrate 121p, an n-type semiconductor layer 123n on the p-type semiconductor layer 122p, a p-type semiconductor layer 124p located in a region different from the n-type semiconductor layer 123n on the p-type semiconductor layer 122p, a p-type semiconductor layer 125p on the n-type semiconductor layer 123n, and an n-type semiconductor layer 126n located in a region different from the p-type semiconductor layer 125p on the n-type semiconductor layer 123n.

[0111] Furthermore, a contact plug cp10 which is a p-well contact and a contact plug cp11 which is an n-well contact are provided on the fifth surface s5. In the example shown in FIG. 6, a voltage is applied to the p-type semiconductor layer 124p via the contact plug cp10, and a voltage is applied to the n-type semiconductor layer 126n via the contact plug cp11.

[0112] 6 , in the peripheral region R2, pad electrodes p4 and p5 are provided on the third surface s3 side of the second semiconductor substrate 70. The pad electrodes p4 and p5 are, for example, electrodes for supplying a voltage to the third semiconductor substrate 120 or the peripheral circuit 40. Furthermore, a pad electrode electrically connected to the first semiconductor substrate 60 or the second semiconductor substrate 70 may be provided in the peripheral region R2.

[0113] [Modifications] Next, a description will be given of modifications of embodiment 1. The following description will focus on differences from embodiment 1, and descriptions of commonalities will be omitted or simplified.

[0114] Fig. 7 is a schematic cross-sectional view of the device structure of pixel 11A according to this modification. Fig. 8A is a plan view showing the layout within pixel 11A according to this modification. Fig. 8B is another plan view showing the layout within pixel 11A according to this modification. Fig. 7 is a cross-sectional view of pixel 11A cut along line VII-VII in Figs. 8A and 8B.

[0115] FIG. 8A schematically illustrates the arrangement of each element formed on the second semiconductor substrate 70 when viewed from below the second semiconductor substrate 70 shown in FIG. 7 . Specifically, FIG. 8A illustrates the arrangement of the amplifier transistor 22, address transistor 24, and through-electrode pt1 included in the pixel 11A on the second semiconductor substrate 70. Also, in FIG. 8A , the outline of the through-electrode pt1, which is not actually visible because it overlaps with the gate electrode 22e, is indicated by a dashed line. FIG. 8B schematically illustrates the arrangement of each element formed on the first semiconductor substrate 60 when viewed from above the first semiconductor substrate 60 shown in FIG. 7 . Specifically, FIG. 8B illustrates the arrangement of the reset transistor 26 included in the pixel 11A. Also, in FIG. 8B , the outline of the wiring 81a is indicated by a dashed line. Also, FIGS. 8A and 8B illustrate the arrangement of contact plugs connected to each transistor. Note that the layout of the pixel 11A shown in FIG. 8B is the same as the layout of the pixel 10A shown in FIG. 4B .

[0116] 7, 8A, and 8B, pixel 11A of the imaging device according to this modification includes, in place of the through electrode pt, a through electrode pt1 that is connected to a different destination from the through electrode pt, as compared to pixel 10A. Note that in Fig. 7, the through electrode pt1 is indicated by a dashed line because it is not shown in the cross section.

[0117] The through electrode pt1 penetrates the second semiconductor substrate 70 and the insulating layers 52 and 53, and connects the pixel electrode 12a and the gate electrode 22e of the photoelectric conversion unit 12. Although not shown in the figure, an insulating film such as a silicon oxide film is formed around the through electrode pt1 in the second semiconductor substrate 70, and the through electrode pt1 and the second semiconductor substrate 70 are not in contact with each other.

[0118] The through electrode pt1 is connected to the surface of the gate electrode 22e on the second surface s2 side (i.e., the upper surface). The connection position between the through electrode pt1 and the gate electrode 22e does not overlap with the channel region of the amplification transistor 22. In the pixel 11A, the n-type diffusion region 64n and the pixel electrode 12a of the photoelectric conversion unit 12 are electrically connected to each other via the contact plug cp1, the connection structures 81 and 82, the silicide layer 22s, the gate electrode 22e, and the through electrode pt1. The gate electrode 22e and the pixel electrode 12a are electrically connected to each other via the through electrode pt1, without the wiring structure 80. In other words, the through electrode pt1 directly connects the gate electrode 22e and the pixel electrode 12a.

[0119] The connection structures 81 and 82, contact plugs cp1 and cp6, through electrode pt1, pixel electrode 12a of the photoelectric conversion unit 12, gate electrode 22e of the amplification transistor 22, silicide layer 22s, and n-type diffusion region 64n correspond to the above-mentioned charge storage node FD and function as a charge storage region that stores signal charges generated by the photoelectric conversion unit 12.

[0120] In this manner, in the pixel 11A according to this modification, the length of the through electrode pt1 can be shortened by connecting the through electrode pt1 to the gate electrode 22e and the pixel electrode 12a, which reduces the parasitic capacitance of the through electrode pt1, which is part of the charge storage region, and therefore increases the conversion gain of the charge storage region, thereby enabling the imaging device to achieve low noise.

[0121] Although the above description has been made regarding a configuration in which the through electrode pt in pixel 10A is changed to through electrode pt1, the through electrode pt in pixels according to each embodiment described later may be changed to through electrode pt1. That is, in pixels according to each embodiment described later, the pixel electrode 12a and the gate electrode 22e may also be connected by the through electrode pt1.

[0122] (Embodiment 2) Next, a description will be given of embodiment 2. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0123] Fig. 9 is a diagram showing a circuit configuration of a pixel 10B according to the present embodiment. Fig. 10 is a schematic cross-sectional view of a device structure of a pixel 10B according to the present embodiment. Fig. 11A is a plan view showing a layout within a pixel 10B according to the present embodiment. Fig. 11B is another plan view showing a layout within a pixel 10B according to the present embodiment. Fig. 10 is a cross-sectional view of the pixel 10B cut along line X-X in Figs. 11A and 11B.

[0124] FIG. 11A schematically illustrates the arrangement of each element formed on the second semiconductor substrate 70 when viewed from below. Specifically, FIG. 11A illustrates the arrangement of the amplifier transistor 22, address transistor 24, and through-electrode pt included in pixel 10B on the second semiconductor substrate 70. Also, in FIG. 11A, the outline of the wiring 82b is indicated by a dashed line. FIG. 11B schematically illustrates the arrangement of each element formed on the first semiconductor substrate 60B when viewed from above. Specifically, FIG. 11B illustrates the arrangement of the reset transistor 26 and overflow transistor 28 included in pixel 10B. Also, FIGS. 11A and 11B illustrate the arrangement of contact plugs connected to each transistor. The layout of pixel 10B illustrated in FIG. 11A is the same as the layout of pixel 10A illustrated in FIG. 4A.

[0125] The imaging device according to the present embodiment has a configuration in which the plurality of pixels 10A of the imaging device 100A according to Embodiment 1 are replaced with a plurality of pixels 10B. Each of the plurality of pixels 10B has, for example, the circuit configuration and device structure shown in FIGS.

[0126] 9 to 11B differs from pixel 10A according to embodiment 1 mainly in that pixel 10B further includes overflow transistor 28. Specifically, as shown in FIGS. 9 to 11B, pixel 10B differs from pixel 10A according to embodiment 1 in that pixel 10B includes a first semiconductor substrate 60B on which reset transistor 26 and overflow transistor 28 are formed, instead of first semiconductor substrate 60 on which reset transistor 26 is formed. Pixel 10B also differs from pixel 10A according to embodiment 1 in that pixel 10B includes a wiring structure 80B instead of wiring structure 80.

[0127] As schematically shown in FIG. 9 , the overflow transistor 28 is formed on the first semiconductor substrate 60B of the first pixel layer 1. The overflow transistor 28 may be, for example, an N-channel MOSFET. The gate and one of the source and drain of the overflow transistor 28 are connected to the charge storage node FD. The other of the source and drain of the overflow transistor 28 is connected to a voltage line 37 to which a predetermined voltage VOF is applied. When excessive signal charge accumulates in the charge storage node FD and the potential of the charge storage node FD exceeds a predetermined potential, the overflow transistor 28 turns on, and the excess signal charge is discharged via the overflow transistor 28. In other words, the potential of the charge storage region that accumulates the signal charge can be clipped. This protects transistors (e.g., the amplifier transistor 22 and the reset transistor 26) connected to the charge storage node FD and improves the reliability of the imaging device. The predetermined potential can be adjusted by setting the voltage VOF. The voltage VOF is, for example, about 0.5 to 1 V, but is not particularly limited as long as it is set according to the characteristics of the overflow transistor, for example, the threshold voltage.

[0128] 10 , the first semiconductor substrate 60B has a configuration in which an n-type diffusion region 66n is added to the first semiconductor substrate 60. The n-type diffusion region 66n is located in the p-type semiconductor layer 63p, more specifically, on the first surface s1 side of the p-type semiconductor layer 63p. The n-type diffusion region 66n is an impurity diffusion region containing n-type impurities provided in the p-type semiconductor layer 63p. The n-type diffusion region 66n is formed by implanting impurities into the p-type semiconductor layer 63p from the first surface s1 side.

[0129] As shown in FIGS. 10 and 11B , the reset transistor 26 and the overflow transistor 28 are disposed on the first surface s1 of the first semiconductor substrate 60B. The overflow transistor 28 includes n-type diffusion regions 64n and 66n, an insulating layer 51 formed on the first surface s1 of the first semiconductor substrate 60B, and a gate electrode 28e on the insulating layer 51. In the example shown in FIGS. 10 and 11B , the overflow transistor 28 shares the n-type diffusion region 64n with the reset transistor 26. The overflow transistor 28 includes the n-type diffusion region 64n as one of the source and drain, and the n-type diffusion region 66n as the other of the source and drain. The overflow transistor 28 also includes the gate electrode 28e on the insulating layer 51 as its gate. The gate electrode 28e is formed of, for example, polysilicon doped with impurities such as n-type impurities.

[0130] 10 and 11B, the first semiconductor substrate 60B includes an isolation region in the p-type semiconductor layer 63p. The isolation region is disposed between adjacent pixels 10B and electrically isolates the pairs of reset transistor 26 and overflow transistor 28 therebetween. The isolation region is provided, for example, around the pair of reset transistor 26 and overflow transistor 28 in a plan view. The isolation region may be formed by implantation isolation in which impurities such as p-type impurities are implanted, or by shallow trench isolation (STI).

[0131] The wiring structure 80B has a configuration in which the connection structure 81 of the above-described wiring structure 80 is changed to a connection structure 83, and contact plugs cp12 and cp13 formed in the interlayer insulating layer 90 are further added.

[0132] The contact plug cp12 penetrates the insulating layer 51 and is connected to the n-type diffusion region 66n. The contact plug cp13 is connected to the gate electrode 28e. The contact plug cp12 is made of, for example, polysilicon doped with impurities such as n-type impurities. The contact plug cp13 is made of, for example, a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide.

[0133] The wiring structure 80B includes connection structures 83 and 82 connected to each other at the junction surface 3. The connection structures 83 and 82 are part of the charge storage node FD. The connection structure 83 is composed of multiple wirings and multiple plugs formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. The connection structure 83 is disposed in the interlayer insulating layer 90 and connected to contact plugs cp1 and cp13. That is, the connection structure 83 connects the contact plugs cp1, cp13, and the connection structure 82. The n-type diffusion region 64n and the gate electrode 22e of the amplification transistor 22 are electrically connected to each other via the contact plugs cp1 and cp6, the connection structures 83 and 82, and the silicide layer 22s. The n-type diffusion region 64n and the pixel electrode 12a of the photoelectric conversion unit 12 are electrically connected to each other via the contact plug cp1, the connection structures 83 and 82, and the through-electrode pt.

[0134] The wiring structure 80B may include the above-described voltage line 37. The voltage line 37 is connected to the n-type diffusion region 66n via a contact plug cp12.

[0135] In pixel 10B, the connection structures 83 and 82, contact plugs cp1, cp6 and cp13, the through electrode pt, the pixel electrode 12a of the photoelectric conversion unit 12, the gate electrode 22e of the amplifying transistor 22, the silicide layer 22s, and the n-type diffusion region 64n function as a charge storage region that stores the signal charge generated by the photoelectric conversion unit 12.

[0136] 11B, the gate length L28 of the overflow transistor 28 is shorter than the gate length L26 of the reset transistor 26. Therefore, in a plan view, the area of ​​the gate electrode 28e is smaller than the area of ​​the gate electrode 26e. This reduces the capacitance of the gate electrode 28e, which functions as a charge storage region, and increases the conversion gain of the signal charge.

[0137] The layout within pixel 10B is not limited to the above example, and is not particularly limited. Fig. 11C is yet another plan view showing the layout within pixel 10B according to the present embodiment. Fig. 11C schematically shows another example of the arrangement of elements formed on first semiconductor substrate 60B when first semiconductor substrate 60B is viewed from above, which is different from that shown in Fig. 11B.

[0138] 11C , the gate electrode 26e has a bent shape in plan view. Furthermore, in plan view, the n-type diffusion region 64n and the n-type diffusion region 65n are arranged so as to straddle the bent portion of the gate electrode 26e, i.e., so that the channel region of the reset transistor 26 is also bent. This allows the gate length L26 of the reset transistor 26 to be increased, thereby suppressing leakage current when the reset transistor 26 is off.

[0139] (Embodiment 3) Next, a description will be given of embodiment 3. The following description will focus on the differences from embodiments 1 and 2, and the description of commonalities will be omitted or simplified.

[0140] Fig. 12 is a diagram showing a circuit configuration of a pixel 10C according to the present embodiment. Fig. 13 is a schematic cross-sectional view of a device structure of the pixel 10C according to the present embodiment. Fig. 14A is a plan view showing a layout within the pixel 10C according to the present embodiment. Fig. 14B is another plan view showing a layout within the pixel 10C according to the present embodiment. Fig. 13 is a cross-sectional view of the pixel 10C taken along line XIII-XIII in Figs. 14A and 14B.

[0141] FIG. 14A schematically illustrates the arrangement of each element formed on the second semiconductor substrate 70 when viewed from below the second semiconductor substrate 70 shown in FIG. 13 . Specifically, FIG. 14A illustrates the arrangement of the amplifier transistor 22, address transistor 24, and through-electrode pt included in pixel 10C on the second semiconductor substrate 70. Also, in FIG. 14A , the outline of the wiring 82b is indicated by a dashed line. FIG. 14B schematically illustrates the arrangement of each element formed on the first semiconductor substrate 60C when viewed from above the first semiconductor substrate 60C shown in FIG. 13 . Specifically, FIG. 14B illustrates the arrangement of the reset transistor 26C included in pixel 10C. Also, FIGS. 14A and 14B illustrate the arrangement of contact plugs connected to each transistor. The layout of pixel 10C shown in FIG. 14A is the same as the layout of pixel 10A shown in FIG. 4A .

[0142] The imaging device according to the present embodiment has a configuration in which the pixels 10A of the imaging device 100A according to Embodiment 1 are replaced with a plurality of pixels 10C. Each of the pixels 10C has, for example, the circuit configuration and device structure shown in FIGS. 12 to 14B.

[0143] 12 to 14B differs from pixel 10A according to embodiment 1 mainly in that pixel 10C includes a reset transistor 26C that uses a P-channel MOSFET instead of reset transistor 26. Specifically, as shown in FIGS. 12 to 14B , pixel 10C differs from pixel 10A according to embodiment 1 in that pixel 10C includes a first semiconductor substrate 60C on which reset transistor 26C is formed, instead of first semiconductor substrate 60 on which reset transistor 26 is formed.

[0144] 12, the pixel 10C has a circuit configuration in which the reset transistor 26 of the pixel 10A shown in FIG. 2 is replaced with a reset transistor 26C. The reset transistor 26C is formed on a first semiconductor substrate 60C of the first pixel layer 1. A P-channel MOSFET is used for the reset transistor 26C. One of the source and drain of the reset transistor 26C is connected to the charge storage node FD. The gate of the reset transistor 26C is connected to a reset signal line 36. The other of the source and drain of the reset transistor 26C is connected to a reset voltage line 31.

[0145] The first semiconductor substrate 60C is a semiconductor substrate including at least an n-type semiconductor layer 63n. In the example shown in FIG. 13 , the first semiconductor substrate 60C includes a support substrate 61n and one or more semiconductor layers formed on the support substrate 61n. Here, an n-type silicon substrate is used as the support substrate 61n. The first semiconductor substrate 60C includes an n-type semiconductor layer 62n on the support substrate 61n and an n-type semiconductor layer 63n on the n-type semiconductor layer 62n. A portion of the n-type semiconductor layer 63n is located on the first surface s1. Specifically, the upper surface of the n-type semiconductor layer 63n, i.e., the surface facing the second semiconductor substrate 70, constitutes at least a portion of the first surface s1. The n-type semiconductor layer 63n is located highest among the semiconductor layers included in the first semiconductor substrate 60C, i.e., the semiconductor layer closest to the second semiconductor substrate 70. The n-type semiconductor layers 62n and 63n are semiconductor layers containing n-type impurities. Each of the n-type semiconductor layers 62n and 63n is formed by, for example, ion implantation of impurities into a semiconductor layer formed by epitaxial growth.

[0146] During operation of the imaging device according to this embodiment, a third voltage V3 is applied to the n-type semiconductor layer 63n. That is, the n-type semiconductor layer 63n is configured to be applied with the third voltage V3. The potential of the n-type semiconductor layer 63n is controlled, for example, via a pad electrode provided outside the imaging region R1. The pad electrode is connected, for example, to a voltage supply circuit (not shown) that supplies the third voltage V3. The third voltage may be applied to the n-type semiconductor layer 63n via the support substrate 61n or the n-type semiconductor layer 62n.

[0147] The first semiconductor substrate 60C further includes p-type diffusion regions 64p and 65p. The p-type diffusion regions 64p and 65p are located in the n-type semiconductor layer 63n, more specifically, on the first surface s1 side of the n-type semiconductor layer 63n. The p-type diffusion regions 64p and 65p are impurity diffusion regions containing p-type impurities provided in the n-type semiconductor layer 63n. The p-type diffusion regions 64p and 65p are formed by implanting impurities into the n-type semiconductor layer 63n from the first surface s1 side.

[0148] The p-type diffusion region 64p is an example of a first impurity region electrically connected to the photoelectric conversion unit 12 via the through electrode pt and functions as a charge accumulation region that temporarily accumulates signal charges generated by the photoelectric conversion unit 12. Also, in FIGS. 13 and 14B , the p-type diffusion region 64p is the source or drain region of the reset transistor 26C and is a charge accumulation region. When the reset transistor 26C is turned on, it initializes the charge in the p-type diffusion region 64p and resets the potential of the p-type diffusion region 64p to the first voltage V1. That is, the p-type diffusion region 64p is configured so that the potential of the p-type diffusion region 64p is reset to the first voltage V1.

[0149] 13 and 14B , a reset transistor 26C is disposed on the first surface s1 of the first semiconductor substrate 60C. The reset transistor 26C includes p-type diffusion regions 64p and 65p, an insulating layer 51 formed on the first surface s1 of the first semiconductor substrate 60C, and a gate electrode 26e on the insulating layer 51. The reset transistor 26C includes the p-type diffusion region 64p, which accumulates photocharges converted by the photoelectric conversion unit 12, as one of the source and drain, and the p-type diffusion region 65p as the other of the source and drain. The reset transistor 26C also includes the gate electrode 26e on the insulating layer 51 as its gate.

[0150] 13 and 14B, the first semiconductor substrate 60C includes an isolation region in the n-type semiconductor layer 63n. The isolation region is disposed between adjacent pixels 10C and electrically isolates the reset transistors 26C therebetween. The isolation region is provided, for example, around the reset transistor 26C in a plan view. The isolation region may be formed by implantation isolation in which impurities such as n-type impurities are implanted, or by shallow trench isolation (STI).

[0151] During operation of the imaging device according to this embodiment, first, the reset transistor 26C is turned on, resetting the potential of the p-type diffusion region 64p, which accumulates signal charge, to the first voltage V1. In this embodiment, the signal charge is a hole, as described above. Then, the reset transistor 26C is turned off, ending the reset operation. When the imaging device is driven by a rolling shutter system, for example, a second voltage V2 is constantly applied to the transparent electrode 12c, such that holes generated by photoelectric conversion in the photoelectric conversion layer 12b are collected in the pixel electrode 12a. The exposure period begins simultaneously with the end of the reset operation. When the imaging device is driven by a global shutter system, for example, a voltage is applied to the transparent electrode 12c during the reset operation, such that movement of holes to the pixel electrode 12a is substantially prevented. After the reset transistor 26C is turned off, the second voltage V2 is applied to the transparent electrode 12c, beginning the exposure period. During these exposure periods, holes generated by light incident on the photoelectric conversion unit 12 are accumulated in the p-type diffusion region 64p via the pixel electrode 12a. As a result, the potential of the p-type diffusion region 64p increases as holes accumulate in the p-type diffusion region 64p. During operation of the imaging device, a third voltage V3 is applied to the n-type semiconductor layer 63n at least during the exposure period. After the exposure period ends, a signal corresponding to the potential of the charge accumulation region including the p-type diffusion region 64p is read out.

[0152] In the imaging device according to this embodiment, the p-type diffusion region 64p, which is part of the charge accumulation region, is a p-type impurity diffusion region provided in the n-type semiconductor layer 63n, which is an n-well, and the first voltage V1, the second voltage V2, and the third voltage V3 have a predetermined relationship, so that clipping of the potential of the charge accumulation region is possible without providing the overflow transistor 28 described in the second embodiment.

[0153] In the imaging device according to the present embodiment, the second voltage V2 is greater than the first voltage V1, and the third voltage V3 is a voltage between the first voltage V1 and the second voltage V2. That is, the first voltage V1 < the third voltage V3 < the second voltage V2. For ease of explanation, it is assumed here that the first voltage V1 is 1.5 V, the second voltage V2 is 10 V, and the third voltage V3 is 2.8 V, as an example.

[0154] At the start of the exposure period, the potential of the p-type diffusion region 64p is 1.5 V because it has been reset to the first voltage V1. Furthermore, because the third voltage V3 applied to the n-type semiconductor layer 63n is 2.8 V, the voltage applied to the p-n junction between the p-type diffusion region 64p (a p-type impurity diffusion region) and the n-type semiconductor layer 63n (an n-well) is reverse biased, and holes do not move from the p-type diffusion region 64p to the n-type semiconductor layer 63n. During the exposure period, holes accumulate in the p-type diffusion region 64p as light enters the photoelectric conversion unit 12, causing the potential of the p-type diffusion region 64p to rise. As the potential of the p-type diffusion region 64p rises with the accumulation of holes in the p-type diffusion region 64p, the difference with the potential of the n-type semiconductor layer 63n becomes smaller, and the voltage applied to the p-n junction between the p-type diffusion region 64p and the n-type semiconductor layer 63n approaches a forward bias. Therefore, even if an excessive number of holes accumulate in the p-type diffusion region 64p, the holes accumulated in the p-type diffusion region 64p can be released to the n-type semiconductor layer 63n, and the potential of the p-type diffusion region 64p is clipped at around 2.8 V. This prevents damage to the amplification transistor 22 and other components due to an excessive rise in the potential of the p-type diffusion region 64p, thereby improving the reliability of the imaging device. Furthermore, because the potential of the p-type diffusion region 64p is clipped without providing an overflow transistor 28, the gate electrode 28e is not added as a capacitance of the charge storage region, and a decrease in the conversion gain of signal charges is prevented while improving reliability. Furthermore, miniaturization of the pixel 10C is also possible.

[0155] In this embodiment, the reset transistor 26C formed on the first semiconductor substrate 60C is a P-channel MOSFET, whereas the amplifier transistor 22 and the address transistor 24 are N-channel MOSFETs because they are formed on the second semiconductor substrate 70. Specifically, the amplifier transistor 22 and the address transistor 24 include, as their source and drain, n-type impurity diffusion regions formed in the p-type semiconductor layer 71p, which is a p-well. This allows the amplifier transistor 22 and the address transistor 24 to use electrons as carriers, thereby improving the driving capabilities of the amplifier transistor 22 and the address transistor 24.

[0156] Although the above description deals with an example in which the signal charges are holes, the signal charges may also be electrons. In this case, the first semiconductor substrate 60 on which the reset transistor 26 is formed is used instead of the first semiconductor substrate 60C on which the reset transistor 26C is formed. When the signal charges are electrons, the second voltage V2 is smaller than the first voltage V1, and the third voltage V3 applied to the p-type semiconductor layer 63p is a voltage between the first voltage V1 and the second voltage V2. In other words, the second voltage V2 < the third voltage V3 < the first voltage V1. As a result, even if excessive electrons accumulate in the n-type diffusion region 64n, which is part of the charge accumulation region, causing a drop in the potential of the charge accumulation region, the electrons can be released to the p-type semiconductor layer 63p on which the n-type diffusion region 64n is formed, and the potential of the n-type diffusion region 64n is clipped by the third voltage V3. In this case, an example of the voltages is as follows: the first voltage V1 is 1.5 V, the second voltage V2 is −10 V, and the third voltage V3 is 0 V. In addition, as another example of the voltages in this case, the first voltage V1 is 11.5V, the second voltage V2 is 0V, and the third voltage V3 is 10V.

[0157] (Fourth Embodiment) Next, a description will be given of a fourth embodiment. The following description will focus on the differences from the first to third embodiments, and the description of the commonalities will be omitted or simplified.

[0158] Fig. 15 is a diagram showing a circuit configuration of a pixel 10D according to the present embodiment. Fig. 16 is a schematic cross-sectional view of a device structure of a pixel 10D according to the present embodiment. Fig. 17A is a plan view showing a layout within a pixel 10D according to the present embodiment. Fig. 17B is another plan view showing a layout within a pixel 10D according to the present embodiment. Fig. 16 is a cross-sectional view of the pixel 10D when cut along line XVI-XVI in Figs. 17A and 17B.

[0159] FIG. 17A schematically illustrates the arrangement of each element formed on the second semiconductor substrate 70 when the second semiconductor substrate 70 shown in FIG. 16 is viewed from below. Specifically, FIG. 17A illustrates the arrangement of the amplifier transistor 22, address transistor 24, and through-electrode pt included in the pixel 10D on the second semiconductor substrate 70. Also, in FIG. 17A, the outline of the wiring 82b is indicated by a dashed line. FIG. 17B schematically illustrates the arrangement of each element formed on the first semiconductor substrate 60D when the first semiconductor substrate 60D shown in FIG. 16 is viewed from above. Specifically, FIG. 17B illustrates the arrangement of the reset transistor 26, overflow transistor 28, and bandwidth control transistor 30 included in the pixel 10D. Also, FIGS. 17A and 17B illustrate the arrangement of contact plugs connected to each transistor.

[0160] The imaging device according to the present embodiment has a configuration in which the pixels 10A of the imaging device 100A according to Embodiment 1 are replaced with a plurality of pixels 10D. Each of the pixels 10D has, for example, the circuit configuration and device structure shown in FIGS. 15 to 17B.

[0161] The pixel 10D shown in FIGS. 15 to 17B differs from the pixel 10B according to the second embodiment mainly in that a feedback circuit is further provided that negatively feeds back the potential of the charge storage node FD during the reset operation. Specifically, as shown in FIGS. 15 to 17B, the pixel 10D differs from the pixel 10B according to the second embodiment in that, instead of the first semiconductor substrate 60B, the pixel 10D includes a first semiconductor substrate 60D on which a band control transistor 30 is further formed. The pixel 10D also differs from the pixel 10B according to the second embodiment in that it further includes capacitance elements 20 and 21 and a feedback line 38. The pixel 10D also differs from the pixel 10B according to the second embodiment in that it includes a wiring structure 80D instead of the wiring structure 80B.

[0162] 15, the band control transistor 30 is formed on the first semiconductor substrate 60D of the first pixel layer 1. For example, an N-channel MOSFET is used for the band control transistor 30. One of the source and drain of the band control transistor 30 is connected to the other of the source and drain of the amplification transistor 22 via a feedback line 38. The other of the source and drain of the band control transistor 30 is connected to a node RD.

[0163] One end of the capacitance element 20 is connected to a node RD. A reference voltage VTP is applied to the other end of the capacitance element 20. The band control transistor 30 and the capacitance element 20 form an RC filter circuit. One end of the capacitance element 21 is connected to the node RD. The other end of the capacitance element 21 is connected to a charge storage node FD. The capacitance elements 20 and 21 are, for example, MIM (Metal Insulator Metal) capacitances or MIS (Metal Insulator Semiconductor) capacitances.

[0164] The gate of the band control transistor 30 is connected to a control signal line 33 to which a control voltage VFB is applied. The control signal line 33 is connected to, for example, a vertical scanning circuit 46, which applies the control voltage VFB to the control signal line 33. The state of the band control transistor 30 is determined by the control voltage VFB. For example, when the control voltage VFB is at a high level, the band control transistor 30 is turned on. At this time, a feedback circuit is formed by the charge storage node FD, the amplification transistor 22, the band control transistor 30, and the capacitance element 21.

[0165] When the control voltage VFB becomes lower than the high level, the resistance component of the band control transistor 30 increases, so the band of the band control transistor 30 narrows and the frequency range of the feedback signal becomes narrower.

[0166] When a feedback path is formed, the signal output from the band control transistor 30 is attenuated by an attenuation circuit formed by the parasitic capacitance of the capacitive element 21 and the charge storage node FD, and is fed back to the charge storage node FD. If the capacitance of the capacitive element 21 is Cc and the parasitic capacitance of the charge storage node FD is Cfd, the attenuation rate is expressed as Cc / (Cc+Cfd).

[0167] When the control voltage VFB further decreases to a low level, the band control transistor 30 is turned off and no feedback path is formed.

[0168] In the pixel 10D, one of the source and drain of the reset transistor 26 is connected to the charge storage node FD, and the other of the source and drain of the reset transistor 26 is connected to the node RD. This allows the voltage of the other of the source and drain of the amplifier transistor 22 to be applied to the reset transistor 26.

[0169] In pixel 10D, a voltage VA1 is applied to a power supply line 32 connected to one of the source and drain of the amplification transistor 22 via a switch element SW1, and a voltage VA2 is applied to the power supply line 32 via a switch element SW2. The voltage applied to the power supply line 32 by the switch elements SW1 and SW2 is switched between the voltage VA1 and the voltage VA2. The on and off of the switch elements SW1 and SW2 is controlled, for example, by a control circuit (not shown). The voltage VA1 is a voltage applied to the power supply line 32 during a reset operation, and is a voltage that resets the voltage of the charge storage node FD to the first voltage V1. The voltage VA2 is a voltage applied during signal readout, and is, for example, the above-mentioned power supply voltage VDD.

[0170] It should be noted that the pixel 10D does not necessarily have to include the overflow transistor 28.

[0171] 16 , the first semiconductor substrate 60D has a configuration in which an n-type diffusion region 67n is added to the first semiconductor substrate 60B. The n-type diffusion region 67n is located in the p-type semiconductor layer 63p, more specifically, on the first surface s1 side of the p-type semiconductor layer 63p. The n-type diffusion region 67n is an impurity diffusion region containing n-type impurities provided in the p-type semiconductor layer 63p. The n-type diffusion region 67n is formed by implanting impurities into the p-type semiconductor layer 63p from the first surface s1 side.

[0172] As shown in FIGS. 16 and 17B , the reset transistor 26, the overflow transistor 28, and the band control transistor 30 are disposed on the first surface s1 of the first semiconductor substrate 60D. The band control transistor 30 includes n-type diffusion regions 65n and 67n, an insulating layer 51 formed on the first surface s1 of the first semiconductor substrate 60D, and a gate electrode 30e on the insulating layer 51. In the example shown in FIGS. 16 and 17B , the band control transistor 30 shares the n-type diffusion region 65n with the reset transistor 26. The band control transistor 30 includes the n-type diffusion region 67n as one of the source and drain, and the n-type diffusion region 65n as the other of the source and drain. The band control transistor 30 also includes a gate electrode 30e on the insulating layer 51 as its gate. The gate electrode 30e is formed of, for example, polysilicon doped with impurities such as n-type impurities.

[0173] 16 and 17B, the first semiconductor substrate 60D includes an isolation region in the p-type semiconductor layer 63p. The isolation region is disposed between adjacent pixels 10D, and electrically isolates the sets of the reset transistor 26, the overflow transistor 28, and the band control transistor 30 therebetween. The isolation region is provided, for example, around the set of the reset transistor 26, the overflow transistor 28, and the band control transistor 30 in a plan view. The isolation region may be formed by implantation isolation in which impurities such as p-type impurities are implanted, or may be formed by shallow trench isolation (STI).

[0174] The wiring structure 80D has a configuration in which contact plugs cp14 and cp15 and a connection structure 84 formed in the interlayer insulating layer 90, and contact plug cp16 and a connection structure 85 formed in the interlayer insulating layer 91 are further added to the above wiring structure 80B.

[0175] The contact plug cp14 penetrates the insulating layer 51 and is connected to the n-type diffusion region 67n. The contact plug cp15 is connected to the gate electrode 30e. The contact plug cp16 penetrates the insulating layer 52 and is connected to the silicide layer 73b. The contact plug cp14 is formed, for example, from polysilicon doped with impurities such as n-type impurities. The contact plugs cp15 and cp16 are formed, for example, from a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide.

[0176] The wiring structure 80D includes connection structures 84 and 85 connected to each other at the junction surface 3. The connection structures 84 and 85 are composed of multiple wirings and multiple plugs formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. The connection structure 84 is disposed in the interlayer insulating layer 90 and connected to the contact plug cp14. That is, the connection structure 84 connects the contact plug cp14 and the connection structure 85. The connection structure 85 is disposed in the interlayer insulating layer 91 and connected to the contact plug cp16. That is, the connection structure 85 connects the contact plug cp16 and the connection structure 84. The contact plugs cp14 and cp16 and the connection structures 84 and 85 constitute at least a part of the feedback line 38. The n-type diffusion region 67n and the n-type diffusion region 72bn are electrically connected to each other via the contact plugs cp14 and cp16, the connection structures 84 and 85, and the silicide layer 73b.

[0177] The wiring structure 80D may include the above-described control signal line 33. The control signal line 33 is connected to the gate electrode 30e via a contact plug cp15.

[0178] In this embodiment, connection structures 82, 83, 84, and 85 are provided as connection structures connecting transistors arranged on the first surface s1 and transistors arranged on the second surface s2, and because the first surface s1 and the second surface s2 face each other, the connection structures 82, 83, 84, and 85 can be short. This reduces the parasitic capacitance between the connection structures 82 and 83, which function as charge accumulation regions, and the connection structures 84 and 85, and therefore reduces the capacitance of the charge accumulation regions. This increases the conversion gain provided by the charge accumulation regions, and reduces noise in the imaging device.

[0179] In pixel 10D, capacitance elements 20 and 21 are formed in interlayer insulating layer 90. Note that capacitance element 21 is disposed at a position other than the cross section shown in Fig. 16 and is not shown in Fig. 16. Capacitance elements 20 and 21 are electrically connected to contact plug cp2.

[0180] 17B, ​​the gate length L28 of the overflow transistor 28 is shorter than the gate length L26 of the reset transistor 26 and the gate length L30 of the band control transistor 30. Therefore, in a plan view, the area of ​​the gate electrode 28e is smaller than the areas of the gate electrodes 26e and 30e. This reduces the capacitance of the gate electrode 28e, which functions as a charge storage region, and increases the conversion gain of signal charges. Furthermore, the gate length L26 of the reset transistor 26 may be shorter than the gate length L30 of the band control transistor 30. That is, in a plan view, the area of ​​the gate electrode 26e may be smaller than the area of ​​the gate electrode 30e.

[0181] In the image pickup device according to this embodiment, in the reset operation, first, the address transistor 24 is turned off, the band control transistor 30 is turned on, and the reset transistor 26 is turned on. At this time, the switch element SW1 is turned on, and a voltage VA1 is applied to the power supply wiring 32. This resets the potential of the charge storage node FD to the first voltage V1. Then, after the reset transistor 26 is turned off, the control voltage VFB applied to the gate of the band control transistor 30 is set to a voltage between high and low levels, thereby suppressing noise generated during the reset operation. The reset operation is then completed by turning the band control transistor 30 off.

[0182] With this configuration, it is possible to reduce the change in voltage of the charge storage node FD before and after the reset transistor 26 is turned off, thereby enabling faster noise suppression.

[0183] The layout within pixel 10D is not limited to the above example, and is not particularly limited. Fig. 17C is yet another plan view showing the layout within pixel 10D according to the present embodiment. Fig. 17C schematically shows another example of the arrangement of elements formed on first semiconductor substrate 60D when first semiconductor substrate 60D is viewed from above, which is different from Fig. 17B.

[0184] In the example shown in FIG. 17C , the gate electrode 26e and the n-type diffusion region 65n have a bent shape in a plan view. Furthermore, in a plan view, the n-type diffusion region 64n and the n-type diffusion region 65n are arranged so as to straddle the bent portion of the gate electrode 26e, i.e., so that the channel region of the reset transistor 26 is also bent. In the example shown in FIG. 17B , the overflow transistor 28, the reset transistor 26, and the band control transistor 30 are arranged in a straight line in the gate length direction in a plan view. On the other hand, in the example shown in FIG. 17C , the overflow transistor 28, the reset transistor 26, and the band control transistor 30 are arranged in a U-shape, bent at the gate electrode 26e and the n-type diffusion region 65n in a plan view. This allows the gate length L26 of the reset transistor 26 to be longer even with the same pixel area, thereby suppressing leakage current when the reset transistor 26 is off. Furthermore, since the gate length L30 of the band control transistor 30 can be increased, it is possible to improve the gm / Gds of the reset transistor 26 and the band control transistor 30. Here, gm is the mutual conductance, and Gds is the conductance between the drain and the source.

[0185] (Embodiment 5) Next, a description will be given of embodiment 5. The following description will focus on the differences from embodiments 1 to 4, and the description of commonalities will be omitted or simplified.

[0186] Fig. 18 is a diagram showing a circuit configuration of a pixel 10E according to the present embodiment. Fig. 19 is a schematic cross-sectional view of a device structure of a pixel 10E according to the present embodiment. Fig. 20A is a plan view showing a layout within a pixel 10E according to the present embodiment. Fig. 20B is another plan view showing a layout within a pixel 10E according to the present embodiment. Fig. 19 is a cross-sectional view of the pixel 10E taken along line XIX-XIX in Figs. 20A and 20B.

[0187] FIG. 20A schematically illustrates the arrangement of each element formed on the second semiconductor substrate 70 when viewed from below the second semiconductor substrate 70 shown in FIG. 19 . Specifically, FIG. 20A illustrates the arrangement of the amplifier transistor 22, address transistor 24, and through-electrode pt included in the pixel 10E on the second semiconductor substrate 70. Also, in FIG. 20A , the outline of the wiring 82b is indicated by a dashed line. FIG. 20B schematically illustrates the arrangement of each element formed on the first semiconductor substrate 60E when viewed from above the first semiconductor substrate 60E shown in FIG. 19 . Specifically, FIG. 20B illustrates the arrangement of the reset transistor 26C and the band control transistor 30C included in the pixel 10E. Also, FIGS. 20A and 20B illustrate the arrangement of contact plugs connected to each transistor. The layout of the pixel 10E shown in FIG. 20A is the same as the layout of the pixel 10D shown in FIG. 17A .

[0188] The imaging device according to the present embodiment has a configuration in which the pixels 10A of the imaging device 100A according to Embodiment 1 are replaced with a plurality of pixels 10E. Each of the pixels 10E has the circuit configuration and device structure shown in, for example, FIGS. 18 to 20B.

[0189] 18 to 20B , pixel 10E differs from pixel 10D according to embodiment 4 mainly in that pixel 10E includes reset transistor 26C and band control transistor 30C, which are P-channel MOSFETs, instead of reset transistor 26 and band control transistor 30, and does not include overflow transistor 28. Specifically, as shown in FIGS. 18 to 20B , pixel 10E differs from pixel 10D according to embodiment 4 in that pixel 10E includes first semiconductor substrate 60E on which reset transistor 26C and band control transistor 30C are formed, instead of first semiconductor substrate 60D on which reset transistor 26, overflow transistor 28, and band control transistor 30 are formed. Pixel 10E also differs from pixel 10D according to embodiment 4 in that pixel 10E includes wiring structure 80E instead of wiring structure 80D.

[0190] As shown in FIG. 18 , pixel 10E has a circuit configuration in which the reset transistor 26 and the band control transistor 30 of pixel 10D shown in FIG. 15 are replaced with a reset transistor 26C and a band control transistor 30C, and the overflow transistor 28 is removed. The reset transistor 26C and the band control transistor 30C are formed on a first semiconductor substrate 60E of the first pixel layer 1. A P-channel MOSFET is used for the band control transistor 30C. One of the source and drain of the band control transistor 30C is connected to the other of the source and drain of the amplifier transistor 22 via a feedback line 38. The other of the source and drain of the band control transistor 30C is connected to node RD. A control signal line 33 is connected to the gate of the band control transistor 30C. This circuit configuration of pixel 10E forms a feedback circuit, similar to that of pixel 10D, and can suppress noise generated during the reset operation.

[0191] 19 , the first semiconductor substrate 60E has a configuration in which a p-type diffusion region 67p is added to the first semiconductor substrate 60C. The p-type diffusion region 67p is located in the n-type semiconductor layer 63n, more specifically, on the first surface s1 side of the n-type semiconductor layer 63n. The p-type diffusion region 67p is an impurity diffusion region that is provided in the n-type semiconductor layer 63n and contains p-type impurities. The p-type diffusion region 67p is formed by implanting impurities into the n-type semiconductor layer 63n from the first surface s1 side.

[0192] As shown in FIGS. 19 and 20B , a reset transistor 26C and a band control transistor 30C are disposed on the first surface s1 of a first semiconductor substrate 60E. The band control transistor 30C includes p-type diffusion regions 65p and 67p, an insulating layer 51 formed on the first surface s1 of the first semiconductor substrate 60E, and a gate electrode 30e on the insulating layer 51. In the example shown in FIGS. 19 and 20B , the band control transistor 30C shares the p-type diffusion region 65p with the reset transistor 26C. The band control transistor 30C includes the p-type diffusion region 67p as one of the source and drain, and the p-type diffusion region 65p as the other of the source and drain. The band control transistor 30C also includes the gate electrode 30e on the insulating layer 51 as its gate. The p-type diffusion region 67p is connected to a contact plug cp14, and the p-type diffusion region 65p is connected to a contact plug cp2.

[0193] 19 and 20B, the first semiconductor substrate 60E includes an isolation region in the n-type semiconductor layer 63n. The isolation region is disposed between adjacent pixels 10E and electrically isolates pairs of the reset transistor 26C and the band control transistor 30C between them. The isolation region is provided, for example, around the pair of the reset transistor 26C and the band control transistor 30C in a plan view. The isolation region may be formed by implantation isolation in which impurities such as n-type impurities are implanted, or by shallow trench isolation (STI).

[0194] The wiring structure 80E has a configuration in which the contact plugs cp12 and cp13 are removed from the wiring structure 80D and the connection structure 83 is changed to a connection structure 81.

[0195] In the present embodiment, the second voltage V2 is higher than the first voltage V1, and the third voltage V3 is a voltage between the first voltage V1 and the second voltage V2. As a result, similar to the third embodiment, even if an excessive amount of holes accumulates in the p-type diffusion region 64p, the holes accumulated in the p-type diffusion region 64p can be released to the n-type semiconductor layer 63n, and the potential of the p-type diffusion region 64p can be clipped without providing the overflow transistor 28.

[0196] The layout within pixel 10E is not limited to the above example and is not particularly limited. Fig. 20C is yet another plan view showing the layout within pixel 10E according to the present embodiment. Fig. 20C schematically shows another example of the arrangement of elements formed on first semiconductor substrate 60E when first semiconductor substrate 60E is viewed from above, which is different from Fig. 20B.

[0197] 20C , the reset transistor 26C and the band control transistor 30C do not share the p-type diffusion region 65p. That is, the reset transistor 26C and the band control transistor 30C are arranged apart. The band control transistor 30C includes a p-type diffusion region 67p as one of the source and drain, and a p-type diffusion region 68p as the other of the source and drain. The p-type diffusion region 68p is connected to a contact plug cp17. Although not shown, the p-type diffusion region 65p and the p-type diffusion region 68p are electrically connected by electrically connecting the contact plug cp17 and the contact plug cp2.

[0198] In the example shown in FIG. 20B , the reset transistor 26C and the band control transistor 30C are aligned in a straight line in the gate length direction in a plan view. On the other hand, in the example shown in FIG. 20C , the reset transistor 26C and the band control transistor 30C are aligned in a direction intersecting the gate length direction in a plan view. This allows the gate length L26 of the reset transistor 26C to be increased even with the same pixel area, thereby suppressing leakage current when the reset transistor 26C is off. Furthermore, the gate length L30 of the band control transistor 30C can be increased, thereby improving the gm / Gds of the band control transistor 30C. In the example shown in FIG. 20B , the gate length L26 of the reset transistor 26C is shorter than the gate length L30 of the band control transistor 30C. In other words, the area of ​​the gate electrode 26e is smaller than the area of ​​the gate electrode 30e in a plan view.

[0199] Sixth Embodiment Next, a sixth embodiment will be described. The following description will focus on the differences from the first to fifth embodiments, and the description of the commonalities will be omitted or simplified.

[0200] Fig. 21 is a diagram showing a circuit configuration of a pixel 10F according to the present embodiment, and Fig. 22 is a schematic cross-sectional view of a device structure of a pixel 10F according to the present embodiment.

[0201] The imaging device according to the present embodiment has a configuration in which the plurality of pixels 10A of the imaging device 100A according to Embodiment 1 are replaced with a plurality of pixels 10F. Each of the plurality of pixels 10F has, for example, the circuit configuration and device structure shown in FIGS.

[0202] The pixel 10F shown in FIGS. 21 and 22 differs from the pixel 10B according to the second embodiment mainly in that it further includes a photoelectric conversion unit 12F separate from the photoelectric conversion unit 12. Specifically, as shown in FIGS. 21 and 22, the pixel 10F differs from the pixel 10B according to the second embodiment in that, instead of the first semiconductor substrate 60B, it includes a first semiconductor substrate 60F on which an amplification transistor 22 and an address transistor 24 are further formed, and instead of the second semiconductor substrate 70, it includes a second semiconductor substrate 70F on which a photoelectric conversion unit 12F and the like are formed. The pixel 10F also differs from the pixel 10B according to the second embodiment in that it includes a through electrode pt2 and a wiring structure 80F instead of the through electrode pt and the wiring structure 80B. In FIG. 22, the through electrode pt2 is indicated by a dashed line because it is not shown in the cross section.

[0203] As schematically shown in FIG. 21 , the amplification transistor 22, the address transistor 24, the reset transistor 26, and the overflow transistor 28 are all formed on the first semiconductor substrate 60F of the first pixel layer 1. This allows space to be secured on the second semiconductor substrate 70F for arranging transistors for the circuit connected to the photoelectric conversion unit 12F. The circuit configuration of the circuit connected to the photoelectric conversion unit 12 in the pixel 10F is the same as the circuit configuration of the circuit connected to the photoelectric conversion unit 12 in the pixel 10B according to the second embodiment described with reference to FIG. 9 . Note that some of the amplification transistor 22, the address transistor 24, the reset transistor 26, and the overflow transistor 28 may be formed on a semiconductor substrate separate from the first semiconductor substrate 60F, and the first semiconductor substrate 60F and the separate semiconductor substrate may be stacked together. Furthermore, the circuit configuration of the circuit connected to the photoelectric conversion unit 12 in the pixel 10F may be the same as the circuit configuration of the circuit connected to the photoelectric conversion unit 12 in the pixel according to the embodiment other than the second embodiment described above.

[0204] The pixel 10F includes a photoelectric conversion unit 12F and another signal detection circuit electrically connected to the photoelectric conversion unit 12F. In the configuration illustrated in Fig. 21 , the other signal detection circuit includes a transfer transistor 25, an amplification transistor 22F, an address transistor 24F, and a reset transistor 26F. The photoelectric conversion unit 12F, the transfer transistor 25, the amplification transistor 22F, the address transistor 24F, and the reset transistor 26F are formed on a second semiconductor substrate 70F. In the example illustrated in Fig. 21 , the transfer transistor 25, the amplification transistor 22F, the address transistor 24F, and the reset transistor 26F each include, for example, an N-channel MOSFET.

[0205] The photoelectric conversion unit 12F generates positive and negative charges upon receiving incident light. That is, the photoelectric conversion unit 12F converts light into charges. The positive and negative charges are typically hole-electron pairs. The photoelectric conversion unit 12F is an example of a second photoelectric conversion unit.

[0206] 21 , one of the source and drain of the transfer transistor 25 is electrically connected to the photoelectric conversion unit 12F. The other of the source and drain of the transfer transistor 25 is electrically connected to a charge storage node FD2 between the transfer transistor 25 and the amplification transistor 22F. The transfer transistor 25 transfers the charges generated by the photoelectric conversion unit 12F to the charge storage node FD2. A transfer signal TRS is applied to the gate of the transfer transistor 25 from the vertical scanning circuit 46, controlling the on and off of the transfer transistor 25.

[0207] The power supply voltage VDD is applied to one of the source and drain of the amplifier transistor 22F. The other of the source and drain of the amplifier transistor 22F is connected to one of the source and drain of the address transistor 24F. The gate of the amplifier transistor 22F is electrically connected to the charge storage node FD2.

[0208] The above-mentioned vertical signal line 35 (not shown) is connected to the other of the source and drain of the address transistor 24F. The same vertical signal line 35 as the vertical signal line 35 connected to the other of the source and drain of the address transistor 24F may be connected to the other of the source and drain of the address transistor 24F, or a different vertical signal line 35 may be connected. In other words, multiple vertical signal lines 35 may be connected to one pixel 10F. A row selection signal SEL2 that controls the on / off of the address transistor 24F is applied to the gate of the address transistor 24F from the vertical scanning circuit 46. This causes the row to be readout to be scanned in the vertical direction (i.e., the column direction), and the row to be readout is selected. The signal voltage SIG2 from the pixel 10F output to the vertical signal line 35 via the address transistor 24F is subjected to noise suppression signal processing and analog-to-digital conversion, for example, in a column signal processing circuit, and then input to the horizontal signal readout circuit 48.

[0209] One of the source and drain of the reset transistor 26F is connected to the charge storage node FD2. A reset voltage VR is applied to the other of the source and drain of the reset transistor 26F. A reset signal RS2 that controls the on and off of the reset transistor 26F is applied to the gate of the reset transistor 26F from the vertical scanning circuit 46. When the reset transistor 26F is turned on, the potentials of the charge storage node FD2 and the photoelectric conversion unit 12F are reset.

[0210] 22 , the first semiconductor substrate 60F includes a support substrate 61p, a p-type semiconductor layer 62p, and a p-type semiconductor layer 63p. The amplifier transistor 22, the address transistor 24, the reset transistor 26, and the overflow transistor 28 are arranged on a first surface s1 of the first semiconductor substrate 60F. The amplifier transistor 22 has a gate electrically connected to the photoelectric conversion unit 12 via a through electrode pt2, and is an example of a first transistor arranged on the first surface s1. The amplifier transistor 22 and the address transistor 24 are arranged at positions other than those in the cross section shown in FIG. 22 and are not illustrated in FIG. 22 .

[0211] In the example shown in FIG. 22 , the second semiconductor substrate 70F includes a p-type semiconductor layer 71p and a photoelectric conversion unit 12F. The photoelectric conversion unit 12F is a photodiode formed in the p-type semiconductor layer 71p. In addition, in the example shown in FIG. 22 , the photoelectric conversion unit 12 and the photoelectric conversion unit 12F overlap in a planar view. The photoelectric conversion unit 12F is disposed below the photoelectric conversion unit 12, that is, at a position where light transmitted through the photoelectric conversion unit 12 is incident. This allows the light receiving areas of the photoelectric conversion units 12 and 12F to be increased. Note that the photoelectric conversion unit 12 and the photoelectric conversion unit 12F may be disposed offset from each other in a planar view and may not overlap.

[0212] Furthermore, a transfer transistor 25, an amplifier transistor 22F, an address transistor 24F, and a reset transistor 26F are arranged on the second surface s2 of the second semiconductor substrate 70F. Note that the amplifier transistor 22F and the address transistor 24F are arranged at positions other than those shown in the cross section in FIG. 22 and are not shown in FIG.

[0213] The through electrode pt2 penetrates the second semiconductor substrate 70F and the insulating layers 52 and 53, and connects the photoelectric conversion unit 12 and the wiring structure 80F. Specifically, the through electrode pt2 connects the pixel electrode 12a and the connection structure 86. Although not shown in the figure, an insulating film such as a silicon oxide film is formed around the through electrode pt2 in the second semiconductor substrate 70F, and the through electrode pt2 and the second semiconductor substrate 70F are not in contact with each other.

[0214] The photoelectric conversion units 12 and 12F perform photoelectric conversion on light in different wavelength ranges, for example. In this embodiment, the photoelectric conversion unit 12 converts, for example, near-infrared light into electric charges. In this case, the photoelectric conversion layer 12b is made of a photoelectric conversion material that absorbs near-infrared light and converts it into electric charges. Because the pixel 10F includes two photoelectric conversion units 12 and 12F, it is possible to convert light of different wavelengths into electric charges and read them out as signals. For example, the electric charges generated by photoelectric conversion in the photoelectric conversion unit 12 are used to generate near-infrared images, and the electric charges generated by photoelectric conversion in the photoelectric conversion unit 12F are used to generate color or black-and-white images. Furthermore, because the photoelectric conversion unit 12F is formed on the second semiconductor substrate 70F, the imaging device can be miniaturized.

[0215] The wiring structure 80F includes connection structures 86 and 87 connected to each other at the junction surface 3. The connection structures 86 and 87 are part of the charge storage node FD. The connection structures 86 and 87 are composed of multiple wirings and multiple plugs formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. The connection structure 86 is disposed in an interlayer insulating layer 90, and the connection structure 87 is disposed in an interlayer insulating layer 91. The n-type diffusion region 64n and the pixel electrode 12a of the photoelectric conversion unit 12 are electrically connected to each other via a contact plug cp1, the connection structures 86 and 87, and a through-electrode pt2. Although not shown, the connection structure 86 is electrically connected to the gate of the amplification transistor 22.

[0216] [Modification] Next, a modification of embodiment 6 will be described. The following description will focus on the differences from embodiments 1 to 6, and description of commonalities will be omitted or simplified.

[0217] First, a first modification of the sixth embodiment will be described. Fig. 23 is a diagram showing the circuit configuration of a pixel 10G according to this modification. Fig. 24 is a schematic cross-sectional view of the device structure of the pixel 10G according to this modification. The imaging device according to this modification has a configuration in which the plurality of pixels 10A of the imaging device 100A according to the first embodiment are replaced with a plurality of pixels 10G. Each of the plurality of pixels 10G has, for example, the circuit configuration and device structure shown in Figs. 23 and 24 .

[0218] 23 and 24 differs from pixel 10F according to embodiment 6 mainly in that pixel 10G includes reset transistor 26C, which uses a P-channel MOSFET, instead of reset transistor 26, and does not include overflow transistor 28. Specifically, as shown in FIGS. 23 and 24 , pixel 10G differs from pixel 10F according to embodiment 6 in that pixel 10G includes first semiconductor substrate 60G on which amplifying transistor 22C, address transistor 24C, and reset transistor 26C are formed, instead of first semiconductor substrate 60F on which amplifying transistor 22, address transistor 24, reset transistor 26, and overflow transistor 28 are formed. Pixel 10G also differs from pixel 10F according to embodiment 6 in that pixel 10G includes wiring structure 80G instead of wiring structure 80F.

[0219] As schematically shown in Figure 23, the amplifier transistor 22C, address transistor 24C, and reset transistor 26C are all formed on the first semiconductor substrate 60G of the first pixel layer 1. The circuit configuration of the circuit connected to the photoelectric conversion unit 12 in pixel 10G is the same as the circuit configuration of the circuit connected to the photoelectric conversion unit 12 in pixel 10C described with reference to Figure 12, except that the amplifier transistor 22 and address transistor 24 are replaced with amplifier transistors 22C and address transistors 24C. P-channel MOSFETs are used for the amplifier transistor 22C and address transistor 24C. Note that parts of the amplifier transistor 22C, address transistor 24C, and reset transistor 26C may be formed on a semiconductor substrate separate from the first semiconductor substrate 60G, and the first semiconductor substrate 60G and the separate semiconductor substrate may be stacked together.

[0220] In the example shown in Figure 24, the first semiconductor substrate 60G includes a support substrate 61n, an n-type semiconductor layer 62n, and an n-type semiconductor layer 63n. When the imaging device is in operation, a third voltage V3 is applied to the n-type semiconductor layer 63n. An amplifier transistor 22C, an address transistor 24C, and a reset transistor 26C are arranged on a first surface s1 of the first semiconductor substrate 60G. Note that the amplifier transistor 22C and the address transistor 24C are arranged at positions other than those shown in the cross section of Figure 24 and are not shown in Figure 24.

[0221] The wiring structure 80G includes connection structures 88 and 87 connected to each other at the junction surface 3. The connection structures 88 and 87 are part of the charge storage node FD. The connection structure 88 is composed of multiple wirings and multiple plugs formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or a metal oxide. The connection structure 88 is disposed in an interlayer insulating layer 90. The p-type diffusion region 64p and the pixel electrode 12a of the photoelectric conversion unit 12 are electrically connected to each other via a contact plug cp1, the connection structures 88 and 87, and a through-electrode pt2. Although not shown, the connection structure 88 is electrically connected to the gate of the amplification transistor 22C.

[0222] In the present embodiment, the second voltage V2 is higher than the first voltage V1, and the third voltage V3 is a voltage between the first voltage V1 and the second voltage V2. As a result, similar to the third embodiment, even if an excessive amount of holes accumulates in the p-type diffusion region 64p, the holes accumulated in the p-type diffusion region 64p can be released to the n-type semiconductor layer 63n, and the potential of the p-type diffusion region 64p can be clipped without providing the overflow transistor 28.

[0223] Next, a second modification of the sixth embodiment will be described. Fig. 25 is a diagram showing the circuit configuration of a pixel 10H according to this modification. The imaging device according to this modification has a configuration in which the plurality of pixels 10A of the imaging device 100A according to the first embodiment are replaced with a plurality of pixels 10H. Each of the plurality of pixels 10H has, for example, the circuit configuration shown in Fig. 25.

[0224] 25 differs from the pixel 10F according to the sixth embodiment in that the pixel 10H shown in FIG. 25 includes a plurality of sub-pixels 10Ha, 10Hb, 10Hc, and 10Hd. Specifically, as shown in FIG. 25 , the pixel 10H differs from the pixel 10F according to the sixth embodiment in that the pixel 10H includes, instead of the second semiconductor substrate 70F, a second semiconductor substrate 70H in which a plurality of photoelectric conversion units 12F and a plurality of transfer transistors 25 are added to the second semiconductor substrate 70F.

[0225] 25 , a pixel 10H includes a plurality of sub-pixels 10Ha, 10Hb, 10Hc, and 10Hd, each including a photoelectric conversion unit 12F. A plurality of photoelectric conversion units 12F and a plurality of transfer transistors 25 are formed on a second semiconductor substrate 70H. Each of the plurality of transfer transistors 25 is provided corresponding to a different one of the plurality of photoelectric conversion units 12F. One of the source and the drain of each of the plurality of transfer transistors 25 is electrically connected to a corresponding one of the plurality of photoelectric conversion units 12F.

[0226] 25 , pixel 10H outputs a signal voltage SIG for one pixel based on the charge generated by photoelectric conversion unit 12, and a signal voltage SIG2 for four pixels based on the charge generated by four photoelectric conversion units 12F corresponding to four sub-pixels 10Ha, 10Hb, 10Hc, and 10Hd. In this way, by providing one photoelectric conversion unit 12 corresponding to multiple sub-pixels 10Ha, 10Hb, 10Hc, and 10Hd, the circuit connected to photoelectric conversion unit 12 can be made smaller.

[0227] In the example shown in FIG. 25, the charge storage node FD2, the amplification transistor 22F, the address transistor 24F, and the reset transistor 26F are provided in common to the plurality of sub-pixels 10Ha, 10Hb, 10Hc, and 10Hd, but may also be provided individually to the plurality of sub-pixels 10Ha, 10Hb, 10Hc, and 10Hd.

[0228] Next, a third modification of the sixth embodiment will be described. Fig. 26 is a diagram showing the circuit configuration of a pixel 10I according to this modification. The imaging device according to this modification has a configuration in which the plurality of pixels 10A of the imaging device 100A according to the first embodiment are replaced with a plurality of pixels 10I. Each of the plurality of pixels 10I has, for example, the circuit configuration shown in Fig. 26.

[0229] 26 , pixel 10I differs from pixel 10H according to Modification 2 of Embodiment 6 in that it includes a first semiconductor substrate 60G instead of first semiconductor substrate 60F. That is, pixel 10I has a configuration that combines the first semiconductor substrate 60G described in Modification 1 above with the second semiconductor substrate 70H described in Modification 2 above. Therefore, it is possible to clip the potential of p-type diffusion region 64p without providing an overflow transistor 28, and it is also possible to reduce the size of the circuit connected to photoelectric conversion unit 12.

[0230] While the imaging device according to the present disclosure has been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of the present disclosure.

[0231] For example, in the first to fifth embodiments, the amplifier transistor 22 and the address transistor 24 are arranged on the second surface s2, but this is not limiting. At least one of the amplifier transistor 22 and the address transistor 24 may be arranged on the first surface s1.

[0232] Furthermore, for example, in the above-described first to sixth embodiments, the n-type diffusion region 64n is the source or drain of the reset transistor 26, or the p-type diffusion region 64p is the source or drain of the reset transistor 26C, but this is not limiting. For example, the imaging device according to the present disclosure may be configured not to include a reset transistor, as in the imaging device disclosed in Patent Document 3, and the potential of the n-type diffusion region 64n or the p-type diffusion region 64p may be reset via the photoelectric conversion unit 12.

[0233] Furthermore, for example, while the pixels according to the first to sixth embodiments have a configuration in which two semiconductor substrates, a first semiconductor substrate and a second semiconductor substrate, are stacked, this is not limiting. Three or more semiconductor substrates, including the first semiconductor substrate and the second semiconductor substrate, may be stacked, and the transistors included in the pixel may be distributed. Furthermore, a second semiconductor substrate 70F according to the sixth embodiment may be stacked between the photoelectric conversion unit 12 and the first and second semiconductor substrates according to the first to fifth embodiments.

[0234] Furthermore, for example, in the first to sixth embodiments, the photoelectric conversion section 12 is not limited to a configuration including the pixel electrode 12a, the photoelectric conversion layer 12b, and the transparent electrode 12c, and may be a photodiode.

[0235] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0236] The imaging device according to the present disclosure is useful, for example, in image sensors, digital cameras, etc. The imaging device according to the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, etc.

[0237] REFERENCE SIGNS LIST 1 First pixel layer 2 Second pixel layer 3 Bonding surface 4 Peripheral circuit layer 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 11A Pixel 10Ha, 10Hb, 10Hc, 10Hd Sub-pixel 12, 12F Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c Transparent electrode 13 Shield electrode 14 Protective film 15 Color filter 16 Microlens 20, 21 Capacitor element 22, 22C, 22F Amplification transistor 22e, 24e, 26e, 28e, 30e Gate electrode 22s, 24s, 73a, 73b, 73c Silicide layer 24, 24C, 24F Address transistor 25 Transfer transistor 26, 26C, 26F Reset transistor 28 Overflow transistor 30, 30C Bandwidth control transistor 31 Reset voltage line 32 Power supply wiring 33 Control signal line 34 Address signal line 35 Vertical signal line 36 Reset signal line 37 Voltage line 38 Feedback line 39 Storage control line 40 Peripheral circuit 46 Vertical scanning circuit 48 Horizontal signal readout circuit 51, 52, 53 Insulating layer 60, 60B, 60C, 60D, 60E, 60F, 60G First semiconductor substrate 61n, 61p, 121p Support substrate 62n, 63n, 111n, 112n, 123n, 126n N-type semiconductor layer 62p, 63p, 71p, 113p, 122p, 124p, 125p P-type semiconductor layer 64n, 65n, 66n, 67n, 72an, 72bn, 72cn n-type diffusion regions 64p, 65p, 67p, 68p p-type diffusion regions 70, 70F, 70H second semiconductor substrate 80, 80B, 80D, 80E, 80F, 80G wiring structure 81, 82, 83, 84, 85, 86, 87, 88 connection structure 81a, 82a, 82b wiring 90, 91, 92 interlayer insulating layer 100A imaging device 120 third semiconductor substrate cp1, cp2, cp3, cp4, cp5, cp6, cp7, cp8, cp9, cp10, cp11, cp12, cp13, cp14, cp15, cp16, cp17 contact plugs FD, FD2 Charge storage nodes p1, p2, p3, p4, p5 Pad electrodes pt, pt1, pt2 Through electrodes R1 Imaging region R2 Peripheral region RD Node s1 First surface s2 Second surface s3 Third surface s4 Fourth surface s5 Fifth surfaceSW1, SW2 switch elements

Claims

1. An imaging device comprising: a first semiconductor substrate having a first surface; a second semiconductor substrate having a second surface and a third surface opposite the second surface, the second surface and the second surface being stacked on the first semiconductor substrate such that the second surface and the first surface face each other; a first photoelectric conversion unit located on or above the third surface of the second semiconductor substrate and converting light into electric charges; and a through electrode penetrating the second semiconductor substrate, wherein the first semiconductor substrate is electrically connected to the first photoelectric conversion unit via the through electrode and includes a first impurity region that accumulates the electric charges.

2. The imaging device of claim 1, further comprising a plurality of transistors located on the second surface.

3. The imaging device according to claim 2, wherein the plurality of transistors includes a first transistor having a gate electrically connected to the first photoelectric conversion unit via the through electrode.

4. The imaging device described in claim 3, wherein the second semiconductor substrate includes a second impurity region of a first conductivity type that functions as a source or drain of the first transistor, and the first impurity region is an impurity region of a second conductivity type different from the first conductivity type.

5. The imaging device according to claim 4, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

6. The imaging device described in claim 1, wherein the first photoelectric conversion unit includes: a first electrode electrically connected to the first impurity region; a second electrode opposed to the first electrode; and a photoelectric conversion layer located between the first electrode and the second electrode.

7. The imaging device according to claim 1, wherein the second semiconductor substrate includes a second photoelectric conversion section that converts light into electric charges.

8. The imaging device according to claim 7, wherein the second photoelectric conversion unit is disposed at a position where light that has passed through the first photoelectric conversion unit is incident.

9. An imaging device as described in any one of claims 1, 2 and 6 to 8, further comprising a first transistor located on the first surface, the first transistor including a gate electrically connected to the first photoelectric conversion unit via the through electrode.

10. An imaging device as described in any one of claims 1 to 8, further comprising: a plurality of pixels; and a peripheral circuit electrically connected to the plurality of pixels, each of the plurality of pixels including the first photoelectric conversion unit, the through electrode and the first impurity region, and at least a portion of the peripheral circuit being located on the first surface of the first semiconductor substrate or the second surface of the second semiconductor substrate.

11. An imaging device as described in any one of claims 1 to 8, further comprising a wiring layer located between the first surface and the second surface and overlapping the first impurity region in a planar view.

12. The imaging device according to claim 1, further comprising a second transistor located on the first surface, the second transistor including the first impurity region as one of a source and a drain.

Images