Imaging device, electronic apparatus, and method for manufacturing imaging device

Abstract

Provided is an imaging device including a semiconductor substrate and a plurality of pixels arranged on the semiconductor substrate in a matrix form along a row direction and a column direction, wherein each of the plurality of pixels includes: a charge accumulation unit that performs photoelectric conversion on incident light, generates charges, and accumulates the generated charges; and a common transfer gate that is provided so as to be shared by adjacent ones of the plurality of pixels and transfers charges generated in the pixels to the charge accumulation unit.

Description

Imaging device, electronic device, and method for manufacturing imaging device

[0001] The present disclosure relates to an imaging device, an electronic device, and a method for manufacturing an imaging device.

[0002] In recent years, imaging devices have adopted a method of detecting a phase difference using a pair of phase difference detection pixels as an autofocus function. An example of such a method is the imaging device disclosed in Patent Document 1 listed below.

[0003] International Publication No. 2022 / 176626

[0004] However, as pixels (image sensors) become smaller, the elements that make up the pixels are placed closer to each other, which creates a problem of a strong electric field being generated within the semiconductor substrate.In addition, there is a strong demand for faster readout speeds in image sensors.

[0005] Therefore, the present disclosure proposes an imaging device, an electronic device, and a method for manufacturing an imaging device that can increase the readout speed while suppressing the generation of a strong electric field.

[0006] According to the present disclosure, there is provided an imaging device comprising a semiconductor substrate and a plurality of pixels arranged in a matrix on the semiconductor substrate along row and column directions, each of the plurality of pixels performing photoelectric conversion on incident light to generate electric charges, a charge accumulation section that accumulates the generated electric charges, and a common transfer gate that is shared by the plurality of adjacent pixels and transfers the electric charges generated in the pixels to the charge accumulation section.

[0007] Furthermore, according to the present disclosure, there is provided an electronic device equipped with an imaging device, the imaging device comprising a semiconductor substrate and a plurality of pixels arranged in a matrix along row and column directions on the semiconductor substrate, each of the plurality of pixels performing photoelectric conversion on incident light to generate electric charges and having a charge accumulation section that accumulates the generated electric charges, and a common transfer gate that is shared by the plurality of adjacent pixels and transfers the electric charges generated in the pixels to the charge accumulation section.

[0008] Furthermore, according to the present disclosure, there is provided a method for manufacturing an imaging device including a semiconductor substrate and a plurality of imaging elements arranged in a matrix on the semiconductor substrate along row and column directions, wherein the imaging elements have an element isolation wall provided to surround the imaging element, a plurality of pixels provided adjacent to one another and performing photoelectric conversion on incident light to generate electric charges, a pixel isolation wall provided to extend along the depth direction of the semiconductor substrate to separate the plurality of pixels, a plurality of charge accumulation sections that accumulate the generated electric charges, and a common transfer gate portion provided to be shared by the plurality of adjacent pixels and transferring the electric charges generated in each of the pixels to each of the charge accumulation sections, the common transfer gate portion having a vertical gate portion extending along the depth direction of the semiconductor substrate from a surface of the semiconductor substrate facing a light-receiving surface, and

[0009] FIG. 1 is an explanatory diagram showing an example of a planar configuration of an imaging device 1 according to an embodiment of the present disclosure. FIG. 2 is an explanatory diagram showing an example of a planar configuration of an imaging element 100a according to a comparative example. FIG. 3 is an explanatory diagram showing an example of an operation of the imaging element 100a according to the comparative example. FIG. 4 is an explanatory diagram showing an example of a planar configuration of an imaging element 100 according to a first embodiment of the present disclosure. FIG. 5 is an explanatory diagram showing an example of a cross-sectional configuration of an imaging element 100 according to a first embodiment of the present disclosure. FIG. 6 is an explanatory diagram showing an example of a planar configuration of a pixel array section 30 according to a first embodiment of the present disclosure. FIG. 7 is an explanatory diagram showing an example of a planar configuration of a pixel array section 30 according to a first modification of the first embodiment of the present disclosure. FIG. 8 is an explanatory diagram showing an example of a circuit configuration of a pixel array section 30 according to a first modification of the first embodiment of the present disclosure. FIG. 9 is an explanatory diagram (part 1) including an example of a cross-sectional configuration of an imaging element 100 according to a third embodiment of the present disclosure and a corresponding potential diagram. FIG. 2 is an explanatory diagram (part 2) including an example cross-sectional configuration of an image sensor 100 according to a third embodiment of the present disclosure and a corresponding potential diagram. FIG. 3 is an explanatory diagram showing an example planar configuration of an image sensor 100 according to a fourth embodiment of the present disclosure. FIG. 4 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a fourth embodiment of the present disclosure. FIG. 5 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a fifth embodiment of the present disclosure. FIG. 6 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a sixth embodiment of the present disclosure. FIG. 7 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a seventh embodiment of the present disclosure. FIG. 8 is an explanatory diagram illustrating an effect of an image sensor 100 according to a seventh embodiment of the present disclosure. FIG. 9 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a first modification of the seventh embodiment of the present disclosure. FIG. 10 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a second modification of the seventh embodiment of the present disclosure. FIG. 11 is an explanatory diagram showing an example planar configuration of an image sensor 100 according to an eighth embodiment of the present disclosure. FIG. 13 is an explanatory diagram showing an example of a cross-sectional configuration of an image sensor 100 according to an eighth embodiment of the present disclosure.10 is an explanatory diagram showing an example of a planar configuration of a pixel array unit 30 according to an eighth embodiment of the present disclosure. FIG. 11 is an explanatory diagram showing an example of a circuit configuration of a pixel array unit 30 according to an eighth embodiment of the present disclosure. FIG. 12 is an explanatory diagram showing an example of a planar configuration of a pixel array unit 30 according to a modified example of the eighth embodiment of the present disclosure. FIG. 13 is an explanatory diagram showing an example of a planar configuration of an image sensor 100 according to a ninth embodiment of the present disclosure. FIG. 14 is an explanatory diagram (part 1) showing a manufacturing process of an image sensor 100 according to a tenth embodiment of the present disclosure. FIG. 15 is an explanatory diagram (part 2) showing a manufacturing process of an image sensor 100 according to a tenth embodiment of the present disclosure. FIG. 16 is an explanatory diagram (part 3) showing a manufacturing process of an image sensor 100 according to a first modified example of the tenth embodiment of the present disclosure. FIG. 17 is an explanatory diagram showing an example of a configuration of an image sensor 100 according to a second modified example of the tenth embodiment of the present disclosure. FIG. 18 is an explanatory diagram showing an example of a configuration of an image sensor 100 according to a third modified example of the tenth embodiment of the present disclosure. FIG. 19 is an explanatory diagram showing a manufacturing process of an image sensor 100 according to an eleventh embodiment of the present disclosure. FIG. 20 is an explanatory diagram showing a manufacturing process of an image sensor 100 according to a twelfth embodiment of the present disclosure. FIG. 13 is an explanatory diagram showing an example configuration of an imaging element 100 according to a thirteenth embodiment of the present disclosure. FIG. 14 is an explanatory diagram showing an example planar configuration of a pixel array unit 30 according to a thirteenth embodiment of the present disclosure. FIG. 15 is an explanatory diagram showing an example of a schematic functional configuration of a camera. FIG. 16 is a block diagram showing an example of a schematic functional configuration of a smartphone. FIG. 17 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 18 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0010] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0011] The drawings referred to in the following description are for explaining and facilitating understanding of an embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the imaging device shown in the drawings can be modified as appropriate, taking into consideration the following description and known technologies.

[0012] The shapes expressed in the following description not only refer to geometrically defined shapes, but also include differences (errors and distortions) that are tolerable in the operation of the imaging device and in the manufacturing process of the imaging device.

[0013] Furthermore, in the following description, "electrically connected" means connecting a plurality of elements directly or indirectly via another element.

[0014] In the following description, "sharing" means that different elements (such as pixels) share one other element (such as an on-chip lens).

[0015] The description will be given in the following order: 1. Schematic configuration of an imaging device 2. Schematic configuration of an imaging element according to a comparative example 3. Background 4. First embodiment 4.1 Detailed configuration 4.2 Modified example 5. Second embodiment 6. Third embodiment 7. Fourth embodiment 8. Fifth embodiment 9. Sixth embodiment 10. Seventh embodiment 10.1 Detailed configuration 10.2 Modified example 11. Eighth embodiment 11.1 Detailed configuration 11.2 Modified example 12. Ninth embodiment 13. Tenth embodiment 13.1 Manufacturing process 13.2 Modified example 14. Eleventh embodiment 15. Twelfth embodiment 16. Thirteenth embodiment 17. Summary 18. Application examples 18.1 Application example to a camera 18.2 Application example to a smartphone 18.3 Application example to a mobile object 19. Supplementary information

[0016] <<1. Schematic Configuration of Imaging Device>> First, a schematic configuration of an imaging device 1 according to an embodiment of the present disclosure will be described with reference to FIG. 1 . FIG. 1 is an explanatory diagram showing an example of the planar configuration of the imaging device 1 according to an embodiment of the present disclosure. As shown in FIG. 1 , the imaging device 1 according to an embodiment of the present disclosure includes a pixel array section 30 in which a plurality of imaging elements 100 are arranged in a matrix along row and column directions on a semiconductor substrate 10 made of, for example, silicon. The imaging device 1 also includes a peripheral circuit section provided on the semiconductor substrate 10 to surround the pixel array section 30. The imaging device 1 further includes, as the peripheral circuit section, a vertical drive circuit section 32, a column signal processing circuit section 34, a horizontal drive circuit section 36, an output circuit section 38, a control circuit section 40, and the like. Each block of the imaging device 1 will be described in detail below.

[0017] (Pixel Array Section 30) The pixel array section 30 has a plurality of image sensors 100 arranged two-dimensionally in a matrix along the row and column directions on the semiconductor substrate 10. Each image sensor 100 is an element that performs photoelectric conversion on incident light to generate electric charges, and has a photoelectric conversion section (not shown) and a plurality of pixel transistors (e.g., MOS (Metal-Oxide-Semiconductor) transistors) (not shown). The pixel transistors include, for example, four MOS transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor. Furthermore, in the pixel array section 30, the plurality of image sensors 100 are arranged two-dimensionally, for example, according to a Bayer array. Here, the Bayer array is an arrangement pattern in which image pickup elements 100 that absorb light having a green wavelength (for example, wavelengths of 495 nm to 570 nm) and generate electric charges are arranged in a checkerboard pattern, and in the remaining portion, image pickup elements 100 that absorb light having a red wavelength (for example, wavelengths of 620 nm to 750 nm) and image pickup elements 100 that absorb light having a blue wavelength (for example, wavelengths of 450 nm to 495 nm) and generate electric charges are arranged alternately in each row. The detailed structure of the image pickup element 100 will be described later.

[0018] (Vertical Drive Circuit Unit 32) The vertical drive circuit unit 32 is formed by, for example, a shift register, selects pixel drive wirings 42, supplies pulses for driving the image sensor 100 to the selected pixel drive wirings 42, and drives the image sensor 100 row by row. That is, the vertical drive circuit unit 32 selects and scans each image sensor 100 in the pixel array unit 30 row by row in the vertical direction (up and down in FIG. 1 ), and supplies pixel signals based on signal charges generated in accordance with the amount of light received by a photoelectric conversion unit (not shown) of each image sensor 100 to a column signal processing circuit unit 34 (described later) via vertical signal lines 44.

[0019] (Column Signal Processing Circuit Unit 34) The column signal processing circuit unit 34 is arranged for each column of the image sensor 100, and performs signal processing such as noise removal for each pixel column on pixel signals output from one row of the image sensor 100. For example, the column signal processing circuit unit 34 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion in order to remove fixed pattern noise specific to each pixel.

[0020] (Horizontal drive circuit unit 36) The horizontal drive circuit unit 36 ​​is formed, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the above-mentioned column signal processing circuit units 34 in turn, and cause each column signal processing circuit unit 34 to output a pixel signal to the horizontal signal line 46.

[0021] (Output Circuit Unit 38) The output circuit unit 38 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 34 via the horizontal signal line 46 and outputs the processed signals. The output circuit unit 38 may function as a functional unit that performs buffering, or may perform processes such as black level adjustment, column variation correction, and various digital signal processing. Note that buffering refers to temporarily storing pixel signals to compensate for differences in processing speed and transfer speed when exchanging pixel signals. Furthermore, the input / output terminals 48 are terminals for exchanging signals with external devices.

[0022] (Control Circuit Unit 40) The control circuit unit 40 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the imaging device 1. That is, the control circuit unit 40 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit unit 40 then outputs the generated clock signals and control signals to the vertical drive circuit unit 32, the column signal processing circuit unit 34, the horizontal drive circuit unit 36, etc.

[0023] In the embodiment of the present disclosure, the configuration of the imaging device 1 is not limited to the configuration shown in FIG.

[0024] <<2. Schematic Configuration of Image Sensor According to Comparative Example>> In the above-described image sensor 1, in order to further improve the autofocus function while avoiding degradation of the captured image, i.e., to improve the accuracy of phase difference detection, image sensors 100a capable of phase difference detection are provided on the entire surface of the pixel array unit 30. Specifically, the image sensor 100a functions as a single image sensor during image capture and as a pair of phase difference detection pixels during phase difference detection. By providing such image sensors 100a on the entire surface of the pixel array unit 30, the accuracy of phase difference detection can be improved. Furthermore, since the subject can be captured using all of the image sensors 100a, degradation of the captured image can be avoided.

[0025] Furthermore, in the imaging element 100a, in order to improve the accuracy of phase difference detection, an element is provided that physically and electrically separates the phase difference detection pixels to prevent the outputs of a pair of phase difference detection pixels from being mixed together during phase difference detection.

[0026] The configuration of the image sensor 100a described above will be described below. Note that the image sensor 100a described below is an image sensor that the inventors of the present disclosure had studied extensively before developing the embodiments of the present disclosure, and therefore will be referred to as the image sensor 100a according to the comparative example.

[0027] First, the planar configuration of the image sensor 100a according to the comparative example will be described with reference to Fig. 2. Fig. 2 is an explanatory diagram showing an example of the planar configuration of the image sensor 100a according to the comparative example, and more specifically, shows a cross section of the image sensor 100a cut parallel to the surface of the semiconductor substrate 10.

[0028] 2, the image sensor 100a has an element isolation wall 310 that surrounds the element region of the semiconductor substrate 10 and partitions the element region of each image sensor 100a. The image sensor 100a has adjacent pixels 300a and 300b in the element region surrounded by the element isolation wall 310. The element isolation wall 310 is formed as a through-DTI (Deep Trench Isolation) by a trench (not shown) that penetrates the semiconductor substrate 10 in the film thickness direction of the semiconductor substrate 10 and a silicon oxide film (SiO ２ ) and other materials such as oxide films and metal films.

[0029] Furthermore, each of the pixels 300a and 300b has a photoelectric conversion unit (not shown). The photoelectric conversion unit has, for example, a first conductivity type (e.g., N-type) impurity in a second conductivity type (e.g., P-type) semiconductor substrate 10. The photoelectric conversion unit can absorb incident light having a red wavelength component, a green wavelength component, or a blue wavelength component and generate electric charges.

[0030] The photoelectric conversion unit of pixel 300a and the photoelectric conversion unit of pixel 300b function as a pair of phase difference detection pixels during phase difference detection. Specifically, the amount of charge generated by the photoelectric conversion unit, i.e., its sensitivity, varies depending on the angle of incidence of light relative to its own optical axis (the axis perpendicular to the light-receiving surface). For example, the photoelectric conversion unit has the highest sensitivity when the angle of incidence is 0 degrees. Furthermore, the sensitivity of the photoelectric conversion unit is symmetrical with respect to the angle of incidence, with the axis of symmetry being the angle of incidence of 0 degrees. Therefore, light from the same point is incident at different angles on the photoelectric conversion units of pixel 300a and pixel 300b, and each generates an amount of charge according to the angle of incidence, resulting in a shift (phase difference) in the detected images. That is, the phase difference can be detected by detecting the difference in pixel signals based on the amount of charge generated by the photoelectric conversion units of pixel 300a and pixel 300b. Therefore, autofocusing can be achieved by detecting such a difference (phase difference) between the pixel signals as a differential signal in a detection unit (not shown) of the output circuit unit 38, calculating the defocus amount based on the detected phase difference, and adjusting (moving) the imaging lens (not shown). Note that in the above description, the phase difference is detected as the difference between the pixel signals of the photoelectric conversion unit of pixel 300a and the photoelectric conversion unit of pixel 300b, but this is not limiting, and the phase difference may be detected as the ratio of the pixel signals of the photoelectric conversion unit of pixel 300a and the photoelectric conversion unit of pixel 300b, for example.

[0031] As described above, in the image sensor 100a according to the comparative example, the phase difference can be detected by detecting the difference between pixel signals based on the charges generated by the photoelectric conversion unit of pixel 300a and the photoelectric conversion unit of pixel 300b.

[0032] As shown in FIG. 2 , the pixels 300 a and 300 b are separated by a pixel isolation wall 304 formed integrally with the element isolation wall 310. Specifically, the pixel isolation wall 304 is provided to extend in the column direction (the up-down direction in FIG. 2 ) between the pixels 300 a and 300 b adjacent in the row direction (the left-right direction in FIG. 2 ). The pixel isolation wall 304 is formed as a through-DTI by a trench (not shown) provided to penetrate the semiconductor substrate 10 along the film thickness direction (depth direction) of the semiconductor substrate 10, and a material formed in the trench, such as an oxide film or a metal film. That is, in the comparative example, the pixel isolation wall 304 and the element isolation wall 310 may be formed from the same material. In the image sensor 100 a, if pixel signals output from a pair of pixels 300 a and 300 b mix with each other during phase difference detection, resulting in color mixing, the accuracy of phase difference detection will be degraded. Therefore, in the comparative example, a pixel separation wall 304 is provided that penetrates the semiconductor substrate 10, effectively physically separating the pair of pixels 300a, 300b, thereby suppressing the occurrence of color mixing and further improving the accuracy of phase difference detection.

[0033] Furthermore, the pixel isolation wall 304 has a slit 312 at the center of the image sensor 100a. In other words, the pixel isolation wall 304 has two wall portions that protrude in the column direction from the element isolation wall 310 toward the center of the image sensor 100a and face each other with the slit 312 between them.

[0034] Furthermore, in the region within the slit 312 in the semiconductor substrate 10, impurities of a second conductivity type (e.g., P-type) are diffused through the pixel isolation wall 304 by conformal doping or the like to form a diffusion region (not shown). Similarly, in the region around the element isolation wall 310 in the semiconductor substrate 10, impurities of the second conductivity type are diffused through the element isolation wall 310 by conformal doping to form a diffusion region. The diffusion region within the slit 312 electrically isolates the pair of pixels 300a and 300b to further improve the accuracy of phase difference detection and prevent color mixing. Furthermore, diffusion regions (not shown) containing impurities of the second conductivity type are formed along the element isolation wall 310 and the pixel isolation wall 304. Such diffusion regions provided around the element isolation wall 310 and the pixel isolation wall 304 can suppress the generation of dark current in the image sensor 100a by a pinning effect.

[0035] Furthermore, in this comparative example, the charges generated in the photoelectric conversion units of pixels 300a and 300b are transferred to the charge accumulation unit 340 via transfer gates 400a and 400b of transfer transistors (one type of pixel transistor described above) provided on a surface 10b located on the opposite side from the light-receiving surface of the semiconductor substrate 10. In detail, the transfer gates 400a and 400b are formed of, for example, a metal film provided at the center of each of the pixels 300a and 300b, and transfer the charges to, for example, a charge accumulation unit (floating diffusion (FD) unit) 340 provided in a semiconductor region containing impurities of a first conductivity type (e.g., N-type) provided in the semiconductor substrate 10. In the comparative example, the pixels 300a and 300b share a single charge accumulation unit 340.

[0036] As shown in FIG. 2, on the opposite side of the charge storage section 340 across the center of the pixels 300a and 300b, a well contact 330, which is a semiconductor region containing impurities of a second conductivity type (e.g., P type) and is provided in the semiconductor substrate 10, is provided.

[0037] Next, referring to FIG. 3 , the charge readout operation in the image sensor 100a according to the comparative example will be described. FIG. 3 is an explanatory diagram showing an example of the operation of the image sensor 100a according to the comparative example. As described above, in the comparative example, the pixels 300a and 300b share a single charge accumulation unit 340. Therefore, the charges generated in the photoelectric conversion units of the pixels 300a and 300b are read out as follows. First, as shown on the left side of FIG. 3 , in the image sensor 100a according to the comparative example, the charge accumulation unit (FD) 340 is reset, and the charges generated in the pixel 300a on the left side (L side) are transferred to the charge accumulation unit 340 and read out. Next, as shown on the right side of FIG. 3 , in the image sensor 100a according to the comparative example, the charge accumulation unit 340 is reset, and the charges generated in the pixel 300b on the right side (R side) are transferred to the charge accumulation unit 340 and read out. In this way, in the comparative example, charges can be efficiently read out from the single charge accumulation unit 340 shared by the pixels 300a and 300b.

[0038] <<3. Background>> Next, the background that led the inventors to create the embodiments of the present disclosure will be described, taking into account the image sensor 100a according to the comparative example described above.

[0039] In recent years, there has been a strong demand for further miniaturization of the image sensor 100. Therefore, for example, as miniaturization of the image sensor 100a according to the comparative example progresses, the distance between the well contact 330, the transfer gate 400, and the charge storage section 340 becomes shorter in the image sensor 100a in a planar view, and a strong electric field is generated between them. As a result, a phenomenon has emerged in which unintended transfer of electric charges is more likely to occur in the miniaturized image sensor 100a. In other words, one of the challenges for the image sensor 100a according to the comparative example has been suppressing the generation of a strong electric field (alleviating the electric field).

[0040] There is also a strong demand for a faster readout speed for the imaging device 1. As described with reference to FIG. 3 , in the imaging element 100a according to the comparative example, charges generated in the left and right pixels 300a and 300b are transferred to the charge accumulation section 340 in two stages, and pixel signals are read out. In the imaging element 100a according to the comparative example, the charge is transferred in two stages in this manner, resulting in a slow readout speed. Therefore, increasing the readout speed has been one of the challenges.

[0041] The present inventors conducted extensive research to solve these problems and came up with embodiments of the present disclosure. In one embodiment created by the present inventors, pixels 300a and 300b each have a charge storage unit 340 and share a single transfer gate 400. In this embodiment, charges generated in each of the pixels 300a and 300b are simultaneously transferred to the respective charge storage units 340 via the single shared transfer gate 400. In this embodiment, by having the pixels 300a and 300b share a single transfer gate 400, the distance between the well contact 330, the transfer gate 400, and the charge storage unit 340 can be prevented from becoming too close, thereby reducing the strength of the electric field that is generated. Additionally, in this embodiment, charges generated in each of the pixels 300a and 300b can be simultaneously transferred to the respective charge storage units 340, thereby increasing the readout speed.

[0042] Hereinafter, each embodiment of the present disclosure will be described. In each embodiment of the present disclosure, elements that are not specifically described will basically have the same form as the image sensor 100a of the comparative example.

[0043] <<4. First Embodiment>> <4.1 Detailed Configuration> First, detailed configurations of the image sensor 100 and pixel array section 30 according to this embodiment will be described with reference to FIGS. 4A, 4B, and 5. FIG. 4A is an explanatory diagram showing an example of the planar configuration of the image sensor 100 according to this embodiment, specifically showing a cross section of the image sensor 100 taken parallel to the surface of the semiconductor substrate 10. FIG. 4B is an explanatory diagram showing an example of the cross-sectional configuration of the image sensor 100 according to this embodiment, specifically showing, from the left, a cross section of the image sensor 100 taken along line A-A' in FIG. 4A, a cross section of the image sensor 100 taken along line B-B' in FIG. 4A, and a cross section of the image sensor 100 taken along line C-C' in FIG. 4A. Furthermore, FIG. 5 is an explanatory diagram showing an example of the planar configuration of the pixel array section 30 according to this embodiment.

[0044] 4A and 4B , the imaging element 100 has an element isolation wall 310 that surrounds an element region of the semiconductor substrate 10 and partitions the element region in which each imaging element 100 is formed. The imaging element 100 has pixels 300a and 300b that are adjacent to each other along the row direction (the left-right direction in FIG. 4A ) within the element region surrounded by the element isolation wall 310. In detail, the element isolation wall 310 is formed as a through-DTI by a trench (not shown) that penetrates the semiconductor substrate 10 along the film thickness direction (depth direction) of the semiconductor substrate 10, and a silicon oxide film (SiO ) embedded in the trench. ２ ), silicon nitride film (Si ３ N ４ ), amorphous silicon, polycrystalline silicon, titanium oxide film (TiO ２ ), aluminum (Al), tungsten (W), or other oxide or metal film.

[0045] 4B , each of the pixels 300 a and 300 b includes a photoelectric conversion unit 302. The photoelectric conversion unit 302 has, for example, a first conductivity type (e.g., N-type) impurity in a second conductivity type (e.g., P-type) semiconductor substrate 10. The photoelectric conversion unit 302 can absorb incident light having a red wavelength component, a green wavelength component, or a blue wavelength component and generate electric charges, i.e., can perform photoelectric conversion.

[0046] 4A and 4B , in this embodiment, the pixels 300 a and 300 b are also separated by a pixel isolation wall 304 formed integrally with the element isolation wall 310. Specifically, the pixel isolation wall 304 is provided to extend in the column direction (the vertical direction in FIG. 4A ) between the pixels 300 a and 300 b adjacent in the row direction. The pixel isolation wall 304 is formed as a through-DTI by a trench (not shown) provided to penetrate the semiconductor substrate 10 in the film thickness direction of the semiconductor substrate 10, and a material such as an oxide film or a metal film, such as a silicon oxide film, a silicon nitride film, amorphous silicon, polycrystalline silicon, a titanium oxide film, aluminum, or tungsten, embedded in the trench. That is, in this embodiment, the pixel isolation wall 304 and the element isolation wall 310 may be formed from the same material.

[0047] 4A , the pixel isolation wall 304 has a slit 312 at the center (middle) of the image sensor 100. In other words, the pixel isolation wall 304 has two wall portions that protrude in the column direction from the element isolation wall 310 toward the center of the image sensor 100 and face each other with the slit 312 in between. The slit 312 also extends from the surface 10b of the semiconductor substrate 10 in the film thickness direction of the semiconductor substrate 10.

[0048] 4B , a diffusion region 306 is formed within the slit 312 in the semiconductor substrate 10 by diffusing impurities of a second conductivity type (e.g., P-type) through the pixel isolation wall 304, for example, by conformal doping. Similarly, a diffusion region 308 is formed in the region surrounding the element isolation wall 310 in the semiconductor substrate 10 by diffusing impurities of the second conductivity type through the element isolation wall 310, for example, by conformal doping. The diffusion region 306 in the slit 312 electrically isolates the pair of pixels 300 a, 300 b to further improve the accuracy of phase difference detection and prevent color mixing. Furthermore, a diffusion region 308 containing impurities of the second conductivity type is formed along the element isolation wall 310 and the pixel isolation wall 304. The diffusion region 308 can suppress the generation of dark current in the image sensor 100 by a pinning effect.

[0049] Furthermore, in this embodiment, charges generated in the photoelectric conversion units 302 of the pixels 300a and 300b are transferred to the charge accumulation units 340a and 340b provided for the pixels 300a and 300b, respectively, via a common transfer gate 400 of a transfer transistor provided on the surface 10b of the semiconductor substrate 10, which is located on the opposite side from the light-receiving surface 10a. Specifically, as shown in FIG. 4A , the common transfer gate 400 is made of, for example, a metal film and provided at the center (middle) of the image sensor 100, i.e., within the slit 312. Furthermore, as shown in FIG. 4B , the common transfer gate 400 has a vertical gate portion 402 extending from the surface 10b of the semiconductor substrate 10 in the film thickness direction (depth direction) of the semiconductor substrate 10. By using a vertical gate transistor having such a vertical gate portion 402 as the transfer transistor, charges generated deep within the semiconductor substrate 10 can be efficiently transferred. The cross section of the vertical gate portion 402 is not limited to being rectangular as shown in FIG. 4B, and in this embodiment, it may be, for example, tapered, and is not particularly limited.

[0050] In this embodiment, adjacent pixels 300 a and 300 b in the row direction share one common transfer gate 400. The shared common transfer gate 400 can simultaneously transfer the charges generated in the pixels 300 a and 300 b to the charge storage sections (floating diffusion (FD) sections) 340 a and 340 b provided for each pixel 300 a and 300 b (see the arrows in FIG. 4A ).

[0051] 4A , contact portions 342 for electrically connecting adjacent charge accumulation portions 340 are provided on the element isolation wall 310 at corners of the image sensor 100 located near the charge accumulation portions 340 a and 340 b. Furthermore, the contact portions 342 are provided with through contacts 350.

[0052] 4A , a well contact 330, which is a semiconductor region containing impurities of a second conductivity type (e.g., P-type) and is provided in the semiconductor substrate 10, is provided on the opposite side (position of line symmetry) of the charge accumulation units 340a and 340b with the center of the pixels 300a and 300b as the axis of symmetry. In this embodiment, by providing the well contact 330 in such a position, the energy potential distribution in the semiconductor substrate 10 where the well contact 330, the photoelectric conversion unit 302, and the charge accumulation unit 340 are arranged is set to a desired state, thereby enabling efficient transfer of generated charges. Furthermore, a contact portion 332 for electrical connection to the well contact 330 is provided on the element isolation wall 310 located near the well contact 330. A through contact 350 is also provided in the contact portion 332.

[0053] Although not shown, the image sensor 100 also has one on-chip lens that is provided above the light-receiving surface 10a of the semiconductor substrate 10 and focuses incident light onto the photoelectric conversion unit 302. For example, the image sensor 100 has a structure in which a pair of pixels 300a, 300b are provided for one on-chip lens. In other words, the on-chip lens is shared by the two pixels 300a, 300b. The on-chip lens can be formed from, for example, a silicon nitride film or a resin material such as a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer resin, or a siloxane-based resin.

[0054] The incident light collected by the on-chip lens is incident on each of the photoelectric conversion units 302 of the pixels 300 a and 300 b via a color filter (not shown) provided below the on-chip lens. The color filter is any one of a color filter that transmits red wavelength components, a color filter that transmits green wavelength components, and a color filter that transmits blue wavelength components. For example, the color filter can be formed from a material in which a pigment or dye is dispersed in a transparent binder such as silicone.

[0055] In this embodiment, for example, pixel transistors that operate the image sensor 100 can be formed on another semiconductor substrate (not shown) stacked on the semiconductor substrate 10. Specifically, the image sensor 100, including a photoelectric conversion unit, a common transfer gate 400, a charge storage unit 340, etc., is formed on the semiconductor substrate 10, pixel transistors are formed on the other semiconductor substrate, and the semiconductor substrate 10 and the other semiconductor substrate are further stacked. In this embodiment, employing such a stacked structure also enables the image sensor 1 to be further miniaturized. Furthermore, in such a stacked structure, through contacts 350 are provided to electrically connect the pixel transistors and the image sensor 100. Even in this case, since the common transfer gate 400 is shared, the number of transfer gates 400 is reduced by one, and accordingly, the number of through contacts connected to the transfer gates 400 is reduced. This improves the flexibility of layout in the semiconductor substrate 10 and the other semiconductor substrate, enabling further miniaturization of the image sensor 100. As will be described later, in this embodiment, the pixel transistors are not limited to being provided on another semiconductor substrate, but may be provided on the semiconductor substrate 10 .

[0056] As described above, in this embodiment, the pixels 300a and 300b share one transfer gate 400, and thus the charges generated in each of the pixels 300a and 300b can be simultaneously transferred to the respective charge accumulation units 340 by the single shared transfer gate 400. In this embodiment, the pixels 300a and 300b share one common transfer gate 400, and therefore the distance between the well contact 330, the common transfer gate 400, and the charge accumulation unit 340 can be prevented from becoming too close, thereby reducing the strength of the electric field that is generated. In addition, in this embodiment, the charges generated in each of the pixels 300a and 300b can be simultaneously transferred to the respective charge accumulation units 340, thereby increasing the readout speed.

[0057] 5, the image pickup elements 100 according to this embodiment can be arranged in a matrix along the row and column directions in the pixel array section 30 of the image pickup device 1. For example, in four adjacent image pickup elements 100, the charge storage sections 340 provided for the pixels 300 can be electrically connected to each other and shared by these four image pickup elements 100.

[0058] In this embodiment, the imaging element 100 and the pixel array section 30 are not limited to the forms shown in FIGS. 4A, 4B, and 5, but can be modified into various forms.

[0059] 4.2 Modifications (Modification 1) Next, Modification 1 will be described with reference to FIGS. 6A and 6B . FIG. 6A is an explanatory diagram showing an example of the planar configuration of a pixel array unit 30 according to Modification 1, and FIG. 6B is an explanatory diagram showing an example of the circuit configuration of the pixel array unit 30 according to Modification 1, which corresponds to the example configuration of FIG. 6A . In detail, as shown in FIG. 6A , the color filters 500 of each image sensor 100 are composed of a color filter (R) that transmits red wavelength components, a color filter (G) that transmits green wavelength components, or a color filter (B) that transmits blue wavelength components. These color filters 500 are arranged in a Bayer array. Here, the Bayer array is an array pattern in which color filters (G) that transmit green wavelength components are arranged in a checkerboard pattern, and color filters (R) that transmit red wavelength components and color filters (B) that transmit blue wavelength components are arranged alternately in each row in the remaining portion.

[0060] Furthermore, in Figures 6A and 6B, area C indicates the range of one image sensor 100, and the four image sensors 100 arranged in a 2x2 pattern are shown in area B, and as described above, they share one charge storage section (FD) 340 (more specifically, they are electrically connected to form one charge storage section 340).

[0061] (Variation 2) Next, Variation 2 will be described with reference to FIG. 7 . FIG. 7 is an explanatory diagram showing an example of the planar configuration of a pixel array unit 30 according to Variation 2. As shown in FIG. 7 , in Variation 2, four image sensors 100 arranged in a 2×2 matrix have color filters 500 of the same color. The color filters 500 of these four image sensors 100 form one unit, and the color filters 500 made up of these multiple units are arranged in a Bayer array. Note that a Bayer array in which the color filters 500 of four image sensors 100 form one unit is referred to as a quad-Bayer array.

[0062] In this embodiment and its modifications, the color filter 500 is not limited to a color filter that transmits a red wavelength component, a color filter that transmits a green wavelength component, or a color filter that transmits a blue wavelength component, but may be a color filter that transmits wavelength components of other colors. Furthermore, in this embodiment and its modifications, the color filter 500 is not limited to a Bayer array or a Quad Bayer array, and can be modified as appropriate according to the desired specifications of the image capture device 1.

[0063] 5. Second Embodiment Next, a second embodiment of the present disclosure will be described with reference to Fig. 8A and Fig. 8B. Fig. 8A is an explanatory diagram showing an example of the planar configuration of a pixel array unit 30 according to this embodiment, and Fig. 8B is an explanatory diagram showing an example of the circuit configuration of the pixel array unit 30 according to this embodiment, which corresponds to the example configuration of Fig. 8A.

[0064] In the previously described first modification, four image sensors 100 arranged in a 2×2 matrix share one charge accumulation section 340. However, this embodiment is not limited to this. For example, in the second modification, as shown in FIGS. 8A and 8B , eight image sensors 100 arranged in a 2×4 matrix, designated as region D, share one charge accumulation section (FD) 340 (more specifically, are electrically connected to form one charge accumulation section 340). Note that the charge accumulation sections (FD) 340 within region D shown in FIG. 8A are electrically connected to each other by wiring (not shown in FIG. 8A ), as shown in the circuit diagram of FIG. 8B . In this embodiment, sharing the charge accumulation section 340 increases the length of the wiring connecting the charge accumulation sections 340, and the resistance of the wiring reduces the conversion efficiency of the image sensor 100. However, in this embodiment, sharing the charge accumulation section 340 improves the flexibility of the layout of pixel transistors. For example, if the degree of freedom in layout is improved, it becomes possible to increase the gate length of the amplifying transistor, thereby making it possible to suppress the occurrence of random noise.

[0065] 6. Third Embodiment Next, a detailed configuration of an image sensor 100 according to a third embodiment of the present disclosure will be described with reference to FIGS. 9 and 10. FIGS. 9 and 10 are explanatory diagrams including an example cross-sectional configuration of the image sensor 100 according to this embodiment and a corresponding potential diagram. In detail, the left side of the diagram shows a cross section of the image sensor 100 according to the third embodiment, which corresponds to the cross section taken along line B-B' in FIG. 4B, and the right side of the diagram shows potential energy within the semiconductor substrate 10 of the image sensor 100.

[0066] In this embodiment, as shown on the left side of FIGS. 9 and 10 , a blooming path 360 is provided between a pair of pixels 300a and 300b to prevent degradation of the captured image (blooming) due to saturation of the image sensor 100. Blooming is a phenomenon in which a large amount of charge is generated when strong light is incident on the image sensor 100, and the overflowing charge leaks to the other neighboring image sensor 100, resulting in degradation of the captured image. Therefore, during normal image capture, when the charge of one of the pair of pixels 300a and 300b approaches saturation, the charge is transferred to the other pixel 300 via the blooming path 360, thereby preventing saturation of the one pixel 300. By providing such a blooming path 360, the linearity of the pixel signal output from the image sensor 100 can be ensured, preventing degradation of the captured image.

[0067] Specifically, as shown on the left side of FIG. 9 , the blooming path 360 can be provided directly below the vertical gate portion 402 of the common transfer gate 400 and on the surface of the diffusion region 306 on the surface 10b side. The blooming path 360 can contain impurities of a second conductivity type (e.g., P-type) like the diffusion region 306, but at a lower concentration than the diffusion region 306. The distribution of impurities in the diffusion region 306 and the blooming path 360 can be observed using a scanning spread resistance microscope (SSRM) or the like. By providing such a blooming path 360, the potential energy in the semiconductor substrate 10 changes from the dashed line to the solid line, as shown on the right side of FIG. 9 . In other words, the blooming path 360, which is the position where the potential drops, functions as a path for exchanging generated charges between the pixels 300a and 300b.

[0068] Therefore, in the image sensor 100 according to this embodiment, during phase difference detection, the pair of pixels 300 a, 300 b is separated by the pixel separation wall 304 and the diffusion region 306, while during normal imaging, charge can be exchanged between the pixels 300 a, 300 b via the blooming path 360. Therefore, according to this embodiment, it is possible to improve the accuracy of phase difference detection while avoiding degradation of the captured image.

[0069] In this embodiment, the blooming path 360 may be provided at a deep position separated by a predetermined distance from the surface on the front surface 10b side of the diffusion region 306, as shown on the left side of Fig. 10. By doing so, the potential energy in the semiconductor substrate 10 changes from the state shown by the dashed line to the state shown by the solid line, as shown on the right side of Fig. 10. In other words, the blooming path 360, which is the position where the potential drops, is separated from the vertical gate portion 402 of the common transfer gate 400, and therefore the occurrence of dark current leakage can be suppressed.

[0070] In this embodiment, the image sensor 100 is not limited to the configuration shown on the left side of Fig. 9 and Fig. 10, but can be modified into various other configurations. For example, the position at which the blooming path 360 is provided in the film thickness direction of the semiconductor substrate 10 is not limited to the position shown in Fig. 10.

[0071] 7. Fourth Embodiment Next, a detailed configuration of an image sensor 100 according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 11A and 11B . FIG. 11A is an explanatory diagram showing an example of the planar configuration of the image sensor 100 according to this embodiment, and more specifically, shows a cross section of the image sensor 100 taken parallel to the surface of the semiconductor substrate 10. FIG. 11B is an explanatory diagram showing an example of the cross-sectional configuration of the image sensor 100 according to this embodiment, and more specifically, shows, from the left, a cross section of the image sensor 100 taken along line A-A' in FIG. 11A , a cross section of the image sensor 100 taken along line B-B' in FIG. 11A , and a cross section of the image sensor 100 taken along line C-C' in FIG. 11A .

[0072] In this embodiment, as shown in FIG. 11A , the common transfer gate 400 is provided so as to extend from the center of one pixel 300 a to the center of the other pixel 300 b. Furthermore, in this embodiment, as shown in FIG. 11B , the common transfer gate 400 has multiple vertical gate portions 402. Specifically, the multiple vertical gate portions 402 are provided in different pixels 300 a and 300 b. For example, the vertical gate portions 402 are located at the center (middle) of each pixel 300 a and 300 b. In this embodiment, by providing the common transfer gate 400 with multiple vertical gate portions 402, charges can be efficiently transferred from the photoelectric conversion portions 302 located deep in the central regions of the pixels 300 a and 300 b. Note that in this embodiment, the number of vertical gate portions 402 included in one common transfer gate 400 is not limited to two, and may be three or more.

[0073] 11A and 11B, the image sensor 100 may be modified into various forms. For example, the blooming path 360 of the third embodiment may be provided in the present embodiment.

[0074] In addition, in this embodiment, an insulating film (not shown) may be provided around the two vertical gate portions 402 at a shallow position on the surface 10b side within the semiconductor substrate 10, thereby reducing the electric field strength at a shallow position in the semiconductor substrate 10.

[0075] <<8. Fifth Embodiment>> Next, a detailed configuration of an image sensor 100 according to a fifth embodiment of the present disclosure will be described with reference to Fig. 12A and Fig. 12B . Fig. 12A is an explanatory diagram showing an example of the planar configuration of the image sensor 100 according to this embodiment, and more specifically, shows a cross section of the image sensor 100 taken parallel to the surface of the semiconductor substrate 10. Fig. 12B is an explanatory diagram showing an example of the cross-sectional configuration of the image sensor 100 according to this embodiment, and more specifically, shows, from the left, a cross section of the image sensor 100 taken along line A-A' in Fig. 12A , a cross section of the image sensor 100 taken along line B-B' in Fig. 12A , and a cross section of the image sensor 100 taken along line C-C' in Fig. 12A .

[0076] In the above-described fourth embodiment, the common transfer gate 400 has a plurality of vertical gate portions 402. On the other hand, in the present embodiment, as shown in Figures 12A and 12B, although the common transfer gate 400 has one vertical gate portion 402, the width of the vertical gate portion 402 in the row direction is increased so that the vertical gate portion 402 extends from the center of one pixel 300a to the center of the other pixel 300b.

[0077] In the fourth embodiment, there is a possibility that charges that have entered between the two vertical gate portions 402 may stray, but in this embodiment, the vertical gate portions 402 are extended so as to connect the two vertical gate portions 402 in the fourth embodiment, so that charges do not enter between the two vertical gate portions 402 and it is possible to suppress the occurrence of stray charges. Therefore, in this embodiment, charges from the photoelectric conversion portion 302 can be transferred efficiently.

[0078] 12A and 12B, the image sensor 100 may be modified into various forms. For example, the blooming path 360 of the third embodiment may be provided in the present embodiment.

[0079] <<9. Sixth Embodiment>> Next, a detailed configuration of an image sensor 100 according to a sixth embodiment of the present disclosure will be described with reference to Fig. 13. An example of the planar configuration of the image sensor 100 according to this embodiment corresponds to the example of the planar configuration of the image sensor 100 according to the first embodiment shown in Fig. 4A, except for the vertical gate portion 402. Fig. 13 is also an explanatory diagram showing an example of the cross-sectional configuration of the image sensor 100 according to this embodiment, and in detail shows, from the left, a cross section of the image sensor 100 taken along line A-A' shown in Fig. 4A, a cross section of the image sensor 100 taken along line B-B' shown in Fig. 4A, and a cross section of the image sensor 100 taken along line C-C' shown in Fig. 4A.

[0080] In the first embodiment described above, the common transfer gate 400 has the vertical gate portion 402. On the other hand, in the present embodiment, as shown in FIG.

[0081] In this embodiment, since the common transfer gate 400 does not have the vertical gate portion 402, the charge transfer efficiency is inferior to that of the first embodiment. However, since the photoelectric conversion portion 302 can be extended close to the surface 10b of the semiconductor substrate 10, it is possible to avoid a reduction in the volume of the photoelectric conversion portion 302. As a result, in this embodiment, it is possible to suppress a decrease in the amount of saturated charge. Furthermore, in this embodiment, since the common transfer gate 400 does not have the vertical gate portion 402, it is possible to simplify part of the manufacturing process, improve the yield of the image pickup device 1, and suppress an increase in manufacturing costs.

[0082] <<10. Seventh Embodiment>> <10.1 Detailed Configuration> Next, a detailed configuration of an image sensor 100 according to a seventh embodiment of the present disclosure will be described with reference to FIGS. 14A , 14B , and 15 . FIG. 14A is an explanatory diagram showing an example of the planar configuration of the image sensor 100 according to this embodiment, specifically showing a cross section of the image sensor 100 taken parallel to the surface of the semiconductor substrate 10. FIG. 14B is an explanatory diagram showing an example of the cross-sectional configuration of the image sensor 100 according to this embodiment, specifically showing, from the left, a cross section of the image sensor 100 taken along line A-A' in FIG. 14A , a cross section of the image sensor 100 taken along line B-B' in FIG. 14A , and a cross section of the image sensor 100 taken along line C-C' in FIG. 14A . FIG. 15 is an explanatory diagram illustrating the effect of the image sensor 100 according to this embodiment.

[0083] In the embodiments described so far, the pixel separation wall 304 has a slit 312 at the center of the image sensor 100, and a diffusion region 306 provided within the slit 312 electrically separates the pair of pixels 300a and 300b. In contrast, in this embodiment, the slit 312 and the diffusion region 306 are not provided, and the pair of pixels 300a and 300b are physically separated by the pixel separation wall 304. In detail, in this embodiment, as shown in FIG. 14A , the pixel separation wall 304 extends along the column direction so as to pass through the center of the image sensor 100. Furthermore, as shown in FIG. 14B , the common transfer gate 400 has a plurality of vertical gate portions 402, and is arranged so that the pixel separation wall 304 is sandwiched between two vertical gate portions 402.

[0084] According to this embodiment, the pair of pixels 300 a, 300 b can be physically separated by the pixel separation wall 304 that does not have the slit 312, and therefore it is possible to further suppress the occurrence of color mixing between the adjacent pixels 300 a, 300 b. As a result, in this embodiment, the angle responsiveness of light of the image sensor 100 is improved, and the accuracy of phase difference detection can be further improved.

[0085] Furthermore, in this embodiment, a diffusion region 308 containing impurities of the second conductivity type can be formed along the pixel separation wall 304 that does not have the slit 312. This diffusion region 308 along the pixel separation wall 304 can generate a strong electric field at the interface of the pixel separation wall 304. As a result, in this embodiment, a potential valley that suddenly deepens as shown in FIG. 15 can be provided in each of the pixels 300 a, 300 b, and the amount of saturation charge in the pixels 300 a, 300 b can be increased.

[0086] Furthermore, pixel signal loss is likely to occur in regions close to the saturated charge amount, making it difficult to ensure linearity of pixel signals in such regions. Therefore, in the image sensor 100a according to the comparative example, the usable range of the image sensor 100a is set so as not to include the range where such loss is likely to occur. Furthermore, in the image sensor 100a according to the comparative example, a blooming path 360 is provided to improve linearity. However, when the range is set in this manner, the image sensor 100a according to the comparative example inevitably has a narrow usable range due to the low saturated charge amount.

[0087] However, in this embodiment, the saturated charge amount of the pixels 300a and 300b is increased, and therefore the range in which the linearity of the pixel signal is ensured is broadened. Therefore, in this embodiment, even if the range in which defects are likely to occur is set not to include the range in which the linearity of the pixel signal is ensured, the usable range in which the linearity of the pixel signal is ensured can be broadened compared to the comparative example. Furthermore, in this embodiment, the range in which the linearity of the pixel signal is ensured is broad, and therefore there is no need to provide the blooming path 360 described above.

[0088] In this embodiment, the imaging element 100 is not limited to the configuration shown in FIGS. 14A and 14B, but can be modified into various other configurations.

[0089] 10.2 Modifications Next, a detailed configuration of an image sensor 100 according to a modification of this embodiment will be described with reference to FIGS. 16 and 17 . FIG. 16 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a first modification of this embodiment, and FIG. 17 is an explanatory diagram showing an example cross-sectional configuration of an image sensor 100 according to a second modification of this embodiment. The planar configuration examples of the image sensor 100 according to the first and second modifications correspond to the planar configuration example of the image sensor 100 according to this embodiment shown in FIG. 14A . Furthermore, FIGS. 16 and 17 show, from the left, a cross section of the image sensor 100 taken along line A-A' in FIG. 14A , a cross section of the image sensor 100 taken along line B-B' in FIG. 14A , and a cross section of the image sensor 100 taken along line CC' in FIG. 14A .

[0090] As shown in FIG. 16, in the first modification, the width in the row direction of the vertical gate portions 402 of the common transfer gate 400 provided so as to sandwich the pixel separation wall 304 is made wider than that of the present embodiment.

[0091] Furthermore, as shown in FIG. 17, in the second modification, the common transfer gate 400 does not have to have the vertical gate portion 402 .

[0092] <<11. Eighth Embodiment>> <11.1 Detailed Configuration> Next, a detailed configuration of an image sensor 100 according to an eighth embodiment of the present disclosure will be described with reference to FIGS. 18A , 18B , 19A , and 19B . FIG. 18A is an explanatory diagram showing an example of the planar configuration of the image sensor 100 according to this embodiment, and more specifically, shows a cross section of the image sensor 100 taken parallel to the surface of the semiconductor substrate 10. FIG. 18B is an explanatory diagram showing an example of the cross-sectional configuration of the image sensor 100 according to this embodiment, and more specifically, shows, from the left, a cross section of the image sensor 100 taken along line A-A' in FIG. 18A , a cross section of the image sensor 100 taken along line B-B' in FIG. 18A , and a cross section of the image sensor 100 taken along line C-C' in FIG. 18A . Furthermore, Figure 19A is an explanatory diagram showing an example of the planar configuration of the pixel array section 30 according to this embodiment, and Figure 19B is an explanatory diagram showing an example of the circuit configuration of the pixel array section 30 according to this embodiment, which corresponds to the example configuration of Figure 19A.

[0093] In the embodiments described so far, the pixels 300a and 300b share one common transfer gate 400. On the other hand, in the eighth embodiment, the pixels 300a and 300b have individual transfer gates.

[0094] Specifically, as shown in FIG. 18A , the pixels 300 a and 300 b each have a transfer gate (common transfer gate) 400 a and 400 b provided on a portion of the element isolation wall 310. The transfer gates 400 a and 400 b are provided at positions that are symmetrical with respect to a line passing through the center of the image sensor 100 along the column direction. Furthermore, as shown in FIG. 18B , the transfer gates 400 a and 400 b each have a plurality of vertical gate portions 402 that extend from the surface 10 b of the semiconductor substrate 10 along the film thickness direction (depth direction) of the semiconductor substrate 10. The plurality of vertical gate portions 402 sandwich the portion of the element isolation wall 310 on the surface 10 b side. In this embodiment, the transfer gates 400 a and 400 b simultaneously transfer electric charges generated in the pixels 300 a and 300 b to the charge storage portions 340 provided for each pixel 300 a and 300 b.

[0095] 19A , a pixel 300b included in one of the adjacent imaging elements 100 and a pixel 300a included in the other imaging element 100 share one transfer gate 400. Two vertical gate portions 402 of the transfer gate 400 are provided in the pixel 300b included in one imaging element 100 and the pixel 300a included in the other imaging element 100. In other words, the two vertical gate portions 402 are provided so as to sandwich the element isolation wall 310 therebetween.

[0096] Furthermore, in Figures 19A and 19B, area E indicates the range of one image sensor 100, and the four image sensors 100 arranged in a 2x2 pattern are shown in area F and share one charge storage section (FD) 340 (more specifically, they are electrically connected to form one charge storage section 340).

[0097] 18A , the charge accumulation units 340a and 340b provided for the pixels 300a and 300b are arranged so as to sandwich the pixel separation wall 304, and are arranged at positions that are point-symmetric with respect to the center of the image sensor 100 with respect to the well contact 330. In this embodiment, the charge accumulation units 340a and 340b are electrically connected to each other, and can be shared between the pixels 300a and 300b.

[0098] As described above, in this embodiment, the pixels 300a and 300b located on different image sensors 100 share a single transfer gate 400, and thus the shared single transfer gate 400 can simultaneously transfer charges generated in the pixels 300a and 300b to the respective charge storage sections 340 located on the different image sensors 100. In this embodiment, the pixels 300a and 300b share a single common transfer gate 400, which prevents the well contact 330, the common transfer gate 400, and the charge storage section 340 from being close to each other, thereby reducing the strength of the electric field that is generated. In addition, in this embodiment, the charges generated in the pixels 300a and 300b located on different image sensors 100 can be simultaneously transferred to the respective charge storage sections 340 located on the different image sensors 100, thereby increasing the readout speed.

[0099] Additionally, in this embodiment, the pixels 300a and 300b located in the same image sensor 100 have different transfer gates 400a and 400b, respectively. Because the transfer gates 400 are different in this way, in this embodiment, it becomes easier to adjust the potential between the pixels 300a and 300b located in the same image sensor 100, and the difficulty of design can be reduced.

[0100] In this embodiment, the image sensor 100 and the pixel array unit 30 are not limited to the configurations shown in FIGS. 18A , 18B , 19A , and 19B , and can be modified into various configurations. For example, the blooming path 360 of the third embodiment described above may also be provided in this embodiment. Also, in this embodiment, multiple vertical gate units 402 may be provided, the width of the transfer gate 400 may be increased, or no vertical gate unit 402 may be provided, as in the fourth to sixth embodiments described above. Furthermore, in this embodiment, the pixel separation wall 304 may not have a slit 312, as in the seventh embodiment.

[0101] <11.2 Modification> Next, a detailed configuration of a pixel array section 30 according to a modification of the present embodiment will be described with reference to Fig. 20. Fig. 20 is an explanatory diagram showing an example of the planar configuration of the pixel array section 30 according to this modification.

[0102] In this modification, for example, as shown in FIG. 20, the color filters 500 can be arranged in a Quad Bayer array.

[0103] <<12. Ninth Embodiment>> Next, a detailed configuration of an image sensor 100 according to a ninth embodiment of the present disclosure will be described with reference to Fig. 21. Fig. 21 is an explanatory diagram showing an example of the planar configuration of the image sensor 100 according to this embodiment, and in detail shows a cross section of the image sensor 100 cut parallel to the surface of the semiconductor substrate 10.

[0104] In the first to seventh embodiments of the present disclosure described above, two pixels 300a and 300b share one common transfer gate 400, which increases the degree of freedom in layout. Therefore, in this embodiment, as shown in FIG. 21 , a pixel transistor 650 can be disposed above the pixels 300a and 300b. For example, in this embodiment, the space above the pixels 300a and 300b is larger than in the comparative example, so an amplification transistor with a long gate length can also be disposed. That is, the pixel transistor 650 can be provided on the semiconductor substrate 10. Note that in the example shown in FIG. 21 , the pixel transistor 650 is disposed above the pixels 300a and 300b of the seventh embodiment, but this embodiment is not limited thereto. For example, the pixel transistor 650 may be disposed above the pixels 300a and 300b of the first embodiment.

[0105] In this embodiment, the pixel transistor 650 provided on the semiconductor substrate 10 may be at least one of a plurality of types of pixel transistors, such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor.

[0106] 22A to 22C are explanatory views showing the manufacturing process of the image sensor 100 according to this embodiment, and in detail, the upper part of each figure shows a cross section of the semiconductor substrate 10 cut parallel to the surface of the semiconductor substrate 10, and the lower part of each figure shows a cross section of the semiconductor substrate 10 cut along line A-A' shown in the upper part of the figure.

[0107] First, as shown on the left side of FIG. 22A , a trench is formed in the semiconductor substrate 10, and a silicon oxide film 600 is embedded in the trench. Next, a trench 602 is further formed in the silicon oxide film 600. Then, as shown in the center of FIG. 22A , a resist 604 is formed in a position corresponding to the common transfer gate 400, and the trench 602 is further excavated. In this manner, the shallow trench 602 corresponding to the vertical gate portion 402 of the common transfer gate 400 and the deep trench 602 corresponding to the element isolation wall 310 and the pixel isolation wall 304 can be simultaneously formed by using the resist 604. Note that the trench 602 corresponding to the element isolation wall 310 and the trench 602 corresponding to the vertical gate portion 402 are formed simultaneously but are separated from each other. In this embodiment, the resist 604 may be formed first, and then the trench 602 may be formed, and the resist 604 may be peeled off in the middle, and the trench 602 may be further excavated. That is, in the manufacturing method of the image sensor 100 according to this embodiment, the shallow trench 602 corresponding to the vertical gate portion 402 of the common transfer gate 400 and the deep trench 602 corresponding to the element isolation wall 310 and the pixel isolation wall 304 are simultaneously formed. In this way, according to this embodiment, it is possible to simplify part of the manufacturing process, thereby improving the yield of the image sensor 1 and suppressing an increase in manufacturing costs.

[0108] Then, as shown on the right side of FIG. 22A , for example, a diffusion region 308 is formed by introducing impurities through the trench 602. The diffusion region 308 provided around the element isolation wall 310 and the pixel isolation wall 304 can suppress the generation of dark current in the image sensor 100 by a pinning effect, but the introduction of impurities for the diffusion region 308 need only be shallow relative to the sidewall of the trench 602. Next, a polysilicon film 608 and a silicon oxide film 600 are sequentially buried in the trench 602. In this manner, the element isolation wall 310 and the pixel isolation wall 304 are formed. In this embodiment, after the polysilicon film 608 is buried, the upper end of the polysilicon film 608 in the trench 602 corresponding to the vertical gate portion 402 may be removed, and then the silicon oxide film 600 may be buried.

[0109] 22B, a trench 610 is formed at the upper end of the element isolation wall 310. Then, as shown in the center of Fig. 22B, a polysilicon film 612 is buried in the trench 610. The buried polysilicon film 612 becomes the contact portions 332 and 342.

[0110] 22B, impurities are introduced into the semiconductor substrate 10 surrounded by the element isolation wall 310 to form the photoelectric conversion portion 302 and the diffusion region 306. Furthermore, as shown on the right side of FIG. 22B, a silicon oxide film 616 is stacked on the semiconductor substrate 10, and a position of the silicon oxide film 616 corresponding to the vertical gate portion 402 of the common transfer gate 400 is etched to form a trench 614.

[0111] 22C, a gate oxide film and a polysilicon film are buried in the trench 614 to form the vertical gate portion 402 of the common transfer gate 400. Then, as shown in the right side of FIG. 22C, impurities are implanted to form the charge storage portion 340 and the well contact 330.

[0112] Furthermore, in this embodiment, it is possible to manufacture the semiconductor device by using the method, apparatus, and conditions that are used in the manufacture of a general semiconductor device, i.e., in this embodiment, it is possible to use the existing semiconductor device manufacturing process.

[0113] Examples of the above-mentioned method include a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, and an ALD (Atomic Layer Deposition) method. Examples of PVD methods include vacuum deposition, EB (electron beam) deposition, various sputtering methods (magnetron sputtering, RF (radio frequency)-DC (direct current) combined bias sputtering, ECR (electron cyclotron resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD. Other methods include electroplating, electroless plating, spin coating, dipping, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Furthermore, patterning methods include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. Additionally, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0114] <13.2 Modifications> Next, modifications of this embodiment will be described with reference to Fig. 23 to Fig. 25. Fig. 23 is an explanatory diagram showing a manufacturing process of an image sensor 100 according to Modification 1. In detail, the upper part of the diagram shows a cross section of the semiconductor substrate 10 cut parallel to the surface of the semiconductor substrate 10, and the lower part of the diagram shows a cross section of the semiconductor substrate 10 cut along line B-B' shown in the diagram shown in the upper part. Fig. 24 is an explanatory diagram showing an example configuration of an image sensor 100 according to Modification 2. In detail, the upper part of the diagram shows a cross section of the image sensor 100 cut parallel to the surface of the semiconductor substrate 10, and the lower part of the diagram shows a cross section of the image sensor 100 cut along line A-A' shown in the diagram shown in the upper part. Furthermore, Figure 25 is an explanatory diagram showing an example configuration of an imaging element 100 relating to variant example 3, and in detail, the upper part of the figure shows a cross section of the imaging element 100 cut parallel to the surface of the semiconductor substrate 10, and the lower part of the figure shows a cross section of the imaging element 100 cut along line CC' shown in the figure shown in the upper part.

[0115] 22A, the depth of the shallow trench 602a corresponding to the vertical gate portion 402 of the common transfer gate 400 may be adjusted by adjusting the timing of stripping the resist 604 or the etching after stripping the resist 604. Also, as shown on the right side of Fig. 23, after the polysilicon film 608 is filled, the upper end of the polysilicon film 608 in the trench 602 corresponding to the vertical gate portion 402 may be removed, and then the silicon oxide film 600 may be filled.

[0116] 24, when a negative bias is applied within the element isolation wall 310, it is preferable to ensure a breakdown voltage by leaving the silicon oxide film 616 between the contact portion 332 and the common transfer gate 400. In this manner, in this modification, electrical isolation by the silicon oxide film 616 makes it possible to achieve a structure that can withstand the application of a negative bias.

[0117] Also, similar to the third embodiment of the present disclosure described above, a blooming path 360 may be provided in the diffusion region 306 below the vertical gate portion 402 of the common transfer gate 400, as shown in FIG.

[0118] In this modified example, the imaging element 100 is not limited to the configuration shown in FIGS. 24 and 25, but can be modified into various other configurations.

[0119] <<14. Eleventh Embodiment>> Next, a method for manufacturing the image sensor 100 according to the first modification of the seventh embodiment described above will be described as an eleventh embodiment of the present disclosure with reference to Fig. 26. Fig. 26 is an explanatory diagram showing the manufacturing process of the image sensor 100 according to this embodiment, and in detail, the upper part of the figure shows a cross section of the semiconductor substrate 10 cut parallel to the surface of the semiconductor substrate 10, and the lower part of the figure shows a cross section of the semiconductor substrate 10 cut along line B-B' shown in the diagram shown in the upper part.

[0120] As shown in FIG. 26, in the step shown on the right side of FIG. 22B described above, the width of the trench 614 is increased, thereby making it possible to increase the width of the vertical gate portion 402 of the common transfer gate 400.

[0121] <<15. Twelfth Embodiment>> Next, a method for manufacturing the image sensor 100 according to the above-described eighth embodiment will be described as a twelfth embodiment of the present disclosure with reference to Fig. 27. Fig. 27 is an explanatory diagram showing the manufacturing process of the image sensor 100 according to this embodiment, and in detail, the upper part of the figure shows a cross section of the semiconductor substrate 10 cut parallel to the surface of the semiconductor substrate 10, and the lower part of the figure shows a cross section of the semiconductor substrate 10 cut along line A-A' shown in the diagram shown in the upper part.

[0122] As shown in FIG. 27, by using the silicon oxide film 616 used when embedding the silicon oxide film 616 in the upper part of the element isolation wall 310 as a mask, trenches 614 corresponding to the vertical gate portions 402 of the transfer gates 400 a, 400 b according to the eighth embodiment can be formed.

[0123] <<16. Thirteenth Embodiment>> Next, configurations of an image sensor 100 and a pixel array section 30 according to a thirteenth embodiment of the present disclosure will be described with reference to Figures 28A and 28B. Figure 28A is an explanatory diagram showing an example configuration of the image sensor 100 according to this embodiment, and in detail, the upper part shows a cross section of the image sensor 100 cut parallel to the surface of the semiconductor substrate 10, and the lower part shows a cross section of the image sensor 100 cut along line D-D' shown in the upper diagram. Also, Figure 28B is an explanatory diagram illustrating the planar configuration of the pixel array section 30 according to this embodiment.

[0124] In the first to seventh embodiments of the present disclosure described above, two pixels 300a and 300b share one common transfer gate 400, which increases the degree of freedom in layout. Therefore, in this embodiment, as shown in FIGS. 28A and 28B , the pixel transistor 650 can be disposed on the element isolation wall 310. That is, in this embodiment, the pixel transistor 650 can be provided on the semiconductor substrate 10. Furthermore, by doing so, for example, as shown in the lower diagram of FIG. 28A , the pixel transistor 650 may be formed in a vertical gate structure, so that a channel is generated at the interface of the vertical gate portion embedded in the element isolation wall 310. This can reduce the area occupied by the pixel transistor 650. Furthermore, as shown in FIG. 28B , the source / drain of adjacent pixel transistors 650 may be shared by these pixel transistors 650, thereby reducing the area occupied by these pixel transistors 650.

[0125] In this embodiment, the imaging element 100 and the pixel array section 30 are not limited to the forms shown in FIGS. 28A and 28B, but can be modified into various forms.

[0126] <<17. Summary>> As described above, in each embodiment of the present disclosure, the pixels 300a and 300b of the same imaging element 100 or of adjacent imaging elements 100 share a single common transfer gate 400. In this manner, in these embodiments, the shared single common transfer gate 400 can simultaneously transfer charges generated in each of the pixels 300a and 300b of the same imaging element 100 or of adjacent imaging elements 100 to the respective charge accumulation units 340 of the same imaging element 100 or of the adjacent imaging elements 100. According to this embodiment, the pixels 300a and 300b share a single common transfer gate 400, which makes it possible to prevent the well contact 330, the common transfer gate 400, and the charge accumulation unit 340 from being close to each other, thereby reducing the strength of the electric field that is generated. Additionally, in this embodiment, the charges generated in the pixels 300a and 300b can be simultaneously transferred to the charge storage sections 340, thereby increasing the readout speed.

[0127] Note that, in the above-described embodiment of the present disclosure, an example has been described in which the present disclosure is applied to the image sensor 100 including a pair of phase difference detection pixels 300 a and 300 b. However, the embodiment of the present disclosure is not limited to such an example, and may be applied to the image sensor 100 including one pixel 300.

[0128] Furthermore, in the above-described embodiments of the present disclosure, a case has been described in which the present disclosure is applied to a back-illuminated CMOS (Complementary MOS) image sensor structure, but the embodiments of the present disclosure are not limited to this and may be applied to other structures.

[0129] In the above-described embodiment of the present disclosure, the image sensor 100 is described in which the first conductivity type is N-type, the second conductivity type is P-type, and electrons are used as signal charges, but the embodiment of the present disclosure is not limited to this example. For example, this embodiment can be applied to an image sensor 100 in which the first conductivity type is P-type, the second conductivity type is N-type, and holes are used as signal charges.

[0130] In the above-described embodiment of the present disclosure, the semiconductor substrate 10 does not necessarily have to be a silicon substrate, but may be another substrate (for example, an SOI (Silicon On Insulator) substrate, a SiGe substrate, etc.) The semiconductor substrate 10 may also be one in which a semiconductor structure or the like is formed on such various substrates.

[0131] Furthermore, the imaging device 1 according to the embodiment of the present disclosure is not limited to an imaging device that detects the distribution of incident light amounts of visible light and captures an image. For example, the present embodiment can be applied to an imaging device that captures the distribution of incident amounts of infrared rays, X-rays, particles, etc. as an image, or an imaging device (physical quantity distribution detection device) such as a fingerprint detection sensor that detects the distribution of other physical quantities such as pressure or capacitance and captures an image.

[0132] <<18. Application Examples>> <18.1 Application Example to Camera> The technology according to the present disclosure (the present technology) can be further applied to various products. For example, the technology according to the present disclosure may be applied to a camera or the like. Therefore, with reference to FIG. 29 , a configuration example of a camera 700 as an electronic device to which the present technology is applied will be described. FIG. 29 is an explanatory diagram showing an example of a schematic functional configuration of a camera 700 to which the technology according to the present disclosure (the present technology) can be applied.

[0133] As shown in FIG. 29 , the camera 700 includes an imaging device 702, an optical lens 710, a shutter mechanism 712, a drive circuit unit 714, and a signal processing circuit unit 716. The optical lens 710 focuses image light (incident light) from a subject on the imaging surface of the imaging device 702. This causes signal charge to accumulate for a certain period in the image sensor 100 of the imaging device 702. The shutter mechanism 712 opens and closes to control the light irradiation period and light blocking period for the imaging device 702. The drive circuit unit 714 supplies drive signals to the imaging device 702 that control the signal transfer operation and the shutter operation of the shutter mechanism 712. In other words, the imaging device 702 transfers signals based on the drive signals (timing signals) supplied from the drive circuit unit 714. The signal processing circuit unit 716 performs various signal processing. For example, the signal processing circuit unit 716 outputs the processed video signal to a storage medium such as a memory (not shown), or to a display unit (not shown).

[0134] <18.2 Application Example to Smartphone>> For example, the technology according to the present disclosure may be applied to a smartphone or the like. Therefore, a configuration example of a smartphone 900 as an electronic device to which the present technology is applied will be described with reference to Fig. 30. Fig. 30 is a block diagram showing an example of a schematic functional configuration of a smartphone 900 to which the technology according to the present disclosure (the present technology) can be applied.

[0135] 30 , the smartphone 900 includes a CPU (Central Processing Unit) 901, a ROM (Read Only Memory) 902, and a RAM (Random Access Memory) 903. The smartphone 900 also includes a storage device 904, a communication module 905, and a sensor module 907. The smartphone 900 also includes an imaging device 909, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. The smartphone 900 may also include a processing circuit such as a DSP (Digital Signal Processor) instead of or in addition to the CPU 901.

[0136] The CPU 901 functions as an arithmetic processing unit and control device, and controls all or part of the operations within the smartphone 900 in accordance with various programs recorded in the ROM 902, RAM 903, storage device 904, etc. The ROM 902 stores programs and calculation parameters used by the CPU 901. The RAM 903 temporarily stores programs used in the execution of the CPU 901 and parameters that change as appropriate during the execution. The CPU 901, ROM 902, and RAM 903 are interconnected by a bus 914. The storage device 904 is a data storage device configured as an example of a storage unit of the smartphone 900. The storage device 904 is configured, for example, by a magnetic storage device such as an HDD (hard disk drive), a semiconductor storage device, an optical storage device, etc. This storage device 904 stores programs executed by the CPU 901, various data, and various data acquired from outside.

[0137] The communication module 905 is a communication interface configured with, for example, a communication device for connecting to the communication network 906. The communication module 905 may be, for example, a communication card for a wired or wireless local area network (LAN), Bluetooth (registered trademark), or wireless USB (WUSB). The communication module 905 may also be a router for optical communication, a router for asymmetric digital subscriber line (ADSL), or a modem for various communications. The communication module 905 transmits and receives signals between the Internet and other communication devices using a predetermined protocol such as TCP (Transmission Control Protocol) / IP (Internet Protocol). Furthermore, the communication network 906 connected to the communication module 905 is a wired or wireless network, such as the Internet, a home LAN, infrared communication, or satellite communication.

[0138] The sensor module 907 includes various sensors such as a motion sensor (e.g., an acceleration sensor, a gyro sensor, a geomagnetic sensor, etc.), a biometric information sensor (e.g., a pulse sensor, a blood pressure sensor, a fingerprint sensor, etc.), or a position sensor (e.g., a GNSS (Global Navigation Satellite System) receiver, etc.).

[0139] The imaging device 909 is provided on the surface of the smartphone 900 and can capture an image of an object located on the back or front side of the smartphone 900. Specifically, the imaging device 909 can include an imaging element (not shown) such as a CMOS image sensor to which the technology according to the present disclosure (the present technology) can be applied, and a signal processing circuit (not shown) that performs imaging signal processing on a signal photoelectrically converted by the imaging element. Furthermore, the imaging device 909 can further include an optical system mechanism (not shown) including an imaging lens, a zoom lens, a focus lens, and the like, and a drive system mechanism (not shown) that controls the operation of the optical system mechanism. The imaging element collects incident light from the object as an optical image, and the signal processing circuit photoelectrically converts the formed optical image on a pixel-by-pixel basis, reads out the signal from each pixel as an imaging signal, and performs image processing to obtain a captured image.

[0140] The display device 910 is provided on the surface of the smartphone 900 and can be, for example, a display device such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display. The display device 910 can display an operation screen, an image captured by the imaging device 909 described above, and the like.

[0141] The speaker 911 can output, for example, telephone call audio and audio accompanying the video content displayed by the display device 910 described above to the user.

[0142] The microphone 912 can collect, for example, the user's voice during a call, voice including commands to activate functions of the smartphone 900, and voice from the surrounding environment of the smartphone 900.

[0143] The input device 913 is a device operated by a user, such as a button, a keyboard, a touch panel, or a mouse. The input device 913 includes an input control circuit that generates an input signal based on information input by the user and outputs the signal to the CPU 901. By operating the input device 913, the user can input various data to the smartphone 900 and instruct processing operations.

[0144] The above describes an example configuration of the smartphone 900. Each of the above components may be configured using general-purpose components, or may be configured using hardware specialized for the function of each component. Such a configuration may be changed as appropriate depending on the technical level at the time of implementation.

[0145] <18.3 Application Examples to Mobile Bodies> For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0146] FIG. 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0147] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 31 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0148] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0149] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0150] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0151] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0152] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0153] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0154] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0155] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0156] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 31, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0157] FIG. 32 is a diagram showing an example of the installation position of the imaging unit 12031.

[0158] In FIG. 32 , a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0159] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0160] 32 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0161] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0162] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0163] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0164] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0165] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 and the like among the above-described components.

[0166] <<19. Supplementary Information>> Although preferred embodiments of the present disclosure have been described above in detail with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0167] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0168] The present technology can also be configured as follows: (1) An imaging device comprising: a semiconductor substrate; and a plurality of pixels arranged on the semiconductor substrate in a matrix along row and column directions, wherein each of the plurality of pixels performs photoelectric conversion on incident light to generate charges, and comprises: a charge accumulation section that accumulates the generated charges; and a common transfer gate that is shared by the plurality of adjacent pixels and transfers the charges generated in the pixels to the charge accumulation section. (2) The imaging device according to (1) above, comprising: a plurality of imaging elements arranged on the semiconductor substrate in a matrix along the row and column directions, wherein the imaging elements have a pair of pixels that are adjacent to each other and separated by a pixel separation wall that extends along the depth direction of the semiconductor substrate, and the pair of pixels function as phase difference pixels. (3) The imaging device according to (2) above, wherein the common transfer gate is shared by the pair of pixels in one of the imaging elements, is located at the center of the imaging element when viewed from above on the surface opposite the light-receiving surface of the semiconductor substrate, and transfers charge generated in the pixel to the charge accumulation section provided for each of the pixels. (4) The imaging device according to (3) above, wherein the common transfer gate has a vertical gate section extending from the surface along the depth direction of the semiconductor substrate. (5) The imaging device according to (4) above, wherein the common transfer gate has a plurality of the vertical gate sections. (6) The imaging device according to (5) above, wherein the plurality of vertical gate sections are provided for each of the pixels. (7) The imaging device according to any one of (3) to (6) above, wherein the common transfer gate extends from the center of one of the pixels to the center of the other of the pixels when viewed from above on the surface. (8) The imaging device according to any one of (3) to (7) above, wherein the pixel separation wall has a slit located at the center of the imaging element when viewed from above the surface, the slit extends from the surface along the depth direction of the semiconductor substrate, and a diffusion region containing impurities of a second conductivity type having a conductivity type opposite to that of the first conductivity type impurities contained in the pixels is provided within the slit.(9) The imaging device according to (8) above, wherein the diffusion region has a path for exchanging the charge between the plurality of pixels, and wherein a concentration of the second conductivity type impurity included in the path is lower than that of the diffusion region. (10) The imaging device according to (9) above, wherein the path is provided on a surface on the front side of the diffusion region. (11) The imaging device according to (9) above, wherein the path is provided at a position spaced apart from the surface on the front side of the diffusion region along the depth direction of the semiconductor substrate. (12) The imaging device according to any one of (2) to (11) above, wherein four of the imaging elements arranged in a 2x2 matrix share one of the charge accumulation units. (13) The imaging device according to any one of (2) to (11) above, wherein eight of the imaging elements arranged in a 4x2 matrix share one of the charge accumulation units. (14) The imaging device according to (2) above, wherein the imaging element further includes an element isolation wall provided so as to surround the imaging element, and the common transfer gate is provided for each pixel on a part of the element isolation wall, and transfers charge generated in each pixel to the charge accumulation section provided for each pixel. (15) The imaging device according to (14) above, wherein the common transfer gate has a plurality of vertical gate sections, and a portion of the element isolation wall on a surface side facing the light receiving surface of the semiconductor substrate is sandwiched between the plurality of vertical gate sections. (16) The imaging device according to (14) or (15) above, wherein two imaging elements adjacent to each other in the row direction share the common transfer gate. (17) The imaging device according to any one of (2) to (16) above, wherein each of the plurality of imaging elements has a color filter, and the plurality of color filters are arranged according to a Bayer array. (18) The imaging device according to any one of (2) to (16), wherein each of the plurality of imaging elements has a color filter, and the plurality of color filters are arranged according to a Quad Bayer array.(19) An electronic device equipped with an imaging device, the imaging device comprising: a semiconductor substrate; and a plurality of pixels arranged in a matrix on the semiconductor substrate along row and column directions, each of the plurality of pixels performing photoelectric conversion on incident light to generate electric charges and having a charge accumulation section that accumulates the generated electric charges; and a common transfer gate that is provided so as to be shared by the plurality of adjacent pixels and that transfers the electric charges generated in the pixel to the charge accumulation section. (20) A method for manufacturing an imaging device including a semiconductor substrate and a plurality of imaging elements arranged in a matrix on the semiconductor substrate in row and column directions, wherein the imaging elements have: an element isolation wall surrounding the imaging elements; a plurality of pixels arranged adjacent to each other, performing photoelectric conversion on incident light and generating electric charges; a pixel isolation wall extending in the depth direction of the semiconductor substrate to separate the plurality of pixels; a plurality of charge accumulation sections that accumulate the generated electric charges; and a common transfer gate portion shared by the plurality of adjacent pixels, which transfers the electric charges generated in each pixel to each of the charge accumulation sections, the common transfer gate portion having a vertical gate portion extending in the depth direction of the semiconductor substrate from a surface facing a light-receiving surface of the semiconductor substrate; and the method for manufacturing an imaging device includes simultaneously forming trenches of different depths corresponding to the vertical gate portions and parts of the trenches corresponding to the pixel isolation walls in the semiconductor substrate using a mask.

[0169] 1, 702, 909 Image pickup device 10 Semiconductor substrate 10a Light receiving surface 10b Surface 30 Pixel array section 32 Vertical drive circuit section 34 Column signal processing circuit section 36 Horizontal drive circuit section 38 Output circuit section 40 Control circuit section 42 Pixel drive wiring 44 Vertical signal line 46 Horizontal signal line 48 Input / output terminal 100, 100a Image pickup element 300, 300a, 300b Pixel 302 Photoelectric conversion section 304 Pixel isolation wall 306, 308 Diffusion region 310 Element isolation wall 312 Slit 330 Well contact 332, 342 Contact section 340, 340a, 340b Charge storage section 350 Through contact 360 Blooming path 400, 400a, 400b Transfer gate 402 Vertical gate portion 500 Color filter 600, 616 Silicon oxide film 602, 602a, 610, 614 Trench 604 Resist 608, 612 Polysilicon film 650 Pixel transistor 700 Camera 710 Optical lens 712 Shutter mechanism 714 Drive circuit unit 716 Signal processing circuit unit 900 Smartphone 901 CPU 902 ROM 903 RAM 904 Storage device 905 Communication module 906 Communication network 907 Sensor module 910 Display device 911 Speaker 912 Microphone 913 Input device 914 Bus

Claims

1. An imaging device comprising: a semiconductor substrate; and a plurality of pixels arranged in a matrix on the semiconductor substrate in row and column directions, each of the plurality of pixels having: a charge accumulation section that performs photoelectric conversion on incident light to generate electric charges and accumulates the generated electric charges; and a common transfer gate that is shared by the plurality of adjacent pixels and transfers the electric charges generated in the pixels to the charge accumulation section.

2. The imaging device according to claim 1, comprising a plurality of imaging elements arranged in a matrix along the row and column directions on the semiconductor substrate, the imaging elements having a pair of pixels arranged adjacent to each other and separated by a pixel separation wall extending along the depth direction of the semiconductor substrate, the pair of pixels functioning as phase difference pixels.

3. The imaging device described in claim 2, wherein the common transfer gate is shared by the pair of pixels within one of the imaging elements, is located in the center of the imaging element when viewed from above the surface facing the light-receiving surface of the semiconductor substrate, and transfers electric charges generated in the pixels to the charge accumulation section provided for each of the pixels.

4. The imaging device according to claim 3, wherein the common transfer gate has a vertical gate portion extending from the surface along a depth direction of the semiconductor substrate.

5. The imaging device according to claim 4, wherein the common transfer gate has a plurality of the vertical gate portions.

6. The imaging device according to claim 5, wherein the plurality of vertical gate portions are provided for each of the pixels.

7. The imaging device according to claim 3, wherein said common transfer gate extends from the center of one of said pixels to the center of the other of said pixels when viewed from above said surface.

8. The imaging device described in claim 3, wherein the pixel separation wall has a slit located at the center of the imaging element when viewed from above the surface, the slit extending from the surface along the depth direction of the semiconductor substrate, and a diffusion region containing a second conductivity type impurity having a conductivity type opposite to that of a first conductivity type impurity contained in the pixel is provided within the slit.

9. The imaging device according to claim 8, wherein the diffusion region has a path for transferring the electric charges between the plurality of pixels, and the concentration of the second conductivity type impurity contained in the path is lower than that of the diffusion region.

10. The imaging device according to claim 9, wherein the path is provided on a surface of the diffusion region on the front side.

11. The imaging device according to claim 9, wherein the path is provided at a position spaced apart from the surface of the diffusion region on the front side along the depth direction of the semiconductor substrate.

12. The imaging device according to claim 2, wherein the four imaging elements arranged in a 2 x 2 matrix share one of the charge storage sections.

13. The imaging device according to claim 2, wherein the eight imaging elements arranged in a 4 x 2 matrix share one of the charge storage sections.

14. The imaging device of claim 2, wherein the imaging element further comprises an element isolation wall arranged to surround the imaging element, and the common transfer gate is provided for each pixel on a portion of the element isolation wall, and transfers electric charges generated in each pixel to the charge accumulation section provided for each pixel.

15. The imaging device according to claim 14, wherein the common transfer gate has a plurality of vertical gate portions, and a portion of the element isolation wall on the surface side facing the light receiving surface of the semiconductor substrate is sandwiched between the plurality of vertical gate portions.

16. The imaging device according to claim 14, wherein two of the imaging elements adjacent to each other along the row direction share the common transfer gate.

17. The imaging device according to claim 2, wherein each of the plurality of imaging elements has a color filter, and the plurality of color filters are arranged according to a Bayer array.

18. The imaging device according to claim 2, wherein each of the plurality of imaging elements has a color filter, and the plurality of color filters are arranged according to a Quad Bayer array.

19. An electronic device equipped with an imaging device, the imaging device comprising: a semiconductor substrate; and a plurality of pixels arranged in a matrix on the semiconductor substrate along row and column directions, each of the plurality of pixels having: a charge accumulation section that performs photoelectric conversion on incident light to generate electric charges and accumulates the generated electric charges; and a common transfer gate that is shared by the plurality of adjacent pixels and transfers the electric charges generated in the pixels to the charge accumulation section.

20. A method for manufacturing an imaging device comprising a semiconductor substrate and a plurality of imaging elements arranged in a matrix on the semiconductor substrate in row and column directions, wherein the imaging elements have: an element isolation wall surrounding the imaging element; a plurality of pixels arranged adjacent to each other and performing photoelectric conversion on incident light to generate electric charges; a pixel isolation wall arranged extending along the depth direction of the semiconductor substrate to separate the plurality of pixels; a plurality of charge accumulation sections for accumulating the generated electric charges; and a common transfer gate portion arranged to be shared by the plurality of adjacent pixels and transferring the electric charges generated in each of the pixels to each of the charge accumulation sections, the common transfer gate portion having a vertical gate portion extending along the depth direction of the semiconductor substrate from a surface opposite to the light-receiving surface of the semiconductor substrate; and the method for manufacturing an imaging device further comprising: simultaneously forming, in the semiconductor substrate using a mask, trenches of different depths corresponding to the vertical gate portions and portions of the trenches corresponding to the pixel isolation walls.

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