Display device

Abstract

[Problem] To suppress any deviation of luminance and chromaticity caused by a frame rate. [Solution] This display device comprises light-emitting pixels, an interface, and a signal processing circuit. The interface receives a signal based on a first clock frequency. The signal processing circuit processes the signal at a second clock frequency controlled at a prescribed frequency independent of a frame rate. The light-emitting pixels are each provided with a light-emitting element and a drive element that drives the light-emitting element on the basis of the signal processed by the signal processing circuit.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] In some display devices, the light emission intensity of each light-emitting element is controlled by controlling a signal based on a ramp signal in accordance with a clock frequency at the output. Furthermore, the display device may have a variable frame rate. When the frame rate is changed in a display device that controls light emission intensity based on a clock frequency, the clock signal may change according to the frame rate in the readout control of the ramp signal. This causes a change in the correction period for the threshold voltage of the transistor that controls light emission, which is likely to result in changes in brightness and chromaticity.

[0003] Japanese Patent Application Laid-Open No. 2015-090438

[0004] Therefore, one of the non-limiting problems that the embodiments of the present disclosure aim to solve is to suppress deviations in luminance and chromaticity due to frame rate. As some further non-limiting examples, the problem that the embodiments of the present disclosure aim to solve can also be a problem corresponding to the effects described in the embodiments. That is, a problem that corresponds to at least one of the effects described in the description of the embodiments of the present disclosure can be a problem that the present disclosure aims to solve.

[0005] According to one embodiment, a display device includes a pixel, an interface, and a signal processing circuit. The interface receives a signal based on a first clock frequency. The signal processing circuit processes the signal at a second clock frequency controlled by a predetermined frequency independent of the frame rate. The pixel includes a light-emitting element and a drive element that drives the light-emitting element based on the signal processed by the signal processing circuit.

[0006] The interface may be a high speed interface.

[0007] The device may further include a memory for storing signals transferred by the interface.

[0008] The memory may be a line buffer.

[0009] The memory may be a frame memory.

[0010] The signal processing circuit may perform signal processing using a ramp signal having a predetermined slope based on the second clock frequency, regardless of the frame rate.

[0011] The driving element may be self-discharging.

[0012] The driving element may be initialized by self-discharge to determine the threshold voltage.

[0013] The initialization of the driving element may be controlled by a correction period determined by the second clock frequency.

[0014] The signal processing circuit may convert a digital signal into an analog signal based on a ramp signal according to the second clock frequency and output the analog signal to the pixel circuit, and the pixel circuit may cause the light-emitting element to emit light based on the analog signal.

[0015] The signal processing circuit may output an analog signal converted from a digital signal to the pixel circuit via a voltage follower, and the pixel circuit may cause the light-emitting element to emit light based on the signal output from the voltage follower.

[0016] The device may further include an internal clock generation circuit that generates the second clock frequency.

[0017] The internal clock generation circuit may include at least one of a DLL (Delay Locked Loop) and a PLL (Phase Locked Loop).

[0018] The internal clock generating circuit may include an oscillator.

[0019] The first clock frequency may be obtained externally via the interface.

[0020] 1 is a block diagram schematically showing a display unit of a display device according to an embodiment; a circuit diagram showing an outline of a pixel of the display device according to an embodiment; a timing chart showing an example of signals supplied to signal lines of a pixel circuit according to an embodiment; a timing chart showing an example of reading out of signal values ​​in a signal processing circuit according to an embodiment; a timing chart showing an example of reading out of signal values ​​in a signal processing circuit according to a comparative example; a diagram schematically showing an example of a circuit configuration for generating an internal clock signal according to an embodiment; a diagram schematically showing an example of a circuit configuration for generating an internal clock signal according to an embodiment; a diagram schematically showing an example of a circuit configuration for generating an internal clock signal according to an embodiment; a circuit diagram schematically showing an example of a configuration of a pixel circuit according to an embodiment; a circuit diagram schematically showing an example of a configuration of a pixel circuit according to an embodiment; a circuit diagram schematically showing an example of a configuration of a pixel circuit according to an embodiment; a circuit diagram schematically showing an example of a configuration of a pixel circuit according to an embodiment; a circuit diagram schematically showing an example of a configuration of a pixel circuit according to an embodiment; a circuit diagram schematically showing an example of a configuration of a pixel circuit according to an embodiment; a diagram showing the interior of a vehicle from the rear to the front of the vehicle. 1 is a diagram showing the interior of a vehicle from diagonally rear to diagonally front of the vehicle; a front view of a digital camera which is a second application example of the electronic device; a rear view of the digital camera; an external view of an HMD which is a third application example of the electronic device; an external view of smart glasses; an external view of a TV which is a fourth application example of the electronic device; and an external view of a smartphone which is a fifth application example of the electronic device.

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0022] FIG. 1 is a diagram showing an example of a pixel array and peripheral circuits relating to display of a display device 1 according to an embodiment.

[0023] The display device 1 includes a data input / output interface (input / output I / F 100), a gamma generation circuit 102, a power supply 104, a high-speed interface (high-speed I / F 106), a control circuit 108, a vertical logic circuit 110, a vertical analog circuit 112, a horizontal logic circuit 114, a horizontal analog circuit 116, and a pixel array 118. The display device 1 acquires video information as image information for each frame and appropriately causes light-emitting elements provided in the pixel array 118 to emit light, thereby appropriately displaying video information (moving images) or image information (still images), etc.

[0024] In this disclosure, the term "image data" may be used simply, but this is intended to be a concept that can be recognized as so-called image data, including both moving images and still images, such as frame data related to the video information described above.

[0025] The input / output I / F 100 is an interface for inputting image data to be input to peripheral circuits for images. In addition, if necessary, it may also include a configuration that operates as an interface for transmitting signals from the peripheral circuits to the outside.

[0026] The gamma generation circuit 102 is a circuit that generates and supplies gamma voltages for lines of pixels included in the pixel array 118. Note that if gamma voltages are not used, the gamma generation circuit 102 is not an essential component in the pixel value control process of the present disclosure.

[0027] The power supply 104 converts an externally input power supply voltage into an appropriate power supply voltage and applies it to the peripheral circuits of the pixel array 118. The power supply 104 is configured to include a regulator such as an LDO (Low Drop Out). In the drawings, the power supply 104 is connected to the pixel array 118 as an example, but is not limited to this and may be connected appropriately to other components that require power.

[0028] The high-speed I / F 106 is an interface that transfers various signals input from the input / output I / F 100 to necessary locations at high speed. The high-speed I / F 106 transmits, for example, signals required for controlling the display unit to the control circuit 108. The high-speed I / F 106 also acquires, for example, video data via the input / output I / F 100 and transmits it to the control circuit 108.

[0029] The high-speed I / F 106 may be, by way of example and not limitation, an interface based on the LVDS (Low Voltage Differential Signaling) standard (including the mini-LVDS standard and the sub-LVDS standard), an interface based on the MIPI (registered trademark, Mobile Industry Processor Interface, including MIPI-D-PHY / C-PHY) standard, or an interface based on V-by-One (registered trademark).In addition, the high-speed I / F 106 may be an interface known as a high-speed interface.

[0030] In the present disclosure, in processing data input via the high-speed I / F 106, various processes are performed using an internally generated clock signal, thereby executing processes that are independent of the frame rate.

[0031] The control circuit 108 is a circuit that controls the processing of each circuit related to display. The control circuit 108 appropriately outputs signals that control the vertical logic circuit 110 and the horizontal logic circuit 114 based on, for example, image data (including data for each frame of video data) acquired via the high-speed I / F 106. The control circuit 108 may also include, for example, a circuit that oscillates a clock signal and transmits this clock signal to an appropriate circuit.

[0032] The vertical logic circuit 110 generates signals for controlling line-by-line processing in the pixel array 118 based on signals from the control circuit 108. The vertical logic circuit 110 outputs, for example, digital control signals to the vertical analog circuit 112, which indicate which line in the pixel array 118 a signal should be output for.

[0033] The vertical analog circuit 112 is a circuit that outputs signals that control pixels in the pixel array 118 based on signals output by the vertical logic circuit 110. The vertical analog circuit 112 converts, for example, digital signals output from the vertical logic circuit 110 into analog signals for controlling pixels, and controls the pixels in the pixel array 118 using these analog signals.

[0034] A plurality of control lines for controlling pixels in the pixel array 118 may be provided from the vertical analog circuit 112 along a line direction (e.g., a first direction) of the pixel array 118. A plurality of control lines may be provided to transmit signals for performing a plurality of different controls for pixels belonging to each line in the pixel array 118.

[0035] Based on the signal acquired via the control circuit 108, the horizontal logic circuit 114 outputs to the horizontal analog circuit 116 digital control signals for pixels belonging to each column in the line controlled by the vertical logic circuit 110 and the vertical analog circuit 112.

[0036] The horizontal analog circuit 116 is a circuit that outputs signals that control pixels in the pixel array 118 based on signals output by the horizontal logic circuit 114. The horizontal analog circuit 116 converts, for example, digital signals output from the horizontal logic circuit 114 into analog signals for controlling pixels, and controls the pixels in the pixel array 118 using these analog signals.

[0037] For example, an appropriate display is achieved by each pixel on a line specified by the vertical analog circuit 112 emitting light at an intensity specified by the horizontal analog circuit 116. A plurality of data lines are provided from the horizontal analog circuit 116 along a column direction (e.g., a second direction) of the pixel array 118, transmitting data for causing light-emitting elements in the pixels in the pixel array 118 to emit light.

[0038] The above first and second directions are given as examples, and the present invention is not limited to these directions.

[0039] The pixel array 118 includes pixels arranged in a two-dimensional array. Each pixel emits light at an appropriate intensity to display an image or the like on the display device 1. The arrangement of the pixels in the pixel array 118 may be, for example, a Bayer arrangement, but is not limited thereto and embodiments of the present disclosure can be applied to any arrangement that allows for appropriate display.

[0040] In this disclosure, the term "signal processing circuit" may refer to, by way of example and not limitation, a circuit including the control circuit 108, vertical logic circuit 110, vertical analog circuit 112, horizontal logic circuit 114, and horizontal analog circuit 116 in FIG. 1.

[0041] The generator 120 is a circuit that generates a clock signal for executing signal processing inside the input / output I / F 100. For example, the generator 120 can drive a signal processing circuit at a second clock frequency, which is a predetermined frequency internally regardless of fluctuations in a first clock frequency that is the frequency of a clock signal outside the input / output I / F 100. The generator 120 is a circuit that outputs a clock frequency that conforms to the second clock frequency. The generator 120 may be, for example, an oscillation circuit that includes at least one of an oscillator, a DLL (Delay Locked Loop), or a PLL (Phase Locked Loop).

[0042] The memory 122 is a storage circuit that temporarily stores data acquired from the outside via the high-speed I / F 106. The memory 122 may be a storage circuit that includes at least one of a line buffer, a frame memory, or a FIFO (First In First Out). Either of these configurations can be applied to the embodiments of the present disclosure to achieve new effects.

[0043] Next, the circuitry that controls the pixels in the pixel array 118 will be described in more detail.

[0044] 2 is a circuit diagram showing an outline of a non-limiting example of a pixel circuit. Pixel 130 includes transistors Tdr, Tds, Tws, and Taz, capacitors C1 and C2, and a light-emitting element L. Note that the pixel circuit in this disclosure is not limited to this diagram, as will be seen in examples described later. Similar effects can be achieved by applying any circuit configuration in which transistor Tdr is initialized by self-discharge before writing the light-emitting intensity of light-emitting element L.

[0045] Although the body of each transistor is connected to the signal line VCCP, this is shown as an example and is not limiting, and the body may be set to an appropriate potential to drive the transistor appropriately.

[0046] The anode of the light emitting element L is connected to the source of the transistor Taz and the drain of the transistor Tdr. The light emitting element L may be, for example, an LED (Light Emitting Diode), and in particular, an O-LED (Organic LED).

[0047] The transistor Taz is, for example, a p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), with its source connected to the anode of the light-emitting element L, its drain connected to a power supply line VSS, and its gate connected to a signal line AZ. The transistor Taz initializes the potential of the anode of the light-emitting element L based on an auto-zero signal applied to the signal line AZ. A reference voltage in the power supply voltage, for example, may be applied to the power supply line VSS, and this reference voltage may be a ground voltage or a voltage indicating a potential of 0V.

[0048] The capacitor C1 is a capacitor for controlling the potential on the anode side of the light emitting element L.

[0049] The transistor Tws is, for example, a p-type MOSFET, and is a transistor that controls the writing of pixel values. The source of the transistor Tws is connected to a signal line SIG that supplies a signal Sig indicating the pixel value, the drain is connected to the other end of the capacitor C1 and the gate of the transistor Tdr, and the gate is connected to a signal line WS that supplies a signal Ws for writing control. In accordance with the signal Ws, the transistor Tws flows a drain current corresponding to the strength of the signal Sig, and controls the writing to the capacitor C1 and the gate potential of the transistor Tdr. When the transistor Tws is turned on, a voltage based on the strength of the signal Sig is charged (written) into the capacitor C1, and the light emission intensity of the light-emitting element L is controlled by the amount of charge in the capacitor C1.

[0050] The transistor Tds is, for example, a p-type MOSFET, and is a transistor that controls driving to pass a current based on a potential corresponding to a written pixel value to the light-emitting element L. The transistor Tds has a source connected to the power supply line VCCP, a drain connected to the source of the transistor Tdr, and a gate connected to a signal line DS. The transistor Tds passes a drain current in accordance with a drive signal Ds supplied from the signal line DS, and raises the drain potential of the transistor Tdr.

[0051] The transistor Tdr is, for example, a p-type MOSFET, and drives the transistor Tds to pass a current based on the signal Sig written by the transistor Tws to the light-emitting element L. As a result, the transistor Tdr operates as a transistor that drives the light-emitting element L. In other words, the transistor Tdr operates as an element that drives light emission based on the signal value processed by the signal processing circuit.

[0052] The source of transistor Tdr is connected to the drain of transistor Tds, its drain is connected to the anode of light-emitting element L, and its gate is connected to the drain of transistor Tws. Because signal Sig stored by transistor Tws and capacitor C1 is applied to the gate of transistor Tdr, when the source potential becomes sufficiently high, a drain current corresponding to signal Sig flows. This drain current causes light-emitting element L to emit light with an intensity (brightness) corresponding to signal Sig.

[0053] 3 is a timing chart showing an example of signals supplied to each signal line. A 1F period indicates the period of one frame, and a 1H period indicates the period for executing processing for one line. The 1H period is much shorter than the 1F period.

[0054] The circuit in the pixel 130 controls signals for each of the phases of initialization, threshold correction, writing, light emission, and quenching.

[0055] The initialization phase is a phase in which the pixel circuit is initialized after the light emission of the light emitting element L in the previous frame. In this initialization phase, first, a reference signal Ref is applied to the signal line SIG.

[0056] In this state, supplying a low signal from signal line AZ turns on transistor Taz and initializes the potential on the anode side of light-emitting element L. At the same time, supplying a low signal from signal line WS turns on transistor Tws, supplies reference signal Ref, and initializes capacitor C1 to the reference potential. After these initializations are complete, setting the potentials of signal lines AZ and WS to high turns off transistors Taz and Tws. After transistors Taz and Tws are turned off, an offset signal Ofs is applied to signal line SIG.

[0057] The threshold correction (Vth correction) phase is the phase in which the gate-source voltage of transistor Tdr is initialized. In the threshold correction phase, first, the signal values ​​of signal lines AZ and WS are set low, and the offset of transistor Tdr is set by the offset signal Ofs applied to signal line SIG. In the figure, the solid line shown as the voltage of Tdr indicates the potential of the gate of transistor Tdr, and the dotted line indicates the potential of the source of transistor Tdr.

[0058] By turning on transistors Taz and Tws, the gate and source potentials of transistor Tdr are controlled to the level of offset signal Ofs, and then the voltage applied to signal lines AZ and WS is set high, causing transistor Tdr to self-discharge during this correction period. During this correction period, an offset is set for the gate and source potentials of transistor Tdr. Specifically, the self-discharge during this correction period initializes the gate and source voltages relative to the threshold voltage of transistor Tdr.

[0059] This initialization by self-discharge makes it possible to set an offset that suppresses uneven brightness due to variations in threshold voltage caused by individual differences in the transistor Tdr for each pixel 130.

[0060] During the threshold correction phase, with the transistors Taz and Tws in an off state, a signal Sig instructing the intensity at which the light emitting element L emits light is applied to the signal line SIG.

[0061] The write phase is the phase in which the signal value that determines the light emission intensity is written to capacitor C1. After the offset correction of transistor Tdr is completed, signal lines AZ and WS are set to low, and a potential based on the intensity of signal Sig, which indicates the brightness value supplied from signal line SIG, is charged to capacitor C1. After sufficient time has passed to charge capacitor C1, a high signal is applied to signal lines AZ and WS, turning off transistors Taz and Tws.

[0062] The light-emitting phase is the phase in which the light-emitting element L emits light at a light intensity based on a specified brightness. By turning the signal Ds applied to the signal line DS low, the transistor Tds is turned on and the source potential of the transistor Tdr is increased, causing a drain current based on the potential corresponding to the signal Sig applied to the gate of the transistor Tdr to flow to the anode side of the light-emitting element L, raising the anode potential of the light-emitting element L to the potential corresponding to the signal Sig. This increase in potential makes it possible for the light-emitting element L to emit light at an appropriate intensity.

[0063] After a predetermined time has elapsed, the system transitions to the extinction phase (initialization phase), in which transistor Tds is turned off, transistors Taz and Tws are turned on, and a reference voltage is applied to signal line SIG, thereby lowering the anode potential of light-emitting element L below a predetermined value to extinguish the light, and resetting the potential difference between the gate potential and source potential of transistor Tdr by discharging capacitor C1.

[0064] After this, the control is repeated from the initialization phase.

[0065] In this way, the pixel 130 according to the present disclosure can achieve light emission with luminance that suppresses individual differences by setting the offset potential due to the self-discharge of the transistor Tdr, which is the driving element.

[0066] Here, the clock frequency and the processing of the signal processing circuit when the frame rate changes will be described.

[0067] For example, in the setting of signal Sig in Figure 3, while offset signal Ofs is applied to signal line SIG, signal Sig indicating the brightness indication value is read from the digital signal, and written to capacitor C1. Reading of signal Sig from the digital signal is achieved by counting the value of the digital signal using a clock signal, and reading the analog ramp signal value at this counting timing.

[0068] In the present disclosure, by setting the frequency of this clock signal to a second clock frequency that is generated internally, the time between the conversion of the signal Sig to an analog signal and its application to the signal line SIG is aligned regardless of the frequency of the external clock signal, thereby suppressing deviations in brightness and chromaticity of the brightness value due to changes in the first clock frequency, which is dependent on the frame rate.

[0069] Fig. 4 is a diagram showing an example of readout timing using a ramp signal of brightness values ​​in one embodiment, and Fig. 5 is a diagram showing an example of readout timing in a comparative example.

[0070] The signal processing circuit can convert the signal value temporarily stored in the memory 122 into an analog signal to be applied to the signal line, for example, by reading it out at the second clock frequency.

[0071] By setting the second clock frequency to a predetermined value regardless of the first clock frequency, which is an external clock frequency, or the frame rate, which is the timing at which the brightness value is reset from the outside, the time from the offset signal Ofg to the completion of reading the signal Sig indicating the light emission intensity can be set to a predetermined period. By performing this control, the signal processing circuit can write the signal value Sig to the pixel 130 at an appropriate timing. In other words, regardless of the frame rate, the slope of the ramp signal can be set to a predetermined value, i.e., the maximum value of the reading time can be set to a predetermined value.

[0072] Furthermore, the correction period can be appropriately set by the second clock frequency, which is the frequency of the internally generated clock signal. Specifically, by defining the correction period as a time period with a sufficient margin for appropriately reading the ramp signal from its maximum value to its minimum value using the second clock frequency and transferring this read signal value to the pixel 130, it becomes possible to appropriately offset the reference value of the threshold voltage in the pixel 130. Similarly, the ramp signal can also be appropriately defined based on the second clock frequency.

[0073] This process allows the correction period for the offset due to self-discharge of the transistor Tdr in the pixel 130 to be the same regardless of the frame rate, which makes it possible to suppress fluctuations in the offset value of the drive transistor in the pixel 130 and suppress deviations in the luminance value and chromaticity of the light-emitting element L.

[0074] 5, a change in the frame rate causes a change in the clock frequency for internally executing counting, and therefore the slope of the ramp signal must also be changed in accordance with this change. That is, when forming a display device with a variable frame rate, the slope of the ramp signal changes in the comparative example, which means that different readout periods are required even when converting the same digital signal value into an analog signal.

[0075] As a result, the correction period in FIG. 3 cannot be fixed, and the offset values ​​of the gate and source of the drive transistor vary depending on the frame rate.

[0076] On the other hand, as described above, according to the example of FIG. 4, it is possible to suppress the offset values ​​of the gate and source of the driving transistor from varying due to the frame rate, regardless of the variation in the frame rate.

[0077] Although the above describes the case where a ramp signal is used, the present invention is not limited to this. For example, even when the signal processing circuit instructs the pixel circuit of a luminance value via a voltage follower circuit, the period for correcting the offset of the drive transistor can be set to a predetermined period by performing processing using a second clock frequency that is independent of the frame rate, and the same effect can be achieved.

[0078] Next, the generator 120 will be described with some examples.

[0079] 6 is a diagram illustrating an example of a circuit configuration for generating an internal clock signal according to an embodiment. The generator 120 includes an oscillator 1200, an oscillator 1202, and a clock generation circuit 1204.

[0080] The oscillator 1200 is an oscillator that oscillates at a high-speed clock frequency corresponding to the second clock frequency.

[0081] The oscillator 1202 is an oscillator that oscillates at a low-speed clock frequency corresponding to the first clock frequency. The first clock frequency may be, for example, a frequency based on a frame rate input from an external device. Alternatively, instead of the oscillator 1202, a circuit that receives and outputs an external clock frequency via an interface may be used.

[0082] The clock generation circuit 1204 is a circuit that generates a clock signal that oscillates at the second clock frequency and a clock signal that transmits at the first clock frequency based on the oscillation signals output from the respective oscillators. These circuits may be circuits with a general configuration. The clock generation circuit 1204 may be a circuit that performs control using a clock enable signal that enables the clock signal and transmits the clock signal to downstream circuits.

[0083] Thus, generator 120 may comprise multiple oscillators oscillating at different frequencies.

[0084] A clock signal based on the second clock frequency, which is based on the oscillation of the oscillator 1200, is input to a transmission gate that performs pixel control in the control circuit 108, and the clock signal having the second clock frequency output from this transmission gate is appropriately input to circuits and elements required for the processing in the pixel 130 shown in Figures 3 and 4, such as the vertical analog circuit 112, the horizontal logic circuit 114, and the horizontal analog circuit 116.

[0085] Meanwhile, a clock signal based on a first clock frequency based on the oscillation of the oscillator 1202 is input to the memory 122. The memory 122 outputs data based on the clock signal having the first clock frequency.

[0086] At the same time, the clock signal having the first clock frequency is input to the image processing block of the control circuit 108 and to transmission gates that perform control other than pixel control. The output from the image processing block controlled by the clock signal having the first clock frequency is output to, for example, the vertical logic circuit 110.

[0087] This configuration makes it possible to separate a circuit that operates at the first clock frequency and a circuit that operates at the second clock frequency inside the high-speed I / F 106, thereby achieving both data acquisition in accordance with the frame rate and pixel control that is independent of the frame rate. For example, while image processing is performed based on the frame rate, the clock signal for processing within the pixels can be executed using a high-speed clock signal that is independent of the frame rate.

[0088] This configuration makes it possible to generate a high-speed clock signal having a second clock frequency that is independent of the frame rate, and to realize processing using this high-speed clock signal in necessary circuits.

[0089] 7 is a diagram showing another example of an internal clock signal generation circuit. The generator 120 may be configured to include a multiplication control PLL 1206 instead of multiple oscillators. The multiplication control PLL 1206 may be configured to include a DLL instead of a PLL.

[0090] The multiplication control PLL 1206 obtains a high-speed clock signal having a second clock frequency, which is a predetermined frequency, by performing a multiplication process on the clock signal output from the oscillator 1202. The configuration of this multiplication control PLL 1206 may be a circuit that performs multiplication control and includes a general PLL or DLL.

[0091] The downstream circuitry can have the same configuration as that shown in FIG.

[0092] This configuration also makes it possible to generate a high-speed clock signal having a second clock frequency that is independent of the frame rate, and to realize processing using this high-speed clock signal in necessary circuits.

[0093] 8 is a diagram showing another example of an internal clock signal generation circuit. The generator 120 may receive an external clock signal as a low-speed clock signal having a first clock frequency without including an oscillator, and generate a high-speed clock signal having a second clock frequency based on the low-speed clock signal.

[0094] As shown in the figure, the multiplication control PLL 1206 generates a high-speed clock signal having a second clock frequency from an externally input low-speed clock signal. The externally input low-speed clock signal is a clock signal that does not depend on the frame rate.

[0095] In this case, the clock signal from the outside may be input as a signal divided by 1, 2, or 4, or a frequency divider circuit may be provided inside the generator 120 to generate these clock signals.

[0096] This configuration also makes it possible to generate a high-speed clock signal having a second clock frequency that is independent of the frame rate, and to realize processing using this high-speed clock signal in necessary circuits.

[0097] According to these embodiments and modifications, for example, it is possible to reduce the number of external pins by generating a clock signal inside the high-speed I / F 106, or to reduce the number of built-in blocks by acquiring a predetermined clock signal from the outside.

[0098] As described above, according to the embodiments of the present disclosure, it is possible to suppress deviations in luminance and chromaticity caused by the correction period, which may vary depending on the frame rate. Accordingly, in the necessary circuits, high-speed processing based on a high-speed clock signal having a second clock frequency independent of the frame rate, specifically, control of processing such as writing, can be performed based on the high-speed clock signal. As a result, it is possible to suppress toggling during periods when operation is not required and to implement bias stop.

[0099] (Examples of Pixel Circuit) Although the pixel circuit of Fig. 2 has been described above, examples of the pixel 130 are not limited to this. By adopting a configuration including the generator 120, it is possible to perform similar high-speed signal processing on pixels 130 other than those shown in Fig. 2, and the same effects as those described above can be achieved. Below, several non-limiting examples of the pixel 130 are described.

[0100] It should be noted that there are cases where the polarity of a transistor is reversed, but in this case, if the characteristics of the voltage applied to the gate are reversed, the same operation as above can be realized.

[0101] 9 shows an example of the configuration of the pixel 130. The pixel 130 has a capacitor C01, transistors MN02 and MN03, and a light-emitting element L. The transistors MN02 and MN03 are n-type MOSFETs. The transistor M03 corresponds to the transistor Tdr.

[0102] The gate of the transistor MN02 is connected to the signal line WS, the drain is connected to the signal line SGL, and the source is connected to the gate of the transistor MN03 and the capacitor C01.

[0103] One end of the capacitor C01 is connected to the source of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to the source of the transistor MN03 and the anode of the light-emitting element L.

[0104] The gate of the transistor MN03 is connected to the source of the transistor MN02 and one end of the capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of the capacitor C01 and the anode of the light emitting element L .

[0105] The light emitting element L is, for example, an organic EL light emitting element, and its anode is connected to the source of the transistor MN03 and the other end of the capacitor C01, and its cathode is connected to the power supply line Vcath.

[0106] With this configuration, in pixel 130, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During the period when the voltage of power supply line VCCP is at the first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MN03. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal.

[0107] 10 shows another example of the configuration of the pixel 130. This pixel 130 has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element L. The transistors MP12 to MP15 are p-type MOSFETs. The transistor MP14 corresponds to the transistor Tdr.

[0108] The gate of the transistor MP12 is connected to the signal line WS, the source is connected to the signal line SGL, and the drain is connected to the gate of the transistor MP14 and the capacitor C12.

[0109] One end of the capacitor C11 is connected to the power supply line VCCP, and the other end is connected to the capacitor C12, the drain of the transistor MP13, and the source of the transistor MP14.

[0110] One end of the capacitor C12 is connected to the other end of the capacitor C11, the drain of the transistor MP13, and the source of the transistor MP14, and the other end is connected to the drain of the transistor MP12 and the gate of the transistor MP14.

[0111] The gate of the transistor MP13 is connected to the signal line DS, the source is connected to the power supply line VCCP, and the drain is connected to the source of the transistor MP14, the other end of the capacitor C11, and one end of the capacitor C12.

[0112] The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of light-emitting element L and the source of transistor MP15.

[0113] The gate of the transistor MP15 is connected to the signal line AZ, the source is connected to the drain of the transistor MP14 and the anode of the light emitting element L, and the drain is connected to the power supply line VSS.

[0114] With this configuration, in pixel 130, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on signal line DS. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP14. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on signal line AZ. While transistor MP15 is on, the anode voltage of light-emitting element L is initialized by being set to the voltage of power supply line VSS.

[0115] 11 shows another example of the configuration of the pixel 130. This pixel 130 has a capacitor C21, transistors MN22 to MN25, and a light-emitting element L. The transistors MN22 to MN25 are n-type MOSFETs. The transistor MN24 corresponds to the transistor Tdr.

[0116] The gate of the transistor MN22 is connected to the signal line WS, the drain is connected to the signal line SGL, and the source is connected to the gate of the transistor MN24 and the capacitor C21.

[0117] One end of the capacitor C21 is connected to the source of the transistor MN22 and the gate of the transistor MN24, and the other end is connected to the source of the transistor MN24, the drain of the transistor MN25, and the anode of the light-emitting element L.

[0118] The gate of the transistor MN23 is connected to the signal line DS, the drain is connected to the power supply line VCCP, and the source is connected to the drain of the transistor MN24.

[0119] The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, and the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element L.

[0120] The gate of the transistor MN25 is connected to the signal line AZ, the drain is connected to the source of the transistor MN24, the other end of the capacitor C21 and the anode of the light emitting element L, and the source is connected to the power supply line VSS.

[0121] With this configuration, in pixel 130, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on signal line DS. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MN24. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on signal line AZ. While transistor MN25 is on, the anode voltage of light-emitting element L is initialized by being set to the voltage of power supply line VSS.

[0122] 12 shows another example of the configuration of the pixel 130. This pixel 130 has a capacitor C31, transistors MP32 to MP36, and a light-emitting element L. The transistors MP32 to MP36 are P-type MOSFETs. The transistor MP35 corresponds to the transistor Tdr.

[0123] The gate of the transistor MP32 is connected to the signal line WS, the source is connected to the signal line SGL, and the drain is connected to the gate of the transistor MP33, the drain of the transistor MP34, and the capacitor C31.

[0124] One end of the capacitor C31 is connected to the power supply line VCCP, and the other end is connected to the drain of the transistor MP32, the gate of the transistor MP33, and the drain of the transistor MP34.

[0125] The gate of transistor MP34 is connected to signal line AZ1, the source is connected to the drain of transistor MP33 and the source of transistor MP35, and the drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31.

[0126] The gate of the transistor MP35 is connected to the signal line DS, the source is connected to the drain of the transistor MP33 and the source of the transistor MP34, and the drain is connected to the source of the transistor MP36 and the anode of the light emitting element L.

[0127] The gate of the transistor MP36 is connected to the signal line AZ2, the source is connected to the drain of the transistor MP35 and the anode of the light emitting element L, and the drain is connected to the power supply line VSS.

[0128] With this configuration, in pixel 130, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on signal line DS. During the period when transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP33. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on signal line AZ1. During the period when transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on signal line AZ2. During the period when transistor MP36 is on, the anode voltage of light-emitting element L is initialized by being set to the voltage of power supply line VSS.

[0129] 13 shows another example of the configuration of pixel 130. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a p-type MOSFET, with its gate connected to signal line WS2, its source connected to signal line SGL1, and its drain connected to signal line SGL2. Transistor MP124 corresponds to transistor Tdr.

[0130] The pixel 130 includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element L. Each transistor is a p-type MOSFET. The transistor MP46 corresponds to the transistor Tdr.

[0131] The gate of the transistor MP42 is connected to the signal line WS1, the source is connected to the signal line SGL2, and the drain is connected to the gate of the transistor MP43 and the capacitor C41.

[0132] One end of the capacitor 41 is connected to the power supply line VCCP, and the other end is connected to the drain of the transistor MP42 and the gate of the transistor MP43.

[0133] The gate of the transistor MP43 is connected to the drain of the transistor MP42 and the other end of the capacitor C41, the source is connected to the power supply line VCCP, and the drain is connected to the sources of the transistors MP44 and MP45.

[0134] The gate of the transistor MP44 is connected to the signal line AZ1, the source is connected to the drain of the transistor MP43 and the source of the transistor MP45, and the drain is connected to the signal line SGL2.

[0135] The gate of the transistor MP45 is connected to the signal line DS, the source is connected to the drain of the transistor MP43 and the source of the transistor MP44, and the drain is connected to the source of the transistor MP46 and the anode of the light-emitting element L.

[0136] The gate of the transistor MP46 is connected to the signal line AZ2, the source is connected to the drain of the transistor MP45 and the anode of the light emitting element L, and the drain is connected to the power supply line VSS.

[0137] With this configuration, in pixel 130, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on signal line DS. During the period when transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP43. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on signal line AZ1. During the period when transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on signal line AZ2. During the period when transistor MP46 is on, the voltage of the anode of light-emitting element L is initialized by being set to the voltage of power supply line VSS.

[0138] 14 shows another example of the configuration of the pixel 130. A plurality of pixels 130 are arranged in a matrix in the display area 100, and the display area 100 is provided between the first control unit 40 and the second control unit 70. The transistor MP124 corresponds to the transistor Tdr.

[0139] The first control unit 40 has transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61.

[0140] The transistors MP56 and MP57 are P-type MOSFETs. A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of the signal line 14a.

[0141] The input terminal of the transmission gate TG46 is connected to the signal line 14b, and the output terminal of the transmission gate TG46 is connected to the power supply line Vorst. One terminal of the capacitor C61 is connected to the signal line 14a, and the other terminal is connected to the power supply line VSS1.

[0142] The gate of the transistor MP56 is connected to the control line INIL, the source is connected to the power supply line Vini, and the drain is connected to the signal line 14b.

[0143] The gate of the transistor MP57 is connected to the control line ELL, the source is connected to the power supply line Vel, and the drain is connected to the signal line 14b.

[0144] The second control unit 70 includes a transmission gate TG72, a transistor MP73, and a capacitor C82.

[0145] The input terminal of the transmission gate TG72 is connected to the other end of the signal line 14a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82.

[0146] The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82.

[0147] One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 14b.

[0148] The pixel 130 includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element L. The transistors MP121 to MP125 are P-type MOSFETs.

[0149] The gate of the transistor MP122 is connected to the signal line WS, the source is connected to the signal line 14b, and the drain is connected to the gate of the transistor MP121 and the capacitor C132.

[0150] One end of the capacitor C132 is connected to the power supply line Vel, and the other end is connected to the drain of the transistor MP122 and the gate of the transistor MP121.

[0151] The gate of the transistor MP121 is connected to the drain of the transistor MP122 and the other end of the capacitor C132, the source is connected to the power supply line Vel, and the drain is connected to the sources of the transistors MP123 and MP124.

[0152] The gate of the transistor MP123 is connected to the signal line AZ, the source is connected to the drain of the transistor MP121 and the source of the transistor MP124, and the drain is connected to the signal line 14b.

[0153] The gate of the transistor MP124 is connected to the signal line DS, the source is connected to the drain of the transistor MP121 and the source of the transistor MP123, and the drain is connected to the drain of the transistor MP125 and the anode of the light emitting element 130.

[0154] The gate of the transistor MP125 is connected to the signal line AZ, the source is connected to the power supply line Vorst, and the drain is connected to the drain of the transistor MP124 and the anode of the light emitting element 130.

[0155] With this configuration, in pixel 130, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 turns on and off based on the signal on signal line DS. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP121. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal. Transistors MP123 and MP125 turn on and off based on the signal on signal line AZ. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 14b. During the period when transistor MP125 is in the ON state, the anode voltage of light-emitting element L is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is in the ON state, signal line 14b is set to the voltage of power supply line Vini, and when transistor MP57 is in the ON state, signal line 14b is set to the voltage of power supply line Vel. When transistor MP73 is in the ON state, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0156] 15 shows another example of the configuration of the pixel 130. This pixel 130 has a capacitor C51, transistors MP52 to MP60, and a light-emitting element L. The transistors MP52 to MP60 are P-type MOSFETs. The transistor MP59 corresponds to the transistor Tdr.

[0157] The gate of the transistor MP52 is connected to the signal line WS, the source is connected to the signal line SGL, and the drain is connected to the drain of the transistor MP53 and the source of the transistor MP54.

[0158] The gate of the transistor MP53 is connected to the signal line DS, the source is connected to the power supply line VCCP, and the drain is connected to the drain of the transistor MP52 and the source of the transistor MP54.

[0159] The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, the source is connected to the drains of transistors MP52 and MP53, and the drain is connected to the sources of transistors MP58 and MP59.

[0160] One end of the capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of the transistor MP54, the source of the transistor MP55, and the drain of the transistor MP57.

[0161] Capacitor C51 may include two capacitors connected in parallel with each other.

[0162] The gate of transistor MP55 is connected to signal line AZ1, the source is connected to the gate of transistor MP54, the drain of transistor MP57 and the other end of capacitor C51, and the drain is connected to the source of transistor MP56.

[0163] The gate of the transistor MP56 is connected to the signal line AZ1, the source is connected to the drain of the transistor MP55, and the drain is connected to the power supply line VSS.

[0164] The gate of transistor MP57 is connected to signal line WS, the drain is connected to the gate of transistor MP54, the source of transistor MP55 and the other end of capacitor C51, and the source is connected to the drain of transistor MP58.

[0165] The gate of the transistor MP58 is connected to the signal line WS, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59.

[0166] The gate of the transistor 59 is connected to the signal line DS, the source is connected to the drain of the transistor MP54 and the source of the transistor MP58, and the drain is connected to the source of the transistor MP60 and the anode of the light emitting element L.

[0167] The gate of the transistor MP60 is connected to the signal line AZ2, the source is connected to the drain of the transistor MP59 and the anode of the light emitting element L, and the drain is connected to the power supply line VSS.

[0168] With this configuration, in pixel 130, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on signal line DS. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP54. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on signal line AZ1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on signal line AZ2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light emitting element L is initialized by being set to the voltage of the power supply line VSS.

[0169] 16 shows another example of the configuration of the pixel 130. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0170] The pixel 130 has capacitors C61 and C62, transistors MN63, MP64, MN65 to MN67, and a light-emitting element L. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The transistor MN65 corresponds to the transistor Tdr.

[0171] The gate of the transistor MN63 is connected to the control line WSNL, the drain is connected to the signal line SGL and the source of the transistor MP64, and the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65.

[0172] The gate of transistor MP64 is connected to the control line WSPL, the source is connected to the signal line SGL and the drain of transistor MN63, and the drain is connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65.

[0173] The capacitor C61 is configured using, for example, a MOM (Metal Oxide Metal) capacitor, and has one end connected to the source of the transistor MN63, the drain of the transistor MP64, the capacitor C62, and the gate of the transistor MN65, and the other end connected to the power supply line VSS2. Note that the capacitor C61 may also be configured using, for example, a MOS capacitor or a MIM (Metal Insulator Metal) capacitor.

[0174] The capacitor C62 is configured using, for example, a MOS capacitor, and has one end connected to the source of the transistor MN63, the drain of the transistor MP64, one end of the capacitor C61, and the gate of the transistor MN65, and the other end connected to the power supply line VSS2. Note that the capacitor C62 may also be configured using, for example, a MOM capacitor or an MIM capacitor. The other end of the capacitor C62 may also be connected to the power supply line VSS3 (not shown).

[0175] The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67.

[0176] The gate of the transistor MN66 is connected to the signal line AZ, the drain is connected to the source of the transistor MN65 and the drain of the transistor MN67, and the source is connected to the power supply line VSS1.

[0177] The gate of the transistor MN67 is connected to the signal line DS, the drain is connected to the source of the transistor MN65 and the drain of the transistor MN66, and the source is connected to the anode of the light emitting element L.

[0178] With this configuration, in pixel 130, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on signal line DS. While transistor MN65 is on, it passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP65. In this way, pixel 130 emits light at a brightness corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on signal line AZ. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on signal line AZ. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0179] (Application Examples of the Display Device 1 According to the Present Disclosure) (First Application Example) The display device 1 according to the present disclosure can be used for various purposes. Fig. 17A and Fig. 17B are diagrams showing the internal configuration of a vehicle 360, which is a first application example of the display device 1 according to the present disclosure. Fig. 17A is a diagram showing the interior of the vehicle 360 ​​from the rear to the front of the vehicle 360, and Fig. 17B is a diagram showing the interior of the vehicle 360 ​​from diagonally rear to diagonally front of the vehicle 360.

[0180] Vehicle 360 ​​of FIGS. 17A and 17B includes a center display 361, a console display 362, a head-up display 363, a digital rearview mirror 364, a steering wheel display 365, and a rear entertainment display 366.

[0181] The center display 361 is disposed on the dashboard 367 in a position facing the driver's seat 368 and the passenger's seat 369. FIG. 17 shows an example of a horizontally elongated center display 361 extending from the driver's seat 368 side to the passenger's seat 369 side, but the screen size and location of the center display 361 are arbitrary. The center display 361 can display information detected by various sensors. As a specific example, the center display 361 can display an image captured by an image sensor, a distance image to obstacles in front of or on the side of the vehicle measured by a ToF sensor, and the body temperature of a passenger detected by an infrared sensor. The center display 361 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0182] The safety-related information includes information such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger has been abandoned. This information is detected, for example, by a sensor placed on the back side of the center display 361. The operation-related information is obtained by detecting gestures related to passenger operations using a sensor. The detected gestures may include operations of various equipment within the vehicle 360. For example, operations of the air conditioning system, navigation system, AV system, lighting system, etc. are detected. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's actions while on board. By acquiring and storing the life log, the passenger's condition at the time of an accident can be confirmed. The health-related information is obtained by detecting the passenger's body temperature using a temperature sensor and inferring the passenger's health condition based on the detected body temperature. Alternatively, the passenger's face may be captured using an image sensor and the passenger's health condition may be inferred from the facial expression in the captured image. Furthermore, the passenger may be spoken to by an automated voice and the passenger's health condition may be inferred based on the passenger's responses. The authentication / identification-related information includes a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes a function that uses a sensor to detect operation information of an AV device by an occupant, a function that recognizes the occupant's face with a sensor and provides content suitable for the occupant via the AV device, etc.

[0183] Console display 362 can be used to display, for example, life log information. Console display 362 is disposed near a shift lever 371 on a center console 370 between a driver's seat 368 and a passenger seat 369. Information detected by various sensors can also be displayed on console display 362. Furthermore, console display 362 may display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0184] The head-up display 363 is virtually displayed behind a windshield 372 in front of the driver's seat 368. The head-up display 363 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 363 is often virtually located in front of the driver's seat 368, it is suitable for displaying information directly related to the operation of the vehicle 360, such as the speed of the vehicle 360 ​​and the remaining fuel (battery) level.

[0185] The digital rearview mirror 364 can not only display the rear of the vehicle 360, but also the status of passengers in the rear seats. Therefore, by placing a sensor on the back side of the digital rearview mirror 364, it can be used to display life log information, for example.

[0186] Steering wheel display 365 is disposed near the center of steering wheel 373 of vehicle 360. Steering wheel display 365 can be used to display at least one of, for example, safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because steering wheel display 365 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information regarding the operation of AV equipment, air conditioning equipment, etc.

[0187] The rear entertainment display 366 is attached to the back of the driver's seat 368 and the passenger seat 369 and is intended for viewing by rear seat passengers. The rear entertainment display 366 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 366 is located directly in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 366. For example, the rear entertainment display 366 may display information related to the operation of an AV device or an air conditioning system, or may display the results of measurements such as the body temperature of the rear seat passengers using a temperature sensor.

[0188] As described above, by arranging a sensor on the rear side of the display device 1, the distance to surrounding objects can be measured. Optical distance measurement methods can be broadly divided into passive and active types. Passive methods measure distance by receiving light from an object without projecting light from the sensor onto the object. Passive methods include the lens focusing method, the stereo method, and the monocular vision method. Active methods measure distance by projecting light onto an object and receiving the light reflected from the object with a sensor. Active methods include the optical radar method, the active stereo method, the photometric stereo method, the moire topography method, and the interferometry method. The display device 1 according to the present disclosure can be applied to any of these distance measurement methods. By using a sensor arranged on the rear side of the display device 1 according to the present disclosure, the above-mentioned passive or active distance measurement can be performed.

[0189] (Second Application Example) The display device 1 according to the present disclosure is applicable not only to various displays used in vehicles but also to displays mounted on various electronic devices.

[0190] Fig. 18A is a front view of a digital camera 310 which is a second application example of the display device 1, and Fig. 18B is a rear view of the digital camera 310. The digital camera 310 in Fig. 18A and Fig. 18B shows an example of a single-lens reflex camera with an interchangeable lens 121, but the digital camera 310 can also be applied to a camera in which the lens 121 cannot be interchangeable.

[0191] 18A and 18B, when the photographer holds the grip 313 of the camera body 311, looks through the electronic viewfinder 315, decides on the composition of the shot, adjusts the focus, and presses the shutter, the captured data is saved in the camera's internal memory. As shown in Fig. 18B, the rear side of the camera is provided with a monitor screen 316 that displays the captured data, live images, etc., and the electronic viewfinder 315. In addition, a sub-screen that displays setting information such as the shutter speed and exposure value may be provided on the top surface of the camera.

[0192] By arranging the sensor on the back side of the monitor screen 316, electronic viewfinder 315, sub-screen, etc. used in a camera, it can be used as the display device 1 according to the present disclosure.

[0193] (Third Application Example) The display device 1 according to the present disclosure can also be applied to a head-mounted display (hereinafter referred to as an HMD). The HMD can be used for VR, AR, MR (Mixed Reality), SR (Substitutional Reality), or the like.

[0194] Fig. 19A is an external view of an HMD 320, which is a third application example of the display device 1. The HMD 320 in Fig. 19A has a mounting member 322 for being worn over a person's eyes. This mounting member 322 is secured by hooking it onto a person's ear, for example. A display device 321 is provided inside the HMD 320, and a person wearing the HMD 320 can view 3D images and the like on this display device 321. The HMD 320 is equipped with, for example, a wireless communication function and an acceleration sensor, and can switch the 3D images and the like displayed on the display device 321 according to the posture, gestures, and the like of the wearer.

[0195] Alternatively, a camera may be provided in the HMD 320 to capture an image of the wearer's surroundings, and an image obtained by combining the image captured by the camera with an image generated by a computer may be displayed on the display device 321. For example, a camera may be placed on the back side of the display device 321, which is viewed by the wearer of the HMD 320, to capture an image of the area around the wearer's eyes, and the captured image may be displayed on another display provided on the outer surface of the HMD 320, allowing people around the wearer to grasp the wearer's facial expressions and eye movements in real time.

[0196] Various types of HMD 320 are possible. For example, as shown in FIG. 19B , the display device 1 according to the present disclosure can also be applied to smart glasses 340 that display various information on glasses 344. The smart glasses 340 in FIG. 19B include a main body 341, an arm 342, and a lens barrel 343. The main body 341 is connected to the arm 342. The main body 341 is detachable from the glasses 344. The main body 341 incorporates a control board for controlling the operation of the smart glasses 340 and a display unit. The main body 341 and the lens barrel are connected to each other via the arm 342. The lens barrel 343 emits image light emitted from the main body 341 via the arm 342 toward lenses 345 of the glasses 344. This image light enters the human eye through the lens 345. A person wearing the smart glasses 340 of FIG. 19B can visually recognize not only the surrounding situation but also various pieces of information emitted from the lens barrel portion 343, just like with regular glasses.

[0197] (Fourth Application Example) The display device 1 according to the present disclosure can also be applied to a television device (hereinafter referred to as a TV). Recent TVs tend to have as small a frame as possible from the viewpoints of miniaturization and design. For this reason, when a camera for capturing images of viewers is installed in a TV, it is desirable to place the camera on the back side of the TV's display panel 331.

[0198] FIG. 20 is an external view of a TV 330, which is a fourth application example of the display device 1. The TV 330 in FIG. 20 has a minimized frame, with almost the entire front side being the display area. The TV 330 has a built-in sensor, such as a camera, for capturing images of the viewer. The sensor in FIG. 20 is disposed on the back side of a portion of the display panel 331 (for example, the area enclosed by the dashed line). The sensor may be an image sensor module, or various other sensors such as a face authentication sensor, a distance measurement sensor, or a temperature sensor may be used, and multiple types of sensors may be disposed on the back side of the display panel 331 of the TV 330.

[0199] As described above, according to the display device 1 of the present disclosure, the image sensor module can be placed on top of the back side of the display panel 331, which eliminates the need to place a camera or the like in the frame, allowing the TV 330 to be made smaller, and there is no risk of the frame compromising the design.

[0200] (Fifth Application Example) The display device 1 according to the present disclosure can also be applied to smartphones and mobile phones. FIG. 21 is an external view of a smartphone 350, which is a fifth application example of the display device 1. In the example of FIG. 21, a display surface 350z extends to nearly the outer size of the display device 1, and the width of a bezel 350y surrounding the display surface 350z is set to a few millimeters or less. Typically, a front camera is mounted in the bezel 350y. However, in FIG. 21, as shown by the dashed line, an image sensor module 351 functioning as a front camera is disposed on the rear side of the display surface 2z, for example, in the approximate center thereof. By providing the front camera on the rear side of the display surface 2z in this manner, there is no need to dispose the front camera in the bezel 350y, and the width of the bezel 350y can be narrowed.

[0201] The above-described embodiment may be modified as follows.

[0202] (1) A display device comprising: a light-emitting pixel; an interface that receives a signal based on a first clock frequency; and a signal processing circuit that processes the signal at a second clock frequency that is controlled by a predetermined frequency independent of the frame rate, wherein the light-emitting pixel comprises: a light-emitting element; and a drive element that drives the light-emitting element based on the signal processed by the signal processing circuit.

[0203] (2) The display device according to (1), wherein the interface is a high-speed interface.

[0204] (3) The display device according to (2), further comprising: a memory that stores signals transferred by the interface.

[0205] (4) The display device according to (3), wherein the memory is a line buffer.

[0206] (5) The display device according to (3), wherein the memory is a frame memory.

[0207] (6) The display device according to any one of (1) to (5), wherein the signal processing circuit performs signal processing using a ramp signal having a predetermined slope based on the second clock frequency, regardless of the frame rate.

[0208] (7) The display device according to any one of (1) to (6), wherein the driving element is self-discharged.

[0209] (8) The display device according to (7), wherein the drive element is initialized by self-discharge to determine the threshold voltage.

[0210] (9) The display device according to (8), wherein initialization of the driving element is controlled by a correction period determined by the second clock frequency.

[0211] (10) The display device according to any one of (1) to (6), wherein the signal processing circuit converts a digital signal into an analog signal based on a ramp signal according to the second clock frequency and outputs the analog signal to the pixel circuit, and the pixel circuit causes the light-emitting element to emit light based on the analog signal.

[0212] (11) The display device according to any one of (1) to (5), wherein the signal processing circuit outputs an analog signal converted from a digital signal to the pixel circuit via a voltage follower, and the pixel circuit causes the light-emitting element to emit light based on the signal output from the voltage follower.

[0213] (12) The display device according to any one of (1) to (11), further comprising: an internal clock generating circuit that generates the second clock frequency.

[0214] (13) The display device according to (12), wherein the internal clock generating circuit includes at least one of a DLL (Delay Locked Loop) and a PLL (Phase Locked Loop).

[0215] (14) The display device according to (12), wherein the internal clock generating circuit includes an oscillator.

[0216] (15) The display device according to any one of (1) to (11), wherein the first clock frequency is obtained from an external source via the interface.

[0217] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0218] 1: display device, 100: input / output I / F, 102: gamma generation circuit, 104: power supply, 106: high-speed I / F, 108: control circuit, 110: vertical logic circuit, 112: vertical analog circuit, 114: horizontal logic circuit, 116: horizontal analog circuit, 118: pixel array, 120: generator, 1200, 1202: oscillator, 1204: clock generation circuit, 1206: multiplication control PLL, 122: memory, 130: pixel, L: light-emitting element, Tdr, Tds, Tws, Taz: transistor, C1, C2: capacitor

Claims

1. A display device comprising: a light-emitting pixel; an interface that receives a signal based on a first clock frequency; and a signal processing circuit that processes the signal at a second clock frequency that is controlled at a predetermined frequency independent of a frame rate, wherein the light-emitting pixel comprises: a light-emitting element; and a drive element that drives the light-emitting element based on the signal processed by the signal processing circuit.

2. The display device according to claim 1, wherein the interface is a high-speed interface.

3. The display device according to claim 2, further comprising: a memory that stores a signal transferred by the interface.

4. The display device according to claim 3, wherein the memory is a line buffer.

5. The display device according to claim 3, wherein the memory is a frame memory.

6. The display device according to claim 1, wherein the signal processing circuit executes signal processing using a ramp signal having a predetermined slope based on the second clock frequency and independent of the frame rate.

7. The display device according to claim 1, wherein the driving element is self-discharging.

8. The display device according to claim 7, wherein the drive element is initialized by self-discharge to determine the threshold voltage.

9. The display device according to claim 8, wherein initialization of the drive element is controlled by a correction period determined by the second clock frequency.

10. The display device of claim 1, wherein the signal processing circuit converts a digital signal into an analog signal based on a ramp signal according to the second clock frequency and outputs the analog signal to the pixel circuit, and the pixel circuit causes the light-emitting element to emit light based on the analog signal.

11. The display device according to claim 1, wherein the signal processing circuit outputs an analog signal converted from a digital signal to the pixel circuit via a voltage follower, and the pixel circuit causes the light-emitting element to emit light based on the signal output from the voltage follower.

12. The display device of claim 1, further comprising: an internal clock generating circuit that generates the second clock frequency.

13. The display device according to claim 12, wherein the internal clock generating circuit comprises at least one of a DLL (Delay Locked Loop) or a PLL (Phase Locked Loop).

14. The display device according to claim 12, wherein the internal clock generating circuit includes an oscillator.

15. The display device according to claim 1, wherein the first clock frequency is obtained from outside via the interface.

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