X-ray detector

Abstract

The present invention provides an X-ray detector comprising: a pixel array panel including a plurality of pixels; a single-photon avalanche diode disposed within the pixels; a diode driving circuit disposed within the pixels and comprising a pulse generation circuit converting an electrical signal output from an output terminal of the single-photon avalanche diode into an output signal in the form of a pulse; a pixel control circuit disposed within the pixels and comprising a first control circuit outputting the output signal as a clock signal; a second control circuit; and a counter circuit disposed within the pixels and comprising an n-bit counter (N is an integer of 2 or more) for counting the clock signal.

Description

X-ray detector

[0001] The present invention relates to an X-ray detector.

[0002] In recent years, digital detectors have become widely used for X-ray photography.

[0003] X-ray detectors are equipped with photodiodes, and recently, research is being conducted on using avalanche diodes, especially signal-photon avalanche diodes (SPADs), which have the advantage of high signal gain.

[0004] However, existing image sensors using single-photon avalanche diodes are equipped with analog counters to count pulses. In this case, it is difficult to achieve high resolution and a wide dynamic range, and there is a problem of noise occurring in the process of converting and reading analog signals into digital signals.

[0005] Therefore, if an X-ray detector has the same pixel configuration as a conventional image sensor, it will have essentially the same problems.

[0006] The present invention has as its object a method for implementing high resolution and a wide dynamic range and also preventing noise generation in an X-ray detector using a single-photon avalanche diode.

[0007] In order to achieve the above-described task, the present invention provides an X-ray detector comprising: a pixel array panel including a plurality of pixels; a single-photon avalanche diode disposed within the pixel; a diode driving circuit disposed within the pixel and including a pulse generation circuit that converts an electric signal output from an output terminal of the single-photon avalanche diode into an output signal in a pulse form; a pixel control circuit disposed within the pixel and including a first control circuit that outputs the output signal as a clock signal; and a counter circuit disposed within the pixel and including an n-bit (n is an integer greater than or equal to 2) counter that counts the clock signal.

[0008] The diode driving circuit may include a recharge transistor connected to an output terminal of the single-photon avalanche diode; a recharge control circuit having a first input terminal connected to an output terminal of the pulse generation circuit, a second input terminal receiving an enable control signal, and an output terminal connected to a gate electrode of the recharge transistor; and an enable transistor having a gate electrode receiving the enable control signal, a source electrode connected to the output terminal of the single-photon avalanche diode, and a drain electrode receiving a deactivation voltage.

[0009] The bias voltage applied to the cathode of the above single-photon avalanche diode is the sum of the breakdown voltage and the access voltage, and the deactivation voltage may be greater than the access voltage.

[0010] The pixel control circuit includes a second control circuit that receives an enable signal and an output control signal output from the counter and outputs the enable control signal, the enable signal determines an accumulation interval, and the output control signal can be turned off when the counting value of the counter reaches the maximum value of the n bits.

[0011] The counter circuit includes an output circuit that outputs the n-bit data signal stored in the counter to a data wire, and the counter can divide the n-bit data signal into k (k is an integer greater than or equal to 2 and less than n) and output a first division signal to a k-th division signal of n / k bits.

[0012] The output circuit includes n / k first driving transistors to kth driving transistors and n / k first switching transistors and kth switching transistors corresponding to the first to kth division signals, respectively, and each of the first to kth driving transistors has a gate electrode connected to a corresponding output terminal of the counter, and a drain electrode connected to the first to kth switching transistors, and each of the first to kth switching transistors has a gate electrode that receives the first to kth scan signals, and a drain electrode connected to a corresponding data wire, and the data wire can transmit a corresponding bit of the division signal output from the switching transistor connected thereto.

[0013] The above counter can receive a bit adjustment signal for adjusting the number of n bits.

[0014] According to the present invention, by configuring a digital counter within a pixel equipped with a single-photon avalanche diode, a digital data signal can be generated and read directly within the pixel.

[0015] Accordingly, noise generation during data signal extraction is virtually zero, maximizing image quality. Furthermore, the use of an n-bit digital counter enables the implementation of images with a wide dynamic range and high resolution, both of which are difficult to achieve with analog counters.

[0016] FIG. 1 is a drawing schematically illustrating the configuration of an X-ray detector according to an embodiment of the present invention.

[0017] FIG. 2 is a circuit diagram schematically illustrating an example of a pixel configuration of an X-ray detector according to an embodiment of the present invention.

[0018] FIG. 3 is a circuit diagram illustrating a single-photon avalanche diode and diode driving circuit of a pixel according to an embodiment of the present invention.

[0019] FIG. 4 is a circuit diagram schematically illustrating a control circuit and a counter circuit of a pixel according to an embodiment of the present invention.

[0020] FIG. 5 is a timing diagram illustrating signals for operating a pixel according to an embodiment of the present invention.

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0022] FIG. 1 is a schematic diagram illustrating the configuration of an X-ray detector according to an embodiment of the present invention. FIG. 2 is a circuit diagram schematically illustrating an example of the configuration of a pixel of an X-ray detector according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a single-photon avalanche diode and a diode driving circuit of a pixel according to an embodiment of the present invention, and FIG. 4 is a circuit diagram schematically illustrating a control circuit and a counter circuit of a pixel according to an embodiment of the present invention.

[0023] Referring to FIGS. 1 and 2, an X-ray detector (10) according to an embodiment of the present invention may include a pixel array panel (or sensor panel) (100) and a fluorescent substance (200).

[0024] The phosphor (200) may be placed on the light-receiving surface of the pixel array panel (100). The phosphor (200) converts incident X-rays into visible light, and the visible light is provided to the pixel array panel (100). An avalanche photodiode (or avalanche light-receiving element) provided in the pixel (P), for example, a single-photon avalanche diode (SPAD), may detect visible light photons and generate an electrical signal.

[0025] The pixel array panel (100) may include an active area, which is a region that actually receives and detects X-rays, and a non-active area located outside the active area.

[0026] In the active area, a pixel array composed of a plurality of pixels (P) is arranged, and these plurality of pixels (P) can be arranged in a matrix form along a plurality of row lines and a plurality of column lines.

[0027] A pixel (P) can detect a photon of visible light generated from a phosphor (200) using a single-photon avalanche diode (SPAD), generate a corresponding pulse signal, count the number of photons, and output the counted value.

[0028] With reference to FIGS. 2 to 4, regarding the configuration of a pixel (P), for example, each pixel (P) may include a single-photon avalanche diode (SPAD), a diode driving circuit (PDC), a pixel control circuit (PCC), and a counter circuit (COC).

[0029] One electrode (or first electrode) of a single-photon avalanche diode (SPAD), for example, an anode, can be connected to a diode driving circuit (PDC). And, the other electrode (or second electrode) of the single-photon avalanche diode (SPAD), for example, a cathode, can receive a bias voltage (or reverse voltage) (Vb), which is a driving voltage.

[0030] Here, the bias voltage (Vb) is a voltage for generating avalanche amplification by operating the single-photon avalanche diode (SPAD) in Geiger mode, and it is preferable to have a voltage greater than the breakdown (or breakdown) voltage (Vbd). For example, the bias voltage (Vb) can be expressed as the sum of the breakdown voltage (Vbd) and the access voltage (Vex), which is a voltage greater than the minimum level value for operating the single-photon avalanche diode in Geiger mode, i.e. (Vb = Vbd + Vex).

[0031] In this way, when a bias voltage (Vb) higher than the breakdown voltage (Vbd) is applied to operate the single-photon avalanche diode (SPAD), i.e., in an activated state, the single-photon avalanche diode (SPAD) generates an electrical signal (or diode signal or detection signal) in response to an incident photon.

[0032] The diode driver circuit (PDC) may include, for example, a pulse generation circuit (or delay circuit or shaping circuit) (PSC), a recharge transistor (or first transistor) (Mar), an enable transistor (or second transistor) (Maq), and a recharge control circuit (RCC).

[0033] A pulse generation circuit (PSC) may be connected to a node (N) between the anode of the SPAD and the recharge transistor (Mar) as an output terminal of a single-photon avalanche diode (SPAD). This pulse generation circuit (PSC) may convert (or shape) an electrical signal output in response to a photon from the SPAD into a pulse-shaped (or square-wave) digital signal, which is an output signal (PS), and output it. This pulse generation circuit (PSC) may be composed of, for example, a plurality of inverters, more specifically, an even number of inverters, connected in series. In this case, the pulse generation circuit (PSC) may delay the output signal (PS) by a predetermined time (for example, several ns to several us).

[0034] The recharge transistor (Mar) can be connected in series with a single-photon avalanche diode (SPAD), and an electrical signal can be output through an output terminal, which is a node (N) between the recharge transistor (Mar) and the single-photon avalanche diode (SPAD). The recharge transistor (Mar) can be composed of, for example, an N-type transistor, but is not limited thereto.

[0035] When a recharge signal (Φar), which is a control signal, is applied to the gate electrode of the recharge transistor (Mar), the recharge transistor (Mar) is turned on, and accordingly, the single-photon avalanche diode (SPAD) is recharged to its initial state, and a diode voltage corresponding to a bias voltage (Vb) can be applied to both terminals of the single-photon avalanche diode (SPAD).

[0036] The recharge control circuit (RCC) can generate and output a recharge signal (Φar) that controls the switching operation of the recharge transistor (Mar). In this regard, for example, the recharge control circuit (RCC) can be configured with an AND gate, and at this time, the AND gate can receive an output signal (PS) of a pulse generation circuit (PSC) at a first input terminal and an enable control signal (Φaq) output from a pixel control circuit (PCC) at a second input terminal. In this case, the AND gate circuit can perform an AND logic operation on the output signal (PS) and the enable control signal (Φaq) to output the recharge signal (Φar).

[0037] In this regard, for example, when the pixel (P) is in a normal state and is activated, the enable control signal (Φaq) can have a high level with a logic value of "1", and in this state, when a pulse-shaped output signal (PS) is generated, the recharge control circuit (RCC) can output a pulse-shaped recharge signal (Φar). In this case, the recharge transistor (Mar) is turned on by the recharge signal (Φar), and accordingly, the single-photon avalanche diode (SPAD) is recharged, and a diode voltage substantially corresponding to the bias voltage (Vb) is applied to both terminals of the single-photon avalanche diode (SPAD), and the SPAD can be activated to detect a photon.

[0038] The enable transistor (Maq) may be of a type opposite to the recharge transistor (Mar), for example, but is not limited to, a P-type transistor.

[0039] The drain electrode (or source electrode) of the enable transistor (Maq) can be connected to the node (N) between the recharge transistor (Mar) and the single-photon avalanche diode (SPAD). In addition, the source electrode (or drain electrode) of the enable transistor (Maq) can be applied with a deactivation voltage (Vna). In addition, the gate electrode of the enable transistor (Maq) can be applied with an enable control signal (Φaq).

[0040] Here, the deactivation voltage (Vna) may have a voltage greater than the access voltage (Vex) of the bias voltage (Vb). And, the deactivation voltage (Vna) may be a voltage less than the breakdown voltage (Vbd).

[0041] In this regard, for example, when the enable control signal (Φaq) is a low level with a logic value of "0", the enable transistor (Maq) can be turned on, and a deactivation voltage (Vna) can be applied to the node (N) between the recharge transistor (Mar) and the single-photon avalanche diode (SPAD). In this case, the diode voltage applied to the single-photon avalanche diode (SPAD) becomes (Vb - Vna = Vbd + Vex - Vna; Vna > Vex), so that a voltage smaller than the breakdown voltage (Vbd) is applied to both terminals of the single-photon avalanche diode (SPAD). As a result, the single-photon avalanche diode (SPAD) is in a deactivated state and does not detect a photon.

[0042] Meanwhile, when the enable control signal (Φaq) is at a high level with a logic value of "1", the enable transistor (Maq) can be turned off, and the deactivation voltage (Vna) is not applied to the node (N) between the recharge transistor (Mar) and the single-photon avalanche diode (SPAD), so that the single-photon avalanche diode (SPAD) remains activated and can output an electric signal in response to the input photon.

[0043] As described above, depending on the logic value of the enable control signal (Φaq), the pixel (P), more specifically the single-photon avalanche diode (SPAD), can be activated or deactivated, and in the activated state, the single-photon avalanche diode (SPAD) generates an electrical signal according to the photon, which can be converted into a pulse-shaped output signal (PS) by the diode driving circuit (PDC) and output.

[0044] In this way, the enable control signal (Φaq) can have a logic value "1" (or turn-off level) so that the single-photon avalanche diode (SPAD) can be in an activated state during the integration time, which is a period for detecting X-rays. Meanwhile, the enable control signal (Φaq) can have a logic value "0" (or turn-on level) so that the single-photon avalanche diode (SPAD) can be in an inactivated state during the readout time, which reads (or outputs) the data signal (or pixel signal) detected (or counted) from the pixel (P) after the end of the integration time.

[0045] The pixel control circuit (PCC) may include, for example, a first control circuit (CC1) and a second control circuit (CC2).

[0046] The first control circuit (CC1) can output an output signal (PS) output from a diode driving circuit (PDC) as a clock signal (Φclk). Such a first control circuit (CC1) can receive, for example, an output signal (PS) output from a diode driving circuit (PDC) and an output control signal (or overflow signal) (Φof) provided from a counter circuit (COC), more specifically, a counter (CNT), as input signals.

[0047] Here, with respect to the output control signal (Φof), when the counted value of the counter (CNT) reaches a predetermined bit, for example, the most significant bit of the set number of bits, the operation of the single-photon avalanche diode (SPAD) is stopped, that is, the generation of the output signal (PS) and the clock signal (Φclk) is stopped, thereby corresponding to a signal to stop the counting operation of the counter (CNT). In other words, when the counted value of the counter (CNT) reaches a predetermined saturation value, the output control signal (Φof) can be used to stop counting.

[0048] For example, the output control signal (Φof) can have a low level (or on level) with a logic value of "0" before the counting value is saturated in the accumulation section, and can have a high level (or off level) with a logic value of "1" when the counting value reaches a predetermined saturation value.

[0049] And, the first control circuit (CC1) can be configured as, for example, an OR gate, and can output a clock signal (Φclk) by performing an OR logic operation on the output signal (PS) and the output control signal (Φof).

[0050] When the output control signal (Φof) is “0”, the first control circuit (CC1) can output the input output signal (PS) as a clock signal (Φclk), and the counter (CNT) can count the clock signal (Φclk).

[0051] Meanwhile, when the counting value is saturated, the output control signal (Φof) becomes “1” and the output signal (PS) is not generated, and the first control circuit (CC1) can stop outputting the clock signal (Φclk).

[0052] The second control circuit (CC2) can output an enable control signal (Φaq) that controls the activation / deactivation of a single-photon avalanche diode (SPAD). Such a second control circuit (CC2) can receive, for example, an enable signal (EN) and an output control signal (Φof) as input signals.

[0053] The enable signal (EN) is a signal that determines the accumulation section. For example, the enable signal (EN) can have a high level with a logic value of "1" during the accumulation section, and the enable signal (EN) can have a low level with a logic value of "0" during the readout section after the accumulation section.

[0054] This second control circuit (CC2) can be configured, for example, with a NOR gate, and the first input terminal of this NOR gate can receive an output control signal (Φof), and the second input terminal can receive an enable signal (EN) as an inverting input terminal.

[0055] In this case, the second control circuit (CC2) can output an enable control signal (Φaq) by performing a NOR logic operation on the inverted signal of the output control signal (Φof) and the enable signal (EN).

[0056] Here, when the counting of the counter circuit (COC) becomes saturated and the output control signal (Φof) becomes a high level, the enable control signal (Φaq) becomes a low level, which is a turn-on level, so that the enable transistor (Maq) is turned on, and a deactivation voltage (Vna) is applied to the node (N), so that the single-photon avalanche diode (SPAD) can be deactivated. Accordingly, the operation of the single-photon avalanche diode (SPAD) is stopped, so that power consumption can be reduced.

[0057] And, when the accumulation period ends, the enable signal (EN) becomes a low level, the enable control signal (Φaq) becomes a low level, which is a turn-on level, and the enable transistor (Maq) is turned on, so that the single-photon avalanche diode (SPAD) can be in an inactive state.

[0058] The counter circuit (COC) may include, for example, a counter (CNT) and an output circuit (OC).

[0059] The counter (CNT) can receive a pulse-shaped clock signal (Φclk) output from the first control circuit (CC1) during the accumulation period, count it, and store the counted value. When the counted value in the counter (CNT) becomes saturated by becoming the maximum value of a set bit, for example, n (an integer greater than or equal to 2), the counting operation can be stopped and an output control signal (Φof) can be generated.

[0060] Meanwhile, the counter (CNT) can receive a bit adjustment signal (BIT_SEL) and a reset signal (Φrst).

[0061] The bit adjustment signal (BIT_SEL) is a signal for adjusting (or setting) the number of bits that the counter (CNT) can count, i.e., the number of bits of the data signal of the pixel (P). For example, n can be adjusted to 8 bits, 9 bits, 10 bits, etc. Through such bit adjustment, the dynamic range required for the X-ray detector (10) can be optimized and power consumption can be reduced.

[0062] The reset signal (Φrst) can be used to reset the counter (CNT) and initialize the counting value. For example, the reset signal (Φrst) can be applied before the start of the accumulation period to reset the counter (CNT).

[0063] The output circuit (OC) can output a data signal, which is a digital value counted by the counter (CNT) during the readout period, to the data line (DL).

[0064] Such an output circuit (OC) can be configured to output, for example, n bits of a data signal by dividing them into k (an integer greater than or equal to 2 and less than n) bits. In this embodiment, an example is given of dividing an n bit data signal into two, a first division signal which is a signal of n / 2 bits, and a second division signal which is a signal of another n / 2 bits, and outputting the divided signals.

[0065] In this case of dividing the data signal into two, the output circuit (OC) may include a first driving transistor (Td1) and a first switching transistor (Ts1) for outputting a first division signal of n / 2 bits, and a second driving transistor (Td2) and a second switching transistor (Ts2) for outputting a second division signal of n / 2 bits. Here, the first division signal may be, for example, the upper n / 2 bits (or lower n / 2 bits) of the data signal, and the second division signal may be, for example, the lower n / 2 bits (or upper n / 2 bits) of the data signal.

[0066] Here, the first driving transistor (Td1) and the first switching transistor (Ts1) may be configured to correspond to each of n / 2 bits of the first division signal. In other words, n / 2 first driving transistors (Td1) and first switching transistors (Ts1) may be provided to correspond to each of n / 2 bits of the first division signal.

[0067] Similarly, the second driving transistor (Td2) and the second switching transistor (Ts2) may be configured to correspond to each of n / 2 bits of the second division signal. In other words, n / 2 second driving transistors (Td2) and second switching transistors (Ts2) may be provided to correspond to each of n / 2 bits of the second division signal.

[0068] Meanwhile, for the data lines (DL) connected to each pixel (P), n / 2 data lines (DL), which are the number of bits of the first division signal and the second division signal, may be provided. In other words, each of the n / 2 data lines (DL) may be configured to be connected to n / 2 first switching transistors (Ts1) and also to be connected to n / 2 second switching transistors (Ts2). In this case, during a section in which the first division signal is output, each of the n / 2 data lines (DL) may transmit n / 2 bits of the first division signal output from the n / 2 first switching transistors (Ts1), and during a section in which the second division signal is output, each of the n / 2 data lines (DL) may transmit n / 2 bits of the second division signal output from the n / 2 second switching transistors (Ts2).

[0069] The first driving transistor (Td1) may have a gate electrode connected to a first output terminal of a counter (CNT) that outputs a corresponding bit of a first division signal, a drain electrode connected to a first switching transistor (Ts1), and a source electrode connected to a ground voltage (or a low potential voltage). In addition, the first switching transistor (Ts1) may have a gate electrode that receives a first scan signal (Φrow_A), a source electrode connected to a corresponding first driving transistor (Td1), and a drain electrode connected to a corresponding data line (DL).

[0070] And, the second driving transistor (Td2) may have a gate electrode connected to a second output terminal of a counter (CNT) that outputs a corresponding bit of a second division signal, a drain electrode connected to a second switching transistor (Ts2), and a source electrode connected to a ground voltage (or a low potential voltage). And, the second switching transistor (Ts2) may have a gate electrode that receives a second scan signal (Φrow_B), a source electrode connected to a corresponding second driving transistor (Td2), and a drain electrode connected to a corresponding data line (DL).

[0071] In this case, while the first scan signal (Φrow_A) of the turn-on level is applied, the first switching transistor (Ts1) is turned on, so that the first division signal of n / 2 bits can be output to n / 2 data lines (DL). Then, while the second scan signal (Φrow_B) of the turn-on level is applied, the second switching transistor (Ts2) is turned on, so that the second division signal of n / 2 bits can be output to n / 2 data lines (DL).

[0072] In this way, during the reading section, the pixels (P) located in each row line can divide and output an n-bit data signal in digital form.

[0073] In this way, by dividing the data signal and outputting it, the number of data wires connected to each column line can be reduced to the number of bits of the divided signal, thereby reducing the area occupied by the data wires.

[0074] Hereinafter, with reference to FIG. 5, the operation of the pixel (P) in the accumulation section and the readout section will be examined. FIG. 5 is a timing diagram illustrating signals for operating a pixel according to an embodiment of the present invention.

[0075] Referring to FIGS. 2 to 4 and 5, before the start of the accumulation period (Tint), a reset signal (Φrst) may be applied to the counter (CNT) so that the counter (CNT) may be reset.

[0076] After that, an enable signal (EN) is applied to activate the single photon avalanche diode (SPAD) and start the accumulation period (Tint). In the accumulation period (Tint), when a photon is incident on the single photon avalanche diode (SPAD) by X-ray irradiation, an electrical signal is generated and input to the diode driving circuit (PDC).

[0077] A diode driving circuit (PDC) delays and outputs a pulse-shaped output signal (PS) in response to an input electrical signal, and can also generate a recharge signal (Φar) according to this output signal (PS).

[0078]

[0079] *The output signal (PS) is input to the first control circuit (CC1) of the pixel control circuit (PCC), and a clock signal (Φclk) can be output accordingly.

[0080] A clock signal (Φclk) can be input to a counter (CC) of a counter circuit (COC) and counted. This counting can be performed until the maximum value of a set bit is reached within an accumulation interval (Tint). When the counted value within the accumulation interval (Tint) reaches the maximum value, the counting operation can be stopped.

[0081] After the accumulation section (Tint) ends, in the read section (Trd), the digital data signal stored in the counter (CNT) can be output through the data line (DL). In this regard, for example, during the output time when the first scan signal (Φrow_A) is applied, the first division signal, which is a data signal of n / 2 bits, can be output, and thereafter, during the output time when the second scan signal (Φrow_B) is applied, the second division signal, which is a data signal of the remaining n / 2 bits, can be output.

[0082] After the reading section (Trd) like this is finished, the reset signal (Φclk) is applied again to reset the counter (CNT), and then the above operation can be repeated.

[0083] As described above, in this embodiment, an electric signal detected by a single-photon avalanche diode (SPAD) is converted into a pulse-shaped output signal (PS) and counted using a digital counter (CNT), thereby generating a digital data signal directly within a pixel (P) and reading it out.

[0084] Since these digital data signals are virtually immune to noise, the process of reading them virtually eliminates noise, maximizing image quality. Furthermore, the use of an n-bit digital counter enables the implementation of images with a wide dynamic range and high resolution, both of which are difficult to achieve with analog counters.

[0085] The above-described embodiments of the present invention are merely examples of the present invention, and may be freely modified within the scope encompassed by the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention within the scope of the appended claims and their equivalents.

Claims

1. A pixel array panel including a plurality of pixels; A single-photon avalanche diode disposed within the pixel; A diode driving circuit disposed within the pixel and including a pulse generation circuit that converts an electric signal output from an output terminal of the single-photon avalanche diode into an output signal in the form of a pulse; A pixel control circuit disposed within the pixel and including a first control circuit that outputs the output signal as a clock signal; A counter circuit disposed within the pixel and including an n-bit counter (n is an integer greater than or equal to 2) that counts the clock signal. An X-ray detector including:

2. In paragraph 1, The above diode driving circuit is, A recharge transistor connected to the output terminal of the above single-photon avalanche diode; A recharge control circuit having a first input terminal connected to the output terminal of the pulse generation circuit, a second input terminal receiving an enable control signal, and an output terminal connected to the gate electrode of the recharge transistor; An enable transistor including a gate electrode to which the enable control signal is applied, a source electrode connected to the output terminal of the single-photon avalanche diode, and a drain electrode to which a deactivation voltage is applied. X-ray detector.

3. In paragraph 2, The bias voltage applied to the cathode of the above single-photon avalanche diode is the sum of the breakdown voltage and the access voltage, The above deactivation voltage is greater than the above access voltage. X-ray detector.

4. In paragraph 1 or 2, The above pixel control circuit, It includes a second control circuit that receives an enable signal and an output control signal output from the counter and outputs the enable control signal. The above enable signal determines the accumulation interval, The above output control signal becomes off level when the counting value of the counter reaches the maximum value of the n bits. X-ray detector.

5. In paragraph 1 or 2, The above counter circuit includes an output circuit that outputs the n-bit data signal stored in the counter to a data wire, The above counter is an X-ray detector that divides the n bits of the data signal into k (k is an integer greater than or equal to 2 and less than n) and outputs a first division signal to a kth division signal of n / k bits.

6. In paragraph 5, The output circuit includes n / k first driving transistors to kth driving transistors and n / k first switching transistors and kth switching transistors corresponding to the first to kth division signals, respectively. Each of the first to kth driving transistors has its gate electrode connected to the corresponding output terminal of the counter, and its drain electrode connected to the first to kth switching transistors. Each of the first switching transistor to the kth switching transistor has a gate electrode that receives a first scan signal to the kth scan signal, and a drain electrode that is connected to a corresponding data wire. The above data wiring transmits the corresponding bit of the split signal output from the switching transistor connected thereto. X-ray detector.

7. In paragraph 1, The above counter receives a bit adjustment signal that adjusts the number of n bits. X-ray detector.

Images