X-ray detector

Abstract

The present invention provides an X-ray detector including: a pixel array panel including a plurality of pixels arranged in a matrix form along a plurality of row lines and a plurality of column lines; an avalanche diode provided in the pixels and having a cathode to which a bias voltage is applied; a recharge transistor connected to an anode of the avalanche diode; an activation transistor having a source electrode connected between the anode of the avalanche diode and the recharge transistor and drain electrode to which an deactivation voltage is applied; an activation circuit including a gate control circuit connected to a gate electrode of the activation transistor; and an activation control circuit for outputting a control signal to the gate control circuit, wherein the bias voltage is a sum of a breakdown voltage and an access voltage, and a difference between the bias voltage and the deactivation voltage is less than the breakdown voltage.

Description

X-ray detector

[0001] The present invention relates to an X-ray detector.

[0002] In recent years, digital detectors have become widely used for X-ray photography.

[0003] X-ray detectors are equipped with photodiodes, and recently, research is being conducted on using avalanche diodes, especially signal-photon avalanche diodes (SPADs), which have the advantage of high signal gain.

[0004] However, when using a single-photon avalanche diode, the high signal gain and high-speed operation of the pixel circuit result in high power consumption, which in turn causes performance degradation such as heat generation and voltage drop in the X-ray detector.

[0005] The present invention has a problem of providing a method for reducing power consumption of an X-ray detector using an avalanche diode and thereby improving performance degradation such as heat generation and voltage drop of the detector.

[0006] In order to achieve the above-described object, the present invention provides an X-ray detector comprising: a pixel array panel including a plurality of pixels arranged in a matrix form along a plurality of row lines and a plurality of column lines; an avalanche diode provided in the pixel and having a bias voltage applied to a cathode; a recharge transistor connected to the anode of the avalanche diode; an activation circuit including an activation transistor having a source electrode connected between the anode of the avalanche diode and the recharge transistor and a drain electrode to which a deactivation voltage is applied, and a gate control circuit connected to a gate electrode of the activation transistor; and an activation control circuit outputting a control signal to the gate control circuit, wherein the bias voltage is a sum of a breakdown voltage and an access voltage, and a difference between the bias voltage and the deactivation voltage is less than the breakdown voltage.

[0007] The above activation control circuit may include a first activation control circuit including a first control circuit that outputs a first control signal to the gate control circuit; and a second activation control circuit including a second control circuit that outputs a second control signal to the gate control circuit.

[0008] The pixel array panel may define a plurality of group areas arranged in a matrix form, the group areas may be configured with the pixels arranged in an N*N matrix, the first activation control circuit may include a first circuit group composed of N first control circuits corresponding to each of the pixels arranged in N row lines of the group area, and the second activation control circuit may include a second circuit group composed of N second control circuits corresponding to each of the pixels arranged in N column lines of the group area.

[0009] A first control circuit of the first circuit group corresponding to a pixel of the first row line within the group area may receive a basic signal, a first control circuit of the first circuit group corresponding to a pixel of the second row line within the group area may receive a first binning setting signal, a second control circuit of the second circuit group corresponding to a pixel of the first column line within the group area may receive the basic signal, and a second control circuit of the second circuit group corresponding to a pixel of the second column line within the group area may receive the first binning setting signal.

[0010] A first control circuit of the first circuit group corresponding to a pixel of the third row line within the group area may receive a second binning setting signal, a first control circuit of the first circuit group corresponding to a pixel of the fourth row line within the group area may receive the first binning setting signal, a second control circuit of the second circuit group corresponding to a pixel of the third column line within the group area may receive the second binning setting signal, and a second control circuit of the second circuit group corresponding to a pixel of the fourth column line within the group area may receive the first binning setting signal.

[0011] The above basic signal may have a constant logic value in the normal mode and the binning mode, the first binning setting signal may have the same logic value as the basic signal in the normal mode, and may have a logic value opposite to the basic signal in the binning mode in which the corresponding pixel is deactivated among the binning modes, and the second binning setting signal may have the same logic value as the basic signal in the normal mode, and may have the same logic value as the basic signal in the binning mode in which the corresponding pixel is activated among the binning modes, and may have a logic value opposite to the basic signal in the binning mode in which the corresponding pixel is deactivated among the binning modes.

[0012] A first control circuit of the first circuit group corresponding to a pixel of the first row line within the group area may receive a basic signal, a first control circuit of the first circuit group corresponding to a pixel of the second row line within the group area may receive a first-1 binning setting signal, a second control circuit of the second circuit group corresponding to a pixel of the first column line within the group area may receive a basic signal, and a second control circuit of the second circuit group corresponding to a pixel of the second column line within the group area may receive a first-2 binning setting signal.

[0013] The first control circuit of the first circuit group corresponding to the pixel of the third row line within the group area may receive the 2-1 binning setting signal, the first control circuit of the first circuit group corresponding to the pixel of the fourth row line within the group area may receive the 1-1 binning setting signal, the second control circuit of the second circuit group corresponding to the pixel of the third column line within the group area may receive the 2-2 binning setting signal, and the second control circuit of the second circuit group corresponding to the pixel of the fourth column line within the group area may receive the 1-2 binning setting signal.

[0014] The basic signal has a constant logic value in the normal mode and the binning mode, the 1-1 binning setting signal has the same logic value as the basic signal in the normal mode, and has a logic value opposite to the basic signal in the binning mode in which the pixels of the corresponding row line are deactivated in the binning mode, the 2-1 binning setting signal has the same logic value as the basic signal in the normal mode, and has the same logic value as the basic signal in the binning mode in which the pixels of the corresponding row line are activated in the binning mode, and has a logic value opposite to the basic signal in the binning mode in which the pixels of the corresponding row line are deactivated in the binning mode, the 1-2 binning setting signal has the same logic value as the basic signal in the normal mode, and has a logic value opposite to the basic signal in the binning mode in which the pixels of the corresponding column line are deactivated in the binning mode, and the 2-2 binning setting signal has the same logic value as the basic signal in the normal mode, and has the logic value opposite to the basic signal in the binning mode in which the pixels of the corresponding column line are activated in the binning mode. It has the same logic value as the basic signal, and in the binning mode in which the pixels of the corresponding column line are deactivated among the binning modes, it can have a logic value opposite to the basic signal.

[0015] The avalanche diode is a single-photon avalanche diode, and further includes a pulse generation circuit connected to the node, and the gate electrode of the recharge transistor can be connected to the output terminal of the pulse generation circuit.

[0016] According to the present invention, the avalanche diode of a pixel that does not require a pixel signal in binning mode is in an inactive state, so that no power is consumed.

[0017] Accordingly, the power consumption of an X-ray detector equipped with an avalanche diode can be reduced, thereby improving performance degradation such as heat generation and voltage drop of the detector.

[0018] FIG. 1 is a block diagram schematically illustrating the configuration of an X-ray detector according to a first embodiment of the present invention.

[0019] FIG. 2 is a circuit diagram schematically illustrating an example of the configuration of pixels of an X-ray detector according to a first embodiment of the present invention.

[0020] FIG. 3 is a drawing illustrating a case where the pixels of an X-ray detector according to the first embodiment of the present invention are in an inactive state.

[0021] FIG. 4 is a drawing illustrating a case where the pixels of an X-ray detector according to the first embodiment of the present invention are in an activated state.

[0022] FIG. 5 is a drawing illustrating a pixel array panel and first and second activation control circuits according to a first embodiment of the present invention.

[0023] FIG. 6 is a drawing showing an example of the configuration of a first activation control circuit according to a first embodiment of the present invention.

[0024] FIG. 7 is a drawing showing an example of the configuration of a second activation control circuit according to the first embodiment of the present invention.

[0025] FIG. 8 is a diagram illustrating a case where an X-ray detector according to a first embodiment of the present invention is driven in a 2*2 binning mode.

[0026] FIG. 9 is a diagram illustrating a case where an X-ray detector according to a first embodiment of the present invention is driven in a 4*4 binning mode.

[0027] Figure 10 is a schematic drawing of an X-ray detector according to a second embodiment of the present invention.

[0028] FIG. 11 is a drawing showing an example of the configuration of a first activation control circuit according to a second embodiment of the present invention.

[0029] FIG. 12 is a drawing showing an example of the configuration of a second activation control circuit according to a second embodiment of the present invention.

[0030] FIG. 13 is a diagram illustrating a case where an X-ray detector according to a second embodiment of the present invention is driven in a 2*1 binning mode.

[0031] FIG. 14 is a diagram illustrating a case where an X-ray detector according to a second embodiment of the present invention is driven in a 2*2 binning mode.

[0032] FIG. 15 is a diagram illustrating a case where an X-ray detector according to a second embodiment of the present invention is driven in a 2*4 binning mode.

[0033] FIG. 16 is a diagram illustrating a case where an X-ray detector according to a second embodiment of the present invention is driven in a 4*4 binning mode.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0035] <First Embodiment>

[0036] Fig. 1 is a block diagram schematically illustrating the configuration of an X-ray detector according to a first embodiment of the present invention. Fig. 2 is a circuit diagram schematically illustrating an example of the configuration of pixels of an X-ray detector according to a first embodiment of the present invention.

[0037] Referring to FIGS. 1 and 2, an X-ray detector (10) according to a first embodiment of the present invention may include a pixel array panel (or sensor panel) (100) and a driving circuit (or panel driving circuit).

[0038] Here, the driving circuit may include a scan circuit (or row decoder) (120), a readout circuit (or memory) (130), and an output control circuit (or column decoder) (140).

[0039] Moreover, the driving circuit may include an activation control circuit (210, 220) that controls activation / deactivation of pixels (P). At this time, the activation control circuit (210, 220) may include, for example, a first activation control circuit (210) that controls activation of pixels (P) arranged along a vertical direction (or a column direction or a first direction), and a second activation control circuit (220) that controls activation of pixels (P) arranged along a horizontal direction (or a row direction or a second direction).

[0040] Each pixel (P) can have an activated / deactivated state according to the control signal (or activation control signal) output from the first and second activation control circuits (210, 220). By these first and second activation control circuits (210, 220), the pixel array panel (100) can be driven in a normal mode or a binning mode (more specifically, a binning mode of a skipping method). The configuration and operation of these activation control circuits (210, 220) will be described in more detail below.

[0041] Meanwhile, although not specifically illustrated, the X-ray detector (10) may include a phosphor arranged on the light-receiving surface of the pixel array panel (100). The phosphor converts the incident X-ray into visible light, and the visible light is provided to the pixel array panel (100), and an avalanche photodiode (or avalanche light-receiving element), for example, a single-photon avalanche diode (SPAD), provided in the pixel (P) can detect a photon of the visible light and generate an electrical signal.

[0042] The pixel array panel (100) may include an active area, which is a region that actually receives and detects X-rays, and a non-active area located outside the active area.

[0043] In the active area, a pixel array composed of a plurality of pixels (P) is arranged, and these plurality of pixels (P) can be arranged in a matrix form along a plurality of row lines and a plurality of column lines.

[0044] Although not specifically illustrated, a pixel array panel (100) may be provided with a plurality of scan lines (or gate lines) extending along a plurality of row lines and a plurality of signal transmission lines (or data lines) extending along a plurality of column lines. These scan lines and signal transmission lines may be connected to corresponding pixels (P).

[0045] The scan circuit (120) can control the pixel array panel (100) in units of rows and lines. In this regard, the scan circuit (120) sequentially outputs scan signals to scan lines in units of rows and lines, and in response to this, the pixels (P) of the corresponding rows and lines can be selected.

[0046] The readout circuit (130) is connected to a signal transmission line (or data line) extending along each column line, and can receive and store a pixel signal (or data signal) output from a pixel (P) of a selected row line through a scan line.

[0047] The output control circuit (140) can control the output operation of the pixel signal stored in the readout circuit (130).

[0048] A pixel (P) can detect visible light photons generated from a phosphor using a single-photon avalanche diode (SPAD), generate a corresponding pulse signal, count the number of photons, and output the counted value.

[0049] With reference to FIG. 2, with respect to the configuration of the pixels (P), for example, each pixel (P) may include a single-photon avalanche diode (SPAD) and a transistor connected thereto, for example, a recharge transistor (Tre).

[0050] In addition, the pixel (P) may include a pulse generation circuit (or pulse shaper) (PSC) connected to a node (N) between a single-photon avalanche diode (SPAD) and a recharge transistor (Tre). In addition, the pixel (P) may include a counter circuit (CC) that counts the number of pulse signals generated from the pulse generation circuit (PSC). At this time, the counter circuit (CC) may count the number of pulse signals having a certain size or greater.

[0051] One electrode (or first electrode) of a single-photon avalanche diode (SPAD), for example, an anode, can be connected to a drain electrode (or source electrode) of a recharge transistor (Tre). And, the other electrode (or second electrode) of the single-photon avalanche diode (SPAD), for example, a cathode, can receive a bias voltage (or reverse voltage) (Vb), which is a driving voltage.

[0052] The recharge transistor (Tre) can have its source electrode (or drain electrode) applied with a ground voltage (or a low-potential voltage). Meanwhile, the gate electrode of the recharge transistor (Tre) can be connected to, for example, the output terminal of a pulse generation circuit (PSC). Such a recharge transistor (Tre) can be composed of, for example, an N-type transistor, but is not limited thereto.

[0053] Here, the bias voltage (Vb) is a voltage for generating avalanche amplification by operating the single-photon avalanche diode (SPAD) in Geiger mode, and it is preferable to have a voltage greater than the breakdown (or breakdown) voltage (Vbd). For example, the bias voltage (Vb) can be expressed as the sum of the breakdown voltage (Vbd) and the access voltage (Vex), which is greater than the minimum level value for operating the single-photon avalanche diode (SPAD) in Geiger mode, i.e., (Vb = Vbd + Vex).

[0054] In this way, when a bias voltage (Vb) higher than the breakdown voltage (Vbd) is applied to operate the single-photon avalanche diode (SPAD), i.e., in an activated state, the single-photon avalanche diode (SPAD) generates an electrical signal (or diode signal or detection signal) in response to an incident photon.

[0055] The electrical signal generated in this way can be output through the output terminal, which is the node (N) between the single-photon avalanche diode (SPAD) and the recharge transistor (Tre), and input to the pulse generation circuit (PSC).

[0056] A pulse generation circuit (PSC) converts an input electrical signal into a digital (or square wave) pulse signal and outputs it. The pulse generation circuit (PSC) may be composed of, for example, a plurality of inverters (more specifically, an even number of inverters), in which case the signal conversion operation may be delayed for a certain period of time (for example, several nanoseconds to several microseconds).

[0057] The pulse signal output in this manner can be provided to a counter circuit (CC). The counter circuit (CC) counts the number of pulse signals generated from the pulse generation circuit (PSC), and the counted value can be output as a pixel signal.

[0058] Meanwhile, a pulse signal output from the output terminal of the pulse generation circuit (PSC) can be applied to the recharge transistor (Tre). Accordingly, the recharge transistor (Tre) is turned on, and the single-photon avalanche diode (SPAD) is recharged, so that the bias voltage (Vb) is applied again to both terminals of the single-photon avalanche diode (SPAD), and it can be activated to detect a photon.

[0059] Moreover, in the present embodiment, an activation circuit (ENC) that controls activation / deactivation of a pixel (P), more specifically, activation / deactivation of a single-photon avalanche diode (SPAD) of the pixel (P), may be provided in the pixel (P).

[0060] Such an activation circuit (ENC) may include an activation transistor (Ten) and a gate control circuit (LGC).

[0061] Here, the source electrode (or drain electrode) of the activation transistor (Ten) can be connected to the node (N) between the recharge transistor (Tre) and the single-photon avalanche diode (SPAD). In addition, the drain electrode (or source electrode) of the activation transistor (Ten) can receive a deactivation voltage (Vna). In addition, the gate electrode of the activation transistor (Ten) can be connected to the output terminal of the gate control circuit (LGC). This activation transistor (Ten) can be composed of, for example, an N-type transistor, but is not limited thereto.

[0062] Here, the deactivation voltage (Vna) may be a voltage greater than the access voltage (Vex) of the bias voltage (Vb). And, the deactivation voltage (Vna) may be a voltage less than the breakdown voltage (Vbd). That is, the difference between the bias voltage (Vb) and the deactivation voltage (Vna) may be less than the breakdown voltage (Vbd).

[0063] When the activation transistor (Ten) is turned on, a deactivation voltage (Vna) can be applied to the node (N) between the recharge transistor (Tre) and the single-photon avalanche diode (SPAD). In this case, the diode voltage applied to the single-photon avalanche diode (SPAD) becomes (Vb - Vna = Vbd + Vex - Vna; Vna > Vex), so that a voltage smaller than the breakdown voltage (Vbd) is applied to both terminals of the single-photon avalanche diode (SPAD). As a result, the single-photon avalanche diode (SPAD) is in a deactivated state, so that the pixel (P) consumes practically no power.

[0064] Meanwhile, when the activation transistor (Ten) is turned off, the deactivation voltage (Vna) is not applied to the node (N) between the recharge transistor (Tre) and the single-photon avalanche diode (SPAD), so the single-photon avalanche diode (SPAD) remains activated and can output an electrical signal corresponding to the input photon.

[0065] The gate control circuit (LGC) can output a switching signal (or control signal or activation control signal) that controls the on / off of the activation transistor (Ten). In other words, the gate control circuit (LGC) can generate a switching signal that controls the activation / deactivation of the pixel (P).

[0066] This gate control circuit (LGC) can receive a first control signal (CS1) output from a first activation control circuit (210) and a second control signal (CS2) output from a second activation control circuit (220) at the corresponding input terminal and use them to generate a switching signal.

[0067] In this regard, for example, the gate control circuit (LGC) may be configured with a NAND gate. In this case, the logic value of the switching signal may be determined according to the logic values ​​of the first control signal (CS1) and the second control signal (CS2). In this case, when both the first control signal (CS1) and the second control signal (CS2) are "1", the switching signal may be "0", and when at least one of the first control signal and the second control signal is "0", the switching signal may be "1".

[0068] Accordingly, as illustrated in FIG. 3, when at least one of the first and second control signals (CS1, CS2) is “0”, the activation transistor (Ten) is turned on, and in this case, a deactivation voltage (Vna) is applied to the single-photon avalanche diode (SPAD), so that the pixel (P) can be in an inactivated state.

[0069] And, as shown in Fig. 4, when both the first and second control signals (CS1, CS2) are “1”, the activation transistor (Ten) is turned off, and in this case, the deactivation voltage (Vna) is not applied to the single-photon avalanche diode (SPAD), so the pixel (P) can be in an activated state.

[0070] As above, the activation circuit (ENC) can implement the activation / deactivation state of the pixel (P) according to the input first and second control signals (CS1, CS2).

[0071] The first and second activation control circuits (210, 220) that provide the first and second control signals (CS1, CS2) that control the activation circuit (ENC) will be examined with reference to FIGS. 5 to 7.

[0072] FIG. 5 is a drawing showing a pixel array panel and first and second activation control circuits according to a first embodiment of the present invention, FIG. 6 is a drawing showing an example of the configuration of a first activation control circuit according to a first embodiment of the present invention, and FIG. 7 is a drawing showing an example of the configuration of a second activation control circuit according to a first embodiment of the present invention.

[0073] In Fig. 5, for convenience of explanation, a case is illustrated where pixels (P) are arranged in an 8*8 matrix in a pixel array panel (100), and the order of the row lines increases from bottom to top and the order of the column lines increases from left to right.

[0074] Meanwhile, in this embodiment, up to N*N (N is an even number greater than or equal to 2) binning can be performed in binning mode, and for the convenience of explanation, an example in which up to 4*4 binning is performed is taken. In other words, in this embodiment, for the convenience of explanation, an example in which a group area (or segmented area) (GA) consisting of 4*4 pixels (P) capable of implementing maximum binning is set is taken. In this case, 4*4 binning mode and 2*2 binning mode can be performed.

[0075] The first activation control circuit (210) can output a corresponding first control signal (CS1) to a plurality of first control lines (CL1) arranged in each of a plurality of row lines of the pixel array panel (100). Accordingly, the corresponding first control signal (CS1) can be commonly provided to the pixels (P) arranged in each row line.

[0076] The second activation control circuit (220) can output a corresponding second control signal (CS2) to a plurality of second control lines (CL2) arranged in each of a plurality of column lines of the pixel array panel (100). Accordingly, the corresponding second control signal (CS2) can be commonly provided to the pixels (P) arranged in each column line.

[0077] The first activation control circuit (210) may be provided with a plurality of first control circuits (211) that output a corresponding first control signal (CS1) to each of a plurality of first control lines (CL1). Here, the plurality of first control circuits (211) may be divided into a plurality of first circuit groups (CG1) corresponding to each of a plurality of group areas (GA). In other words, the first activation control circuit (210) may include a plurality of first circuit groups (CG1) corresponding to each of a plurality of group areas (GA) arranged along the column line direction, and each first circuit group (CG1) may be provided with four first control circuits (211) corresponding to four row lines included in the corresponding group area (GA). For example, the first circuit group (CG1) corresponding to the group area (GA) located in the first to fourth row lines may include the first to fourth first control circuits (211[1] to 211[4]).

[0078] Meanwhile, the first control circuit (211) may be configured as, for example, an inverter, but is not limited thereto. In the case where the first control circuit (211) is configured as an inverter, the logic value of the input signal may be inverted and output as the first control signal (CG1).

[0079] The second activation control circuit (220) may be provided with a plurality of second control circuits (221) that output a corresponding second control signal (CS2) to each of a plurality of second control lines (CL2). Here, the plurality of second control circuits (221) may be divided into a plurality of second circuit groups (CG2) corresponding to each of a plurality of group areas (GA). In other words, the second activation control circuit (220) may include a plurality of second circuit groups (CG2) corresponding to each of a plurality of group areas (GA) arranged along the row line direction, and each second circuit group (CG2) may be provided with four second control circuits (221) corresponding to each of four column lines included in the corresponding group area (GA). For example, the second circuit group (CG2) corresponding to the group area (GA) located in the first to fourth column lines may include the first to fourth second control circuits (221[1] to 221[4]).

[0080] Meanwhile, the second control circuit (221) may be configured as, for example, an inverter, but is not limited thereto. In the case where the second control circuit (221) is configured as an inverter, the logic value of the input signal may be inverted and output as a second control signal (CG2).

[0081] For the first and second activation control circuits (210, 220) configured as above, the basic signal (or default signal or fixed signal) (Vs) and the binning setting signal (BIN2, BIN4) can be commonly applied to each of the first circuit group (CG1) and the second circuit group (CG2).

[0082] For example, for the first circuit group (CG1), one basic signal (Vs) and two binning setting signals (BIN2, BIN4), the first and second binning setting signals (BIN2, BIN4) may be provided, and for the second circuit group (CG2), one basic signal (Vs) and two binning setting signals (BIN2, BIN4), the first and second binning setting signals (BIN2, BIN4) may be provided.

[0083] In this case, the basic signal (Vs) may be applied to the first control circuit (211) of the first circuit group (CG1) and the second control circuit (221) of the second circuit group (CG2), which correspond to the pixel (P) designated to have an active state in both the 2*2 binning and the 4*4 binning of the binning mode in each group area (GA), for example. In the present embodiment, for convenience of explanation, it is taken as an example that the basic signal (Vs) is applied to the first and second control circuits (211, 221) connected to the pixel (P) located in the first row line and the first column line based on each binning area (BA).

[0084] In addition, the first binning setting signal (BIN2) is a signal for setting 2*2 binning, and can be applied to the first control circuit (211) of the first circuit group (CG1) and the second control circuit (221) of the second circuit group (CG2) corresponding to the pixel (P) designated to have an inactive state in both 2*2 binning and 4*4 binning in each group area (GA), for example. In the present embodiment, for convenience of explanation, it is taken as an example that the first binning setting signal (BIN2) is applied to the first and second control circuits (211, 221) connected to the pixel (P) located in the 2nd and 4th row lines and the 2nd and 4th column lines based on each group area (GA).

[0085] In addition, the second binning setting signal (BIN4) is a signal for setting 4*4 binning, and can be applied to the first control circuit (211) of the first circuit group (CG1) and the second control circuit (221) of the second circuit group (CG2) corresponding to a pixel (P) designated to have an active state in 2*2 binning and a deactivated state in 4*4 binning in each group area (GA), for example. In the present embodiment, for convenience of explanation, it is taken as an example that the second binning setting signal (BIN4) is applied to the first and second control circuits (211, 221) connected to a pixel (P) located at the third row line and the third column line based on each group area (GA).

[0086] In the above case, the basic signal (Vs) can be a low level signal whose logic value is "0", for example, in normal mode and binning mode. In addition, the first binning setting signal (BIN2) can have a low level whose logic value is "0", the same as the basic signal (Vs), in normal mode, and a high level whose logic value is "1", the opposite of the basic signal (Vs), in 2*2 binning and 4*4 binning. In addition, the second binning setting signal (BIN4) can have a low level whose logic value is "0", the same as the basic signal (Vs), in normal mode, and a low level whose logic value is "0", the same as the basic signal (Vs), in 2*2 binning, and a high level whose logic value is "1", the opposite of the basic signal (Vs), in 4*4 binning.

[0087] Accordingly, in normal mode, the low-level basic signal (Vs) and the low-level first and second binning setting signals (BIN2, BIN4) are applied to all of the first to fourth first control circuits (211) of the first circuit group (CG1), so that the first to fourth first control circuits (211) of the first circuit group (CG1) can all output the high-level first control signal (CS1). Similarly, the low-level basic signal (Vs) and the low-level first and second binning setting signals (BIN2, BIN4) are applied to all of the first to fourth second control circuits (221) of the second circuit group (CG2), so that the first to fourth second control circuits (221) of the second circuit group (CG2) can all output the high-level second control signal (CS2). Accordingly, since the first and second control signals (CS1, CS2) of high level are applied to all 4*4 pixels (P) of each group area (GA), all 4*4 pixels (P) are activated and normal mode can be executed.

[0088] Next, referring to FIG. 8, in 2*2 binning of the binning mode, a low-level basic signal (Vs) may be applied to the first first control circuit (211) of the first circuit group (CG1), a high-level first binning setting signal (BIN2) may be applied to the second and fourth first control circuits (211), and a low-level second binning setting signal (BIN4) may be applied to the third first control circuit (211). Likewise, a low-level basic signal (Vs) may be applied to the first second control circuit (221) of the second circuit group (CG2), a high-level first binning setting signal (BIN2) may be applied to the second and fourth second control circuits (221), and a low-level second binning setting signal (BIN4) may be applied to the third second control circuit (221). Accordingly, within the group area (GA) of each 4*4 matrix, low-level first and second control signals (CS1, CS2) may be applied to pixels (P) located at positions (1,1), (1,3), (3,1), and (3,3) of the matrix, and the first and second control signals (CS1, CS2) applied to pixels (P) located at other positions of the matrix may have both a high level and a low level, or a low level and a high level, or both a high level. Due to this, the pixels (P) located at the positions (1,1), (1,3), (3,1), (3,3) of the matrix in each group area (GA) are activated, and the remaining pixels (P) are deactivated, so that a 2*2 binning mode can be executed.

[0089] Next, referring to FIG. 9, in 4*4 binning of the binning mode, a low-level basic signal (Vs) may be applied to the first first control circuit (211) of the first circuit group (CG1), a high-level first binning setting signal (BIN2) may be applied to the second and fourth first control circuits (211), and a high-level second binning setting signal (BIN4) may be applied to the third first control circuit (211). Likewise, a low-level basic signal (Vs) may be applied to the first second control circuit (221) of the second circuit group (CG2), a high-level first binning setting signal (BIN2) may be applied to the second and fourth second control circuits (221), and a high-level second binning setting signal (BIN4) may be applied to the third second control circuit (221). Accordingly, within the group area (GA) of each 4*4 matrix, the low-level first and second control signals (CS1, CS2) may be applied to the pixel (P) located at the matrix (1,1) position, and the first and second control signals (CS1, CS2) applied to the pixels (P) located at other positions of the matrix may have both a high level and a low level, or a low level and a high level, or both a high level. Due to this, the pixel (P) located at the matrix (1,1) position in each group area (GA) becomes active and the remaining pixels (P) become inactive, so that a 4*4 binning mode can be executed.

[0090] [Table 1] below shows the normal mode and binning mode implemented according to the value of the binning setting signal in this embodiment.

[0091] BIN2BIN4 Driving Mode 00 Normal Mode (1*1) 10 Binning Mode (2*2) 11 Binning Mode (4*4)

[0092] Meanwhile, in the above-described embodiment, the case where the gate control circuit (LGC) is configured as a NAND gate and the activation transistor (Ten) is of N type was taken as an example. As another example, the gate control circuit (LGC) may be configured as an AND gate and the activation transistor (Ten) may be configured as a P type. In addition, in the above-described embodiment, for the convenience of explanation, the position of the lower left in relation to the position of the pixel (P) within each group area (GA) is referred to as (1,1), but alternatively, the position of (1,1) in each group area (GA) may be set to the upper left, lower right, or upper right.

[0093] In addition, in the above-described embodiment, the case of the maximum 4*4 binning mode was described as an example of the maximum N*N binning mode. Of course, in the present embodiment, by adding a binning setting signal, the maximum binning mode can have a size such as 8*8, 16*16, etc., which is a multiple of 4*4. For example, in the case where the maximum 8*8 binning mode can be implemented, the group area is composed of an 8*8 matrix of pixels, and in addition to the first and second binning setting signals (BIN2, BIN3) described above, a third binning setting signal capable of setting 8*8 binning is added, and the third binning setting signal can be configured to be provided to the first and second control circuits (211, 221) corresponding to the fifth row line and the fifth column line. And, in case that a maximum 16*16 binning mode can be implemented, the group area is composed of pixels of a 16*16 matrix, and in addition to the 1st, 2nd, and 3rd binning setting signals described above, a 4th binning setting signal capable of setting 16*16 binning is added, and the 4th binning setting signal can be configured to be provided to the 1st and 2nd control circuits (211, 221) corresponding to the 9th row line and the 9th column line.

[0094] As described above, according to the present embodiment, a voltage higher than the access voltage can be applied to a single-photon avalanche diode (SPAD) of a pixel for which a pixel signal is not required in the binning mode. Accordingly, the single-photon avalanche diode (SPAD) is not operated in the Geiger mode and is in an inactive state, so that the pixel does not consume actual power. Accordingly, the power consumption of the X-ray detector can be reduced, and thus, performance degradation such as heat generation and voltage drop of the detector can be improved.

[0095] <Second Embodiment>

[0096] FIG. 10 is a schematic diagram illustrating an X-ray detector according to a second embodiment of the present invention, FIG. 11 is a diagram illustrating an example of the configuration of a first activation control circuit according to a second embodiment of the present invention, and FIG. 12 is a diagram illustrating an example of the configuration of a second activation control circuit according to a second embodiment of the present invention.

[0097] In this embodiment, a detailed description of the configuration identical to or similar to the first embodiment described above may be omitted. Furthermore, in Fig. 10, for convenience of explanation, the first and second activation control circuits among the driving circuits are illustrated.

[0098] The X-ray detector (10) of the second embodiment can be configured, unlike the first embodiment, so that the first activation control circuit (210) and the second activation control circuit (220) do not receive a common binning setting signal but receive individual binning setting signals.

[0099] In this regard, the first activation control circuit (210) may be provided with, for example, a first-first binning signal (BIN2-1) and a second-first binning signal (BIN4-1) for setting 2*1 binning and 4*1 binning as binning setting signals for setting vertical binning together with a reference signal (Vs) in units of the first circuit group (CG1). In this regard, for example, the first first control circuit (211[1]) of the first circuit group (CG1) may be supplied with the reference signal (Vs), the second and fourth first control circuits (211[2], 211[4]) may be supplied with the first-first binning signal (BIN2-1), and the third first control circuit (211[3]) may be supplied with the second-first binning signal (BIN4-1).

[0100] And, the second activation control circuit (220) can be provided with, for example, a first-second binning signal (BIN2-2) and a second-second binning signal (BIN4-2) for setting 1*2 binning and 1*4 binning as binning setting signals for setting horizontal binning together with a reference signal (Vs) in units of the second circuit group (CG2). In this regard, for example, the first second control circuit (221[1]) of the second circuit group (CG2) can be supplied with the reference signal (Vs), the second and fourth second control circuits (221[2], 221[4]) can be supplied with the first-second binning signal (BIN2-2), and the third second control circuit (221[3]) can be supplied with the second-second binning signal (BIN4-2).

[0101] As described above, the first activation control circuit (210) and the second activation control circuit (220) are configured to receive signals for individually setting binning along the vertical and horizontal directions, so that by combining the first control signal (CS1) output from the first activation control circuit (210) and the second control signal (CS2) output from the second activation control circuit (220), not only 2*2 binning and 4*4 binning, but also 1*2 binning, 1*4 binning, 2*1 binning, 4*1 binning, 2*4 binning, and 4*2 binning can be implemented.

[0102] In this regard, for example, when implementing 2*1 binning, referring to FIG. 13, a low-level basic signal (Vs) may be applied to the first first control circuit (211) of the first circuit group (CG1), a high-level first-1 binning setting signal (BIN2-1) may be applied to the second and fourth first control circuits (211), and a low-level second-1 binning setting signal (BIN4-1) may be applied to the third first control circuit (211). And, a low-level basic signal (Vs) may be applied to the first second control circuit (221) of the second circuit group (CG2), a low-level first-second binning setting signal (BIN2-2) may be applied to the second and fourth second control circuits (221), and a low-level second-second binning setting signal (BIN4-2) may be applied to the third second control circuit (221). Accordingly, high-level first and second control signals (CS1, CS2) may be applied to pixels (P) placed on the first and third row lines in each column line within the group area (GA) of each 4*4 matrix, and a low-level first control signal (CS1) and a high-level second control signal (CS2) may be applied to pixels (P) placed on the second and fourth row lines. Due to this, the pixels (P) placed on the 1st and 3rd row lines in each column line of each binning area (BA) become active, and the pixels (P) placed on the 2nd and 4th row lines become inactive, so that a 2*1 binning mode can be executed.

[0103] For 1*2 binning mode and other types of binning modes, the corresponding binning modes can be executed by adjusting the 1-1, 1-2, 2-1, 2-2 binning setting signals (BIN2-1, BIN2-2, BIN4-1, BIN4-2).

[0104] In this regard, when implementing 2*2 binning, referring to FIG. 14, a low-level basic signal (Vs) may be applied to the first first control circuit (211) of the first circuit group (CG1), a high-level first-1 binning setting signal (BIN2-1) may be applied to the second and fourth first control circuits (211), and a low-level second-1 binning setting signal (BIN4-1) may be applied to the third first control circuit (211). And, a low-level basic signal (Vs) may be applied to the first second control circuit (221) of the second circuit group (CG2), a high-level 1-2 binning setting signal (BIN2-2) may be applied to the second and fourth second control circuits (221), and a low-level 2-2 binning setting signal (BIN4-2) may be applied to the third second control circuit (221). Accordingly, within the group area (GA) of each 4*4 matrix, pixels (P) located at the intersection of the 1st and 3rd row lines and the 1st and 3rd column lines become activated, and pixels (P) located at the 2nd and 4th row lines and pixels (P) located at the 2nd and 4th column lines become inactivated, so that a 2*2 binning mode can be executed.

[0105] In the case of implementing 2*4 binning, referring to FIG. 15, a low-level basic signal (Vs) may be applied to the first first control circuit (211) of the first circuit group (CG1), a high-level first-1 binning setting signal (BIN2-1) may be applied to the second and fourth first control circuits (211), and a low-level second-1 binning setting signal (BIN4-1) may be applied to the third first control circuit (211). And, a low-level basic signal (Vs) may be applied to the first second control circuit (221) of the second circuit group (CG2), a high-level first-second binning setting signal (BIN2-2) may be applied to the second and fourth second control circuits (221), and a high-level second-second binning setting signal (BIN4-2) may be applied to the third second control circuit (221). Accordingly, within the group area (GA) of each 4*4 matrix, the pixels (P) located at the intersection of the 1st and 3rd row lines and the 1st column line become activated, and the pixels (P) located at the 2nd and 4th row lines and the pixels (P) located at the 2nd to 4th column lines become inactivated, so that the 2*4 binning mode can be executed.

[0106] When implementing 4*4 binning, referring to FIG. 16, a low-level basic signal (Vs) may be applied to the first first control circuit (211) of the first circuit group (CG1), a high-level first-1 binning setting signal (BIN2-1) may be applied to the second and fourth first control circuits (211), and a high-level second-1 binning setting signal (BIN4-1) may be applied to the third first control circuit (211). And, a low-level basic signal (Vs) may be applied to the first second control circuit (221) of the second circuit group (CG2), a high-level first-second binning setting signal (BIN2-2) may be applied to the second and fourth second control circuits (221), and a high-level second-second binning setting signal (BIN4-2) may be applied to the third second control circuit (221). Accordingly, within the group area (GA) of each 4*4 matrix, the pixel (P) located at the intersection of the 1st row line and the 1st column line becomes activated, and the pixels (P) located at the 2nd to 4th row lines and the pixels (P) located at the 2nd to 4th column lines become inactivated, so that the 4*4 binning mode can be executed.

[0107] [Table 2] below shows the normal mode and binning mode implemented according to the value of the binning setting signal in this embodiment.

[0108] BIN2-1BIN4-1BIN2-2BIN4-2Operating mode0000Normal mode(1*1)1000Binning mode(2*1)1100Binning mode(4*1)0010Binning mode(1*2)1010Binning mode(2*2)1110Binning mode(4*2)0011Binning mode(1*4)1011Binning mode(2*4)1111Binning mode(4*4)

[0109] As described above, in this embodiment, since a binning setting signal is used to individually set vertical binning and horizontal binning, more diverse binning modes can be implemented compared to the first embodiment that shares the binning setting signal. As described above, according to the embodiments of the present invention, a voltage higher than the access voltage can be applied to a single-photon avalanche diode of a pixel that does not require a pixel signal in the binning mode. Accordingly, the single-photon avalanche diode is not operated in Geiger mode and is in an inactive state, so that the pixel does not consume actual power.

[0110] Therefore, the power consumption of an X-ray detector equipped with a single-photon avalanche diode can be reduced, thereby improving performance degradation such as heat generation and voltage drop of the detector.

[0111] The above-described embodiments of the present invention are merely examples of the present invention, and may be freely modified within the scope encompassed by the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention within the scope of the appended claims and their equivalents.

Claims

1. A pixel array panel comprising a plurality of pixels arranged in a matrix form along a plurality of row lines and a plurality of column lines; An avalanche diode provided within the above pixel and having a bias voltage applied to the cathode; A recharge transistor connected to the anode of the above avalanche diode; An activation circuit including an activation transistor having a source electrode connected between the anode of the avalanche diode and the recharge transistor and a drain electrode to which a deactivation voltage is applied, and a gate control circuit connected to a gate electrode of the activation transistor; An activation control circuit that outputs a control signal to the above gate control circuit Including, The above bias voltage is the sum of the breakdown voltage and the access voltage, An X-ray detector wherein the difference between the bias voltage and the deactivation voltage is less than the breakdown voltage.

2. In paragraph 1, The above activation control circuit, A first activation control circuit including a first control circuit that outputs a first control signal to the gate control circuit; An X-ray detector comprising a second activation control circuit including a second control circuit that outputs a second control signal to the gate control circuit.

3. In paragraph 2, In the above pixel array panel, a plurality of group areas arranged in a matrix form are defined, and the group areas are composed of the pixels arranged in an N*N matrix. The first activation control circuit includes a first circuit group composed of N first control circuits corresponding to each pixel arranged in N rows and lines of the group area, The second activation control circuit includes a second circuit group composed of N second control circuits corresponding to each pixel arranged in the N column lines of the group area. X-ray detector.

4. In paragraph 3, The first control circuit of the first circuit group corresponding to the pixel of the first row line within the above group area receives a basic signal, The first control circuit of the first circuit group corresponding to the pixel of the second row line within the above group area receives the first binning setting signal, The second control circuit of the second circuit group corresponding to the pixel of the first column line within the above group area receives the basic signal, The second control circuit of the second circuit group corresponding to the pixel of the second column line within the above group area receives the first binning setting signal. X-ray detector.

5. In paragraph 4, The first control circuit of the first circuit group corresponding to the pixel of the third row line within the above group area receives the second binning setting signal, The first control circuit of the first circuit group corresponding to the pixel of the fourth row line within the above group area receives the first binning setting signal, The second control circuit of the second circuit group corresponding to the pixel of the third column line within the above group area receives the second binning setting signal, The second control circuit of the second circuit group corresponding to the pixel of the fourth column line within the above group area receives the first binning setting signal. X-ray detector.

6. In paragraph 4 or paragraph 5, The above basic signal has a constant logic value in normal mode and binning mode, The above first binning setting signal has the same logic value as the basic signal in the normal mode, and has the opposite logic value to the basic signal in the binning mode in which the corresponding pixel is deactivated among the binning modes. The second binning setting signal has the same logic value as the basic signal in the normal mode, has the same logic value as the basic signal in the binning mode in which the corresponding pixel is activated among the binning modes, and has the opposite logic value as the basic signal in the binning mode in which the corresponding pixel is deactivated among the binning modes. X-ray detector.

7. In paragraph 3, The first control circuit of the first circuit group corresponding to the pixel of the first row line within the above group area receives a basic signal, The first control circuit of the first circuit group corresponding to the pixel of the second row line within the above group area receives the 1-1 binning setting signal, The second control circuit of the second circuit group corresponding to the pixel of the first column line within the above group area receives the basic signal, The second control circuit of the second circuit group corresponding to the pixel of the second column line within the above group area receives the 1st-2nd binning setting signal. X-ray detector.

8. In paragraph 7, The first control circuit of the first circuit group corresponding to the pixel of the third row line within the above group area receives the 2-1 binning setting signal, The first control circuit of the first circuit group corresponding to the pixel of the fourth row line within the above group area receives the first-1 binning setting signal, The second control circuit of the second circuit group corresponding to the pixel of the third column line within the above group area receives the second-2 binning setting signal, The second control circuit of the second circuit group corresponding to the pixel of the fourth column line within the above group area receives the first-second binning setting signal. X-ray detector.

9. In paragraph 7 or 8, The above basic signal has a constant logic value in normal mode and binning mode, The above 1-1 binning setting signal has the same logic value as the basic signal in the normal mode, and has the opposite logic value to the basic signal in the binning mode in which the pixels of the corresponding row line among the binning modes are deactivated. The above 2-1 binning setting signal has the same logic value as the basic signal in the normal mode, has the same logic value as the basic signal in the binning mode in which the pixels of the corresponding row line are activated in the binning mode, and has the opposite logic value as the basic signal in the binning mode in which the pixels of the corresponding row line are deactivated in the binning mode. The above 1-2 binning setting signal has the same logic value as the basic signal in the normal mode, and has the opposite logic value to the basic signal in the binning mode in which the pixels of the corresponding column line are deactivated among the binning modes. The above 2-2 binning setting signal has the same logic value as the basic signal in the normal mode, has the same logic value as the basic signal in the binning mode in which the pixels of the corresponding column line are activated in the binning mode, and has the opposite logic value as the basic signal in the binning mode in which the pixels of the corresponding column line are deactivated in the binning mode. X-ray detector.

10. In paragraph 1, The above avalanche diode is a single-photon avalanche diode, Further comprising a pulse generating circuit connected to the above node, The gate electrode of the above recharge transistor is connected to the output terminal of the pulse generation circuit. X-ray detector.

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