Display panel, display apparatus, and tiled display apparatus

Abstract

A display panel, a display apparatus, and a tiled display apparatus. The display panel comprises a substrate, a plurality of front electrodes, a plurality of back electrodes, a plurality of connection vias, and a plurality of connection traces. The plurality of front electrodes are arranged on one side of a first surface of the substrate, and the plurality of back electrodes are arranged on one side of a second surface of the substrate. The plurality of connection vias penetrate through the substrate, and at least one connection via among the plurality of connection vias comprises a first joint hole and a second joint hole. The size of a first end of the first joint hole away from the second joint hole is greater than or equal to the size of a second end of the first joint hole close to the second joint hole, and the size of a first end of the second joint hole away from the first joint hole is greater than or equal to the size of a second end of the second joint hole close to the first joint hole. Each connection trace among the plurality of connection traces passes through one connection via, and connects to one front electrode among the plurality of front electrodes and one back electrode among the plurality of back electrodes. The described display panel is used for displaying an image.

Description

Display panel, display device, and spliced ​​display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a spliced ​​display device. Background Art

[0002] Compared with traditional LEDs, Micro LED (Micro Light Emitting Diode) and Mini LED (Mini Light Emitting Diode Display) have smaller particles and smaller volume. They are widely used in display devices to form Micro LED / Mini LED display devices with higher display effects.

[0003] Summary of the Invention

[0004] In one aspect, a display panel is provided. The display panel includes a substrate, multiple front electrodes, multiple back electrodes, multiple connection vias, and multiple connection traces. The substrate includes a first surface and a second surface disposed opposite each other; the multiple front electrodes are disposed on one side of the first surface of the substrate; and the multiple back electrodes are disposed on the second surface of the substrate.

[0005] The multiple connecting vias pass through the substrate, and at least one of the multiple connecting vias includes a first stitching hole and a second stitching hole, the size of the first end of the first stitching hole away from the second stitching hole is greater than or equal to the size of the second end of the first stitching hole close to the second stitching hole, and the size of the first end of the second stitching hole away from the first stitching hole is greater than or equal to the size of the second end of the second stitching hole close to the first stitching hole.

[0006] Each of the plurality of connecting wires passes through a connecting via to connect a front electrode of the plurality of front electrodes and a back electrode of the plurality of back electrodes.

[0007] In some embodiments, the size of the first splicing hole gradually decreases along the direction from the first end to the second end of the first splicing hole; the size of the second splicing hole gradually decreases along the direction from the first end to the second end of the second splicing hole.

[0008] In some embodiments, the taper value of the first splicing hole and the second splicing hole is 0-0.26; the ratio of the size of the first end to the size of the second end of the first splicing hole is 0.9-1.1, and the ratio of the size of the first end to the size of the second end of the second splicing hole is 0.9-1.1.

[0009] In some embodiments, the thickness direction of the substrate is a first direction, and the ratio of the size of the first stitching hole in the first direction to the size of the second stitching hole in the first direction is in a range of 0.5 to 2.

[0010] In some embodiments, a difference between a size of the first end of the first stitching hole and a size of the first end of the second stitching hole ranges from 0 to 5 μm.

[0011] In some embodiments, the size of the first end of the first stitching hole and the first end of the second stitching hole is 10 μm to 300 μm.

[0012] In some embodiments, an orthographic projection of at least some of the plurality of connecting vias on the first surface of the substrate overlaps with an orthographic projection of the front electrode on the first surface of the substrate.

[0013] In some embodiments, the orthographic projections of at least some of the multiple front electrodes on the first surface do not overlap with the first connecting vias corresponding thereto; the extension direction of the front electrodes is the second direction, and the front electrodes are arranged on one side of the connecting vias corresponding thereto in the second direction.

[0014] In some embodiments, the light-emitting substrate further includes a plurality of light-emitting devices disposed on one side of the first surface; some of the plurality of light-emitting devices are disposed between two adjacent front electrodes.

[0015] In some embodiments, the substrate further includes multiple side surfaces, the multiple connecting vias and the multiple front electrodes are close to the first side surface of the substrate; the minimum distance between the partial light-emitting devices and the first side surface is less than the minimum distance between the multiple front electrodes and the first side surface.

[0016] In some embodiments, the display panel also includes a bridging structure, the bridging structure is arranged on one side of the second surface, and the multiple back electrodes are arranged on the surface of the bridging structure away from the substrate; the substrate also includes multiple side surfaces, the multiple connecting vias and the multiple front electrodes are close to the first side surface of the substrate; the bridging structure is located on the side of the multiple connecting vias away from the first side surface.

[0017] In some embodiments, the bridging structure includes multiple side surfaces, and the side surface facing the first side surface among the multiple side surfaces is the second side surface; the distance between the orthographic projection of the second side surface on the first surface and the opening edge of the multiple connecting vias is equal to and greater than or equal to 0.

[0018] In some embodiments, the bridging structure includes multiple side surfaces, and the side surface facing the first side surface among the multiple side surfaces is the second side surface; the second side surface of the bridging structure is provided with multiple grooves, and each groove in the multiple grooves corresponds to exposing one connecting via among the multiple connecting vias.

[0019] In some embodiments, the shapes of the groove include square, semicircle and trapezoid.

[0020] In some embodiments, the connecting trace includes a first sub-section, a second sub-section, and a third sub-section connected in sequence, the second sub-section is located in the connecting via, the first sub-section is located on one side of the first surface and is connected to the front electrode, and the third sub-section is located on one side of the second surface and is connected to the back electrode.

[0021] In some embodiments, the display panel further includes a first protective layer and a second protective layer, the first protective layer is located on one side of the first surface, the first protective layer covers the first sub-portion, and the second protective layer is located on one side of the second surface, the second protective layer covers the third sub-portion.

[0022] In some embodiments, the display panel further includes a plurality of light-emitting devices and an encapsulation layer, which are arranged on one side of the first surface; the encapsulation layer covers the plurality of light-emitting devices, the front electrode and the connecting wiring, and the distance between the boundary of the orthographic projection of the encapsulation layer on the first surface and the boundary of the first surface ranges from 0 to 10 μm.

[0023] In another aspect, a display device is provided, comprising the display panel according to any of the above embodiments and a driving circuit board, wherein the driving circuit board is electrically connected to the display panel and configured to drive the display panel to display an image.

[0024] In another aspect, a spliced ​​display device is provided, comprising a plurality of display devices according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1A is a structural diagram of a display panel according to some embodiments;

[0027] FIG1B is another structural diagram of a display panel according to some embodiments;

[0028] FIG1C is another structural diagram of a display panel according to some embodiments;

[0029] FIG1D is a cross-sectional view of the display panel along section line AA in FIG1A , FIG1B or FIG1C ;

[0030] FIG2A is another structural diagram of a display panel according to some embodiments;

[0031] FIG2B is another structural diagram of a display panel according to some embodiments;

[0032] FIG3 is a structural diagram of a connection via according to some embodiments;

[0033] FIG4 is a structural diagram of another connection via according to some embodiments;

[0034] FIG5A is a structural diagram of another connection via according to some embodiments;

[0035] FIG5B is a structural diagram of another connection via according to some embodiments;

[0036] FIG5C is a structural diagram of yet another connection via according to some embodiments;

[0037] FIG5D is a structural diagram of yet another connection via according to some embodiments;

[0038] FIG6A is another structural diagram of a display panel according to some embodiments;

[0039] FIG6B is another structural diagram of a display panel according to some embodiments;

[0040] FIG7 is another structural diagram of a display panel according to some embodiments;

[0041] FIG8 is another structural diagram of a display panel according to some embodiments;

[0042] FIG9 is another structural diagram of a display panel according to some embodiments;

[0043] FIG10 is another structural diagram of a display panel according to some embodiments;

[0044] FIG11 is another structural diagram of a display panel according to some embodiments;

[0045] FIG12 is another structural diagram of a display panel according to some embodiments;

[0046] FIG13 is another structural diagram of a display panel according to some embodiments;

[0047] FIG14A is a structural diagram of a display device according to some embodiments;

[0048] FIG14B is another structural diagram of a display device according to some embodiments;

[0049] FIG15 is a structural diagram of a spliced ​​display device according to some embodiments;

[0050] FIG. 16 is a flow chart of a process for preparing a display panel according to some embodiments. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0061] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0063] It should be noted that, for example, 81-8 appearing in the drawings of the present disclosure indicates that component 81 belongs to component 8, and other similar numbers appearing in the drawings also follow the above description.

[0064] In order to improve product reliability and reduce transportation and maintenance costs, a large-size display device can be assembled by splicing multiple small-size display devices.

[0065] In order to avoid the sense of fragmentation in the display caused by splicing, it is necessary to reduce the bezel size of a single small-sized display device and reduce the width of the splicing seam. The small-sized display device includes a display panel. For example, a connection via can be provided on the substrate to connect the traces located on the display surface side of the display panel to a circuit board (such as a flexible circuit board) provided on the non-display surface side of the display panel. Therefore, when multiple small-sized display devices are spliced ​​together to form a larger large-sized display device, the spacing between adjacent small-sized display devices can be smaller, thereby reducing the width of the splicing seam of the large-sized display device formed by splicing multiple small-sized display devices and improving the display quality.

[0066] Based on this, as shown in Figures 1A, 1B, 1C, and 1D, Figure 1D is a cross-sectional view of the display panel 10 along the AA section line in Figures 1A, 1B, or 1C. In some embodiments, the display panel 10 includes a substrate 1, multiple front electrodes 7, multiple back electrodes 3, multiple connection vias 5, and multiple connection traces 4. The substrate 1 includes a first surface 1a and a second surface 1b that are arranged opposite to each other; the multiple front electrodes 7 are arranged on one side of the first surface 1a of the substrate 1, and the multiple front electrodes 7 are electrically connected to at least a portion of the driving circuit layer (not shown in the figure); the multiple back electrodes 3 are arranged on one side of the second surface 1b of the substrate 1, and the multiple back electrodes 3 can serve as binding electrodes for connecting to a flexible circuit board (not shown in the figure).

[0067] Multiple connection vias 5 penetrate the substrate 1, and each connection trace 4 of the multiple connection traces 4 passes through a connection via 5, connecting one of the multiple front electrodes 3 and one of the multiple back electrodes 7. In other words, the connection trace 4 includes a first sub-portion 4a, a second sub-portion 4b, and a third sub-portion 4d connected in sequence, the second sub-portion 4b is located in the connection via 5, the first sub-portion 4a is located on the side of the first surface 1a and is connected to the front electrode 7, and the third sub-portion 4d is located on the side of the second surface 1b and is connected to the back electrode 3.

[0068] In some embodiments, as shown in Figures 1A, 1B, 1C, and 1D, the display panel 10 further includes a first protective layer 61 and a second protective layer 62. The first protective layer 61 is located on one side of the first surface 1a and covers the first sub-section 4a. The second protective layer 62 is located on one side of the second surface 1b and covers the third sub-section 4d. The first protective layer 61 and the second protective layer 62 provide all-round protection for the first sub-section 4a and the third sub-section 4d, preventing the first sub-section 4a and the third sub-section 4d from contact with air and / or water vapor, thereby preventing water-oxygen corrosion, which could affect the conductivity of the first sub-section 4a and the third sub-section 4d.

[0069] Exemplarily, the materials of the first protective layer 61 and the second protective layer 62 are insulating materials such as silicon oxide and resin.

[0070] In some embodiments, as shown in Figures 2A and 2B, one side of the first surface 1a of the substrate 1 is the front of the display panel 10, and a plurality of light-emitting devices 8 and an encapsulation layer 9 are provided on one side of the first surface 1a of the substrate 1. The light-emitting devices 8 include at least a first color light-emitting device 81, a second color light-emitting device 82, and a third color light-emitting device 83. The first color, the second color, and the third color are three primary colors (for example, red, green, and blue).

[0071] Exemplarily, the light emitting device 8 is a Micro LED (Micro Light Emitting Diode) or a Mini LED (Mini Light Emitting Diode).

[0072] As shown in Figures 1A to 1C, multiple light-emitting devices 8 are arranged in an array. Figures 1A to 1C illustrate three arrangements of light-emitting devices. The density of the multiple light-emitting devices is uniform, achieving a uniform display brightness. The display panel includes multiple pixel areas P, each of which is provided with multiple sub-pixels. Each sub-pixel includes at least one light-emitting device. For example, each pixel area P is provided with at least a first color light-emitting device 81, a second color light-emitting device 82, and a third color light-emitting device 83. Each pixel area P is also provided with a driver chip and / or pixel circuit. Under the control of the driver chip and / or pixel circuit, the multiple light-emitting devices 8 emit light, thereby causing the display panel 10 to display an image.

[0073] For example, as shown in FIG1C , three adjacent light-emitting devices among a plurality of light-emitting devices constitute a pixel, and each pixel area P is provided with a first color light-emitting device 81, a second color light-emitting device 82, and a third color light-emitting device 83. The first color light-emitting device 81, the second color light-emitting device 82, and the third color light-emitting device 83 can be arranged in a triangle, and the driving chip or the pixel circuit can be provided in an area within the pixel area P where the light-emitting device 8 is not provided, such as the upper right corner area of ​​each pixel area P in FIG1C .

[0074] In some embodiments, as shown in Figures 2A and 2B, an encapsulation layer 9 is disposed on one side of the first surface 1a of the substrate 1 and covers the plurality of light-emitting devices 8, the front electrode 7, and the first connecting trace 4a. The encapsulation layer 9 can protect the plurality of light-emitting devices 8, the front electrode 7, and the first connecting trace 4a.

[0075] Exemplarily, the encapsulation layer 9 may be made of an organic material and be black or dark green in color as a whole, which is beneficial for improving the display contrast of the display panel 10 .

[0076] In some embodiments, a side wiring scheme is used to connect the front and back sides of the substrate 1, that is, the side wiring is arranged on the first surface 1a, the side, and the second surface 1b of the substrate 1, and the two ends of the side wiring are respectively connected to the front electrode 7 and the back electrode 3. The connecting wiring 4 can be prepared by, for example, patterning after coating, or directly prepared by a printing process. A side protective layer is also provided on the side of the side wiring away from the substrate 1 to protect the connecting wiring 4 and prevent the line from being scratched. An encapsulation layer 9 is also provided on one side of the first surface 1a of the substrate 1. The encapsulation layer 9 covers a plurality of light-emitting devices 8 and the front electrode 7, thereby protecting the front devices.

[0077] In the side wiring scheme, since the connecting wiring 4 and the side protective layer are provided on the side of the substrate 1, a space is formed on the side of the substrate 1, which is not conducive to the narrowing of the frame of the display panel 10. As a result, the seam distance will increase when the display panel 10 is spliced, affecting the display effect. In addition, in the process of forming the encapsulation layer 9, the coil is usually first set on one side of the first surface 1a, and then the encapsulation layer 9 of appropriate size is formed by cutting. In order to prevent damage to the connecting wiring and the side protective layer when cutting the coil, a safety distance needs to be reserved to avoid damage to the line on the side of the substrate 1 when the display panel 10 is cut to form the encapsulation layer 9, thereby preventing the line from being short-circuited or corroded or oxidized due to the exposed surface. In this way, the boundary of the encapsulation layer needs to exceed the side protective layer, which will further increase the seam distance of the spliced ​​display panel. In addition, due to the difference in encapsulation between the front and side surfaces of the substrate 1, the spliced ​​display panel will have abnormal display in the seam area, such as bright seams and other defects.

[0078] Please continue to refer to Figures 2A and 2B. In some embodiments, since the second sub-portion 4b of the connecting trace 4 is arranged in the connecting via 5 opened on the substrate 1, there is no need to set a circuit on the side of the substrate 1 to realize the connection between the front electrode 7 and the back electrode 3. Therefore, there is no need to consider the safety distance when forming the packaging layer 9 by cutting. Therefore, when only considering the tolerance or process error, the distance d1 between the boundary of the positive projection of the packaging layer 9 on the plane where the first surface 1a of the substrate 1 is located and the boundary of the first surface 1a can be set to a range of 0 to 10 μm. It is understood that the boundary of the orthographic projection of the encapsulation layer 9 on the first surface 1a of the substrate 1 can be set within the first surface 1a and the distance between the boundary of the first surface 1a is less than or equal to 10μm; as shown in Figure 2B, the boundary of the orthographic projection of the encapsulation layer 9 on the plane where the first surface 1a of the substrate 1 is located can also coincide with the boundary of the first surface 1a, that is, the side of the encapsulation layer 9 is flush with the side of the substrate 1; the boundary of the orthographic projection of the encapsulation layer 9 on the plane where the first surface 1a of the substrate 1 is located can also be set outside the first surface 1a and the distance between the boundary of the first surface 1a is less than or equal to 10μm. This can narrow the display panel frame, reduce the size of the seam when the display panels are spliced ​​to form a spliced ​​panel, achieve a seamless splicing display effect, and improve the resolution of the spliced ​​panel.

[0079] To sum up, by setting a through hole in the substrate 1, that is, setting a connecting via 5 in the substrate 1, and realizing the connection between the first surface 1a and the second surface 1b of the substrate 1 by passing the connecting trace 4 through the connecting via 5, there is no need to set the connecting trace 4 and the side protective layer on the side of the substrate 1 to form a placeholder, which can narrow the frame of the display panel 10, improve the resolution of the display panel 10, and reduce the seam size of the spliced ​​display panel 10. In addition, there is no need to reserve a safety distance when encapsulating the encapsulation layer 9, and the distance between the side boundary of the encapsulation layer 9 and the side of the substrate is reduced. The seam size of the spliced ​​display panel can be further reduced, and the resolution of the spliced ​​display panel can be further improved.

[0080] As shown in Figure 1D, the connecting trace 4 passes through the connecting via 5 and is respectively connected to the front electrode 7 and the back electrode 3. The preparation process of the connecting trace 4 is, for example: forming a metal seed layer in the connecting via 5, for example, by a sputtering coating process or a vacuum evaporation process to form the metal seed layer, and then increasing the thickness of the metal seed layer through an electroplating process or a chemical plating process to form the connecting trace 4.

[0081] The preparation process of the above-mentioned connecting trace 4 is, for example, as follows: using a printing process, a conductive paste is set on the first surface 1a of the substrate 1, the connecting via 5 and the second surface 1b of the substrate 1, and then the conductive paste is cured by laser or heating to form the connecting trace 4. The above-mentioned conductive paste can be, for example, silver paste. The above-mentioned printing process can be, for example, screen printing, pad printing, transfer printing and printing. The printing process can be, for example, a three-dimensional printing process. The three-dimensional printing process uses a needle with a certain caliber and air pressure to squeeze the conductive paste in the needle tube to a specific position on the substrate. After the conductive paste is cured, a trace will be formed. Since the connecting trace 4 includes parts located on different surfaces, each connecting trace 4 needs to be formed separately by printing in batches. For example, it can be printed in three batches to form a first sub-portion 4a located on the first surface 1a, a second sub-portion 4b located in the connecting via 5, and a third sub-portion 4d located on the second surface 1b.

[0082] The preparation process of the above-mentioned multiple connecting vias 5 is, for example: using a certain concentration of hydrofluoric acid (HF) solution as an etching solution to etch the first surface 1a or the second surface 1b of the substrate 1 to obtain connecting vias 5' that penetrate the substrate 1. During the etching process, the contact area between the portion of the substrate 1 at the end of the first surface 1a or the second surface 1b for forming the connecting vias 5' and the etching solution is larger than that of other portions. Therefore, the etching amount of the portion at the end of the connecting via 5' will be greater than the etching amount of other portions, forming the connecting vias 5' as shown in Figure 3. The above-mentioned connecting vias 5' are conical in shape and have a large taper, that is, the size of the end at which the etching starts is much larger than the size of the other end.

[0083] The preparation process of the above-mentioned multiple connection vias 5 is, for example: using laser to ablate on the substrate 1 to obtain connection vias 5'. Due to the taper of the laser, the connection vias 5' shown in Figure 3 are formed by laser. The connection vias 5' are also conical in shape and have a large taper, that is, the size of one end where the etching starts is much larger than the size of the other end.

[0084] In a display panel 10 with a relatively small pixel pitch, the aperture of the connecting via 5 is also relatively small. When the connecting via 5 is the aforementioned connecting via 5' with a relatively large taper, i.e., the size of the connecting via 5' decreases from the first end 5'a to the second end 5'b, and the size difference between the first end 5'a and the second end 5'b is relatively large, resulting in the aperture of the second end 5'b of the connecting via 5' and the aperture of the portion near the second end 5'b being too small. On the one hand, burrs may exist within the connecting via 5, and the burrs may occupy the internal space of the connecting via 5. Since some portions of the connecting via 5' are relatively small, such as the second end 5'b of the connecting via 5', the burrs may occupy most or even all of the internal space near the second end 5'b of the connecting via 5'. When conductive material is injected into the connecting via 5' to form the connecting trace 4, the conductive material cannot be placed in the area where the burrs are present, potentially causing a short circuit. On the other hand, this may cause the width of the connecting trace 4 to vary significantly, leading to differences in resistance stability and the possibility of excessive local heating of the connecting trace 4.

[0085] Based on this, as shown in Figures 4 and 5A to 5D, some embodiments of the present disclosure provide a display panel 10. The display panel 10 includes a plurality of connection vias 5, at least one of which includes a first stitching hole 51 and a second stitching hole 52. The size of a first end 51a of the first stitching hole 51 away from the second stitching hole 52 is greater than or equal to the size of a second end 51b of the first stitching hole 51 close to the second stitching hole 52, and the size of a first end 52a of the second stitching hole 52 away from the first stitching hole 51 is greater than or equal to the size of a second end 52b of the second stitching hole 52 close to the first stitching hole 51.

[0086] It should be noted that the dimensions of the first end 51a and the second end 51b of the first stitching hole 51, and the dimensions of the first end 52a and the second end 52b of the second stitching hole 52 are all dimensions in a set direction parallel to the plane on which their end faces are located. For example, as shown in Figure 5A, the end face of the first end 51a of the first stitching hole 51 is parallel to the first surface 1a of the substrate 1, and the set direction is the second direction Y. The dimensions at other locations of the first stitching hole 51 and the dimensions at other locations of the second stitching hole 52 are all dimensions in a direction parallel to the first surface 1a. As shown in Figure 5A, the dimensions at a certain location of the first stitching hole 51 or the second stitching hole 52 mentioned in this application refer to the dimension L3 in a direction parallel to the first surface 1a.

[0087] It is understandable that the first stitching hole 51 and the second stitching hole 52 can be cylindrical holes or tapered holes. For example, as shown in FIG4 , when the first stitching hole 51 and the second stitching hole 52 are both cylindrical holes, the connecting hole 5 formed by the stitching of the first stitching hole 51 and the second stitching hole 52 is also cylindrical, the size of the first end 51a of the first stitching hole 51 is equal to the size of the second end 51b, the size of the first end 52a of the second stitching hole 52 is equal to the size of the second end 52b, and the end surface of the second end 51b of the first stitching hole 51 and the end surface of the second end 52b of the second stitching hole 52 (forming the stitching interface AA) are the same size.

[0088] As shown in FIG. 5A to FIG. 5D , when the first splicing hole 51 and the second splicing hole 52 are both tapered holes, the size of one end of the first splicing hole 51 and the second splicing hole 52 close to each other is smaller than the size of the other parts thereof.

[0089] It should be noted that the end face of the second end 51b of the first stitching hole 51 and the end face of the second end 52b of the second stitching hole 52 are coplanar, forming a stitching interface AA. Figures 4, 5A, 5C and 5D illustrate the example in which the stitching interface AA of the connecting via 5 formed by stitching the first stitching hole 51 and the second stitching hole 52 is parallel to the first surface 1a of the substrate 1. However, the setting method of the stitching interface AA and the first surface 1a of the substrate 1 in the present disclosure is not limited to this. For example, as shown in Figure 5B, there may be an angle between the stitching interface AA and the first surface 1a of the substrate 1.

[0090] For example, when the first splicing hole 51 and the second splicing hole 52 are both tapered holes, the sizes of the second end 51 b of the first splicing hole 51 and the second end 52 b of the second splicing hole 52 may be the same or different.

[0091] For example, as shown in Figures 5A and 5B, the end surface of the second end 51b of the first splicing hole 51 and the end surface of the second end 52b of the second splicing hole 52 can completely overlap, and the end surface area of ​​the second end 51b of the first splicing hole 51 is equal to the end surface area of ​​the second end 52b of the second splicing hole 52. In other words, the size of the splicing interface AA of the connecting via 5 formed by splicing the first splicing hole 51 and the second splicing hole 52 is the same as the size of the second end 51b of the first splicing hole 51 or the size of the second end 52b of the second splicing hole 52.

[0092] At this time, referring to Figure 5B, when there is an angle between the splicing interface AA and the first surface, the size L3 of the second end 51b of the first splicing hole 51, the size of the splicing interface AA, and the size L3 of the second end 52b of the second splicing hole 52 are all sizes in a set direction, and the set direction is the direction parallel to the end face of the second end 51b of the first splicing hole 51.

[0093] For example, as shown in FIG5C , the end surface of the second end 51b of the first stitching hole 51 overlaps the end surface of the second end 52b of the second stitching hole 52. The dimensions of the second end 51b of the first stitching hole 51 are different from the dimensions of the second end 52b of the second stitching hole 52. That is, the end surface area of ​​the second end 51b of the first stitching hole 51 and the end surface area of ​​the second end 52b of the second stitching hole 52 are not equal. The overlapping region BB between the two is the end surface of the second end 51b of the first stitching hole 51 and the end surface of the second end 52b of the second stitching hole 52, and the outline of the overlapping region BB is located within the end surface of the second end 52b of the second stitching hole 52. For example, the end surface area of ​​the second end 51b of the first stitching hole 51 is smaller than the end surface area of ​​the second end 52b of the second stitching hole 52, and the end surface outline of the second end 51b of the first stitching hole 51 is located within the end surface of the second end 52b of the second stitching hole 52.

[0094] For example, as shown in FIG5D , the end face of the second end 51b of the first stitching hole 51 overlaps the end face of the second end 52b of the second stitching hole 52, and the first stitching hole 51 and the second stitching hole 52 are staggered in the first direction X. In this case, the size of the second end 51b of the first stitching hole 51 and the size of the second end 52b of the second stitching hole 52 can be the same or different. The end face area of ​​the second end 51b of the first stitching hole 51 and the end face area of ​​the second end 52b of the second stitching hole 52 are equal or different, and the ratio of the overlapping area BB between the two to the end face area of ​​the second end 51b of the first stitching hole 51 is greater than 50%, or the ratio of the area of ​​the overlapping area BB to the end face area of ​​the second end 52b of the second stitching hole 52 is greater than 50%. In this way, the degree of misalignment between the first stitching hole 51 and the second stitching hole 52 can be reduced, ensuring that the first stitching hole 51 and the second stitching hole 52 are connected to each other and the connected area is large, thereby meeting the line width requirements of the connecting line 4.

[0095] It should be noted that Figures 5C and 5D both take the splicing interface AA being parallel to the first surface 1a as an example. For the case where the end face of the second end 51b of the first splicing hole 51 and the end face of the second end 52b of the second splicing hole 52 do not completely overlap, there may also be an angle between the splicing interface AA and the first surface 1a.

[0096] To simplify the description, the direction from the first surface 1 a to the second surface 1 b of the substrate 1 is taken as the length direction of the first stitching hole 51 , the second stitching hole 52 and the connecting via 5 , that is, the first direction X.

[0097] In some embodiments, the first stitching hole 51 and the second stitching hole 52 can be obtained by wet etching. Specifically, a certain concentration of HF solution is used as an etching solution to etch the first surface 1a of the substrate 1 to obtain the first stitching hole 51; and a certain concentration of HF solution is used as an etching solution to etch the second surface 1b of the substrate 1 to obtain the second stitching hole 52. Among them, the first stitching hole 51 and the second stitching hole 52 need to be connected to each other to obtain the connecting via 5, that is, the length values ​​of the first stitching hole 51 and the second stitching hole 52 in the first direction X are both smaller than the length value of the connecting via 5 in the first direction X, thereby shortening the etching distance, reducing the etching difficulty, and accelerating the corrosion of the substrate 1. Therefore, the etching efficiency is high when preparing the first stitching hole 51 and the second stitching hole 52, and during the etching process, along the etching direction, the difference in contact area between each part in the substrate 1 on the etching path and the etching liquid is small. For example, the contact area between the part at the end of etching and the etching liquid is not much different from the contact area between the part at the starting end of etching and the etching liquid, so that the difference between the size L3 of the first end 51a of the formed first stitching hole 51 and the size L3 of the second end 51b is small, and the difference between the size L3 of the first end 52a of the second stitching hole 52 and the size L3 of the second end 52b is also small.

[0098] 5A and 5B , in a display panel 10 with a relatively small pixel pitch, when the aperture value of the connecting via 5 is small, the difference in the dimension L3 of each portion of the connecting via 5 in the second direction Y along the etching direction is relatively small. Thus, the dimension L3 of the second end 51b of the first stitching hole 51 and the dimension L3 of the second end 52b of the second stitching hole 52 are not too small. On the one hand, there is sufficient space inside the connecting via 5 for arranging the connecting trace 4, which can reduce the impact of burrs in the connecting via 5 on the conductive material when the conductive material is injected into the connecting via 5 and reduce the possibility of circuit breakage when forming the connecting trace 4. On the other hand, the uniform size of the connecting via 5 can reduce the variation in the line width of the connecting trace 4, reduce the difference in resistance stability, and minimize the problem of excessive local heating of the connecting trace 4. As a result, the connection stability and line width uniformity of the connecting trace 4 formed in the connecting via 5 can be improved.

[0099] In other embodiments, a laser can be used to ablate the first surface 1a of the substrate 1 to obtain a first stitching hole 51; a laser can be used to ablate the second surface 1b of the substrate 1 to obtain a second stitching hole 52, wherein the first stitching hole 51 and the second stitching hole 52 need to penetrate each other to obtain a connecting via 5, that is, the length values ​​of the first stitching hole 51 and the second stitching hole 52 in the first direction X are both smaller than the length value of the connecting via 5 in the first direction X, thereby shortening the etching distance and reducing the etching difficulty. Therefore, a low-energy laser can be used, thereby reducing the influence of the laser on the strength of the substrate 1, and the difference between the size of the first end 51a of the first stitching hole 51 and the size of the second end 51b is small, and the difference between the size of the first end 52a and the size of the second end 52b of the second stitching hole 52 is also small. In this way, in the display panel 10 with a relatively small pixel pitch, when the aperture value of the connecting via 5 is small, the size L3 of each part of the connecting via 5 along the etching direction is relatively small. On the one hand, there is enough space inside the connecting via 5 for setting the connecting trace 4, which can reduce the impact of burrs in the connecting via 5 on the conductive material when the conductive material is injected into the connecting via 5, and reduce the possibility of circuit breakage when the connecting trace 4 is formed. On the other hand, the line width variation of the connecting trace 4 can be reduced, the difference in resistance stability can be reduced, and the problem of local heating of the connecting trace 4 can be avoided as much as possible. Therefore, the connection stability and line width uniformity of the connecting trace 4 formed in the connecting via 5 can be improved.

[0100] Continuing with Figures 5A to 5D , in some embodiments, the size of the first stitching hole 51 gradually decreases from the first end 51a of the first stitching hole 51 to the second end 52b; and the size of the second stitching hole 52 gradually decreases from the first end 52a of the second stitching hole 52 to the second end 52b. In other words, both the first stitching hole 51 and the second stitching hole 52 are tapered holes. This arrangement allows for a more uniform linear change in the width of the connecting trace 4, preventing a large difference in width between a certain location on the connecting trace 4 and other locations connected thereto. This helps improve the resistance stability of the connecting trace 4 and further enhances the conductive performance of the connecting trace 4.

[0101] Continuing with Figures 5A to 5D , in some embodiments, the taper value of the first stitching hole 51 and the second stitching hole 52 is 0 to 0.26; the ratio of the size of the first end 51a of the first stitching hole 51 to the size of the second end 51b is 0.9 to 1.1, and the ratio of the size of the first end 52a of the second stitching hole 52 to the size of the second end 52b is also 0.9 to 1.1. For example, the taper value of the first stitching hole 51 and the second stitching hole 52 is 0, and in this case, the ratio of the size of the first end 51a of the first stitching hole 51 to the size of the second end 51b is 1, and the ratio of the size of the first end 52a of the second stitching hole 52 to the size of the second end 52b is also 1.

[0102] Since the taper values ​​of the first splicing hole 51 and the second splicing hole 52 are relatively small, the sizes of the two ends of the first splicing hole 51 are close, the sizes of the two ends of the second splicing hole 52 are close, and the shapes of the first splicing hole 51 and the second splicing hole 52 are close to cylindrical. When the taper values ​​of the first stitching hole 51 and the second stitching hole 52 are consistent and the sizes of the ends close to each other are the same, the shape of the connecting via 5 formed by the stitching of the first stitching hole 51 and the second stitching hole 52 is close to a columnar shape. In this way, in the display panel 10 with a relatively small pixel pitch, when the aperture value of the connecting via 5 is small, along the etching direction, the size L3 of each part of the connecting via 5 close to the columnar shape is relatively small. On the one hand, there is enough space inside the connecting via 5 for setting the connecting trace 4, which can further reduce the impact of burrs in the connecting via 5 on the conductive material when the conductive material is injected into the connecting via 5, and reduce the possibility of circuit breakage when forming the connecting trace 4. On the other hand, the line width variation of the connecting trace 4 can be further reduced, the difference in resistance stability can be reduced, and the problem of local heating of the connecting trace 4 can be avoided as much as possible.

[0103] Illustratively, the taper value of the first splicing hole 51 may be 0, 0.06, 0.1, 0.12, 0.15, 0.18, 0.23, or 0.26.

[0104] Illustratively, the taper value of the second splicing hole 52 may be 0, 0.06, 0.1, 0.12, 0.15, 0.18, 0.23, or 0.26.

[0105] For example, the ratio of the size of the first end 51 a to the size of the second end 51 b of the first splicing hole 51 may be 0.9, 0.93, 0.96, 0.98, 1, 1.02, 1.05, or 1.1.

[0106] For example, the ratio of the size of the first end 52a to the size of the second end 52b of the second splicing hole 52 may be 0.9, 0.93, 0.96, 0.98, 1, 1.02, 1.05, or 1.1.

[0107] For example, in the same connecting via 5 , the size of the first end 51 a of the first splicing hole 51 and the size of the first end 52 a of the second splicing hole 52 may be the same or different.

[0108] 5A to 5D , in some embodiments, the direction from the first surface 1a to the second surface 1b of the substrate 1 is used as the length direction of the first stitching hole 51, the second stitching hole 52 and the connecting via 5, that is, the first direction X shown in the figure, and the ratio of the length L1 of the first stitching hole 51 in the length direction to the length L2 of the second stitching hole 52 in the length direction ranges from 0.5 to 2.

[0109] It can be understood that when the ratio of the length L1 of the first stitching hole 51 to the length L2 of the second stitching hole 52 is too large, for example greater than 2, the length L1 of the first stitching hole 51 is larger and the length L2 of the second stitching hole 52 is smaller. When HF etching or laser ablation is used to obtain the first stitching hole 51 and the second stitching hole 52, only the etching length of the second stitching hole can be shortened, and the etching difficulty of the second stitching hole can be reduced. For the first stitching hole 51, since its etching length is still relatively long, the size of the first end 51a of the first stitching hole 51 and the size of the second end 51b are quite different, that is, the size of the second end 51b of the first stitching hole 51 is smaller. In this way, it is impossible to effectively achieve the effect of small size difference at each position of the connecting via 5, thereby improving the connection stability, line width uniformity and resistance uniformity of the connecting trace 4.

[0110] When the ratio of the length L1 of the first stitching hole 51 to the length L2 of the second stitching hole 52 is too small, for example, less than 0.5, the length L2 of the second stitching hole 52 is larger and the length L1 of the first stitching hole 51 is smaller. When HF etching or laser ablation is used to obtain the first stitching hole 51 and the second stitching hole 52, only the etching length of the first stitching hole 51 can be shortened, thereby reducing the etching difficulty of the first stitching hole 51. However, for the second stitching hole 52, since its etching length is still relatively long, the size of the first end 52a of the second stitching hole 52 and the size of the second end 52b are quite different, that is, the size of the second end 52b of the second stitching hole 52 is smaller. In this way, it is impossible to effectively achieve the effect of small size difference at each position of the connecting via, thereby improving the connection stability, line width uniformity and resistance uniformity of the connecting trace.

[0111] Therefore, by setting the ratio range of the length L1 of the first stitching hole 51 to the length L2 of the second stitching hole 52 to 0.5~2, the ratio of the length L1 of the first stitching hole 51 to the length L2 of the second stitching hole 52 can be maintained within a reasonable range, thereby avoiding the length L1 of the first stitching hole 51 or the length L2 of the second stitching hole 52 being too large, so that the size of the first end 51a of the first stitching hole 51 and the size of the second end 51b are relatively small, and the size of the first end 52a of the second end 52b of the second stitching hole 52 are also relatively small. Therefore, when the conductive material is injected into the first stitching hole 51 or the second stitching hole 52 to form the connecting line 4, the problem of line breaking in the connecting line 4 can be avoided. On the other hand, it is beneficial to make the line width of the connecting line 4 change less, and the resistance stability difference is also small, which can largely avoid the problem of local heating of the connecting line 4.

[0112] It should be noted that in Figures 5A, 5B, and 5D, the ratio of the length L1 of the first splicing hole 51 to the length L2 of the second splicing hole 52 is 1, that is, the length L1 of the first splicing hole 51 is the same as the length L2 of the second splicing hole 52. In this case, the apertures of the first splicing hole 51 and the second splicing hole 52 are the same. However, in this embodiment, the ratio of the length L1 of the first splicing hole 51 to the length L2 of the second splicing hole 52 is not limited to this. For example, the ratio of the length L1 of the first splicing hole 51 to the length L2 of the second splicing hole 52 can range from 0.5, 1, or 2.

[0113] In some embodiments, the dimensions of the first end 51a of the first stitching hole 51 and the first end 52a of the second stitching hole 52 are between 10 μm and 300 μm. The difference between the dimensions of the first end 51a of the first stitching hole 51 and the first end 52a of the second stitching hole 52 is between 0 and 5 μm. It is understood that the dimensions of the first end 51a of the first stitching hole 51 and the first end 52a of the second stitching hole 52 can be the same or different. When the dimensions of the first end 51a of the first stitching hole 51 and the first end 52a of the second stitching hole 52 are different, the difference between the two is less than or equal to 5 μm.

[0114] For example, the size of the first end 51 a of the first splicing hole 51 may be 10 μm, 30 μm, 50 μm, 60 μm, 100 μm, 120 μm, 180 μm, 230 μm, 260 μm, or 300 μm.

[0115] The size of the first end 52 a of the second splicing hole 52 may be 10 μm, 30 μm, 50 μm, 60 μm, 100 μm, 120 μm, 180 μm, 230 μm, 260 μm, or 300 μm.

[0116] The following describes the positional relationship between the connection vias and the front electrodes.

[0117] In some embodiments, as shown in Figures 6A and 6B, at least some of the multiple connecting vias 5 also penetrate at least a portion of the corresponding front electrode 7, that is, after the front electrode 7 is set on the first surface 1a of the substrate 1, the connecting via 5 is formed to penetrate the front electrode 7 and the substrate 1. For example, the outer contour of the positive projection of the connecting via 5 on the first surface 1a of the substrate 1 and the positive projection of the front electrode 7 on the first surface 1a overlap. Therefore, the first sub-portion 4a of the connecting trace 4 set at one end of the first surface 1a of the substrate 1 can be directly connected to the front electrode 7, which not only facilitates the electrical connection between the first sub-portion 4a of the connecting trace 4 and the front electrode 7, but also shortens the routing length of the first sub-portion 4a of the connecting trace 4, thereby reducing the manufacturing cost of the connecting trace 4.

[0118] Exemplarily, the multiple connecting vias 5 and the multiple front electrodes 7 may be arranged in such a manner that the orthographic projections of some of the connecting vias 5 on the first surface 1a of the substrate fall within the outline of the orthographic projections of the front electrodes 7 on the first surface 1a, and some of the connecting vias 5 and the corresponding front electrodes 7 do not overlap; or, the orthographic projections of all of the connecting vias 5 on the first surface 1a of the substrate 1 fall within the outline of the orthographic projections of the front electrodes 7 on the first surface 1a.

[0119] Exemplarily, when the orthographic projection of the connecting via 5 on the first surface 1a of the substrate falls within the outline of the orthographic projection of the front electrode 7 on the first surface 1a, as shown in FIG6A , the orthographic projection of the connecting via 5 on the first surface 1a of the substrate 1 can be completely set within the outer outline of the orthographic projection of the front electrode 7 on the first surface 1a. During the manufacturing process of the display panel 10, when the preparation steps of the front electrode 7 and the connecting via 5 are: first forming a plurality of front electrodes 7 arranged in parallel and spaced apart on the first surface 1a of the substrate 1, and then preparing the connecting via 5, the connecting via 5 must pass through both the substrate 1 and the front electrode 7. When the preparation steps of the front electrode 7 and the connecting via 5 are: first preparing the connecting via 5 on the substrate 1, and then forming a plurality of front electrodes 7 arranged in parallel and spaced apart on the first surface 1a of the substrate 1, during the preparation process, the connecting via 5 only needs to pass through the substrate 1, and part of the material forming the front electrode 7 will enter the connecting via 5 as part of the connecting trace.

[0120] Alternatively, as shown in FIG6B , a portion of the orthographic projection of the connecting via 5 on the first surface 1a of the substrate 1 is disposed within the outer contour of the orthographic projection of the front electrode 7. During the manufacturing process of the display panel 10, when the steps for preparing the front electrode 7 and the connecting via 5 are as follows: first, a plurality of front electrodes 7 arranged in parallel and spaced relation are formed on the first surface 1a of the substrate 1, and then, when preparing the connecting via 5, the first portion 5a of the connecting via 5 must pass through both the substrate 1 and the front electrode 7, the second portion 5b extends to the outside of the front electrode 7 and does not overlap with the front electrode 7, and the second portion 5b only passes through the substrate 1. When the steps for preparing the front electrode 7 and the connecting via 5 are as follows: first, a plurality of front electrodes 7 arranged in parallel and spaced relation are formed on the first surface 1a of the substrate 1, the first portion 5a and the second portion 5b of the connecting via 5 only need to pass through the substrate 1 during the manufacturing process, and part of the material forming the front electrode 7 will enter the connecting via 5 as part of the connecting trace.

[0121] In some embodiments, as shown in Figures 7, 8, and 9, the orthographic projections of at least some of the plurality of front electrodes 7 on the first surface 1a do not overlap with the corresponding connection vias 5; the front electrodes 7 extend in the second direction y, and the front electrodes 7 are disposed on one side of the corresponding connection vias 5 in the second direction y. With this arrangement, since the front electrodes 7 and the connection vias 5 do not overlap, when preparing the connection vias 5 using a wet etching process or a laser ablation process, only the substrate 1 needs to be wet-etched or laser-ablated, without the front electrodes 7 needing to undergo the aforementioned operations. This simplifies the process for preparing the connection vias 5 and improves preparation efficiency.

[0122] Exemplarily, the multiple connecting vias 5 and the multiple front electrodes 7 may be arranged in such a manner that: the orthographic projections of a part of the connecting vias 5 on the first surface 1a do not overlap with the orthographic projections of the corresponding front electrodes 7 on the first surface 1a, and another part of the connecting vias 5 pass through the corresponding front electrodes 7; or, the orthographic projections of all the front electrodes 7 on the first surface 1a do not overlap with the corresponding connecting vias 5.

[0123] For example, when the orthographic projection of the front electrode 7 on the first surface 1 a does not overlap with the corresponding connecting via 5 , the positional relationship between the front electrode 7 and the connecting via 5 may be, for example:

[0124] As shown in Figure 7, substrate 1 includes a first side surface 1c, and the distance between connecting via 5 and first side surface 1c is smaller than the distance between front electrode 7 and first side surface 1c. In other words, connecting via 5 is closer to first side surface 1c of substrate 1 than front electrode 7. Because connecting via 5 is provided on substrate 1 and a gap is provided between connecting via 5 and first side surface 1c, the mechanical strength of substrate 1 is ensured while narrowing the frame of the light-emitting substrate and achieving connection between first surface 1a and second surface 1b of substrate 1 via connecting via 5 and connecting trace 4.

[0125] Alternatively, as shown in FIG8 , the substrate 1 includes a first side surface 1c, and the distance between the connecting via 5 and the first side surface 1c is greater than the distance between the front electrode 7 and the first side surface 1c. In other words, the front electrode 7 is closer to the first side surface 1c than the substrate. Because the connecting via 5 is provided on the substrate 1 and a relatively large spacing is provided between the connecting via 5 and the first side surface 1c, while narrowing the frame of the light-emitting substrate, the connection between the first surface 1a and the second surface 1b of the substrate 1 via the connecting via 5 and the connecting trace 4 is further enhanced, thereby further enhancing the mechanical strength of the substrate 1.

[0126] Alternatively, as shown in FIG9 , the substrate 1 includes a first side surface 1c, the distance between the connecting via 5 and the first side surface 1c is zero, and the front electrode 7 is disposed on the side of the connecting via 5 away from the first side surface 1c. In other words, the connecting via 5 is disposed at an edge of the first surface 1a of the substrate 1, i.e., the connecting via 5 is provided on the first side surface 1c. The side of the connecting via 5 facing the first side surface 1c can be open, which can be understood as the connecting via 5 being an elongated groove provided on the first side surface 1c. Since the connecting via 5 is open, it is convenient to form the connecting trace 4.

[0127] In some embodiments, as shown in FIG. 6A , FIG. 6B , FIG. 7 , FIG. 8 and FIG. 9 , a front electrode 7 is provided between two adjacent light emitting devices 8 close to the side of the substrate among the plurality of light emitting devices 8 .

[0128] The front electrode 7 and the connecting via are arranged near the side of the substrate. By arranging the front electrode 7 between two adjacent light-emitting devices 8 near the side of the substrate, the light-emitting device 8 is made as close to the boundary of the substrate 1 as possible, which can increase the arrangement density of the light-emitting devices 8 on the display panel 10 on the substrate 1, narrow the frame, and help improve the display effect of the display panel 10.

[0129] In some embodiments, as shown in Figures 6A, 6B, 7, 8, and 9, the substrate 1 further includes multiple side surfaces, and the multiple connecting vias 5 and the multiple front electrodes 7 are located near the first side surface 1c of the substrate 1. The minimum distance between some of the light-emitting devices 8 and the first side surface 1c is less than the minimum distance between the multiple front electrodes 7 and the first side surface 1c. In other words, the light-emitting devices are closer to the side surfaces of the substrate than the front electrodes and connecting vias, so that the front electrodes 7 are completely disposed within the gaps in the area of ​​the display panel 10 where the light-emitting devices 8 are located. This can further increase the arrangement density of the light-emitting devices 8 on the substrate 1 of the display panel 10, thereby improving the display effect of the display panel 10.

[0130] 1A to 1C , in a display panel 10 , a plurality of light-emitting devices 8 are arranged in an array, and each pixel region P is provided with at least three adjacent light-emitting devices 8 . As shown in Figure 1A, each pixel area P is provided with three light-emitting devices 8 arranged along the row direction, and as shown in Figure 1B, each pixel area P is provided with three light-emitting devices 8 arranged along the column direction. In a row of pixel areas P close to the first side surface 1c of the substrate 1, a group of connecting vias 5, front electrodes 7, connecting traces 4 and a first protective layer 61 are provided between the light-emitting devices 8 close to each other in two adjacent pixel areas P. For example, a group of connecting vias 5, front electrodes 7, connecting traces 4 and a first protective layer 61 are provided on the boundary between the two pixel areas P. In this way, the positions of the connecting vias 5, the front electrodes 7, and the first protective layer 61 will not occupy the space of the light-emitting devices 8, and the arrangement density of the multiple light-emitting devices 8 will not be affected. On the basis of ensuring that the first surface 1a and the second surface 1b of the substrate 1 are electrically connected, the area occupied by the light-emitting devices 8 on the first surface 1a is increased, and there is no need to set a border area for placing the connecting vias 5, the front electrodes 7, and the first protective layer 61. The border can be narrowed to the greatest extent, thereby improving the display effect of the display panel 10.

[0131] As shown in Figure 1C, a plurality of light-emitting devices 8 are arranged in an array, and each pixel area P is provided with three adjacent light-emitting devices 8. In a row of pixel areas P close to the first side 1c of the substrate 1, each pixel area P is provided with three light-emitting devices 8. It also includes a group of connecting vias 5, a front electrode 7, a connecting trace 4 and a first protective layer 61. A group of connecting vias 5, a front electrode 7, a connecting trace 4 and a first protective layer 61 can be located in the upper right corner area of ​​the pixel area P. It can be understood that a group of connecting vias 5, a front electrode 7, a connecting trace 4 and a first protective layer 61 and a driving chip / pixel circuit are located in different film layers and are avoided in space to avoid mutual interference or contact to cause a short circuit.

[0132] A set of connecting vias 5, front electrodes 7, connecting traces 4, and a first protective layer 61 are disposed between two adjacent light-emitting devices, which are located in two adjacent pixel regions P. This arrangement allows the connecting vias 5, front electrodes 7, connecting traces 4, and first protective layer 61 to be disposed within the pixel region P, eliminating the need for a separate border region and narrowing the border. Furthermore, because the set of connecting vias 5, front electrodes 7, connecting traces 4, and first protective layer 61 is disposed in the upper right corner of the pixel region P, where no light-emitting devices are disposed, and avoids contact with the driver chip / pixel circuit, this does not affect the arrangement density of the light-emitting devices 8 or the normal operation of the devices within the pixel region. Furthermore, the space for the connecting vias 5, front electrodes 7, connecting traces 4, and first protective layer 61 is relatively ample, reducing the possibility of short circuits caused by connection to the light-emitting devices 8.

[0133] The preparation method of the above-mentioned display panel 10 includes: forming a plurality of front electrodes 7 on one side of the first surface 1a of the substrate 1, and forming a plurality of back electrodes 3 on one side of the second surface 1b of the substrate 1. The formation of the plurality of front electrodes 7 and the back electrodes 3 needs to be prepared by a patterning process. In this case, the first surface 1a and the second surface 1b of the substrate 1, for example, both need to undergo an etching process, resulting in high manufacturing costs for the display panel 10. Moreover, in some embodiments, the orthographic projections of the plurality of back electrodes 3 on the substrate 1 overlap with the area where the light-emitting device 8 is located, and when the back electrodes 3 are formed by laser etching, the laser may pass through the substrate 1 and be incident on the light-emitting device 8 on the first surface 1a. Therefore, part of the energy of the laser will pass through the substrate 1 and damage the light-emitting device 8, resulting in problems such as local corrosion and the failure of the light-emitting device to light up.

[0134] Therefore, in order to reduce the manufacturing cost of the display panel 10 and avoid the influence of the back surface process of the substrate 1 on the light-emitting device 8, in some embodiments, as shown in Figures 2A and 2B, the display panel 10 also includes a bridging structure 2 arranged on the second surface 1b of the substrate 1; the bridging structure 2 is arranged on one side of the second surface 1b, and a plurality of back electrodes 3 are arranged on the surface of the bridging structure 2 away from the substrate 1; the substrate 1 also includes multiple side surfaces, and the multiple connecting vias 5 and the multiple front electrodes 7 are close to the first side surface 1c of the substrate 1; the bridging structure 2 is located on the side of the multiple connecting vias 5 away from the first side surface 1c.

[0135] It should be noted that the plurality of back electrodes 3 are arranged in parallel and at intervals on the surface of the bridge structure 2 away from the substrate 1 .

[0136] By providing a bridging structure 2 on the second surface 1b of the substrate 1, the bridging structure 2 can serve as a carrier of a plurality of back electrodes 3. In the case where the display panel 10 includes a bridging structure 2, the formation of a plurality of back electrodes 3 can be achieved through the following two steps: first, a plurality of back electrodes 3 are formed on the surface of the side of the bridging structure 2 away from the substrate 1, and then the bridging structure 2 is connected to the second surface 1b of the substrate 1 with high precision, so that the second surface 1b of the substrate 1 is in contact with the surface of the side of the bridging structure 2 close to the substrate 1, and at the same time, the front electrode 7 and the back electrode 3 are directly opposite in the thickness direction of the substrate 1. The above-mentioned process of precisely connecting the bridging structure 2 to the second surface 1b of the substrate 1 is, for example, bonding. Through the above-mentioned method, the cost can be reduced while avoiding the influence of the etching process on the light-emitting device 8.

[0137] It can be understood that, as shown in Figures 2A and 2B, when the display panel 10 includes a bridging structure 2, the connecting trace 4 includes a first sub-portion 4a, a second sub-portion 4b and a third sub-portion 4d connected in sequence, the second sub-portion 4b is located in the connecting via 5, the first sub-portion 4a is located on one side of the first surface 1a, and corresponds one-to-one with the front electrode 7 and is electrically connected, and the third sub-portion 4d is located on the side surface of the bridging structure 2 away from the substrate 1, and corresponds one-to-one with the back electrode 3 and is electrically connected.

[0138] In some embodiments, as shown in FIG11 , the back electrode 3 includes a straight portion 31 and an oblique portion 32 . The straight portion 31 extends perpendicularly along the second direction Y. The oblique portion 32 is connected to the straight portion 31 , and the extension direction of the straight portion 31 intersects the extension direction of the oblique portion 32 .

[0139] The multiple oblique portions 32 converge inwardly at one end away from the straight portion 31. The total dimension s1 of the straight portions of the multiple back electrodes in the third direction Z is greater than the total dimension s2 of the multiple oblique portions in the third direction. This facilitates electrical connection between the back electrodes and a flexible circuit board (not shown). The third direction Z intersects with the second direction Y, for example, being perpendicular.

[0140] In some embodiments, as shown in FIG10 , the bridging structure 2 includes multiple side surfaces, wherein the side surface facing the first side surface 1c is the second side surface 2c; the distance between the orthographic projection of the second side surface 2c on the first surface 1a and the opening edges of the multiple connecting vias 5 is equal and greater than or equal to 0. In other words, the second side surface 2c of the bridging structure 2 is planar and can be flush with the edge of the connecting via 5, or a gap can be set between the edge of the connecting via 5. By setting the second side surface 2c of the bridging structure 2 as a plane, the preparation process of the bridging structure 2 can be simplified, which is conducive to improving the preparation efficiency of the bridging structure 2. When the edge of the connecting via 5 is flush with the second side surface 2c of the bridging structure 2, the distance between the connecting via 5 and the back electrode 3 is shorter, which can shorten the routing length of the third sub-portion 4d of the connecting trace 4, which is conducive to reducing the manufacturing cost of the connecting trace 4.

[0141] In some embodiments, as shown in Figures 11, 12, and 13, the bridging structure 2 includes multiple side surfaces, wherein the side surface facing the first side surface 1c is the second side surface 2c. The second side surface 2c of the bridging structure 2 is provided with multiple grooves 21, each of which exposes one of the multiple connecting vias 5. In other words, the orthographic projection of the second side surface 2c of the bridging structure 2 on the second surface 1b can be sawtooth-shaped, and the orthographic projection of the connecting via 5 on the second surface 1b of the substrate 1 is located within the orthographic projection of the corresponding groove 21 on the second surface 1b. By arranging the orthographic projection of the connecting via 5 on the second surface 1b within the corresponding groove 21, the distance between the connecting via 5 and the back electrode 3 can be further shortened, and the routing length of the third subsection 4d of the connecting trace 4 can be shortened, which helps to further reduce the manufacturing cost of the connecting trace 4. At the same time, due to the limiting effect of groove 21, the conductive paste is confined within groove 21 during the formation of connecting traces 4, making it easier for the conductive paste to accumulate. This accelerates the accumulation of thickness in the formed connecting traces 4, thereby increasing the printing rate, reducing the step difference between substrate 1 and bridge structure 2 during the printing process, and reducing the printing difficulty. Furthermore, the conductive paste is confined within groove 21, making it difficult to spread in the third direction Z, thus preventing short circuits between the third subsections 4d of two adjacent connecting traces 4.

[0142] For example, a certain distance may be provided between the orthographic projection of the edge of the connecting via 5 on the bridging structure 2 and the edge of the corresponding groove 21; alternatively, the orthographic projection of the edge of the connecting via 5 on the bridging structure 2 may overlap or substantially overlap with the edge of the corresponding groove 21. For example, high-precision attachment equipment may be used to precisely align the groove 21 on the bridging structure 2 with the connecting via 5, so that the orthographic projection of the connecting via 5 on the second surface 1b of the substrate 1 lies within the orthographic projection of the corresponding groove 21 on the second surface 1b.

[0143] 11, 12 and 13, the groove 21 includes a first sub-groove 211, a second sub-groove 212 and a third sub-groove 213. The first sub-groove 211 is square, the second sub-groove 212 is semicircular, and the third sub-groove 213 is trapezoidal.

[0144] On the other hand, as shown in Figures 14A and 14B, some embodiments of the present application provide a display device 100, including a display panel 10 and a driving circuit board 20 provided by any of the aforementioned embodiments; the driving circuit board 20 is electrically connected to the display panel 10; the driving circuit board 20 is configured to drive the display panel 10 to display an image.

[0145] The display device 100 can be any device that displays a display, whether in motion (e.g., video), stationary (e.g., still image), text, or an image. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like.

[0146] For example, the display device 100 may further include a frame and other electronic components, etc. The display panel 10 may be disposed within the frame, for example.

[0147] In another aspect, a spliced ​​display device 1000 is provided, as shown in FIG15 , comprising a plurality of display devices 100 provided by any of the aforementioned embodiments.

[0148] By opening a connecting via 5 on the substrate 1, the second sub-portion 4b of the connecting trace 4 is arranged in the connecting via 5 opened on the substrate 1, so there is no need to set a circuit on the side of the substrate 1 to realize the connection between the front electrode 7 and the back electrode 3, thereby avoiding the occupation of the side circuit, and the encapsulation layer 9 does not need to reserve a safety distance during encapsulation. The distance between the side of the encapsulation layer 9 and the side of the substrate can be shortened, so the splicing distance between the two adjacent display devices 100 can be reduced, which is beneficial to improving the display effect of the spliced ​​display device 1000.

[0149] As shown in FIG15 , the side surfaces of the encapsulation layer 9 of the display panel 10 are flush with the side surfaces of the substrate 1 , so that the encapsulation layers 9 of adjacent display panels 10 are connected, and the side surfaces of the substrate 1 of adjacent display panels 10 are connected, thereby achieving a seamless display effect.

[0150] In another aspect, a method for manufacturing a display panel 10 is provided. As shown in FIG16 , the method for manufacturing the display panel 10 includes:

[0151] R1: Provide a substrate 1 with a plurality of parallel and spaced front electrodes 7 formed on the front surface. The substrate 1 includes a first surface 1a and a second surface 1b opposite to each other.

[0152] R2: forming a plurality of first stitching holes 51 on the first surface 1 a of the substrate 1 by wet etching or laser ablation.

[0153] R3: A plurality of second stitching holes 52 are formed on the second surface 1 b of the substrate 1 by wet etching or laser ablation. A first stitching hole 51 and a second stitching hole 52 are combined to form a connecting via 5 .

[0154] It should be noted that the order of R2 and R3 can be interchanged, as long as blind holes can be formed on two surfaces of the substrate and penetrate each other to form connecting vias.

[0155] R4: Attach the bridging structure 2 to the second surface 1b of the substrate 1; the process of connecting the bridging structure 2 to the second surface 1b of the substrate 1 is, for example, high-precision attachment, so that the back electrode 3 and the front electrode 7 are facing each other in the direction from the first surface 1a to the second surface 1b of the substrate 1.

[0156] Before R4, a plurality of back electrodes 3 are formed on a surface of the bridge structure 2 that is away from the substrate 1. Exemplarily, the plurality of back electrodes 3 are formed by a wet etching process.

[0157] In some embodiments, R4 may be performed before R2 and R3.

[0158] R5: forming a plurality of connecting traces 4 arranged in parallel and at intervals; each of the plurality of connecting traces 4 includes a first sub-portion 4a located on one side of the first surface 1a, a second sub-portion 4b located in the connecting via 5, and a third sub-portion 4d located on the surface of the side of the bridging structure 2 away from the substrate 1; the third sub-portion 4d of each connecting trace 4 is electrically connected to a back electrode 3; the third sub-portion 4d of the connecting trace 4 includes a portion located on the surface of the side of the bridging structure 2 away from the substrate 1 and a portion located on the second side surface 2c.

[0159] Exemplarily, the process of forming multiple connecting lines 4 can refer to the previous description. For example, the connecting lines can be formed by a sputtering coating process or a vacuum evaporation process, or the connecting lines can be formed by a printing process, such as screen printing, pad printing, transfer printing and 3D printing.

[0160] The above-mentioned preparation processes, such as the printing process, are only described as examples and are not intended to limit the actual production process.

[0161] R6: A first protective layer 61 is formed on one side of the first surface 1a of the substrate 1, and the first protective layer 61 covers the first sub-portion 4a. A second protective layer 62 is formed on one side of the second surface 1b of the substrate 1, and the second protective layer 62 covers the third sub-portion 4d.

[0162] R7: A plurality of light emitting devices 8 are formed on one side of the first surface 1 a of the substrate 1 .

[0163] Exemplarily, a plurality of light-emitting devices are mounted on the first surface of the substrate using surface mount technology (SMT), and the light-emitting devices 8 at least include a first color light-emitting device 81 , a second color light-emitting device 82 and a third color light-emitting device 83 .

[0164] R8: forming an encapsulation layer 9 on a side of the plurality of light-emitting devices away from the first surface.

[0165] Exemplarily, the coil is attached to the first surface 1a by roller lamination, and the excess edge of the coil is cut to obtain the encapsulation layer 9, so that the distance between the boundary of the orthographic projection of the encapsulation layer 9 on the plane where the first surface 1a is located and the boundary of the first surface 1a is in the range of 0 to 10 μm, for example, the encapsulation layer 9 and the side of the substrate 1 can be flush.

[0166] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: a substrate, the substrate comprising a first surface and a second surface disposed opposite to each other; A plurality of front electrodes are disposed on one side of the first surface of the substrate; A plurality of back electrodes are provided on one side of the second surface of the substrate; a plurality of connection vias, the plurality of connection vias passing through the substrate, at least one of the plurality of connection vias comprising a first stitching hole and a second stitching hole, a dimension of a first end of the first stitching hole away from the second stitching hole being greater than or equal to a dimension of a second end of the first stitching hole close to the second stitching hole, and a dimension of a first end of the second stitching hole away from the first stitching hole being greater than or equal to a dimension of the second end of the second stitching hole close to the first stitching hole; A plurality of connecting lines, each of the plurality of connecting lines passes through a connecting via hole and connects a front electrode of the plurality of front electrodes and a back electrode of the plurality of back electrodes.

2. The display panel according to claim 1, wherein Along the direction from the first end to the second end of the first splicing hole, the size of the first splicing hole gradually decreases; Along the direction from the first end to the second end of the second splicing hole, the size of the second splicing hole gradually decreases.

3. The display panel according to claim 2, wherein: The taper value of the first splicing hole and the second splicing hole is 0-0.26; The ratio of the size of the first end to the size of the second end of the first splicing hole is 0.9 to 1.1, and the ratio of the size of the first end to the size of the second end of the second splicing hole is 0.9 to 1.

1.

4. The display panel according to claim 1, wherein: The thickness direction of the substrate is a first direction, and the ratio of the size of the first stitching hole in the first direction to the size of the second stitching hole in the first direction is in a range of 0.5 to 2.

5. The display panel according to claim 1, wherein: The difference between the size of the first end of the first stitching hole and the size of the first end of the second stitching hole is in the range of 0 to 5 μm.

6. The display panel according to any one of claims 1 to 5, wherein: The size of the first end of the first splicing hole and the first end of the second splicing hole is 10 μm to 300 μm.

7. The display panel according to any one of claims 1 to 6, wherein: The orthographic projections of at least some of the plurality of connection vias on the first surface of the substrate overlap with the orthographic projections of the front electrodes on the first surface of the substrate.

8. The display panel according to any one of claims 1 to 6, wherein: Orthographic projections of at least some of the plurality of front electrodes on the first surface do not overlap with the first connecting vias corresponding thereto; The front electrode extends in a second direction, and the front electrode is disposed on one side of the corresponding connecting via in the second direction.

9. The display panel according to claim 7 or 8, wherein: The display panel further includes a plurality of light emitting devices, which are arranged on one side of the first surface; Some of the plurality of light-emitting devices are arranged between two adjacent front electrodes.

10. The display panel according to claim 9, wherein: The substrate further includes a plurality of side surfaces, the plurality of connecting vias and the plurality of front electrodes being close to a first side surface of the substrate; A minimum distance between the part of the light emitting devices and the first side surface is smaller than a minimum distance between the plurality of front electrodes and the first side surface.

11. The display panel according to any one of claims 1 to 10, wherein: The display panel further includes a bridge structure, the bridge structure is arranged on one side of the second surface, and the plurality of back electrodes are arranged on a surface of the bridge structure away from the substrate; The substrate further includes a plurality of side surfaces, the plurality of connection vias and the plurality of front electrodes are close to a first side surface of the substrate; the bridging structure is located on a side of the plurality of connection vias away from the first side surface.

12. The display panel according to claim 11, wherein: The bridging structure includes a plurality of side surfaces, wherein the side surface facing the first side surface among the plurality of side surfaces is a second side surface; The distance between the orthographic projection of the second side surface on the first surface and the opening edges of the plurality of connecting vias is equal to or greater than 0.

13. The display panel according to claim 11, wherein: The bridging structure includes a plurality of side surfaces, wherein the side surface facing the first side surface among the plurality of side surfaces is a second side surface; A plurality of grooves are formed on the second side surface of the bridge structure, and each of the plurality of grooves exposes a corresponding connection via hole among the plurality of connection via holes.

14. The display panel according to claim 13, wherein: The shapes of the groove include square, semicircle and trapezoid.

15. The display panel according to any one of claims 1 to 14, wherein: The connecting trace includes a first sub-section, a second sub-section and a third sub-section connected in sequence, the second sub-section is located in the connecting via, the first sub-section is located on one side of the first surface and is connected to the front electrode, and the third sub-section is located on one side of the second surface and is connected to the back electrode.

16. The display panel according to claim 15, wherein: The display panel further includes a first protective layer and a second protective layer, wherein the first protective layer is located on one side of the first surface and covers the first sub-portion, and the second protective layer is located on one side of the second surface and covers the third sub-portion.

17. The display panel according to claim 1, wherein: The display panel further includes a plurality of light-emitting devices and an encapsulation layer, which are arranged on one side of the first surface; The encapsulation layer covers the plurality of light-emitting devices, the front electrode and the connecting traces located in a first sub-portion of the first surface, and a distance between a boundary of an orthographic projection of the encapsulation layer on the plane where the first surface is located and a boundary of the first surface ranges from 0 to 10 μm.

18. A display device comprising: The display panel according to any one of claims 1 to 17; a driving circuit board, the driving circuit board being electrically connected to the display panel; The driving circuit board is configured to drive the display panel to display an image.

19. A spliced ​​display device comprising a plurality of display devices according to claim 18.

Images