Semiconductor device, display panel, and chip

Abstract

A semiconductor device (100), comprising at least one thin film transistor, wherein the thin film transistor comprises a vertical active structure layer (12) formed by stacking a first conductor portion (121), a trench portion (122), and a second conductor portion (123); the material of the trench portion (122) is polycrystalline silicon, and the growth direction of the crystal grains of the polycrystalline silicon is consistent with the moving direction of charge carriers. Further disclosed are a display panel and a chip.

Description

Semiconductor devices, display panels and chips Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device, a display panel, and a chip. Background Art

[0002] Currently, chips for products are manufactured by manufacturers, resulting in high costs. Integrating chip circuitry, such as the multiplexer (MUX), source driver circuits (SOURCE), and timing control circuits (TCON), onto a glass substrate (System on Glass (SOG)) can significantly increase the integration density of display panels, reduce reliance on chips, and lower costs. Implementing SOG requires improving the integration density, maximum operating frequency, and current density of existing thin-film transistors (TFTs). All of these require TFTs with shorter channel lengths, higher mobility, and smaller size.

[0003] Currently, thin-film transistors are mostly made of amorphous silicon, metal oxide semiconductors, and polycrystalline silicon. Polycrystalline silicon, with its advantages of high mobility and small device size, is widely used in mobile phones and VR devices. However, the mobility and size of polycrystalline silicon used in chip manufacturing do not meet the requirements. SUMMARY OF THE INVENTION

[0004] Embodiments of the present application provide a semiconductor device, a display panel, and a chip, which can realize a short channel of a thin film transistor while improving carrier mobility.

[0005] An embodiment of the present application provides a semiconductor device, comprising:

[0006] substrate; and

[0007] At least one thin film transistor, the thin film transistor being disposed on the substrate; the thin film transistor comprising:

[0008] an active structure layer, the active structure layer being disposed on the substrate, the active structure layer comprising a first conductor portion, a channel portion, and a second conductor portion, the first conductor portion being disposed on the substrate, the channel portion being disposed on a side of the first conductor portion away from the substrate, and the second conductor portion being disposed on a side of the channel portion away from the substrate;

[0009] a first insulating layer, wherein the first insulating layer covers the active structure layer and the substrate;

[0010] a gate, the gate being disposed on the first insulating layer and located on at least one side of the active structure layer, and the gate being overlapped with at least a side surface of the channel portion in an extension direction parallel to the substrate; and

[0011] a first electrode and a second electrode, wherein the first electrode is connected to the first conductor portion, and the second electrode is connected to the second conductor portion;

[0012] The material of the channel portion is polysilicon, and the growth direction of the polysilicon grains is consistent with the movement direction of the carriers.

[0013] Optionally, in some embodiments of the present application, the slope angle of the active structure layer is between 80 degrees and 90 degrees.

[0014] Optionally, in some embodiments of the present application, the thickness of the channel portion is between 5 nanometers and 1 micron.

[0015] Optionally, in some embodiments of the present application, the gate includes a first gate and a second gate, the first gate is located on one side of the active structure layer, and the second gate is located on the other side of the active structure layer;

[0016] In an extension direction parallel to the substrate, one side surface of the first conductor portion, one side surface of the channel portion, and one side surface of the second conductor portion are all overlapped with the first gate; another side surface of the first conductor portion, another side surface of the channel portion, and another side surface of the second conductor portion are all overlapped with the second gate.

[0017] Optionally, in some embodiments of the present application, the thickness of the first insulating layer is less than the thickness of the first conductor portion.

[0018] Optionally, in some embodiments of the present application, in the regions on both sides of the active structure layer, the first conductor portion is not provided on the side of the first gate and the second gate close to the substrate.

[0019] Optionally, in some embodiments of the present application, the active structure layer includes a first side surface and a second side surface disposed opposite each other, the first gate covers a side of the first insulating layer facing the first side surface, and the second gate covers a side of the first insulating layer facing the second side surface. The first insulating layer includes a top portion, and the top portion covers a side of the active structure layer away from the substrate.

[0020] In the orthographic projection direction of the semiconductor device, the first gate and the second gate are both flush with a surface of the top away from the substrate.

[0021] Optionally, in some embodiments of the present application, the number of the thin film transistors is at least two, and in an orthographic projection pattern of the semiconductor device, the gates and the active structure layers are alternately and spaced apart along a first direction, where the first direction is perpendicular to a long axis direction of the channel portion;

[0022] Each of the thin film transistors includes two gates. In the same thin film transistor, one gate is arranged on one side of the active structure layer, and the other gate is arranged on the other side of the active structure layer.

[0023] Two adjacent thin film transistors share the first electrode, the second electrode and the gate.

[0024] Optionally, in some embodiments of the present application, the semiconductor device further includes a first connecting portion, the first connecting portion and the first conductor portion being provided in the same layer, the first connecting portion being connected to one side of the first conductor portions of at least two of the thin film transistors, and the first electrode being connected to the first connecting portion through a first via hole;

[0025] The semiconductor device further includes a second connection portion, which is provided in the same layer as the second conductor portion and connected to one side of the second conductor portions of at least two thin film transistors. The second electrode is connected to the second connection portion through a second via.

[0026] Optionally, in some embodiments of the present application, the semiconductor device further includes a third connecting portion, the third connecting portion being provided in the same layer as the gate, and the third connecting portion being connected to one side of the gate of at least two of the thin film transistors;

[0027] In the orthographic projection direction of the semiconductor device, a second insulating layer is provided between the first connecting portion and the third connecting portion, the second insulating layer covers the first connecting portion and exposes the first conductor portion, and the third connecting portion is provided on a side of the second insulating layer away from the substrate.

[0028] Optionally, in some embodiments of the present application, the semiconductor device further includes a fourth connecting portion and a fifth connecting portion, wherein the fourth connecting portion is provided in the same layer as the first conductor portion, and the fourth connecting portion is connected to the other side of the first conductor portion of at least two of the thin film transistors;

[0029] The fifth connecting portion is provided in the same layer as the channel portion, and the fifth connecting portion is connected to one side of the channel portion of at least two of the thin film transistors;

[0030] The second connection portion, the fourth connection portion, and the fifth connection portion all extend along the first direction. In the orthographic projection direction of the semiconductor device, the second connection portion, the fourth connection portion, and the fifth connection portion are overlapped.

[0031] Optionally, in some embodiments of the present application, the channel portion and the second conductor portion extend along the long axis direction of the channel portion and cover a portion of the second insulating layer.

[0032] Optionally, in some embodiments of the present application, the first connection part, the fourth connection part and the first conductor part are made of the same material and are integrally formed, the second connection part and the second conductor part are made of the same material and are integrally formed, the third connection part and the gate part are made of the same material and are integrally formed, and the fifth connection part and the channel part are made of the same material and are integrally formed.

[0033] Correspondingly, an embodiment of the present application further provides a display panel, which includes the semiconductor device as described in any one of the above embodiments.

[0034] For example, the semiconductor device includes:

[0035] substrate; and

[0036] At least one thin film transistor, the thin film transistor being disposed on the substrate; the thin film transistor comprising:

[0037] an active structure layer, the active structure layer being disposed on the substrate, the active structure layer comprising a first conductor portion, a channel portion, and a second conductor portion, the first conductor portion being disposed on the substrate, the channel portion being disposed on a side of the first conductor portion away from the substrate, and the second conductor portion being disposed on a side of the channel portion away from the substrate;

[0038] a first insulating layer, wherein the first insulating layer covers the active structure layer and the substrate;

[0039] a gate, the gate being disposed on the first insulating layer and located on at least one side of the active structure layer, and the gate being overlapped with at least a side surface of the channel portion in an extension direction parallel to the substrate; and

[0040] a first electrode and a second electrode, wherein the first electrode is connected to the first conductor portion, and the second electrode is connected to the second conductor portion;

[0041] The material of the channel portion is polysilicon, and the growth direction of the polysilicon grains is consistent with the movement direction of the carriers.

[0042] Optionally, in some embodiments of the present application, the slope angle of the active structure layer is between 80 degrees and 90 degrees.

[0043] Optionally, in some embodiments of the present application, the thickness of the channel portion is between 5 nanometers and 1 micron.

[0044] Optionally, in some embodiments of the present application, the gate includes a first gate and a second gate, the first gate is located on one side of the active structure layer, and the second gate is located on the other side of the active structure layer;

[0045] In an extension direction parallel to the substrate, one side surface of the first conductor portion, one side surface of the channel portion, and one side surface of the second conductor portion are all overlapped with the first gate; another side surface of the first conductor portion, another side surface of the channel portion, and another side surface of the second conductor portion are all overlapped with the second gate.

[0046] Optionally, in some embodiments of the present application, the thickness of the first insulating layer is less than the thickness of the first conductor portion.

[0047] Optionally, in some embodiments of the present application, in the regions on both sides of the active structure layer, the first conductor portion is not provided on the side of the first gate and the second gate close to the substrate.

[0048] Correspondingly, an embodiment of the present application further provides a chip, which includes the semiconductor device as described in any one of the above embodiments.

[0049] For example, the semiconductor device includes:

[0050] substrate; and

[0051] At least one thin film transistor, the thin film transistor being disposed on the substrate; the thin film transistor comprising:

[0052] an active structure layer, the active structure layer being disposed on the substrate, the active structure layer comprising a first conductor portion, a channel portion, and a second conductor portion, the first conductor portion being disposed on the substrate, the channel portion being disposed on a side of the first conductor portion away from the substrate, and the second conductor portion being disposed on a side of the channel portion away from the substrate;

[0053] a first insulating layer, wherein the first insulating layer covers the active structure layer and the substrate;

[0054] a gate, the gate being disposed on the first insulating layer and located on at least one side of the active structure layer, and the gate being overlapped with at least a side surface of the channel portion in an extension direction parallel to the substrate; and

[0055] a first electrode and a second electrode, wherein the first electrode is connected to the first conductor portion, and the second electrode is connected to the second conductor portion;

[0056] The material of the channel portion is polysilicon, and the growth direction of the polysilicon grains is consistent with the movement direction of the carriers.

[0057] Optionally, in some embodiments of the present application, the slope angle of the active structure layer is between 80 degrees and 90 degrees.

[0058] Optionally, in some embodiments of the present application, the thickness of the channel portion is between 5 nanometers and 1 micron.

[0059] Optionally, in some embodiments of the present application, the gate includes a first gate and a second gate, the first gate is located on one side of the active structure layer, and the second gate is located on the other side of the active structure layer;

[0060] In an extension direction parallel to the substrate, one side surface of the first conductor portion, one side surface of the channel portion, and one side surface of the second conductor portion are all overlapped with the first gate; another side surface of the first conductor portion, another side surface of the channel portion, and another side surface of the second conductor portion are all overlapped with the second gate.

[0061] Optionally, in some embodiments of the present application, the thickness of the first insulating layer is less than the thickness of the first conductor portion.

[0062] Optionally, in some embodiments of the present application, in the regions on both sides of the active structure layer, the first conductor portion is not provided on the side of the first gate and the second gate close to the substrate. Beneficial effects

[0063] The semiconductor device of the embodiment of the present application uses a first conductor portion, a channel portion, and a second conductor portion stacked to form a vertical active structure layer to achieve a narrow channel; and the growth direction of the grains in the channel portion is set to be consistent with the movement of carriers, which can achieve a single-crystal channel structure, thereby improving the carrier mobility. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] FIG1 is a schematic top view of a semiconductor device according to an embodiment of the present application;

[0065] FIG2 is a schematic cross-sectional view along line AA in FIG1 ;

[0066] FIG3 is a schematic cross-sectional view along line BB in FIG1 ;

[0067] FIG4 is a schematic structural diagram of step B1 of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0068] FIG5 is a schematic structural diagram of step B2 of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0069] FIG6 is a schematic structural diagram of step B3 of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0070] FIG7 is a schematic structural diagram of step B4 of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0071] FIG8 is a schematic structural diagram of step B5 of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0072] FIG9 is a structural diagram of step B6 of the method for manufacturing a semiconductor device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0073] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0074] The embodiments of the present application provide a semiconductor device, a display panel, and a chip, which are described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0075] 1 to 3 , an embodiment of the present application provides a semiconductor device 100 , which includes a substrate 11 and at least one thin film transistor (TFT). The thin film transistor TFT is disposed on the substrate 11 .

[0076] The thin film transistor TFT includes an active structure layer 12 , a first insulating layer 13 , a gate electrode 14 , a first electrode 151 and a second electrode 152 .

[0077] The active structure layer 12 is disposed on the substrate 11. The active structure layer 12 includes a first conductor portion 121, a channel portion 122, and a second conductor portion 123. The first conductor portion 121 is disposed on the substrate 11. The channel portion 122 is disposed on a side of the first conductor portion 121 away from the substrate 11. The second conductor portion 123 is disposed on a side of the channel portion 122 away from the substrate 11.

[0078] The first insulating layer 13 covers the active structure layer 12 and the substrate 11. A gate 14 is disposed on the first insulating layer 13 and is located on at least one side of the active structure layer 12. In a direction z perpendicular to the orthographic projection of the semiconductor device 100, the gate 14 overlaps at least one side of the channel portion 122. A first electrode 151 is connected to the first conductor portion 121. A second electrode 152 is connected to the second conductor portion 123.

[0079] The material of the channel portion 122 is polysilicon, and the growth direction of the polysilicon grains is consistent with the movement direction of the carriers.

[0080] The semiconductor device 100 of the embodiment of the present application uses a first conductor portion 121, a channel portion 122, and a second conductor portion 123 stacked to form a vertical active structure layer 12, that is, the thickness of the channel portion 122 is used as the channel length, thereby realizing a narrow channel; in addition, since the growth direction of the grains in the channel portion 122 is from the first conductor portion 121 to the second conductor portion 123 (the thickness direction of the channel portion 122), the grains in the channel portion 122 are single grains in the thickness direction of the channel portion 122. The growth direction of the grains in the channel portion 122 is consistent with the movement of carriers, which can realize a single-crystal channel structure, thereby improving the carrier mobility.

[0081] The crystal grains of the channel portion 122 are arranged in a multi-crystal arrangement in the extending direction parallel to the substrate 11 .

[0082] It should be noted that the direction of extension parallel to the substrate 11 is the first direction x. The orthographic projection direction z of the semiconductor device 100 is also the thickness direction of each film layer. The long axis direction of the channel portion 122 is the second direction y. The first direction x and the second direction y intersect. Optionally, the first direction x is perpendicular to the second direction y; in some embodiments, the angle between the first direction x and the second direction y is acute.

[0083] Optionally, the slope angle α of the active structure layer 12 is between 80 degrees and 90 degrees. This configuration allows the inversion carriers of the active structure layer to be mainly concentrated on the surface, and the current from the source to the drain also flows on the surface. Therefore, controlling the slope angle α between 80 degrees and 90 degrees can ensure that the carrier movement direction moves along the grain growth direction of the channel portion 122.

[0084] It should be understood that when the slope angle α is too large or too small, carriers will cross the grain boundaries, resulting in a decrease in mobility.

[0085] Optionally, the slope angle α can be 80 degrees, 81 degrees, 82 degrees, 83 degrees, 84 degrees, 85 degrees, 86 degrees, 87 degrees, 88 degrees, 89 degrees or 90 degrees. When the slope angle α is 90 degrees, the carrier mobility is the best.

[0086] Optionally, the thickness of the channel portion 122 is between 5 nanometers and 1 micron. It should be understood that if the thickness of the channel portion 122 is too small, the short channel effect cannot be overcome, while if it is too thick, film crystallization becomes difficult. Therefore, selecting a thickness of the channel portion 122 between 5 nanometers and 1 micron can both overcome the short channel effect and reduce the difficulty of film crystallization.

[0087] Optionally, the thickness of the channel portion 122 may be 5 nanometers, 6 nanometers, 7 nanometers, 8 nanometers, 9 nanometers, 10 nanometers, 50 nanometers, 0.1 micrometer, 0.2 micrometer, 0.3 micrometer, 0.4 micrometer, 0.5 micrometer, 0.6 micrometer, 0.7 micrometer, 0.8 micrometer, 0.9 micrometer, or 1 micrometer.

[0088] Optionally, the material of the first conductor portion 121 and the second conductor portion 123 may be a polysilicon layer doped or implanted with conductive ions, and the conductive ions may be N-type doped ions or P-type doped ions, such as phosphorus ions, boron ions, gallium ions, or indium ions.

[0089] Of course, the materials of the first conductor portion 121 and the second conductor portion 123 may also be conductive materials, but are not limited thereto.

[0090] Optionally, the thickness of the first conductor portion 121 and the second conductor portion 123 is respectively between 30 nm and 300 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm.

[0091] The thickness of the first conductor portion 121 and the second conductor portion 123 is selected to be between 30 nm and 300 nm, which avoids excessive resistance of the first conductor portion 121 and the second conductor portion 123 and also avoids excessive film formation time and serious particle diffusion.

[0092] Optionally, in some embodiments, the material of the channel portion 122 may also be other semiconductor materials, such as metal oxide.

[0093] One of the first electrode 151 and the second electrode 152 is a source electrode, and the other of the first electrode 151 and the second electrode 152 is a drain electrode.

[0094] The gate 14, the first electrode 151, and the second electrode 152 can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements. Furthermore, the gate 14, the first electrode 151, and the second electrode 152 can have a single-layer structure or a stacked structure of two or more layers.

[0095] Optionally, the semiconductor device 100 may further include a buffer layer 16 disposed between the substrate 11 and the first conductor portion 121 .

[0096] The materials of the first insulating layer 13 and the buffer layer 16 may be formed of a plurality of inorganic layers stacked in an alternating manner. For example, the first insulating layer 13 may be formed as a double layer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide, magnesium oxide, and titanium oxide, or a multilayer formed by alternately stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide, magnesium oxide, and titanium oxide. However, the present disclosure is not limited thereto, and the first insulating layer 13 and the buffer layer 16 may be formed as a single inorganic layer including the above-mentioned insulating materials.

[0097] Optionally, the substrate 11 may be a rigid substrate or a flexible substrate. The material of the substrate 11 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene diphthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefin, polyimide, or polyurethane.

[0098] Optionally, the gate 14 includes a first gate 141 and a second gate 142. The first gate 141 is located on one side of the active structure layer 12, and the second gate 142 is located on the other side of the active structure layer 12.

[0099] The thin film transistor TFT adopts dual-gate control, which has a strong ability to control the short channel effect and suppress leakage current, as well as a strong electrostatic control capability for the inversion channel.

[0100] In a direction z perpendicular to the orthographic projection of the semiconductor device 100, that is, in a first direction x, one side surface of the first conductor portion 121, one side surface of the channel portion 122, and one side surface of the second conductor portion 123 are all arranged to overlap with the first gate 141. The other side surface of the first conductor portion 121, the other side surface of the channel portion 122, and the other side surface of the second conductor portion 123 are all arranged to overlap with the second gate 142.

[0101] In addition to overlapping with the channel portion 122 , the first gate 141 and the second gate 142 also overlap with the first conductor portion 121 and the second conductor portion 123 , so as to improve the control capability of the gate 14 .

[0102] Optionally, the active structure layer 12 includes a first side surface 12a and a second side surface 12b disposed opposite each other. A first gate 141 covers the side of the first insulating layer 13 facing the first side surface 12a. A second gate 142 covers the side of the first insulating layer 13 facing the second side surface 12b. The first insulating layer 13 includes a top portion 131, which covers the side of the active structure layer 12 away from the substrate 11.

[0103] In the orthographic projection direction z of the semiconductor device 100 , the first gate 141 and the second gate 142 are flush with the side of the top 131 away from the substrate 11 . This arrangement can improve the controllability of the first gate 141 and the second gate 142 .

[0104] Optionally, the thickness of the first insulating layer 13 is smaller than the thickness of the first conductor portion 121. This arrangement allows the gate 14 to overlap with the side surface of the first conductor portion 121 in the first direction x, ensuring that the gate 14 has a strong control capability.

[0105] In some embodiments, grooves or openings may also be provided on the buffer layer 16 , and the grooves or openings are located on both sides of the active structure layer 12 , so that the first insulating layer 13 covers the grooves or openings, so that the gate 14 can overlap with the side surfaces of the first conductor portion 121 in the first direction x, or even completely overlap with the side surfaces of the first conductor portion 21 .

[0106] Optionally, the first conductor portion 121 is not provided on the side of the active structure layer 12 on the side of the gate 14 close to the substrate 11. This arrangement avoids the generation of parasitic capacitance between the gate 14 and the first conductor portion 121, thereby avoiding the GIDL (Gate-induced Drain Leakage) effect.

[0107] Optionally, the number of thin film transistors TFT is at least two. In the orthographic projection pattern of the semiconductor device 100 (as shown in FIG1 ), the gates 14 and the active structure layers 12 are alternately and spaced apart along a first direction x, which is perpendicular to the long axis direction y of the channel portion 122 .

[0108] Each thin film transistor TFT includes two gate electrodes 14 . In the same thin film transistor TFT, one gate electrode 14 is disposed on one side of the active structure layer 12 , and the other gate electrode 14 is disposed on the other side of the active structure layer 12 .

[0109] Two adjacent thin film transistors TFT share a first electrode 151 , a second electrode 152 and a gate electrode 14 ; such a configuration can save materials and layout space and reduce process difficulty.

[0110] Since the active structure layer 12 is prepared first and then the first insulating layer 13 is formed, the first insulating layer 13 forms a recessed portion ax between adjacent active structure layers 12, and the gate 14 can be directly formed in the recessed portion ax. The upper and lower positions of the gate 14 are determined by the depth of the recessed portion ax, which can achieve a self-aligned gate effect, thereby reducing the difficulty of the process.

[0111] Optionally, the semiconductor device 100 further includes a first connection portion 171, which is provided in the same layer as the first conductor portion 121. The first connection portion 171 is connected to one side of the first conductor portion 121 of at least two thin film transistors TFT. The first electrode 151 is connected to the first connection portion 171 through a first via k1.

[0112] The semiconductor device 100 further includes a second connection portion 172, which is provided in the same layer as the second conductor portion 123. The second connection portion 172 is connected to one side of the second conductor portion 123 of at least two thin film transistors TFT. The second electrode 152 is connected to the second connection portion 172 through a second via k2.

[0113] The first conductor portion 121 and the first connecting portion 171 are disposed on the same layer and connected thereto. The first connecting portion 171 and the first conductor portion 121 may be made of the same material and may be formed using the same photomask. In other words, the first connecting portion 171 and the first conductor portion 121 may be made of the same material and may be integrally formed. In some embodiments, the first connecting portion 171 and the first conductor portion 121 may be disposed on different layers and may be made of different materials.

[0114] Secondly, the first via hole k1 is located at the center of the first connecting portion 171 , so that the distance from the center of the first via hole k1 to each first conductor portion 121 is equal, thereby improving the synchronization of signal transmission.

[0115] The second conductor portion 123 and the second connecting portion 172 are arranged in the same layer and connected. They can be made of the same material and can be produced using the same photomask. The second connecting portion 172 and the second conductor portion 123 are made of the same material and are integrally formed. In some embodiments, the second connecting portion 172 and the second conductor portion 123 can also be arranged in different layers and made of different materials.

[0116] Secondly, the second via hole k2 is located at the center of the second connecting portion 172 , so that the distance from the center of the second via hole k2 to each second conductor portion 123 is equal, thereby improving the synchronization of signal transmission.

[0117] Optionally, in the orthographic projection pattern of the semiconductor device 100 , the pattern of the first via holes k1 and the pattern of the second via holes k2 are symmetrically arranged about the first direction x-axis, which can shorten the signal transmission distance and improve the signal transmission rate.

[0118] Optionally, the first connection portion 171 and the second connection portion 172 are both extended along the first direction x, the first conductor portion 121 and the second conductor portion 123 are both extended along the second direction y, and the first direction x is perpendicular to the second direction y. Such a configuration can reduce layout space.

[0119] Optionally, the semiconductor device 100 further includes a third connecting portion 173, which is provided in the same layer as the gate 14. The third connecting portion 173 is connected to one side of the gate 14 of at least two thin film transistors TFT.

[0120] In the orthographic projection direction z of the semiconductor device 100, a second insulating layer 18 is provided between the first connecting portion 171 and the third connecting portion 173. The second insulating layer 18 covers the first connecting portion 171 and exposes the first conductor portion 121. The third connecting portion 173 is provided on a side of the second insulating layer 18 away from the substrate 11.

[0121] Optionally, the third connection portion 173 and the gate 14 are made of the same material and are integrally formed. In some embodiments, the third connection portion 173 and the gate 14 may be provided in different layers and made of different materials.

[0122] Optionally, the semiconductor device 100 further includes a fourth connection portion 174 and a fifth connection portion 175. The fourth connection portion 174 is provided in the same layer as the first conductor portion 121. The fourth connection portion 174 is connected to the other side of the first conductor portion 121 of at least two thin film transistors TFT.

[0123] That is, the first connection portion 171 and the fourth connection portion 174 are located on opposite sides of the first conductor portion 121 .

[0124] The fifth connection portion 175 is provided in the same layer as the channel portion 122. The fifth connection portion 175 is connected to one side of the channel portion 122 of at least two thin film transistors TFT.

[0125] The second connection portion 172 , the fourth connection portion 174 and the fifth connection portion 175 all extend along the first direction x. In the orthographic projection direction z of the semiconductor device 100 , the second connection portion 172 , the fourth connection portion 174 and the fifth connection portion 175 are overlapped.

[0126] The overlapping arrangement of the second connection portion 172 , the fourth connection portion 174 and the fifth connection portion 175 can improve the flatness and stability of the second connection portion 172 and avoid the risk of the second connection portion 172 being disconnected due to step differences.

[0127] The fifth connection portion 175 is made of the same material as the channel portion 122 and is integrally formed. The first connection portion 171 and the fourth connection portion 174 are made of the same material as the first conductor portion 121 and are integrally formed.

[0128] Optionally, the channel portion 122 and the second conductor portion 123 extend along the long axis direction y of the channel portion 122 and cover a portion of the second insulating layer 18 .

[0129] It should be understood that the channel portion 122 and the second conductor portion 123 are patterned using a photolithography process. Due to errors in mask alignment and exposure errors of the exposure machine, the patterns of the channel portion 122 and the second conductor portion 123 may be offset. If the designed pattern is exactly located at the boundary of the second insulating layer 18, due to the influence of the error, the actual pattern of the channel portion 122 and the second conductor portion 123 may move downward toward the boundary of the second insulating layer 18. Then, when the pattern is etched, the etching solution will continue to etch the first conductor portion after etching the channel portion and the second conductor layer, causing the first conductor portion 121 to be disconnected from the first connecting portion 171.

[0130] The channel portion 122 and the second conductor portion 123 are used to overlap the second insulating layer 18 in order to overcome errors and ensure that the first conductor portion 121 and the first connecting portion 171 are effectively connected.

[0131] The method for preparing the semiconductor device 100 of this embodiment is as follows:

[0132] Referring to FIG4 , step B1, a buffer layer 16 and a patterned first conductive layer NP1 are sequentially formed on the substrate 11. The first conductive layer NP1 includes a first conductive portion 121, a first connecting portion 171, and a fourth connecting portion 174. The first connecting portion 171 and the fourth connecting portion 174 are connected to the first conductive portion 121 and are arranged opposite to each other in the second direction y.

[0133] 5 , in step B2 , a patterned second insulating layer 18 is formed on the first conductive layer NP1 . The second insulating layer 18 covers the first connecting portion 171 and exposes the first conductive portion 121 and the fourth connecting portion 174 .

[0134] Referring to FIG. 6 , in step B3, a channel layer P1 and a second conductor layer NP2 are sequentially formed on the buffer layer 16. Subsequently, the same photomask is used to pattern the channel layer P1 and the second conductor layer NP2. The channel layer P1 includes a channel portion 122 and a fifth connecting portion 175, and the second conductor layer NP2 includes a second conductor portion 123 and a second connecting portion 172. The first conductor portion 121, the channel portion 122, and the second conductor portion 123 are stacked to form the active structure layer 12.

[0135] 7 , step B4 is to form a first insulating layer 13 on the second conductive layer NP2 . The first insulating layer 13 covers the active structure layer 12 , the buffer layer 16 , and the second insulating layer 18 .

[0136] 8 , step B5 , a patterned gate layer Ga is formed on the second insulating layer 18 . The gate layer Ga includes the gate electrode 14 and a third connecting portion 173 . The third connecting portion 173 overlaps with the first connecting portion 171 .

[0137] Optionally, a gate layer Ga may be formed on the entire surface of the second insulating layer 18 first, and then the gate layer Ga on the side of the active structure layer 12 away from the substrate 11 may be removed by chemical mechanical polishing (CMP) technology, and then the gate layer Ga may be patterned by a photolithography process to form the gate 14 and the third connecting portion 173.

[0138] Referring to FIG9 , step B6, a third insulating layer 19 and a source / drain metal layer SD are sequentially formed on the gate layer Ga. The third insulating layer 19 covers the gate layer Ga and the first insulating layer 13. A first via k1 and a second via k2 are provided on the third insulating layer 19. The first via k1 penetrates the third insulating layer 19, the first insulating layer 13, and the second insulating layer 18. The second via k2 penetrates the third insulating layer 19 and the first insulating layer 13.

[0139] The source / drain metal layer SD includes a first electrode 151 and a second electrode 152 . The first electrode 151 is connected to the first connection portion 171 through a first via hole k1 , and the second electrode 152 is connected to the second connection portion 172 through a second via hole k2 .

[0140] The above is the process of the method for manufacturing the semiconductor device 100 according to the embodiment of the present application. Optionally, in some embodiments, the first conductor layer NP1, the channel layer P1, and the second conductor layer NP2 may be formed in sequence and then subjected to a single photomask process.

[0141] Accordingly, an embodiment of the present application further provides a display panel, which includes the semiconductor device 100 as described in any of the above embodiments. That is, the structure of the semiconductor device of the display panel of this embodiment is similar to or the same as the structure of the semiconductor device 100 of the above embodiments.

[0142] The display panel of the embodiment of the present application includes a semiconductor device 100, which uses a first conductor portion, a channel portion, and a second conductor portion to stack to form a vertical active structure layer to achieve a narrow channel; and the growth direction of the grains in the channel portion is set to be consistent with the movement of carriers, which can achieve a single-crystal channel structure, thereby improving the carrier mobility.

[0143] Accordingly, an embodiment of the present application further provides a chip, which includes the semiconductor device 100 as described in any of the above embodiments. That is, the structure of the semiconductor device of the chip of this embodiment is similar to or the same as the structure of the semiconductor device 100 of the above embodiments.

[0144] The chip of the embodiment of the present application includes a semiconductor device 100, which uses a first conductor part, a channel part and a second conductor part to stack to form a vertical active structure layer to realize a narrow channel; and the growth direction of the grains in the channel part is set to be consistent with the movement of carriers, which can realize a single-crystal channel structure, thereby improving the carrier mobility.

[0145] The above is a detailed introduction to a semiconductor device, display panel and chip provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor device comprising: substrate; as well as At least one thin film transistor, wherein the thin film transistor is disposed on the substrate; the thin film transistor comprises: an active structure layer, the active structure layer being arranged on the substrate, the active structure layer comprising a first conductor portion, a channel portion and a second conductor portion, the first conductor portion being arranged on the substrate, the channel portion being arranged on a side of the first conductor portion away from the substrate, and the second conductor portion being arranged on a side of the channel portion away from the substrate; a first insulating layer, wherein the first insulating layer covers the active structure layer and the substrate; A gate, the gate being disposed on the first insulating layer and located on at least one side of the active structure layer, and the gate being disposed overlapping at least a side surface of the channel portion in a direction parallel to an extension direction of the substrate; and a first electrode and a second electrode, the first electrode being connected to the first conductor portion, and the second electrode being connected to the second conductor portion; The material of the channel portion is polysilicon, and the growth direction of the polysilicon grains is consistent with the movement direction of the carriers.

2. The semiconductor device according to claim 1, wherein The slope angle of the active structure layer is between 80 degrees and 90 degrees.

3. The semiconductor device according to claim 1, wherein The thickness of the channel portion is between 5 nanometers and 1 micrometer.

4. The semiconductor device according to claim 2, wherein: The gate comprises a first gate and a second gate, the first gate is located on one side of the active structure layer, and the second gate is located on the other side of the active structure layer; In an extension direction parallel to the substrate, one side surface of the first conductor portion, one side surface of the channel portion, and one side surface of the second conductor portion are all overlapped with the first gate; another side surface of the first conductor portion, another side surface of the channel portion, and another side surface of the second conductor portion are all overlapped with the second gate.

5. The semiconductor device according to claim 4, wherein: The thickness of the first insulating layer is smaller than the thickness of the first conductor portion.

6. The semiconductor device according to claim 4, wherein: The active structure layer comprises a first side surface and a second side surface which are arranged opposite to each other, the first gate covers a side of the first insulating layer which faces the first side surface, the second gate covers a side of the first insulating layer which faces the second side surface, and the first insulating layer comprises a top portion, and the top portion covers a side of the active structure layer which faces away from the substrate; In the orthographic projection direction of the semiconductor device, the first gate and the second gate are both flush with a surface of the top away from the substrate.

7. The semiconductor device according to claim 1, wherein The number of the thin film transistors is at least two, and in an orthographic projection pattern of the semiconductor device, the gates and the active structure layers are alternately and spaced apart along a first direction, wherein the first direction is perpendicular to the long axis direction of the channel portion; Each of the thin film transistors comprises two gates. In the same thin film transistor, one gate is arranged on one side of the active structure layer, and the other gate is arranged on the other side of the active structure layer. Two adjacent thin film transistors share the first electrode, the second electrode and the gate.

8. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises a first connection portion, the first connection portion and the first conductor portion are arranged in the same layer, the first connection portion is connected to one side of the first conductor portion of at least two of the thin film transistors, and the first electrode is connected to the first connection portion through a first via hole; The semiconductor device further includes a second connection portion, which is arranged in the same layer as the second conductor portion, connected to one side of the second conductor portions of at least two thin film transistors, and the second electrode is connected to the second connection portion through a second via hole.

9. The semiconductor device according to claim 8, wherein: The semiconductor device further comprises a third connection portion, the third connection portion is arranged in the same layer as the gate, and the third connection portion is connected to one side of the gate of at least two of the thin film transistors; In the orthographic projection direction of the semiconductor device, a second insulating layer is arranged between the first connection part and the third connection part, the second insulating layer covers the first connection part and exposes the first conductor part, and the third connection part is arranged on a side of the second insulating layer away from the substrate.

10. The semiconductor device according to claim 9, wherein The semiconductor device further comprises a fourth connection portion and a fifth connection portion, wherein the fourth connection portion is disposed in the same layer as the first conductor portion, and the fourth connection portion is connected to the other side of the first conductor portion of at least two of the thin film transistors; The fifth connection portion is provided in the same layer as the channel portion, and the fifth connection portion is connected to one side of the channel portion of at least two of the thin film transistors; The second connection portion, the fourth connection portion and the fifth connection portion all extend along the first direction, and in the orthographic projection direction of the semiconductor device, the second connection portion, the fourth connection portion and the fifth connection portion are overlapped.

11. The semiconductor device according to claim 9, wherein: The channel portion and the second conductor portion extend along a long axis direction of the channel portion and cover a portion of the second insulating layer.

12. The semiconductor device according to claim 9, wherein: The first connection part, the fourth connection part and the first conductor part are made of the same material and are integrally formed, the second connection part and the second conductor part are made of the same material and are integrally formed, the third connection part and the gate are made of the same material and are integrally formed, and the fifth connection part and the channel part are made of the same material and are integrally formed.

13. A display panel, comprising a semiconductor device, wherein the semiconductor device comprises: substrate; as well as at least one thin film transistor, wherein the thin film transistor is disposed on the substrate; The thin film transistor comprises: an active structure layer, the active structure layer being arranged on the substrate, the active structure layer comprising a first conductor portion, a channel portion and a second conductor portion, the first conductor portion being arranged on the substrate, the channel portion being arranged on a side of the first conductor portion away from the substrate, and the second conductor portion being arranged on a side of the channel portion away from the substrate; a first insulating layer, wherein the first insulating layer covers the active structure layer and the substrate; A gate, the gate being disposed on the first insulating layer and located on at least one side of the active structure layer, and the gate being disposed overlapping at least a side surface of the channel portion in a direction parallel to an extension direction of the substrate; and a first electrode and a second electrode, the first electrode being connected to the first conductor portion, and the second electrode being connected to the second conductor portion; The material of the channel portion is polysilicon, the growth direction of the polysilicon grains is consistent with the movement direction of the carriers, and the slope angle of the active structure layer is between 80 degrees and 90 degrees.

14. The display panel according to claim 13, wherein: The thickness of the channel portion is between 5 nanometers and 1 micrometer.

15. The display panel according to claim 14, wherein: The gate comprises a first gate and a second gate, the first gate is located on one side of the active structure layer, and the second gate is located on the other side of the active structure layer; In an extension direction parallel to the substrate, one side surface of the first conductor portion, one side surface of the channel portion, and one side surface of the second conductor portion are all overlapped with the first gate; another side surface of the first conductor portion, another side surface of the channel portion, and another side surface of the second conductor portion are all overlapped with the second gate.

16. The display panel according to claim 15, wherein: The thickness of the first insulating layer is smaller than the thickness of the first conductor portion.

17. A chip, comprising a semiconductor device, wherein the semiconductor device comprises: substrate; as well as at least one thin film transistor, wherein the thin film transistor is disposed on the substrate; The thin film transistor comprises: an active structure layer, the active structure layer being arranged on the substrate, the active structure layer comprising a first conductor portion, a channel portion and a second conductor portion, the first conductor portion being arranged on the substrate, the channel portion being arranged on a side of the first conductor portion away from the substrate, and the second conductor portion being arranged on a side of the channel portion away from the substrate; a first insulating layer, wherein the first insulating layer covers the active structure layer and the substrate; A gate, the gate being disposed on the first insulating layer and located on at least one side of the active structure layer, and the gate being disposed overlapping at least a side surface of the channel portion in a direction parallel to an extension direction of the substrate; and a first electrode and a second electrode, the first electrode being connected to the first conductor portion, and the second electrode being connected to the second conductor portion; The material of the channel portion is polysilicon, the growth direction of the polysilicon grains is consistent with the movement direction of the carriers, and the slope angle of the active structure layer is between 80 degrees and 90 degrees.

18. The chip according to claim 17, wherein: The thickness of the channel portion is between 5 nanometers and 1 micrometer.

19. The chip according to claim 18, wherein: The gate comprises a first gate and a second gate, the first gate is located on one side of the active structure layer, and the second gate is located on the other side of the active structure layer; In an extension direction parallel to the substrate, one side surface of the first conductor portion, one side surface of the channel portion, and one side surface of the second conductor portion are all overlapped with the first gate; another side surface of the first conductor portion, another side surface of the channel portion, and another side surface of the second conductor portion are all overlapped with the second gate.

20. The chip according to claim 19, wherein: The thickness of the first insulating layer is smaller than the thickness of the first conductor portion.

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