Silicon carbide semiconductor epitaxial wafer and manufacturing method therefor, and silicon carbide semiconductor device

Abstract

The present application provides a silicon carbide semiconductor epitaxial wafer and a manufacturing method therefor, and a silicon carbide semiconductor device. The silicon carbide semiconductor epitaxial wafer comprises: a substrate and an epitaxial layer, wherein the epitaxial layer comprises a buffer layer and a first drift layer arranged on the buffer layer; the first drift layer comprises a plurality of semiconductor stacks stacked in a direction from the substrate to the buffer layer, and each semiconductor stack comprises a first unit and a second unit stacked on the first unit; the first unit comprises a first doped silicon carbide layer; the second unit comprises at least one second doped silicon carbide layer stacked in the direction from the substrate to the buffer layer; the doping concentration of the first doped silicon carbide layer in the same semiconductor stack is greater than that of the second doped silicon carbide layer; and the second unit of at least one of the plurality of semiconductor stacks comprises at least one high-resistance layer. Thus, the current expansion of a semiconductor device is enhanced, the electric leakage characteristic of the semiconductor device is reduced, and the withstand voltage level of the device is improved.

Description

Silicon carbide semiconductor epitaxial wafer and manufacturing method thereof, and silicon carbide semiconductor device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Chinese patent application No. 202311132937X filed on September 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide semiconductor epitaxial wafer and a manufacturing method thereof, and a silicon carbide semiconductor device. Background Art

[0003] Silicon carbide has excellent properties such as high bandgap, high critical electric field, high thermal conductivity and high electron saturation velocity, and is the most prominent candidate for the next generation of power semiconductor devices.

[0004] However, the traditional silicon carbide epitaxial structure consists of a buffer layer and a drift layer. To improve the reverse leakage characteristics of the device and enhance the reverse withstand voltage of the device, the usual method is to reduce the doping concentration of the drift epitaxial layer or increase the thickness of the drift epitaxial layer. However, reducing the doping concentration of the drift epitaxial layer or increasing the thickness of the drift epitaxial layer will increase the series resistance of the device, thereby affecting the forward characteristics of the device. Therefore, how to improve the reverse leakage characteristics of the device and enhance the reverse withstand voltage performance of the device without increasing the series resistance of the device and affecting the forward characteristics of the device is one of the key technical issues. Summary of the Invention

[0005] The present application provides a silicon carbide semiconductor epitaxial wafer and a manufacturing method thereof, which can solve the problem of traditional silicon nitride epitaxial structure devices in which the series resistance of the semiconductor device increases due to the decrease in the doping concentration of the drift epitaxial layer or the increase in the thickness of the drift epitaxial layer, thereby affecting the forward characteristics of the semiconductor device, thereby improving the reverse leakage characteristics of the semiconductor device and enhancing the voltage resistance level of the device.

[0006] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a silicon carbide semiconductor epitaxial wafer, comprising: a substrate; an epitaxial layer, arranged on the substrate, the epitaxial layer including a buffer layer and a first drift layer arranged on the buffer layer; the first drift layer includes a plurality of semiconductor stacking periodic repeating units stacked along the direction from the substrate to the buffer layer, each of the semiconductor stacking layers includes a first unit and a second unit, and the second unit is stacked on the first unit along the direction from the substrate to the buffer layer; the first unit includes a first doped silicon carbide layer, the second unit includes at least one second doped silicon carbide layer stacked along the direction from the substrate to the buffer layer, the doping concentration of the first doped silicon carbide layer in the same semiconductor stacking layer is greater than the doping concentration of the second doped silicon carbide layer; and the second unit of at least one of the plurality of semiconductor stacking layers includes at least one high-resistance layer, wherein the second doped silicon carbide layer and the high-resistance layer are overlapped.

[0007] To solve the above technical problems, another technical solution adopted in this application is to provide a method for manufacturing a silicon carbide semiconductor epitaxial wafer, comprising:

[0008] The invention relates to a step of providing a substrate; a step of forming a buffer layer on the substrate; a step of forming a plurality of semiconductor stacks on the buffer layer, wherein the step of forming each semiconductor stack comprises a step of forming a first doped silicon carbide layer, a step of forming a second doped silicon carbide layer and a step of forming a high resistance layer; each of the semiconductor stacks comprises a first unit and a second unit, the second unit being stacked on the first unit along the direction from the substrate to the buffer layer; the first unit comprises a first doped silicon carbide layer, the second unit comprises at least one second doped silicon carbide layer stacked along the direction from the substrate to the buffer layer, the doping concentration of the first doped silicon carbide layer in the same semiconductor stack is greater than the doping concentration of the second doped silicon carbide layer; and the second unit of at least one of the plurality of semiconductor stacks comprises at least one high resistance layer, wherein the second doped silicon carbide layer is overlapped with the high resistance layer.

[0009] In order to solve the above technical problems, another technical solution adopted in this application is: to provide a silicon carbide semiconductor device, including the above-mentioned silicon carbide epitaxial wafer.

[0010] The beneficial effect of the present application is that, different from the prior art, the present application provides a silicon carbide semiconductor epitaxial wafer and a manufacturing method thereof, and a silicon carbide semiconductor device. The silicon carbide semiconductor epitaxial wafer is configured to have a drift layer as a multilayer stack design including multiple layers of semiconductor stacks with high and low doping, and at least one semiconductor stack contains a high-resistance insertion layer. The multilayer stack setting of high and low doping semiconductor stacks can effectively reduce the leakage characteristics of the device, improve the device voltage resistance level, and achieve a higher blocking voltage; at the same time, the high resistivity and high breakdown field strength characteristics of the high-resistance insertion layer can be utilized to enhance the current expansion of the device, improve the current expansion capability during forward conduction, reduce the heat loss of the device during operation, and improve the switching characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0012] FIG1 is a schematic structural diagram of an embodiment of a silicon carbide semiconductor epitaxial wafer provided by the present application;

[0013] FIG2 is a schematic structural diagram of a first drift layer of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0014] FIG3 is a schematic structural diagram of a first drift layer of another embodiment of a silicon carbide semiconductor epitaxial wafer provided by the present application;

[0015] FIG4 is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0016] FIG5 is a schematic structural diagram of a semiconductor stack according to another embodiment of a silicon carbide semiconductor epitaxial wafer provided by the present application;

[0017] FIG6( a ) is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0018] FIG6( b ) is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0019] FIG7( a ) is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0020] FIG7( b ) is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0021] FIG8( a ) is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0022] FIG8( b ) is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;

[0023] FIG9( a ) is a schematic diagram showing that the doping concentration of a conventional silicon carbide semiconductor epitaxial wafer does not change with increasing epitaxial thickness;

[0024] FIG9( b ) is a schematic diagram showing how the doping concentration of a silicon carbide semiconductor epitaxial wafer according to an embodiment of the present application changes as the number of semiconductor stacks increases;

[0025] FIG9( c ) is a schematic diagram showing how the doping concentration of the silicon carbide semiconductor epitaxial wafer of FIG5( a ) changes as the number of semiconductor stacks increases;

[0026] FIG9( d ) is a schematic diagram showing how the doping concentration of the silicon carbide semiconductor epitaxial wafer of FIG5( b ) changes as the number of semiconductor stacks increases;

[0027] FIG9( e ) is a schematic diagram showing how the doping concentration of the silicon carbide semiconductor epitaxial wafer of FIG6( a ) changes as the number of semiconductor stacks increases;

[0028] FIG9( f ) is a schematic diagram showing how the doping concentration of the silicon carbide semiconductor epitaxial wafer of FIG6( b ) changes as the number of semiconductor stacks increases;

[0029] FIG9( g ) is a schematic diagram showing how the doping concentration of the silicon carbide semiconductor epitaxial wafer of FIG7( a ) changes as the number of semiconductor stacks increases;

[0030] FIG9(h) is a schematic diagram showing how the doping concentration of the silicon carbide semiconductor epitaxial wafer of FIG7(b) changes with the increase of semiconductor stacking layers;

[0031] FIG10 is a schematic flow chart of an embodiment of a method for manufacturing a silicon carbide semiconductor epitaxial wafer provided by the present application;

[0032] FIG11 is a schematic flow chart of a specific embodiment of step S3 in FIG10 ;

[0033] FIG12 is a schematic structural diagram of another embodiment of the silicon carbide semiconductor epitaxial wafer provided in the present application.

[0034] Description of labels:

[0035] Silicon carbide semiconductor epitaxial wafer 100; substrate 10; epitaxial layer 20; buffer layer 21; first drift layer 22; semiconductor stack A; first unit 221, second unit 222; first doped silicon carbide layer A1; second doped silicon carbide layer A2; first doped silicon carbide sublayer A21; second doped silicon carbide sublayer A22; high resistance layer A3; first high resistance sublayer A31; second high resistance sublayer A32; second drift layer 23. Implementation Method

[0036] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features identified. Therefore, features identified as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional designations in the embodiments of this application (such as up, down, left, right, front, back, etc.) are intended only to illustrate the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional designations will also change accordingly. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to such process, method, product, or apparatus.

[0038] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0039] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0040] Referring to Figures 1 to 4, Figure 1 is a schematic structural diagram of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application; Figure 2 is a schematic structural diagram of a first drift layer of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application; Figure 3 is a schematic structural diagram of a first drift layer of another embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application; Figure 4 is a schematic structural diagram of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application; Figure 5 is a schematic structural diagram of a semiconductor stack of another embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application; Figures 6(a) and 6(b) are schematic structural diagrams of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application; Figures 7(a) and 7(b) are schematic structural diagrams of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application; and Figures 8(a) and 8(b) are schematic structural diagrams of a semiconductor stack of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application.

[0041] As shown in Figures 1-4, a silicon carbide semiconductor epitaxial wafer 100 includes a substrate 10 and an epitaxial layer 20 disposed on the substrate 10. The epitaxial layer 20 includes a buffer layer 21 and a first drift layer 22 disposed on the buffer layer 21. The first drift layer 22 includes a plurality of semiconductor stacks A stacked along the direction from the substrate 10 to the buffer layer 21. Each semiconductor stack A includes a first unit 221 and a second unit 222. The second unit 222 is stacked on the first unit 221 along the direction from the substrate 10 to the buffer layer 21.

[0042] The first unit 221 includes a first doped silicon carbide layer A1, and the second unit 222 includes at least one second doped silicon carbide layer A2 stacked in a direction from the substrate 10 to the buffer layer 21. The doping concentration of the first doped silicon carbide layer A1 is greater than the doping concentration of the second doped silicon carbide layer A2 in the same semiconductor stack A. As shown in FIG3 , the second unit 222 of at least one semiconductor stack A in the plurality of semiconductor stacks A includes at least one high-resistance layer A3, wherein the second doped silicon carbide layer A2 and the high-resistance layer A3 are overlapped. Here, the overlapping arrangement means that when the second unit 222 includes two or more second doped silicon carbide layers A2 and / or two or more high-resistance layers A3, any two second doped silicon carbide layers A2 and / or any two high-resistance layers A3 are not adjacent to each other.

[0043] It should be noted that the second unit 222 includes at least one second doped silicon carbide layer A2, which is generally the first semiconductor stack. The nitrogen doping concentration of the second unit of the semiconductor stack formed later gradually increases. This is actually due to the intentional introduction of a nitrogen source to form a low-doped epitaxial layer. In other words, as the number of semiconductor stacks increases, the concentration of the low-doped epitaxial layer in the second unit gradually increases.

[0044] In some embodiments, the first unit 221 is a first doped silicon carbide layer A1. In other embodiments, the first unit 221 may include more than one first doped silicon carbide layer A1.

[0045] In this way, by setting up a multi-layer stack of high and low doped semiconductor layers, the leakage characteristics of the device can be effectively reduced and the voltage resistance level of the device can be improved.

[0046] In some embodiments, the plurality of semiconductor stacks A includes 2-100 semiconductor stacks.

[0047] Specifically, the number of semiconductor stacks A is adjusted according to the thickness of the first drift layer 22. When the first drift layer 22 is thicker, the number of semiconductor stacks A required is correspondingly greater, and when the first drift layer 22 is thinner, the number of semiconductor stacks A required is correspondingly reduced.

[0048] In some embodiments, the first doped silicon carbide layer A1, the second doped silicon carbide layer A2, and the high-resistance layer A3 are stacked in the same order in each semiconductor stack A. Here, setting the first doped silicon carbide layer A1, the second doped silicon carbide layer A2, and the high-resistance layer A3 in the same order in each semiconductor stack A facilitates the production of semiconductor epitaxial wafers. Of course, in other embodiments, the first doped silicon carbide layer A1, the second doped silicon carbide layer A2, and the high-resistance layer A3 may be stacked in a different order in each semiconductor stack A.

[0049] It should be noted that, in some embodiments, the stacking order of the first doped silicon carbide layer A1, the second doped silicon carbide layer A2 and the high resistance layer A3 in each semiconductor stack A is the same, and the number of the second doped silicon carbide layer A2 and the high resistance layer A3 in each semiconductor stack A is also the same.

[0050] It should be noted that the first doped silicon carbide layer is formed by introducing a doping gas, such as nitrogen, ammonia, or other nitrogen-containing reaction gas, into the process equipment during the manufacturing process, i.e., an intentionally doped layer. The second doped silicon carbide layer is formed by venting the doping gas from the process equipment without introducing a doping gas during the manufacturing process, i.e., an unintentionally doped layer. Furthermore, the second doped silicon carbide layer can be either an unintentionally doped layer or an intentionally doped layer (for example, when there is no high-resistance layer in the semiconductor stack).

[0051] In some embodiments, the dopant of the first doped silicon carbide layer A1 and the second doped silicon carbide layer A2 is nitrogen, and the high resistance layer A3 is a silicon nitride layer.

[0052] In some embodiments, between any two adjacent semiconductor stacks A in the extension direction of the substrate 10 toward the buffer layer 21, the nitrogen concentration of the first doped silicon carbide layer A1 of the semiconductor stack A close to the substrate 10 is greater than the nitrogen concentration of the first doped silicon carbide layer A1 of the semiconductor stack A away from the substrate 10.

[0053] Specifically, as the number of semiconductor stacks A on the buffer layer 21 increases, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack A formed in the later step is lower than the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack A formed in the previous step. That is, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack A tends to gradually decrease as the number of semiconductor stacks A increases.

[0054] In some embodiments, between any two adjacent semiconductor stacks A in the extension direction of the substrate 10 toward the buffer layer 21, the nitrogen concentration of the second doped silicon carbide layer A2 of the semiconductor stack A close to the substrate 10 is less than the nitrogen concentration of the second doped silicon carbide layer A2 of the semiconductor stack A away from the substrate.

[0055] Specifically, as the number of semiconductor stacks A on the buffer layer 21 increases, the nitrogen concentration of the second doped silicon carbide layer A2 in the semiconductor stack A formed in the subsequent step is greater than the nitrogen concentration of the second doped silicon carbide layer A2 in the semiconductor stack A formed in the previous step. That is, the nitrogen concentration of the second doped silicon carbide layer A1 in the semiconductor stack A gradually increases as the number of semiconductor stacks A increases.

[0056] In this way, by gradually changing the concentration of the first unit and the second unit in each semiconductor stack, the lattice mismatch between the highly doped silicon carbide layer and the low-doped silicon carbide layer can be alleviated, the crystal quality of the epitaxial layer can be improved, and the reliability of the device can be improved.

[0057] In some embodiments, the nitrogen concentration of the first doped silicon carbide layer A1 refers to the average nitrogen concentration of the intentionally doped carbide layer. It should be understood that the distribution of the nitrogen concentration in the first doped silicon carbide layer can be uniform or distributed according to certain rules. For example, the nitrogen concentration on the side close to the substrate 10 is greater than the nitrogen concentration on the side away from the substrate 10. Even the distribution of the nitrogen concentration in the first doped silicon carbide layer can be irregular. In short, between any two adjacent semiconductor stacks A, the average nitrogen concentration of the first doped silicon carbide layer A1 of the semiconductor stack A close to the substrate 10 is greater than the average nitrogen concentration of the first doped silicon carbide layer A1 of the semiconductor stack A away from the substrate 10.

[0058] In some embodiments, between any two adjacent semiconductor stacks A in the extension direction of the substrate 10 toward the buffer layer 21 , the thickness of the second unit 222 in the semiconductor stack A close to the substrate 10 is greater than the thickness of the second unit 222 in the semiconductor stack A away from the substrate 10 .

[0059] Specifically, as the number of semiconductor stacks A on the buffer layer 21 increases, the thickness of the second unit 222 in the semiconductor stack A formed in the later step is smaller than the thickness of the second unit 222 in the semiconductor stack A formed in the previous step. That is, the thickness of the second unit 222 in the semiconductor stack A gradually decreases as the number of semiconductor stacks A increases.

[0060] Furthermore, in some embodiments, in the extension direction from the substrate 10 to the buffer layer 21 , the second unit 222 of each semiconductor stack A includes a high resistance layer A3 ; and each high resistance layer A3 has the same thickness.

[0061] Specifically, as the number of semiconductor stacks A on the buffer layer 21 increases, the second unit of the semiconductor stack A formed in the subsequent step includes a high-resistance layer A3. The thickness of the high-resistance layer A3 of the second unit 222 of the semiconductor stack A formed in the subsequent step is equal to the thickness of the high-resistance layer A3 of the second unit 222 of the semiconductor stack A formed in the previous step. That is, the thickness of the high-resistance layer A3 in the semiconductor stack A remains constant as the number of semiconductor stacks A increases. In this embodiment, as the number of semiconductor stacks A increases, the nitrogen concentration of the second unit in the semiconductor stack also gradually increases. Unintentional doping is actually a type of doping where the concentration cannot be controlled manually. Therefore, to achieve a gradual increase in the nitrogen concentration of the second unit, it is necessary to increase the proportion of the high-resistance layer in the second unit, that is, to increase the thickness of the high-resistance layer or to reduce the thickness of the second doped silicon carbide layer. Since the high-resistance layer in this application is a silicon nitride layer, excessive thickness of the silicon nitride layer will lead to insulation of the semiconductor device. Therefore, the thickness of the high-resistance layer is controlled at the atomic layer level and remains constant in each semiconductor stack, while the thickness of the second doped silicon nitride layer is set to gradually decrease as the number of semiconductor stacks increases.

[0062] In some embodiments, the high-resistance layer A3 has an atomic-level thickness; illustratively, the thickness of the high-resistance layer A3 is greater than 0 and less than 2 nm. For example, the thickness of the high-resistance layer A3 can be 0.1 nm, 0.2 nm, 0.3 nm, 0.4 nm, 1 nm, or 1.5 nm, etc., without limitation. Thus, the atomic-level high-resistance layer A3 can spread the current, improving the current spreading capability during forward conduction, reducing heat loss during device operation, and improving the switching characteristics of the device.

[0063] In some embodiments, the ratio of the thickness of the first unit 221 to the thickness of the second unit 222 in each semiconductor stack A is between 1:1 and 10:1. For example, the ratio of the thickness of the first unit 221 to the thickness of the second unit 222 in each semiconductor stack A can be 2:1, 5:1, 7:1, 9:1, etc., without limitation.

[0064] In some embodiments, as shown in FIG5 , the second unit 222 includes two second doped silicon carbide layers A2 and a high resistance layer A3 , wherein the two second doped silicon carbide layers A2 include a first doped silicon carbide sublayer A21 and a second doped silicon carbide sublayer A22 .

[0065] Exemplarily, the semiconductor stack A includes: a first doped silicon carbide layer A1, a first doped silicon carbide sublayer A21 arranged on the first doped silicon carbide layer A1, a high resistance layer A3 arranged on the first doped silicon carbide sublayer A21, and a second doped silicon carbide sublayer A22 arranged on the high resistance layer A3.

[0066] In other embodiments, as shown in Figures 6(a) and 6(b), when the semiconductor stack A includes a three-layer structure of a first doped silicon carbide layer A1, a second doped silicon carbide layer A2 and a high resistance layer A3, the structure of the semiconductor stack A has two combinations of "first doped silicon carbide layer A1, second doped silicon carbide layer A2, high resistance layer A3" and "first doped silicon carbide layer A1, high resistance layer A3, second doped silicon carbide layer A2".

[0067] In other embodiments, as shown in Figures 7(a) and 7(b), when the semiconductor stack A includes a "first doped silicon carbide layer A1, a first doped silicon carbide sublayer A21, a high resistance layer A3, and a second doped silicon carbide sublayer A22" or a "four-layer structure of a first doped silicon carbide layer A1, a first high resistance sublayer A31, a second doped silicon carbide layer A2, and a second high resistance sublayer A32", the structure of the semiconductor stack A has two combinations of "first doped silicon carbide layer A1, a first doped silicon carbide sublayer A21, a high resistance layer A3, and a second doped silicon carbide sublayer A22" and "first doped silicon carbide layer A1, a first high resistance sublayer A31, a second doped silicon carbide layer A2, and a second high resistance sublayer A32".

[0068] In other embodiments, as shown in FIG8( a) and FIG8( b), when the semiconductor stack A includes a five-layer structure of “a first doped silicon carbide layer A1, a first doped silicon carbide sublayer A21, a first high-resistance sublayer A31, a second doped silicon carbide sublayer A22, and a second high-resistance sublayer A32”, the structure of the semiconductor stack A includes two combinations of “a first doped silicon carbide layer A1, a first doped silicon carbide sublayer A21, a first high-resistance sublayer A31, a second doped silicon carbide sublayer A22, and a second high-resistance sublayer A32” or “a first doped silicon carbide layer A1, a first high-resistance sublayer A31, a first doped silicon carbide sublayer A21, a second high-resistance sublayer A32, and a second doped silicon carbide sublayer A22”. When the semiconductor stack A includes three or more second doped silicon carbide layers A2 or high-resistance layers A3, the corresponding structure can be obtained by recursive deduction according to the aforementioned permutations and combinations, which will not be further described here.

[0069] It should be noted that, in the embodiment of the present application, the first doped silicon carbide sublayer A21 is defined as being closer to the first doped silicon carbide layer A1 than the second doped silicon carbide sublayer A22, and the first high resistance sublayer A31 is closer to the first doped silicon carbide layer A1 than the second high resistance sublayer A32.

[0070] In some embodiments, in the extension direction of the substrate 10 toward the buffer layer 21, between any two adjacent semiconductor stacks A, the thickness of the first doped silicon carbide layer A21 in the semiconductor stack A close to the substrate 10 is greater than the thickness of the first doped silicon carbide sublayer A21 in the semiconductor stack A away from the substrate 10.

[0071] Specifically, as the number of semiconductor stacks A on the buffer layer 21 increases, the thickness of the first doped silicon carbide sublayer A21 in the semiconductor stack A formed in the subsequent step is less than the thickness of the first doped silicon carbide sublayer A21 in the semiconductor stack A formed in the previous step. That is, the thickness of the first doped silicon carbide sublayer A21 in the semiconductor stack A tends to gradually decrease as the number of semiconductor stacks A increases.

[0072] In some embodiments, in the extension direction of the substrate 10 toward the buffer layer 21, between any two adjacent semiconductor stacks A, the thickness of the second doped silicon carbide sublayer A22 in the semiconductor stack A close to the substrate 10 is greater than the thickness of the second doped silicon carbide sublayer A22 in the semiconductor stack A away from the substrate 10.

[0073] Specifically, as the number of semiconductor stacks A on the buffer layer 21 increases, the thickness of the second doped silicon carbide sublayer A22 in the semiconductor stack A formed in the subsequent step is less than the thickness of the second doped silicon carbide sublayer A22 in the semiconductor stack A formed in the previous step. That is, the thickness of the first doped silicon carbide sublayer A22 in the semiconductor stack A gradually decreases as the number of semiconductor stacks A increases.

[0074] It should be noted that the high-resistance layer of the present application is a silicon nitride layer. Excessive thickness of the silicon nitride layer can lead to insulation of the semiconductor device. Therefore, the thickness of the high-resistance layer is controlled to the atomic layer level. The thickness of the high-resistance layer can remain constant in each semiconductor stack, while the thickness of the first doped silicon nitride sublayer and the second doped silicon nitride sublayer can be set to gradually decrease as the number of semiconductor stacks increases. It should be noted that the high-resistance layer can also be made of other high-resistance materials, which is not limited here.

[0075] It should be noted that, in the above embodiment, when the plurality of semiconductor layers are stacked in the same order and the second unit 222 includes the high resistance layer A3, the second doped silicon carbide layer A2 may be an unintentionally doped silicon carbide layer.

[0076] In some embodiments, as shown in FIG11 , the epitaxial layer 20 further includes a second drift layer 23 disposed on the first drift layer 22. The nitrogen concentration of the second drift layer 23 is between the nitrogen concentration of the first unit 221 in the semiconductor stack A farthest from the substrate 10 and the nitrogen concentration of the second unit 222 in the semiconductor stack A farthest from the substrate 10. In other embodiments, the thickness of the second drift layer is greater than or equal to 1 μm. For example, the thickness of the second drift layer can be 1.5 μm, 2 μm, 3 μm, 5 μm, 10 μm, etc., without limitation herein.

[0077] Furthermore, in some embodiments, the nitrogen concentration of the second drift layer is 1E15 / cm 3 ~5E17 / cm 3 The doping concentration of the second drift layer 23 is between 1E15 / cm 3 ~5E17 / cm 3 For example, the doping concentration of the second drift layer 23 can be 5E15 / cm 3 、1E16 / cm 3 、5E16 / cm 3 、1E17 / cm 3 etc., not limited here.

[0078] Referring to Figures 9(a) and 9(b), Figure 9(a) is a schematic diagram showing that the doping concentration of an embodiment of a conventional silicon carbide semiconductor epitaxial wafer does not change with increasing epitaxial thickness; Figure 9(b) is a schematic diagram showing that the doping concentration of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application changes with increasing semiconductor stacking.

[0079] As shown in Figures 9(a) and 9(b), compared with the existing silicon carbide semiconductor epitaxial wafer whose doping concentration does not change with the thickness of the epitaxial layer, the silicon carbide semiconductor epitaxial wafer of the present application has a gradually decreasing doping concentration of the first unit and a gradually increasing doping concentration of the second unit as the number of semiconductor stacks increases. The two gradually approach and eventually approach the doping concentration of the second drift layer, thereby forming a partially doped structure with a gradient concentration.

[0080] As shown in Figures 9(c) to 9(h), in the silicon carbide semiconductor epitaxial wafer of the embodiment of the present application, as the number of semiconductor stacks increases, the doping concentration of the first unit (i.e., the first doped silicon carbide layer A1) gradually decreases, and the doping concentration of the second unit (i.e., at least one high-resistance layer A3 and the second doped silicon carbide layer A2) gradually increases, and the two gradually approach and eventually approach the doping concentration of the second drift layer, thereby forming a partially doped structure with a gradient concentration.

[0081] For example, as shown in Figure 9(c) and Figure 6(a), the second unit is composed of the second doped silicon carbide layer A2 and the high-resistance layer A3, and the structure of the semiconductor stack A is a stack of "first doped silicon carbide layer A1, second doped silicon carbide layer A2, and high-resistance layer A3." As the number of semiconductor stacks increases, that is, along the direction from the substrate to the buffer layer, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack gradually decreases, while the average nitrogen concentration in the second unit composed of the second doped silicon carbide layer A2 and the high-resistance layer A3 gradually increases.

[0082] For example, as shown in Figure 9(d) and Figure 6(b), the second unit is composed of the second doped silicon carbide layer A2 and the high-resistance layer A3, and the structure of the semiconductor stack A is a stack of "first doped silicon carbide layer A1, high-resistance layer A3, and second doped silicon carbide layer A2." As the number of semiconductor stacks increases, that is, along the direction from the substrate to the buffer layer, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack gradually decreases, while the average nitrogen concentration in the second unit composed of the high-resistance layer A3 and the second doped silicon carbide layer A2 gradually increases.

[0083] For example, as shown in Figures 9(e) and 7(b), the second unit comprises a first doped silicon carbide sublayer A21, a high-resistance layer A3, and a second unintentionally doped silicon carbide sublayer A22. The structure of the semiconductor stack A is a stack of "first doped silicon carbide layer A1, first doped silicon carbide sublayer A21, high-resistance layer A3, and second doped silicon carbide sublayer A22." As the number of semiconductor stacks increases, that is, along the direction from the substrate to the buffer layer, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack gradually decreases, while the average nitrogen concentration within the second unit comprising the first doped silicon carbide sublayer A21, high-resistance layer A3, and second doped silicon carbide sublayer A22 gradually increases.

[0084] For example, as shown in Figure 9(f) and Figure 7(a), the second unit is composed of the first high-resistance sublayer A31, the second doped silicon carbide layer A2, and the second high-resistance sublayer A32. The structure of the semiconductor stack A is a stack of "first doped silicon carbide layer A1, first high-resistance sublayer A31, second doped silicon carbide layer A2, and second high-resistance sublayer A32." As the number of semiconductor stacks increases, that is, along the direction from the substrate to the buffer layer, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack gradually decreases, while the average nitrogen concentration in the second unit composed of the first high-resistance sublayer A31, the second doped silicon carbide layer A2, and the second high-resistance sublayer A32 gradually increases.

[0085] For example, as shown in Figure 9(g) and Figure 8(a), the second unit is composed of the first doped silicon carbide sublayer A21, the first high-resistance sublayer A31, the second doped silicon carbide sublayer A22, and the second high-resistance sublayer A32. The structure of the semiconductor stack A is a stacked structure of "first doped silicon carbide layer A1, first doped silicon carbide sublayer A21, first high-resistance sublayer A31, second doped silicon carbide sublayer A22, and second high-resistance sublayer A32." As the number of semiconductor stacks increases, that is, along the direction from the substrate to the buffer layer, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack gradually decreases, while the average nitrogen concentration in the second unit composed of the first doped silicon carbide sublayer A21, the first high-resistance sublayer A31, the second doped silicon carbide sublayer A22, and the second high-resistance sublayer A32 gradually increases.

[0086] For example, as shown in Figures 9(h) and 8(b), the second unit comprises a first high-resistance sublayer A31, a first doped silicon carbide sublayer A21, a second high-resistance sublayer A32, and a second doped silicon carbide sublayer A22. The structure of the semiconductor stack A is a stack of "first doped silicon carbide layer A1, first high-resistance sublayer A31, first doped silicon carbide sublayer A21, second high-resistance sublayer A32, and second doped silicon carbide sublayer A22." As the number of semiconductor stacks increases, that is, along the direction from the substrate to the buffer layer, the nitrogen concentration of the first doped silicon carbide layer A1 in the semiconductor stack gradually decreases, while the average nitrogen concentration within the second unit comprising the first high-resistance sublayer A31, first doped silicon carbide sublayer A21, second high-resistance sublayer A32, and second doped silicon carbide sublayer A22 gradually increases.

[0087] Of course, the second unit can also be a combination of more high-resistance layers A3 and / or more second doped silicon carbide layers A2, as long as the N concentration of the second unit becomes higher along the growth direction and is lower than the N concentration of the second drift layer.

[0088] In some embodiments, the thickness ratio of the first drift layer 22 to the second drift layer 23 is between 100:1 and 1:1. For example, the thickness ratio of the first drift layer 22 to the second drift layer 23 can be 95:1, 80:1, 50:1, 30:1, 10:1, 5:1, 2:1, etc., which is not limited here.

[0089] In some embodiments, the carbon-to-silicon ratio of the buffer layer 21 is between 0.4 and 1.5, and the carbon-to-silicon ratio of the first drift layer 22 is between 0.6 and 2. For example, the carbon-to-silicon ratio of the buffer layer 21 can be 0.5, 0.8, 1.1, 1.2, 1.4, etc., and the carbon-to-silicon ratio of the first drift layer 22 can be 0.7, 0.9, 1.1, 1.5, 1.7, 1.9, etc., without limitation herein.

[0090] In this embodiment, further, the substrate 10 is a conductive silicon carbide substrate or a semi-insulating silicon carbide substrate.

[0091] In this embodiment, further, the off angle on the conductive silicon carbide substrate or the semi-insulating silicon carbide substrate is 2°-8° along the <11-20> direction.

[0092] In some embodiments, the buffer layer 21 includes a doped silicon carbide buffer layer, and the doping concentration of the buffer layer is greater than the doping concentration of the first doped silicon carbide layer A1 in the semiconductor stack A closest to the substrate 10. The doping concentration of the buffer layer 21 is 1E17 / cm 3 ~5E18 / cm 3 For example, the doping concentration of the buffer layer 21 can be 3E17 / cm 3 、5E17 / cm 3 、7E17 / cm 3 、1E18 / cm 3 、5E18 / cm 3 etc., not limited here.

[0093] By configuring the drift layer of the epitaxial silicon carbide substrate with a periodic doping structure, the device current expansion can be enhanced while maintaining the forward characteristics of the device, effectively reducing the leakage characteristics of the device and improving the device's voltage resistance. At the same time, the high resistivity and high breakdown field strength of silicon nitride are utilized to improve the device's voltage resistance. Furthermore, by configuring the semiconductor stack with a gradient concentration structure, the lattice mismatch between highly doped silicon carbide and low-doped silicon carbide can be alleviated, improving the crystal quality of the epitaxial layer.

[0094] It should be noted that the first doped silicon carbide layer has a relatively high doping concentration and can be defined as a highly doped layer; the second doped silicon carbide layer has a relatively low doping concentration and can be defined as a low doping layer. In some embodiments, as shown in FIG7 , the high-resistance layer A3 can be considered a thin film inserted into the second doped silicon carbide layer A2.

[0095] In some embodiments of the present application, a silicon carbide semiconductor device is provided, which includes the silicon carbide epitaxial wafer described in any embodiment of the present application. The silicon carbide epitaxial wafer of the silicon carbide semiconductor device is arranged by a multi-layer stack of high- and low-doped semiconductor layers, which can effectively reduce the leakage characteristics of the device, improve the device's voltage resistance level, and achieve a higher blocking voltage; at the same time, by utilizing the high resistivity and high breakdown field strength characteristics of the high-resistance insertion layer, the device current expansion can be enhanced, the current expansion capability during forward conduction can be improved, the heat loss of the device during operation can be reduced, and the switching characteristics of the device can be improved.

[0096] Referring to Figures 10 and 11, Figure 10 is a schematic flow chart of an embodiment of a method for manufacturing a silicon carbide semiconductor epitaxial wafer provided by the present application; and Figure 11 is a schematic flow chart of a specific embodiment of step S3 in Figure 10. The manufacturing method includes:

[0097] Step S1: providing a substrate.

[0098] In one embodiment, the substrate may be a conductive silicon carbide substrate or a semi-insulating silicon carbide substrate, and the off angle on the conductive silicon carbide substrate or the semi-insulating silicon carbide substrate is 2°-8° along the <11-20> direction.

[0099] Step S2: forming a buffer layer on the substrate

[0100] Specifically, the step of forming the buffer layer on the substrate includes: heating the substrate, depositing silicon carbide on the heated substrate, and thereby forming the buffer layer.

[0101] In one embodiment, the thickness of the buffer layer is 0.1 μm-5 μm. For example, the thickness of the buffer layer can be 0.3 μm, 1 μm, 2 μm, 3 μm, 4.5 μm, etc., which is not limited here.

[0102] In one embodiment, before forming the buffer layer on the substrate, the substrate may be etched using a reaction / process gas, wherein the reaction / process gas is hydrogen.

[0103] In a specific embodiment, the substrate can be placed in a graphite carrier, and the substrate and carrier are transferred to a reaction chamber. The reaction chamber is evacuated to 50mbar~150mbar, H2 is introduced into the reaction chamber at a flow rate of 50L / min-200L / min, the rotation speed of the graphite carrier is 10pm / min~100rpm / min, the temperature is raised to 1500℃-1750℃, and the substrate is etched for 5min-25min. The reaction chamber can be any one of a hot wall or warm wall planetary reaction chamber, a vertical hot wall reaction chamber, and a horizontal hot wall reaction chamber. The doping concentration of the substrate can be 5E18 / cm 3 ~1E19 / cm 3 After etching, a silicon source is introduced into the reaction chamber at a flow rate of 5mL / min-30mL / min, a carbon source is introduced at a flow rate of 20mL / min-100mL / min, and a doping nitrogen source is introduced at a flow rate of 5mL / min-100mL / min. A silicon carbide buffer layer with a thickness of about 0.1μm-5μm is grown at a temperature of 1500℃-1750℃ and a pressure of 50mbar-150mbar.

[0104] Step S3: forming a plurality of semiconductor stacks on the buffer layer, wherein the steps of forming each semiconductor stack include forming a first doped silicon carbide layer, forming a second doped silicon carbide layer, and forming a high resistance layer.

[0105] In one embodiment, each semiconductor stack includes a first unit and a second unit, the second unit being stacked on the first unit along the direction from the substrate to the buffer layer; the first unit includes a first doped silicon carbide layer, and the second unit includes at least one second doped silicon carbide layer stacked along the direction from the substrate to the buffer layer, the doping concentration of the first doped silicon carbide layer in the same semiconductor stack being greater than the doping concentration of the second doped silicon carbide layer; and the second unit of at least one semiconductor stack in the plurality of semiconductor stacks includes at least one high-resistance layer, wherein the second doped silicon carbide layer is overlapped with the high-resistance layer. It should be noted that the description of "the step of forming each semiconductor stack as including the step of forming a first doped silicon carbide layer, the step of forming a second doped silicon carbide layer, and the step of forming a high-resistance layer" is for ease of reference and expanded description and should not be construed as limiting the method of the present application.

[0106] In one embodiment, referring to FIG. 11 and FIG. 5 , the step of forming a plurality of semiconductor stacks on the buffer layer, wherein the step of forming each semiconductor stack includes the step of forming a first doped silicon carbide layer, the step of forming a second doped silicon carbide layer, and the step of forming a high-resistance layer, wherein the second unit is two second doped silicon carbide layers and one high-resistance layer, wherein the two second doped silicon carbide layers include a first doped silicon carbide sublayer and a second doped silicon carbide sublayer, comprises:

[0107] S31: performing a step of forming a first doped silicon carbide layer to prepare the first doped silicon carbide layer.

[0108] Specifically, a reaction gas and a doping gas are introduced to form a first doped silicon carbide layer on the buffer layer or the upper semiconductor stack, wherein the reaction gas includes a carbon source gas and a silicon source gas.

[0109] In a specific embodiment, a silicon source is introduced into the reaction chamber at a flow rate of 100 mL / min-350 mL / min, a carbon source is introduced at a flow rate of 50 mL / min-200 mL / min, and a doping nitrogen source is introduced at a flow rate of 10 mL / min-100 mL / min. A 0.1 μm-5 μm thick silicon carbide layer, i.e., a first doped silicon carbide layer, is grown at a temperature of 1500° C.-1750° C. and a pressure of 50 mbar-150 mbar.

[0110] S32: performing a step of forming a second doped silicon carbide layer on the first doped silicon carbide layer to prepare a first doped silicon carbide sub-layer.

[0111] Specifically, after step S31 , the reaction gas is continued to be introduced and the introduction of the doping gas is stopped, so as to form a first doped silicon carbide sub-layer on the first doped silicon carbide layer.

[0112] In a specific embodiment, after the first doped silicon carbide layer is grown, the valve state of the doped nitrogen source is switched from run to vent, and the silicon source and carbon source are continued to be introduced at the original flow rate, and a 0.1μm-0.5μm thick silicon carbide layer is grown at a temperature of 1500℃-1750℃ and a pressure of 50mbar~150mbar. The silicon carbide layer is the first doped silicon carbide sublayer.

[0113] S33: Performing a step of forming a high resistance layer on the first doped silicon carbide sub-layer to prepare a high resistance layer

[0114] Specifically, after step S32, the silicon source gas and the nitrogen source gas are continued to be introduced into the reaction gas, and the carbon source gas is stopped from being introduced into the reaction gas, thereby forming the high-resistance layer on the first doped silicon carbide sublayer. The high-resistance layer can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or other methods.

[0115] In a specific embodiment, after forming the first doped silicon carbide sublayer, the carbon source is turned off, and the doping nitrogen source and silicon source are turned on while keeping the original flow rate unchanged to grow a thin silicon nitride layer, which is the high-resistance layer.

[0116] S34: performing a step of forming a second doped silicon carbide layer on the high resistance layer to prepare a second doped silicon carbide sub-layer.

[0117] Specifically, after step S33 , the reaction gas is continued to be introduced and the introduction of the doping gas is stopped, so as to form a second doped silicon carbide sub-layer on the high-resistance layer.

[0118] In a specific embodiment, after the high-resistance layer is formed, the nitrogen source is turned off, and the silicon source and carbon source are continued to be introduced at the original flow rate, and a 1μm-0.5μm thick silicon carbide layer is grown at a temperature of 1500℃-1750℃ and a pressure of 50mbar~150mbar. The silicon carbide layer is the second doped silicon carbide sublayer.

[0119] It should be noted that the steps of the above-mentioned method for manufacturing the silicon carbide semiconductor epitaxial wafer can be arbitrarily combined and the order can be changed to complete the preparation of the above-mentioned silicon carbide semiconductor epitaxial wafer.

[0120] In one embodiment, the manufacturing method further includes the step of forming a second drift layer on the first drift layer, wherein the second drift layer is a silicon nitride layer.

[0121] Specifically, after the first drift layer is grown, a silicon carbide layer with a predetermined thickness is deposited on the first drift layer to form the second drift layer.

[0122] In some embodiments, the growth rate of the first drift layer is 10 μm / h-100 μm / h, and the growth rate of the buffer layer is 1 μm / h-20 μm / h. For example, the growth rate of the first drift layer may be 10 μm / h, 20 μm / h, 35 μm / h, 50 μm / h, 60 μm / h, 75 μm / h, 90 μm / h, 95 μm / h, etc., and the growth rate of the buffer layer may be 1 μm / h, 3 μm / h, 5 μm / h, 7 μm / h, 9 μm / h, 13 μm / h, 15 μm / h, 17 μm / h, 19 μm / h, etc., without limitation herein.

[0123] In some embodiments, the buffer layer and the first drift layer are formed at a temperature of 1500° C. to 1750° C. and a pressure of 50 mbar to 150 mbar. For example, the buffer layer, the first drift layer, and the second drift layer may be formed at temperatures of 1525° C., 1550° C., 1600° C., 1650° C., 1700° C., 1725° C., etc., and the pressures may be formed at 60 mbar, 75 mbar, 90 mbar, 105 mbar, 120 mbar, 145 mbar, etc., without limitation herein.

[0124] In some embodiments, the growth rate of the second drift layer is 10 μm / h-100 μm / h, the temperature for forming the second drift layer is 1500° C.-1750° C., and the pressure is 50 mbar-150 mbar.

[0125] In some embodiments, as shown in FIG. 12 , the comprehensive resistivity of the epitaxial layer 20 is equal to the comprehensive resistivity of the second drift layer 23 .

[0126] In some embodiments, the method for manufacturing a silicon carbide semiconductor epitaxial wafer further includes, after the growth of the epitaxial layer 20 is completed, shutting off the reaction source gas, cooling the reaction chamber to 600° C. to 900° C., and then transferring the substrate and the carrier out of the reaction chamber.

[0127] It should be noted that those skilled in the art should understand that the specific implementation methods of the above-mentioned manufacturing method embodiments and the technical effects brought about by the manufacturing method embodiments have been described in detail in the embodiments of silicon carbide semiconductor epitaxial wafers and will not be elaborated here.

[0128] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A silicon carbide semiconductor epitaxial wafer, wherein: include: substrate; An epitaxial layer is disposed on the substrate, wherein the epitaxial layer includes a buffer layer and a first drift layer disposed on the buffer layer; The first drift layer includes a plurality of semiconductor stacks stacked along the direction from the substrate to the buffer layer, each of the semiconductor stacks includes a first unit and a second unit, and the second unit is stacked on the first unit along the direction from the substrate to the buffer layer; the first unit includes a first doped silicon carbide layer, and the second unit includes at least one second doped silicon carbide layer stacked along the direction from the substrate to the buffer layer, and the doping concentration of the first doped silicon carbide layer in the same semiconductor stack is greater than the doping concentration of the second doped silicon carbide layer; and the second unit of at least one of the plurality of semiconductor stacks includes at least one high resistance layer, wherein the second doped silicon carbide layer is overlapped with the high resistance layer.

2. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The first unit is a first doped silicon carbide layer.

3. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The plurality of semiconductor stacks includes 2-100.

4. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The stacking order of each of the semiconductor stacks is the same.

5. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The dopant of the first doped silicon carbide layer and the second doped silicon carbide layer is nitrogen, and the high resistance layer is a silicon nitride layer.

6. The silicon carbide semiconductor epitaxial wafer according to claim 5, wherein: In the extension direction of the substrate toward the buffer layer, between any two adjacent semiconductor stacks, the nitrogen concentration of the first doped silicon carbide layer of the semiconductor stack close to the substrate is greater than the nitrogen concentration of the first doped silicon carbide layer of the semiconductor stack far from the substrate.

7. The silicon carbide semiconductor epitaxial wafer according to claim 5, wherein: In the extension direction of the substrate toward the buffer layer, between any two adjacent semiconductor stacks, the nitrogen concentration of the second doped silicon carbide layer of the semiconductor stack close to the substrate is lower than the nitrogen concentration of the second doped silicon carbide layer of the semiconductor stack far from the substrate.

8. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: In the extension direction of the substrate toward the buffer layer, between any two adjacent semiconductor stacks, the thickness of the second unit in the semiconductor stack close to the substrate is greater than the thickness of the second unit in the semiconductor stack far from the substrate.

9. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The second unit of each of the semiconductor stacks includes a high resistance layer; and the thickness of each of the high resistance layers is the same.

10. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The thickness of the high resistance layer is greater than 0 and less than 2 nm.

11. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The ratio of the thickness of the first unit to the thickness of the second unit in each of the semiconductor stacks is between 1:1 and 10:

1.

12. The silicon carbide semiconductor epitaxial wafer according to claim 1, wherein: The nitrogen concentration of the first doped silicon carbide layer of the first unit in each of the semiconductor stacks is 5E15 / cm 3 ~1E17 / cm 3 between.

13. The silicon carbide semiconductor epitaxial wafer according to claim 4, wherein: The second unit is two second doped silicon carbide layers and a high resistance layer, wherein the two second doped silicon carbide layers include: a first doped silicon carbide sublayer and a second doped silicon carbide sublayer; The semiconductor stack includes: the first doped silicon carbide layer, the first doped silicon carbide sublayer disposed on the first doped silicon carbide layer, the high resistance layer disposed on the first doped silicon carbide sublayer, and the second doped silicon carbide sublayer disposed on the high resistance layer.

14. The silicon carbide semiconductor epitaxial wafer according to claim 13, wherein: In the extension direction of the substrate toward the buffer layer, between any two adjacent semiconductor stacks, the thickness of the first doped silicon carbide sublayer in the semiconductor stack close to the substrate is greater than the thickness of the first doped silicon carbide sublayer in the semiconductor stack far from the substrate.

15. The silicon carbide semiconductor epitaxial wafer according to claim 13, wherein: In the extension direction of the substrate toward the buffer layer, between any two adjacent semiconductor stacks, the thickness of the second doped silicon carbide sublayer in the semiconductor stack close to the substrate is greater than the thickness of the second doped silicon carbide sublayer in the semiconductor stack far from the substrate.

16. The silicon carbide semiconductor epitaxial wafer according to claim 4, wherein: The epitaxial layer further includes a second drift layer disposed on the first drift layer; the nitrogen concentration of the second drift layer is between the nitrogen concentration of the first unit in the semiconductor stack farthest from the substrate and the nitrogen concentration of the second unit in the semiconductor stack farthest from the substrate.

17. The silicon carbide semiconductor epitaxial wafer according to claim 14, wherein: The thickness ratio of the first drift layer to the second drift layer is between 100:1 and 1:

1.

18. A method for manufacturing a silicon carbide semiconductor epitaxial wafer, wherein: include: providing a substrate; forming a buffer layer on the substrate; The step of forming a plurality of semiconductor stacks on the buffer layer, wherein the step of forming each semiconductor stack comprises the step of forming a first doped silicon carbide layer, the step of forming a second doped silicon carbide layer and the step of forming a high resistance layer; Each of the semiconductor stacks includes a first unit and a second unit, the second unit is stacked on the first unit along the direction from the substrate to the buffer layer; the first unit includes a first doped silicon carbide layer, the second unit includes at least one second doped silicon carbide layer stacked along the direction from the substrate to the buffer layer, the doping concentration of the first doped silicon carbide layer in the same semiconductor stack is greater than the doping concentration of the second doped silicon carbide layer; and the second unit of at least one of the multiple semiconductor stacks includes at least one high resistance layer, wherein the second doped silicon carbide layer is overlapped with the high resistance layer.

19. The method according to claim 18, wherein: The second unit is two second doped silicon carbide layers and a high resistance layer, wherein the two second doped silicon carbide layers include: a first doped silicon carbide sublayer and a second doped silicon carbide sublayer; The step of forming each semiconductor stack comprises: Performing the step of forming the first doped silicon carbide layer to prepare the first doped silicon carbide layer; Performing the step of forming the second doped silicon carbide layer on the first doped silicon carbide layer to prepare the first doped silicon carbide sub-layer; Performing the step of forming a high resistance layer on the first doped silicon carbide sublayer to prepare a high resistance layer; The step of forming the second doped silicon carbide layer is performed on the high resistance layer to prepare the second doped silicon carbide sub-layer.

20. A silicon carbide semiconductor device, wherein: The invention comprises a silicon carbide epitaxial wafer, wherein the silicon carbide epitaxial wafer comprises: substrate; An epitaxial layer is disposed on the substrate, wherein the epitaxial layer includes a buffer layer and a first drift layer disposed on the buffer layer; The first drift layer includes a plurality of semiconductor stacks stacked along the direction from the substrate to the buffer layer, each of the semiconductor stacks includes a first unit and a second unit, and the second unit is stacked on the first unit along the direction from the substrate to the buffer layer; the first unit includes a first doped silicon carbide layer, and the second unit includes at least one second doped silicon carbide layer stacked along the direction from the substrate to the buffer layer, and the doping concentration of the first doped silicon carbide layer in the same semiconductor stack is greater than the doping concentration of the second doped silicon carbide layer; and the second unit of at least one of the plurality of semiconductor stacks includes at least one high resistance layer, wherein the second doped silicon carbide layer is overlapped with the high resistance layer.

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