Thin film transistor and electronic device

Abstract

The present application provides a thin film transistor and an electronic device. In the thin film transistor, an effective part is arranged on a sidewall of a barrier layer, a second electrode penetrates through a channel layer to be in contact with a second ohmic contact layer, and / or a first electrode penetrates through the barrier layer to be in contact with a first ohmic contact layer, or the first electrode penetrates through the channel layer to be in contact with the first ohmic contact layer, thereby improving the yield of display panels, and reducing the sizes of thin film transistors.

Description

Thin film transistors and electronic devices Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and an electronic device. Background Art

[0002] Integrating pixel driver circuits, gate driver circuits, source driver circuits, and timing controllers on a glass substrate (system on glass, SOG) significantly improves the integration of display panels, reduces reliance on integrated circuit chips, and reduces costs. Implementing SOG requires improving the integration density, maximum operating frequency, and current density of thin-film transistors in existing display panels. These requirements require thin-film transistors with shorter channel lengths, higher mobility, and smaller size.

[0003] To reduce the channel length, existing display devices are designed with a vertical thin-film transistor structure. By depositing the channel on the side of the boss and providing contact layers above and below the boss, the channel length is determined by the distance between the upper and lower contact layers and the angle of the boss. The channel length can be controlled by controlling the thickness and angle of the boss. The thickness and angle of the boss are relatively easy to control in existing processes (with an accuracy of less than 1 micron), which can reduce the channel length and improve mobility. The above design requires that the two contact layers extend out of the channel to connect the source and drain layers. However, in the actual preparation process, it was found that retaining the two contact layers when etching the channel is difficult. The portion of the contact layer that extends beyond the channel is easily etched away during the channel etching process, causing the thin-film transistor to malfunction, resulting in a low yield rate for the thin-film transistor and a low yield rate for the display panel.

[0004] Therefore, existing display devices have a technical problem in that when etching the channel of a vertical thin film transistor, the contact layer is easily etched away, resulting in a low yield rate of the display panel. SUMMARY OF THE INVENTION

[0005] The embodiments of the present application provide a thin film transistor and an electronic device to solve the technical problem that in existing display devices, when etching the channel of a vertical thin film transistor, the contact layer is easily etched away, resulting in a low yield of the display panel.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] An embodiment of the present application provides a thin film transistor, comprising:

[0008] substrate;

[0009] A first ohmic contact layer is provided on one side of the substrate;

[0010] a barrier layer, disposed on a side of the first ohmic contact layer away from the substrate, the barrier layer comprising at least one sidewall;

[0011] a second ohmic contact layer, disposed on a side of the barrier layer away from the first ohmic contact layer;

[0012] a channel layer comprising a first connecting portion, a second connecting portion and an effective portion located on the sidewall, wherein the first connecting portion contacts the first ohmic contact layer, and the second connecting portion is disposed on the second ohmic contact layer;

[0013] a gate insulating layer, disposed on a side of the channel layer away from the second ohmic contact layer;

[0014] a gate layer, disposed on a side of the gate insulating layer away from the channel layer, wherein an orthographic projection of the gate layer in a direction perpendicular to the substrate covers the effective portion;

[0015] an interlayer insulating layer, disposed on a side of the gate layer away from the gate insulating layer;

[0016] a source-drain electrode layer, disposed on a side of the interlayer insulating layer away from the gate layer, the source-drain electrode layer comprising a first electrode and a second electrode;

[0017] Wherein, the second electrode passes through the channel layer and contacts the second ohmic contact layer;

[0018] and / or, the first electrode contacts the first ohmic contact layer through the barrier layer;

[0019] Alternatively, the first connection portion is provided on the first ohmic contact layer, and the first electrode passes through the channel layer and contacts the first ohmic contact layer.

[0020] At the same time, an embodiment of the present application provides an electronic device, which includes a thin film transistor as described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0022] FIG. 1 is a perspective view of a conventional display panel.

[0023] FIG. 2 is a cross-sectional view of the display panel taken along line B1 - B2 in FIG. 1 .

[0024] FIG. 3 is a cross-sectional view of the display panel taken along line A1 - A2 in FIG. 1 .

[0025] FIG4 is a top view of a first film layer structure of a thin film transistor provided in an embodiment of the present application.

[0026] FIG. 5 is an exploded view of the film layers of the thin film transistor in FIG. 4 .

[0027] FIG. 6 is a first B1 - B2 cross-sectional view of the thin film transistor in FIG. 4 .

[0028] FIG. 7 is a cross-sectional view of the thin film transistor taken along line A1 - A2 in FIG. 4 .

[0029] FIG8 is a top view of a second film layer structure of a thin film transistor provided in an embodiment of the present application.

[0030] FIG. 9 is an exploded view of the film layers of the thin film transistor in FIG. 8 .

[0031] FIG10 is a cross-sectional view of the thin film transistor taken along line B1 - B2 in FIG8 .

[0032] FIG11 is a second B1 - B2 cross-sectional view of the thin film transistor in FIG4 .

[0033] FIG12 is a schematic diagram of the structure of a thin film transistor corresponding to each step in the method for manufacturing the thin film transistor in FIG4 .

[0034] FIG13 is a schematic diagram of the structure of the thin film transistor corresponding to each step in the method for manufacturing the thin film transistor in FIG8 . Modes for Carrying Out the Invention

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0036] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0038] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0039] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0040] FIG1 is a perspective view of a conventional display panel, FIG2 is a B1 - B2 cross-sectional view of the display panel in FIG1 , and FIG3 is an A1 - A2 cross-sectional view of the display panel in FIG1 .

[0041] As shown in Figures 1 to 3, with the position of the hole indicated by reference numeral 23, a conventional vertical structure display panel includes a substrate 11, a light-shielding metal 12, a buffer material 13, a first contact layer 14, a boss 15, a second contact layer 16, a channel 17, a first insulating layer 18, a gate 19, a second insulating layer 21, and a source / drain layer 22. As can be seen from Figure 2, by disposing the channel 17 on the side of the boss 15 and disposing the first contact layer 14 and the second contact layer 16 on the upper and lower sides of the boss 15, the channel length can be controlled by the thickness and angle of the boss 15. The thickness of the boss 15 can be easily controlled to less than 1 micron under existing processes, resulting in a smaller channel length and improved mobility. However, as can be seen from Figures 1 to 3, in order to connect the source and drain in the source-drain layer 22 to the first contact layer 14 and the second contact layer 16 respectively, it is necessary to retain the first contact layer 14 and the second contact layer 16 when etching the channel 17. The process is difficult and the first contact layer 14 and the second contact layer 16 are easily etched away when etching the channel 17, resulting in the source-drain layer 22 being unable to connect to the first contact layer 14 and the second contact layer 16. The yield of the thin-film transistor is low, and the yield of the display panel is low. Therefore, the existing display device has a technical problem that the contact layer is easily etched away when etching the channel of the vertically structured thin-film transistor, resulting in a low yield of the display panel.

[0042] In order to solve the above technical problems, the embodiments of the present application provide a thin film transistor and a display panel.

[0043] Figure 4 is a top view of the first film layer structure of the thin film transistor provided in an embodiment of the present application. Figure 5 is an exploded view of the film layers of the thin film transistor in Figure 4; Figure 5 (a) is an exploded view of the first ohmic contact layer of the thin film transistor in Figure 4; Figure 5 (b) is an exploded view of the barrier layer of the thin film transistor in Figure 4; Figure 5 (c) is an exploded view of the second ohmic contact layer of the thin film transistor in Figure 4; Figure 5 (d) is an exploded view of the channel layer of the thin film transistor in Figure 4; and Figure 5 (e) is an exploded view of the gate layer of the thin film transistor in Figure 4. Figure 6 is a first B1-B2 cross-sectional view of the thin film transistor in Figure 4. Figure 7 is an A1-A2 cross-sectional view of the thin film transistor in Figure 4. Figure 8 is a top view of the second film layer structure of the thin film transistor provided in an embodiment of the present application. Figure 9 is an exploded view of the various film layers of the thin-film transistor in Figure 8 ; Figure 9 (a) is an exploded view of the first ohmic contact layer of the thin-film transistor in Figure 8 ; Figure 9 (b) is an exploded view of the barrier layer of the thin-film transistor in Figure 8 ; Figure 9 (c) is an exploded view of the second ohmic contact layer of the thin-film transistor in Figure 8 ; Figure 9 (d) is an exploded view of the channel layer of the thin-film transistor in Figure 8 ; and Figure 9 (e) is an exploded view of the gate layer of the thin-film transistor in Figure 8 . Figure 10 is a B1-B2 cross-sectional view of the thin-film transistor in Figure 8 . The A1-A2 cross-sectional view of the thin-film transistor in Figure 8 is the same as that in Figure 7 . Figure 11 is a second B1-B2 cross-sectional view of the thin-film transistor in Figure 4 . Figure 12 is a schematic diagram of the thin-film transistor structure corresponding to each step in the thin-film transistor manufacturing method in Figure 4 . Figure 13 is a schematic diagram of the thin-film transistor structure corresponding to each step in the thin-film transistor manufacturing method in Figure 8 .

[0044] As shown in FIG. 4 to FIG. 10 , an embodiment of the present application provides a thin film transistor, which includes:

[0045] substrate 31;

[0046] A first ohmic contact layer 34 is provided on one side of the substrate 31;

[0047] a barrier layer 35 disposed on a side of the first ohmic contact layer 34 away from the substrate 31 , the barrier layer 35 including at least one sidewall (e.g., the sidewall on the left side in FIG. 6 );

[0048] A second ohmic contact layer 36 is provided on a side of the barrier layer 35 away from the first ohmic contact layer 34 ;

[0049] The channel layer 37 includes a first connecting portion 371 , a second connecting portion 372 , and an effective portion 373 located on a sidewall thereof. The first connecting portion 371 contacts the first ohmic contact layer 34 , and the second connecting portion 372 is disposed on the second ohmic contact layer 36 .

[0050] a gate insulating layer 38 , disposed on a side of the channel layer 37 away from the second ohmic contact layer 36 ;

[0051] a gate layer 39 disposed on a side of the gate insulating layer 38 away from the channel layer 37 , wherein an orthographic projection of the gate layer 39 in a direction perpendicular to the substrate 31 covers the effective portion 373 ;

[0052] an interlayer insulating layer 41 , disposed on a side of the gate layer 39 away from the gate insulating layer 38 ;

[0053] a source-drain electrode layer 42 , disposed on a side of the interlayer insulating layer 41 away from the gate layer 39 , the source-drain electrode layer 42 including a first electrode 421 and a second electrode 422 ;

[0054] The second electrode 422 passes through the channel layer 37 and contacts the second ohmic contact layer 36;

[0055] and / or, the first electrode 421 passes through the barrier layer 35 and contacts the first ohmic contact layer 34;

[0056] Alternatively, the first connection portion 371 is disposed on the first ohmic contact layer 34 , and the first electrode 421 passes through the channel layer 37 and contacts the first ohmic contact layer 34 .

[0057] An embodiment of the present application provides a thin film transistor, which has an effective portion disposed on a side wall of a barrier layer, and a first connection portion and a second connection portion respectively contacting a first ohmic contact layer and a second ohmic contact layer located above and below the barrier layer. The channel length can be controlled by the thickness and angle of the barrier layer, and the channel length can be reduced using existing processes, thereby reducing the volume of the thin film transistor and improving the mobility. The second electrode is allowed to pass through the channel layer to contact the second ohmic contact layer, so that even if the second ohmic contact layer is over-etched, the second electrode can still work normally with the second ohmic contact layer. The first electrode is allowed to pass through the barrier layer to contact the first ohmic contact layer, or the first electrode is allowed to pass through the channel layer to contact the first ohmic contact layer, so that even if the first ohmic contact layer is over-etched, the first electrode can still work normally with the first ohmic contact layer, thereby improving the yield of the display panel and reducing the size of the thin film transistor.

[0058] Specifically, the second electrode contacts the second ohmic contact layer through the channel layer; and / or the first electrode contacts the first ohmic contact layer through the barrier layer; or, the first connecting portion is provided on the second ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the channel layer, including at least one of the following technical solutions:

[0059] The second electrode contacts the second ohmic contact layer through the channel layer, and the arrangement method of the first electrode is not limited; the first electrode contacts the first ohmic contact layer through the barrier layer, and the arrangement method of the second electrode is not limited; the first connecting portion is arranged on the second ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the channel layer, and the arrangement method of the second electrode is not limited; the second electrode contacts the second ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the barrier layer; the second electrode contacts the second ohmic contact layer, and the first connecting portion is arranged on the second ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the channel layer.

[0060] Specifically, in Figures 4 and 8, the location of the via is indicated by reference numeral 43, and the film layer through which the via passes shall be subject to the actual design. For example, in Figure 4, one via passes through the interlayer insulating layer 41, the gate insulating layer 38, the channel layer 37 and the first ohmic contact layer 34, and the other via passes through the interlayer insulating layer 41, the gate insulating layer 38, the channel layer 37 and the second ohmic contact layer 36. In the following embodiments, the setting method of the via is specifically described with reference to each connection hole.

[0061] In some embodiments, when the second electrode passes through the channel layer and contacts the second ohmic contact layer, at the contact surface between the second ohmic contact layer and the second connecting portion, the upper surface of the second ohmic contact layer coincides with the lower surface of the second connecting portion, and the slopes of the three side surfaces of the second ohmic contact layer that are not in contact with the effective portion are equal to the slope corresponding to the second connecting portion.

[0062] In some embodiments, at the contact surface between the first ohmic contact layer and the barrier layer, the upper surface of the first ohmic contact layer coincides with the lower surface of the barrier layer, and any side surface of the first ohmic contact layer has the same slope as the corresponding side surface of the barrier layer.

[0063] In some embodiments, a side surface of the first ohmic contact layer has the same slope as a side surface of the first connecting portion.

[0064] In some embodiments, the thin film transistor includes a first connection hole, the first connection hole at least penetrates the interlayer insulating layer and the gate insulating layer, and the first electrode contacts the first ohmic contact layer through the first connection hole.

[0065] In some embodiments, the first connection hole further penetrates the barrier layer; or the first connection hole penetrates the barrier layer and the first ohmic contact layer.

[0066] In some embodiments, the first connection hole further passes through the first connection portion; or the first connection hole passes through the first connection portion and the first ohmic contact layer.

[0067] In some embodiments, the thin film transistor includes a second connection hole, the second connection hole at least passes through the interlayer insulating layer, the gate insulating layer and the second connection portion, and the second electrode contacts the second ohmic contact layer through the second connection hole.

[0068] In some embodiments, the second connecting hole also passes through the second connecting portion.

[0069] In some embodiments, in a lateral direction, a width of the second connection portion is smaller than a width of the barrier layer, and in a region where the barrier layer extends beyond the second connection portion, the first electrode contacts the first ohmic contact layer.

[0070] In some embodiments, a ratio of an ion doping concentration of the first ohmic contact layer to an ion doping concentration of the channel layer is greater than or equal to ten to the fifth power.

[0071] In some embodiments, the material of the channel layer includes intrinsic silicon.

[0072] In some embodiments, as shown in FIG6 , when the second electrode 422 passes through the channel layer 37 and contacts the second ohmic contact layer 36, at the interface between the second ohmic contact layer 36 and the second connecting portion 372, the upper surface of the second ohmic contact layer 36 coincides with the lower surface of the second connecting portion 372, and the slopes of the three side surfaces of the second ohmic contact layer 36 not in contact with the effective portion 373 are equal to the slopes corresponding to the second connecting portion 372. By aligning the upper surface of the second ohmic contact layer with the lower surface of the second connecting portion and ensuring that the slopes of the three side surfaces of the second ohmic contact layer not in contact with the effective portion are equal to the slopes corresponding to the second connecting portion, the portion of the second ohmic contact layer that extends beyond the channel layer is removed, reducing process complexity. Furthermore, the channel layer and the second ohmic contact layer can be etched using the same mask. Furthermore, the second electrode passes through the channel layer and contacts the second ohmic contact layer, ensuring proper contact and connection between the second electrode and the second ohmic contact layer. This ensures proper operation of the second electrode and the second ohmic contact layer, thereby improving the yield of the thin film transistor.

[0073] Specifically, as shown in FIG6 , one end of the second ohmic contact layer 36 (e.g., the right end in FIG6 ) and one end of the channel layer 37 (e.g., the right end in FIG6 ) are located in the same plane, and the second electrode 422 passes through the channel layer 37 to contact the second ohmic contact layer 36. By locating one end of the second ohmic contact layer and one end of the channel layer in the same plane, the portion of the second ohmic contact layer that extends beyond the channel layer is removed, thereby reducing process difficulty and improving the yield of the thin film transistor. Furthermore, the second electrode passes through the channel layer to contact the second ohmic contact layer, ensuring normal contact and connection between the second electrode and the second ohmic contact layer, and the second electrode and the second ohmic contact layer function normally.

[0074] Specifically, compared with the current display device that needs to retain the portion of the second ohmic contact layer that extends beyond the channel during channel etching, the embodiment of the present application does not need to retain the portion of the second ohmic contact layer that extends beyond the channel layer, so the process difficulty can be reduced when etching the channel layer of the thin film transistor; and by allowing the second electrode to pass through the channel layer to connect to the second ohmic contact layer, the second electrode can still transmit signals to the second ohmic contact layer, and there is no need to reserve the portion of the second ohmic contact layer that extends beyond the channel layer, so the volume of the thin film transistor can be reduced; and because the signal is still transmitted from the second ohmic contact layer to the channel layer, the channel length can still be controlled by the thickness and angle of the blocking layer, which can improve the mobility of the thin film transistor. While keeping the mobility of the thin film transistor unchanged, the process difficulty is reduced, the yield of the thin film transistor is improved, and the volume of the thin film transistor is reduced.

[0075] Specifically, when designing the second electrode and the second ohmic contact layer, the design of the first electrode and the first ohmic contact layer may not be changed, that is, the first electrode and the first ohmic contact layer are still arranged beyond the barrier layer. For example, the first electrode and the first ohmic contact layer adopt the design of the source / drain layer and the first contact layer in FIG. 3 .

[0076] Specifically, "one end of the first ohmic contact layer 34 and one end of the barrier layer 35 are coplanar" means that one side of the first ohmic contact layer and the barrier layer can be etched using the same mask so that, after etching, one end of the first ohmic contact layer and one end of the barrier layer are coplanar with one another, thereby removing the first ohmic contact layer that extends beyond the barrier layer and the channel layer. Similarly, "one end of the second ohmic contact layer and one end of the channel layer are coplanar" means that one end of the second ohmic contact layer and one end of the barrier layer are coplanar with one another, and "one end of the first ohmic contact layer and one end of the channel layer are coplanar" means that one end of the first ohmic contact layer and one end of the channel layer are coplanar with one another.

[0077] Specifically, the drawings of the embodiments of the present application illustrate the case where the ends of the two film layers are inclined surfaces or vertical planes. It can be understood that the ends of any two contacting film layers can be inclined surfaces or vertical planes, and the drawings of the embodiments of the present application do not show all designs.

[0078] It should be noted that, in the actual process, considering the instability of etching, the ends of the two film layers may not be on the same plane. For example, due to process limitations, the angles of one end of the first ohmic contact layer and one end of the barrier layer are different, or there may be partial misalignment between the ends of the two layers. However, at this time, it is still considered that one end of the first ohmic contact layer and one end of the barrier layer are on the same plane, and the slight difference is only caused by the process error.

[0079] In some embodiments, as shown in FIG10 , at the interface between the first ohmic contact layer 34 and the barrier layer 35, the upper surface of the first ohmic contact layer 34 overlaps with the lower surface of the barrier layer 35, and any side surface of the first ohmic contact layer 34 has the same slope as the corresponding side surface of the barrier layer 35. By aligning the upper surface of the first ohmic contact layer with the lower surface of the barrier layer, and ensuring that any side surface of the first ohmic contact layer has the same slope as the corresponding side surface of the barrier layer, the first ohmic contact layer does not extend beyond the barrier layer, eliminating portions of the first ohmic contact layer that extend beyond the channel layer and barrier layer, reducing process complexity, and allowing the first electrode to pass through the barrier layer to contact the first ohmic contact layer, ensuring proper contact and connection between the first electrode and the first ohmic contact layer. This ensures proper functioning of the first electrode and the first ohmic contact layer, thereby improving the yield of the thin film transistor.

[0080] Specifically, as shown in FIG10 , one end of the first ohmic contact layer 34 (e.g., the right end in FIG10 ) and one end of the barrier layer 35 (e.g., the right end in FIG10 ) are coplanar, and the other end of the first ohmic contact layer 34 (e.g., the left end in FIG10 ) and the other end of the barrier layer 35 (e.g., the left end in FIG10 ) are coplanar. The first electrode 421 passes through the barrier layer 35 and contacts the first ohmic contact layer 34. By ensuring that one end of the first ohmic contact layer and one end of the barrier layer are coplanar, and the other end of the first ohmic contact layer and the other end of the barrier layer are coplanar, the first ohmic contact layer does not extend beyond the barrier layer, eliminating the portion of the first ohmic contact layer that extends beyond the channel layer and barrier layer, reducing process complexity and improving the yield of the thin film transistor. Furthermore, the first electrode passes through the barrier layer and contacts the first ohmic contact layer, ensuring proper contact and connection between the first electrode and the first ohmic contact layer, and ensuring normal operation of the first electrode and the first ohmic contact layer.

[0081] Specifically, compared with the current display device in which the portion of the first ohmic contact layer that extends beyond the channel and the barrier layer needs to be retained during the channel etching process, the embodiment of the present application does not need to retain the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer. Therefore, when etching the channel layer of the thin film transistor, the process difficulty can be reduced; and by allowing the first electrode to pass through the barrier layer to connect to the first ohmic contact layer, the first electrode can still transmit signals to the first ohmic contact layer, and there is no need to retain the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer, thereby reducing the volume of the thin film transistor; and because the signal is still transmitted from the first ohmic contact layer to the channel layer, the channel length can still be controlled by the thickness and angle of the barrier layer, thereby improving the mobility of the thin film transistor. While keeping the mobility of the thin film transistor unchanged, the process difficulty is reduced, the yield of the thin film transistor is improved, and the volume of the thin film transistor is reduced.

[0082] Specifically, when designing the first electrode and the first ohmic contact layer, the design of the second electrode and the second ohmic contact layer may not be changed, that is, the second electrode and the second ohmic contact layer are still arranged beyond the channel layer. For example, the second electrode and the second ohmic contact layer adopt the design of the source and drain layer in Figure 3 and the second contact layer in Figure 2.

[0083] In some embodiments, as shown in FIG6 , one side surface of the first ohmic contact layer 34 has the same slope as the side surface of the first connection portion 371. By making the slope of one side surface of the first ohmic contact layer and the side surface of the first connection portion equal, the first ohmic contact layer does not extend beyond the channel layer, thereby eliminating the portion of the first ohmic contact layer that extends beyond the channel layer and reducing the difficulty of the process. Furthermore, the first electrode passes through the channel layer and contacts the first ohmic contact layer, ensuring normal contact and connection between the first electrode and the first ohmic contact layer. This ensures normal operation of the first electrode and the first ohmic contact layer, thereby improving the yield of the thin film transistor.

[0084] Specifically, as shown in FIG6 , one end of the first ohmic contact layer 34 (e.g., the right end in FIG6 ) and one end of the barrier layer 35 (e.g., the right end in FIG6 ) are coplanar, and the other end of the first ohmic contact layer 34 (e.g., the left end in FIG6 ) and the other end of the channel layer 37 (e.g., the left end in FIG6 ) are coplanar. The first electrode 421 passes through the channel layer 37 and contacts the first ohmic contact layer 34. By ensuring that one end of the first ohmic contact layer and one end of the barrier layer are coplanar, and the other end of the first ohmic contact layer and the other end of the channel layer are coplanar, the first ohmic contact layer does not extend beyond the barrier layer and the channel layer. This eliminates the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer, reduces process complexity, and improves the yield of the thin film transistor. Furthermore, the first electrode passes through the channel layer and contacts the first ohmic contact layer, ensuring proper contact and connection between the first electrode and the first ohmic contact layer, and ensuring normal operation of the first electrode and the first ohmic contact layer.

[0085] Specifically, compared with the current display device in which the portion of the first ohmic contact layer that extends beyond the channel and the barrier layer needs to be retained during the channel etching process, the embodiment of the present application does not need to retain the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer, so when etching the channel layer of the thin film transistor, the process difficulty can be reduced; and by allowing the first electrode to pass through the channel layer to connect to the first ohmic contact layer, the first electrode can still transmit signals to the first ohmic contact layer, and there is no need to retain the portion of the first ohmic contact layer that extends beyond the channel layer and the barrier layer, so the volume of the thin film transistor can be reduced; and because the signal is still transmitted from the first ohmic contact layer to the channel layer, the channel length can still be controlled by the thickness and angle of the barrier layer, which can improve the mobility of the thin film transistor. While keeping the mobility of the thin film transistor unchanged, the process difficulty is reduced, the yield of the thin film transistor is improved, and the volume of the thin film transistor is reduced.

[0086] Specifically, when designing the first electrode and the first ohmic contact layer, the design of the second electrode and the second ohmic contact layer may not be changed, that is, the second electrode and the second ohmic contact layer are still arranged beyond the channel layer. For example, the second electrode and the second ohmic contact layer adopt the design of the source and drain layer in Figure 3 and the second contact layer in Figure 2.

[0087] In some embodiments, as shown in FIG6 , the thin film transistor 3 includes a first connection hole 421 a , which penetrates at least the interlayer insulating layer 41 and the gate insulating layer 38 , and the first electrode 421 contacts the first ohmic contact layer 34 through the first connection hole 421 a .

[0088] In some embodiments, as shown in FIG10 , the first connection hole 421a further penetrates the barrier layer 35; alternatively, the first connection hole 421a penetrates the barrier layer 35 and the first ohmic contact layer 34. By having the first connection hole penetrate the barrier layer, the contact area between the first electrode and the first ohmic contact layer is increased, and the contact stability between the first electrode and the first ohmic contact layer is improved. By having the first connection hole penetrate the barrier layer and the first ohmic contact layer, the first electrode and the first ohmic contact layer are in circular contact. This allows the first ohmic contact layer 34 to be etched simultaneously with the channel layer, preventing the first electrode 421 from being unable to contact or having poor contact with the first ohmic contact layer 34, thereby improving the yield of the thin film transistor.

[0089] In some embodiments, the first connection hole 421a further extends through the first connection portion 371; or, as shown in FIG6 , the first connection hole 421a extends through the first connection portion 371 and the first ohmic contact layer 34. By extending the first connection hole through the first connection portion, the contact area between the first electrode and the first ohmic contact layer is increased, and the contact stability between the first electrode and the first ohmic contact layer is improved. By extending the first connection hole through the first connection portion and the first ohmic contact layer, the first electrode and the first ohmic contact layer are in ring contact. This allows the first ohmic contact layer 34 to be etched simultaneously with the channel layer, preventing the first electrode 421 from contacting or having poor contact with the first ohmic contact layer 34, thereby improving the yield of the thin film transistor.

[0090] Specifically, as shown in Figure 6, one end of the first ohmic contact layer 34 (for example, the right end in Figure 6) and one end of the blocking layer 35 (for example, the right end in Figure 6) are located in the same plane, and the other end of the first ohmic contact layer 34 (for example, the left end in Figure 6) and the other end of the channel layer 37 (for example, the left end in Figure 6) are located in the same plane. At the contact surface between the first ohmic contact layer 34 and the channel layer 37, the first electrode 421 is in contact with the first ohmic contact layer 34; or as shown in Figure 6, the first electrode 421 passes through the first ohmic contact layer 34, and the first electrode 421 is in ring contact with the first ohmic contact layer 34.

[0091] Specifically, by making the first electrode contact the first ohmic contact layer at the interface between the first ohmic contact layer and the channel layer, the contact area between the first electrode and the first ohmic contact layer is increased, and the contact stability between the first electrode and the first ohmic contact layer is improved.

[0092] Specifically, considering that the channel layer and the first ohmic contact layer are made of the same material, dry etching lacks selectivity. When etching the channel layer, retaining the first ohmic contact layer may result in incomplete etching of the channel layer, resulting in no contact or poor contact between the first ohmic contact layer and the first electrode. In the embodiment of the present application, the first electrode 421 passes through the first ohmic contact layer 34, and the first electrode 421 is in circular contact with the first ohmic contact layer 34. This allows the first ohmic contact layer 34 to be etched simultaneously with the channel layer, preventing no contact or poor contact between the first electrode 421 and the first ohmic contact layer 34, thereby improving the yield of the thin film transistor.

[0093] Specifically, as shown in Figure 10, one end of the first ohmic contact layer 34 (for example, the right end in Figure 10) and one end of the blocking layer 35 (for example, the right end in Figure 10) are located in the same plane, and the other end of the first ohmic contact layer 34 (for example, the left end in Figure 10) and the other end of the blocking layer 35 (for example, the left end in Figure 10) are located in the same plane. In the portion where the blocking layer 35 exceeds the second ohmic contact layer 36, the first electrode 421 passes through the blocking layer 35 and contacts the first ohmic contact layer 34, and there is a distance between the first electrode 421 and the second ohmic contact layer 36. By making one end of the first ohmic contact layer and one end of the blocking layer located in the same plane, and the other end of the first ohmic contact layer and the other end of the blocking layer located in the same plane, the first ohmic contact layer will not exceed the blocking layer setting, and the portion of the first ohmic contact layer exceeding the channel layer and the blocking layer setting is removed, thereby reducing the process difficulty and improving the yield of the thin film transistor. The first electrode can pass through the blocking layer from the portion of the blocking layer exceeding the second ohmic contact layer to contact the first ohmic contact layer, which can reduce the size of the thin film transistor, make the first electrode and the first ohmic contact layer normally contact and connected, and the first electrode and the first ohmic contact layer work normally.

[0094] Specifically, compared with making the first electrode pass through the channel layer to connect to the first ohmic contact layer, making the first electrode pass through the barrier layer and extend beyond the second ohmic contact layer can further reduce the size of the thin film transistor.

[0095] In some embodiments, as shown in FIG10 , the first electrode 421 contacts the first ohmic contact layer 34 at the interface between the first ohmic contact layer 34 and the barrier layer 35. By making the first electrode contact the first ohmic contact layer at the interface between the first ohmic contact layer and the barrier layer, the contact area between the first electrode and the first ohmic contact layer is increased, and the stability is improved.

[0096] Specifically, since the material of the first ohmic contact layer is different from the material of the barrier layer, there can be a selectivity when dry etching the barrier layer, so that only the barrier layer can be etched without etching the first ohmic contact layer, so that the contact area between the first electrode and the first ohmic contact layer is larger, the stability is better, and the yield of the thin film transistor is improved.

[0097] Specifically, the first electrode passes through the first ohmic contact layer, and the first electrode is in ring contact with the first ohmic contact layer. When the first electrode is in contact with the first ohmic contact layer, the first electrode can also pass through the first ohmic contact layer and be in ring contact with the first ohmic contact layer.

[0098] The above embodiment is described by taking the first electrode penetrating the first ohmic contact layer as an example, but the embodiments of the present application are not limited to this. For example, as shown in Figure 11, the depth of the via hole of the first ohmic contact layer can be one tenth to nine tenths of the thickness of the first ohmic contact layer, and this process can be achieved by controlling the etching time, that is, ensuring that the etching time is greater than the time required to etch the channel layer, and the process difficulty is relatively low.

[0099] In some embodiments, as shown in FIG6 , the thin film transistor 3 includes a second connection hole 422 a. The second connection hole 422 a penetrates at least the interlayer insulating layer 41, the gate insulating layer 38, and the second connection portion 372. The second electrode 422 contacts the second ohmic contact layer 36 through the second connection hole 422 a. By penetrating the interlayer insulating layer, the gate insulating layer, and the second connection portion, the second electrode can contact the second ohmic contact layer, and the second electrode and the second ohmic contact layer are properly connected.

[0100] In some embodiments, as shown in FIG6 , the second connection hole further passes through the second connection portion.

[0101] In some embodiments, the second electrode 422 contacts the second ohmic contact layer 36 at the contact surface between the second ohmic contact layer 36 and the channel layer 37; or as shown in FIG6 , the second electrode 422 passes through the second ohmic contact layer 36 and the second electrode 422 contacts the second ohmic contact layer 36 in a ring shape.

[0102] Specifically, by making the second electrode contact the second ohmic contact layer at the contact surface between the second ohmic contact layer and the channel layer, the contact area between the second electrode and the second ohmic contact layer is increased, and the contact stability between the second electrode and the second ohmic contact layer is improved.

[0103] Specifically, considering that the channel layer and the second ohmic contact layer are made of the same material, dry etching lacks selectivity. When etching the channel layer, retaining the second ohmic contact layer may result in incomplete etching of the channel layer, resulting in no contact or poor contact between the second ohmic contact layer and the second electrode. In this embodiment of the present application, the second electrode 422 passes through the second ohmic contact layer 36, and the second electrode 422 is in circular contact with the second ohmic contact layer 36. This allows the second ohmic contact layer 36 to be etched simultaneously with the channel layer, preventing no contact or poor contact between the second electrode 422 and the second ohmic contact layer 36, thereby improving the yield of the thin film transistor.

[0104] The above embodiment is illustrated by taking the second electrode penetrating the second ohmic contact layer as an example, but the embodiments of the present application are not limited to this. For example, as shown in Figure 11, the depth of the via hole of the second ohmic contact layer can be one tenth to nine tenths of the thickness of the second ohmic contact layer, and this process can be achieved by controlling the etching time, that is, ensuring that the etching time is greater than the time required to etch the channel layer, and the process difficulty is relatively low.

[0105] In some embodiments, as shown in FIG10 , in the lateral direction, the width of the second connecting portion 372 is smaller than the width of the barrier layer 35. In the region where the barrier layer 35 extends beyond the second connecting portion 372, the first electrode 421 contacts the first ohmic contact layer 34. By making the width of the barrier layer greater than the width of the second connecting portion, at least a portion of the barrier layer extends beyond the second ohmic contact layer, allowing the first electrode to pass through the barrier layer and connect to the first ohmic contact layer, thereby reducing the size of the thin film transistor.

[0106] Regarding the problem that the first electrode and / or the second electrode may be in direct contact with the channel layer and may cause the thin film transistor to be always in the on state. In some embodiments, the ratio of the ion doping concentration of the first ohmic contact layer to the ion doping concentration of the channel layer is greater than or equal to ten to the fifth power. By making the ion doping concentration of the channel layer 5 orders of magnitude smaller than the ion doping concentration of the first ohmic contact layer, the ion doping concentration of the channel layer is low, the channel layer is a nearly insulating material, the thin film transistor will not be always in the on state, the electrical signal will still be transmitted from the first electrode to the first ohmic contact layer, the first ohmic contact layer is transmitted from the channel layer to the second ohmic contact layer, and the second ohmic contact layer is transmitted to the second electrode, so that the channel length can still be controlled by the thickness and angle of the barrier layer, reducing the channel length and improving the mobility of the thin film transistor.

[0107] Specifically, the ion doping concentration is the ion doping concentration per unit area.

[0108] Specifically, the difference between the ion doping concentration of the first ohmic contact layer and the ion doping concentration of the second ohmic contact layer is less than one order of magnitude. More specifically, the ion doping concentration of the first ohmic contact layer is equal to the ion doping concentration of the second ohmic contact layer.

[0109] In some embodiments, the material of the channel layer includes intrinsic silicon. By making the material of the channel layer intrinsic silicon, the insulation of the channel layer can be further improved, thereby preventing the thin film transistor from being in an on state all the time and improving the yield of the thin film transistor.

[0110] Specifically, the material of the channel layer includes polysilicon.

[0111] In some embodiments, the material of the first ohmic contact layer includes polysilicon.

[0112] In some embodiments, the material of the second ohmic contact layer includes polysilicon.

[0113] In some embodiments, the material of the barrier layer includes silicon oxide.

[0114] In some embodiments, as shown in FIG. 6 , the thin film transistor 3 further includes a light shielding layer 32 , a buffer layer 33 , a gate insulating layer 38 and an interlayer insulating layer 41 .

[0115] In some embodiments, the first electrode is a source electrode and the second electrode is a drain electrode; or the first electrode is a drain electrode and the second electrode is a source electrode.

[0116] The above embodiments describe thin film transistors from the perspective of each film layer and the connection relationship between each film layer. It is understood that when there is no conflict between the embodiments, the embodiments can be combined to achieve better technical effects, or the embodiments can be described in a complete manner. For example, to further reduce the process difficulty and reduce the volume of the thin film transistor, one end of the second ohmic contact layer and one end of the channel layer can be located in the same plane, the second electrode can pass through the channel layer to contact the second ohmic contact layer, and one end of the first ohmic contact layer and one end of the barrier layer can be located in the same plane, the other end of the first ohmic contact layer and the other end of the barrier layer can be located in the same plane, and the first electrode can pass through the barrier layer to contact the first ohmic contact layer; or one end of the second ohmic contact layer and one end of the channel layer can be located in the same plane, the second electrode can pass through the channel layer to contact the second ohmic contact layer, one end of the first ohmic contact layer and one end of the barrier layer can be located in the same plane, the other end of the first ohmic contact layer and the other end of the channel layer can be located in the same plane, and the first electrode can pass through the channel layer to contact the first ohmic contact layer.

[0117] At the same time, an embodiment of the present application provides a method for preparing a thin film transistor, which prepares the thin film transistor as described in any of the above embodiments.

[0118] Specifically, a method for preparing a thin film transistor includes:

[0119] Providing a substrate; the structure of the thin film transistor corresponding to this step is shown in (a) of FIG12 ;

[0120] A light shielding layer is formed on the substrate; the structure of the thin film transistor corresponding to this step is shown in (a) of FIG12 ;

[0121] A buffer layer and a first ohmic contact layer are sequentially formed on the light shielding layer; a B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (b1) of FIG12 , and an A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (b2) of FIG12 ;

[0122] A barrier layer and a second ohmic contact layer are formed on the first ohmic contact layer; a B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (c1) of FIG12 , and a A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (c2) of FIG12 ;

[0123] A channel layer is formed on the second ohmic contact layer, and the channel layer and the second ohmic contact layer are etched; a B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (d1) of FIG12 , and an A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (d2) of FIG12 ;

[0124] A gate insulating layer and a gate layer are formed on the channel layer; a B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown as (e1) in FIG12 , and an A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown as (e2) in FIG12 ;

[0125] An interlayer insulating layer is formed on the gate layer, and the interlayer insulating layer, the gate insulating layer, the channel layer, the first ohmic contact layer, and the second ohmic contact layer are etched to form a via hole. A B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (f1) of FIG12 , and an A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (f2) of FIG12 .

[0126] A source-drain electrode layer is formed on the interlayer insulating layer; a B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in FIG6 , and an A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in FIG7 .

[0127] Specifically, another method for preparing a thin film transistor includes:

[0128] Providing a substrate; the structure of the thin film transistor corresponding to this step is shown in (a) of FIG13;

[0129] A light shielding layer is formed on the substrate; the structure of the thin film transistor corresponding to this step is shown in (a) of FIG13 ;

[0130] A buffer layer, a first ohmic contact layer, a barrier layer, and a second ohmic contact layer are sequentially formed on the light shielding layer; the structure of the thin film transistor corresponding to this step is shown in (b) of FIG13 ;

[0131] A channel layer is formed on the second ohmic contact layer, and the channel layer and the second ohmic contact layer are etched; the structure of the thin film transistor corresponding to this step is shown in (c) of FIG13 ;

[0132] A gate insulating layer and a gate layer are formed on the channel layer; the structure of the thin film transistor corresponding to this step is shown in (d) of FIG13 ;

[0133] An interlayer insulating layer is formed on the gate layer, and the interlayer insulating layer, the gate insulating layer, the channel layer, and the second ohmic contact layer are etched to form a via hole; a B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e1) of FIG13 , and an A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in (e2) of FIG13 ;

[0134] The interlayer insulating layer, the gate insulating layer, and the barrier layer are etched to form via holes; a B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown as (f1) in FIG13 , and an A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown as (f2) in FIG13 ;

[0135] A source-drain electrode layer is formed on the interlayer insulating layer; the B1-B2 cross-sectional view of the thin film transistor corresponding to this step is shown in FIG10 , and the A1-A2 cross-sectional view of the thin film transistor corresponding to this step is shown in FIG7 .

[0136] At the same time, an embodiment of the present application provides an electronic device, which includes a thin film transistor as described in any of the above embodiments.

[0137] According to the above embodiments, it can be seen that:

[0138] The embodiments of the present application provide a thin film transistor and an electronic device; the thin film transistor includes a substrate, a first ohmic contact layer, a barrier layer, a second ohmic contact layer, a channel layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source-drain layer, wherein the first ohmic contact layer is arranged on one side of the substrate, the barrier layer is arranged on a side of the first ohmic contact layer away from the substrate, the barrier layer includes at least one sidewall, the second ohmic contact layer is arranged on a side of the barrier layer away from the first ohmic contact layer, the channel layer includes a first connecting portion, a second connecting portion, and an effective portion located on the sidewall, the first connecting portion contacts the first ohmic contact layer, and the second connecting portion is arranged on the second ohmic contact layer. The gate insulating layer is arranged on a side of the channel layer away from the second ohmic contact layer, the gate layer is arranged on a side of the gate insulating layer away from the channel layer, the orthographic projection of the gate layer in the direction perpendicular to the substrate covers the effective part, the interlayer insulating layer is arranged on a side of the gate layer away from the gate insulating layer, the source and drain layer is arranged on a side of the interlayer insulating layer away from the gate layer, and the source and drain layer includes a first electrode and a second electrode; wherein the second electrode contacts the second ohmic contact layer through the channel layer; and / or the first electrode contacts the first ohmic contact layer through the blocking layer; or the first connecting portion is arranged on the first ohmic contact layer, and the first electrode contacts the first ohmic contact layer through the channel layer. The present application arranges the effective portion on the side wall of the barrier layer, and the first connecting portion and the second connecting portion are in contact with the first ohmic contact layer and the second ohmic contact layer located above and below the barrier layer, respectively. The channel length can be controlled by the thickness and angle of the barrier layer, and the channel length can be reduced using the existing process, the volume of the thin film transistor can be reduced, and the mobility can be improved; and by making the second electrode pass through the channel layer to contact the second ohmic contact layer, even if the second ohmic contact layer is over-etched, the second electrode can still work normally with the second ohmic contact layer; and / or making the first electrode pass through the barrier layer to contact the first ohmic contact layer, or the first electrode passes through the channel layer to contact the first ohmic contact layer, even if the first ohmic contact layer is over-etched, the first electrode can still work normally with the first ohmic contact layer, thereby improving the yield of the display panel and reducing the size of the thin film transistor.

[0139] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0140] The above is a detailed introduction to a thin film transistor and an electronic device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A thin film transistor, comprising: substrate; A first ohmic contact layer is disposed on one side of the substrate; A barrier layer, disposed on a side of the first ohmic contact layer away from the substrate, the barrier layer comprising at least one sidewall; A second ohmic contact layer is disposed on a side of the barrier layer away from the first ohmic contact layer; a channel layer, comprising a first connection portion, a second connection portion and an effective portion located on the sidewall, wherein the first connection portion contacts the first ohmic contact layer, and the second connection portion is disposed on the second ohmic contact layer; A gate insulating layer, disposed on a side of the channel layer away from the second ohmic contact layer; A gate layer, disposed on a side of the gate insulating layer away from the channel layer, wherein an orthographic projection of the gate layer in a direction perpendicular to the substrate covers the effective portion; An interlayer insulating layer, disposed on a side of the gate layer away from the gate insulating layer; A source-drain electrode layer, arranged on a side of the interlayer insulating layer away from the gate layer, the source-drain electrode layer comprising a first electrode and a second electrode; Wherein, the second electrode passes through the channel layer and contacts the second ohmic contact layer; and / or, the first electrode contacts the first ohmic contact layer through the barrier layer; Alternatively, the first connection portion is disposed on the first ohmic contact layer, and the first electrode passes through the channel layer and contacts the first ohmic contact layer.

2. The thin film transistor according to claim 1, wherein: When the second electrode passes through the channel layer and contacts the second ohmic contact layer, at the contact surface between the second ohmic contact layer and the second connecting part, the upper surface of the second ohmic contact layer coincides with the lower surface of the second connecting part, and the slopes of the three side surfaces of the second ohmic contact layer that are not in contact with the effective part are equal to the slope corresponding to the second connecting part.

3. The thin film transistor according to claim 1, wherein: At the contact surface between the first ohmic contact layer and the barrier layer, the upper surface of the first ohmic contact layer overlaps with the lower surface of the barrier layer, and any side surface of the first ohmic contact layer has the same slope as the corresponding side surface of the barrier layer.

4. The thin film transistor according to claim 1, wherein: A side surface of the first ohmic contact layer has the same slope as a side surface of the first connecting portion.

5. The thin film transistor according to claim 1, wherein: The thin film transistor includes a first connection hole, the first connection hole at least penetrates the interlayer insulating layer and the gate insulating layer, and the first electrode contacts the first ohmic contact layer through the first connection hole.

6. The thin film transistor according to claim 5, wherein: The first connection hole also penetrates the barrier layer; or the first connection hole penetrates the barrier layer and the first ohmic contact layer.

7. The thin film transistor according to claim 5, wherein: The first connection hole also penetrates the first connection portion; or the first connection hole penetrates the first connection portion and the first ohmic contact layer.

8. The thin film transistor according to claim 1, wherein: The thin film transistor includes a second connection hole, the second connection hole at least penetrates the interlayer insulating layer, the gate insulating layer and the second connection portion, and the second electrode contacts the second ohmic contact layer through the second connection hole.

9. The thin film transistor according to claim 8, wherein: The second connecting hole also passes through the second connecting portion.

10. The thin film transistor according to claim 1, wherein: In the lateral direction, the width of the second connection portion is smaller than the width of the barrier layer, and the first electrode is in contact with the first ohmic contact layer in a region where the barrier layer exceeds the second connection portion.

11. The thin film transistor according to claim 1, wherein: A ratio of an ion doping concentration of the first ohmic contact layer to an ion doping concentration of the channel layer is greater than or equal to ten to the fifth power.

12. The thin film transistor according to claim 1, wherein: The material of the channel layer includes intrinsic silicon.

13. An electronic device, wherein: The electronic device comprises a thin film transistor, and the thin film transistor comprises: substrate; A first ohmic contact layer is disposed on one side of the substrate; A barrier layer, disposed on a side of the first ohmic contact layer away from the substrate, the barrier layer comprising at least one sidewall; A second ohmic contact layer is disposed on a side of the barrier layer away from the first ohmic contact layer; a channel layer, comprising a first connection portion, a second connection portion and an effective portion located on the sidewall, wherein the first connection portion contacts the first ohmic contact layer, and the second connection portion is disposed on the second ohmic contact layer; A gate insulating layer, disposed on a side of the channel layer away from the second ohmic contact layer; A gate layer, disposed on a side of the gate insulating layer away from the channel layer, wherein an orthographic projection of the gate layer in a direction perpendicular to the substrate covers the effective portion; An interlayer insulating layer, disposed on a side of the gate layer away from the gate insulating layer; A source-drain electrode layer, arranged on a side of the interlayer insulating layer away from the gate layer, the source-drain electrode layer comprising a first electrode and a second electrode; Wherein, the second electrode passes through the channel layer and contacts the second ohmic contact layer; and / or, the first electrode contacts the first ohmic contact layer through the barrier layer; Alternatively, the first connection portion is disposed on the first ohmic contact layer, and the first electrode passes through the channel layer and contacts the first ohmic contact layer.

14. The electronic device according to claim 13, wherein: When the second electrode passes through the channel layer and contacts the second ohmic contact layer, at the contact surface between the second ohmic contact layer and the second connecting part, the upper surface of the second ohmic contact layer coincides with the lower surface of the second connecting part, and the slopes of the three side surfaces of the second ohmic contact layer that are not in contact with the effective part are equal to the slope corresponding to the second connecting part.

15. The electronic device according to claim 13, wherein: At the contact surface between the first ohmic contact layer and the barrier layer, the upper surface of the first ohmic contact layer overlaps with the lower surface of the barrier layer, and any side surface of the first ohmic contact layer has the same slope as the corresponding side surface of the barrier layer.

16. The electronic device according to claim 13, wherein: A side surface of the first ohmic contact layer has the same slope as a side surface of the first connecting portion.

17. The electronic device according to claim 13, wherein: The thin film transistor includes a first connection hole, the first connection hole at least penetrates the interlayer insulating layer and the gate insulating layer, and the first electrode contacts the first ohmic contact layer through the first connection hole.

18. The electronic device according to claim 17, wherein: The first connection hole also penetrates the barrier layer; or the first connection hole penetrates the barrier layer and the first ohmic contact layer.

19. The electronic device according to claim 17, wherein: The first connection hole also penetrates the first connection portion; or the first connection hole penetrates the first connection portion and the first ohmic contact layer.

20. The electronic device according to claim 13, wherein: The thin film transistor includes a second connection hole, the second connection hole at least penetrates the interlayer insulating layer, the gate insulating layer and the second connection portion, and the second electrode contacts the second ohmic contact layer through the second connection hole.

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