Improved circuit for convolution operation, chip, device, and method

Abstract

The present disclosure relates to an improved circuit for convolution operation, a chip, a device, and a method. The circuit for convolution operation comprises: a convolution circuit configured to perform, in each period, convolution operation on (1) at least a portion of input data from a plurality of input channels of a convolutional network, and (2) at least a portion of coefficient data of a plurality of convolution kernels of the convolutional network, wherein each of the plurality of convolution kernels is associated with a corresponding output channel among a plurality of output channels of the convolutional network. The circuit for convolution operation is configured to enable (1) a first data block in the input data provided to the convolution circuit, or (2) a second data block in the coefficient data provided to the convolution circuit, which is provided to the convolution circuit to perform convolution operation, to remain unchanged across a plurality of consecutive periods.

Description

Improved circuits, chips, devices and methods for convolution operations

[0001] This application is based on and claims priority to the Chinese patent application with Chinese application number 202311134860.X and application date September 5, 2023. The disclosed content of the Chinese patent application is hereby introduced as a whole into this application. Technical Field

[0002] The present disclosure relates to the field of electronic circuits, and more particularly, to improved circuits, chips, devices, and methods for convolution operations. Background Art

[0003] Convolution is a common mathematical operation with a wide range of applications. For example, convolutional neural networks (CNNs), one of the leading algorithms in deep learning, incorporate numerous convolution operations and possess a deep architecture. With technological advancements and growing demand, the number of convolution operations performed in applications such as CNNs has increased significantly.

[0004] Summary of the Invention

[0005] One aspect of the present disclosure provides a circuit for a convolution operation, the circuit comprising a convolution circuit configured to perform a convolution operation on, in each cycle, (1) at least a portion of input data from a plurality of input channels of a convolutional network, and (2) at least a portion of coefficient data of a plurality of convolution kernels of the convolutional network, wherein each convolution kernel of the plurality of convolution kernels is associated with a corresponding output channel of a plurality of output channels of the convolutional network. The circuit is configured such that, across a plurality of consecutive cycles, one of the following provided to the convolution circuit for performing the convolution operation remains constant: (1) a first data block of the input data provided to the convolution circuit, or (2) a second data block of the coefficient data provided to the convolution circuit.

[0006] Another aspect of the present disclosure provides a method for a convolution operation, comprising: providing a convolution circuit configured to perform a convolution operation on the following two items in each cycle: (1) at least a portion of input data from multiple input channels of a convolution network, and (2) at least a portion of coefficient data of multiple convolution kernels of the convolution network, each of the multiple convolution kernels being associated with a corresponding output channel of multiple output channels of the convolution network; so that the following items provided to the convolution circuit to perform the convolution operation remain unchanged across multiple consecutive cycles: (1) a first data block of the input data provided to the convolution circuit, or (2) a second data block of the coefficient data provided to the convolution circuit.

[0007] Another aspect of the present disclosure provides a computing chip, comprising the circuit for convolution operation as described in the present disclosure.

[0008] Another aspect of the present disclosure provides a computing device, including the computing chip described in the present disclosure.

[0009] Another aspect of the present disclosure provides a computing device, comprising: one or more processors; and a memory storing computer-executable instructions, which, when executed by the one or more processors, cause the one or more processors to perform any method described in the present disclosure.

[0010] Yet another aspect of the present disclosure provides a non-transitory storage medium having computer-executable instructions stored thereon, which, when executed by one or more processors, cause the one or more processors to perform any method according to the present disclosure.

[0011] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings.

[0014] FIG1 is a schematic diagram showing an exemplary embodiment of performing a multi-channel convolution operation.

[0015] FIG2 shows a schematic diagram of a logic gate element according to an embodiment of the present disclosure.

[0016] FIG3 shows a schematic diagram of a circuit for convolution operation according to an embodiment of the present disclosure.

[0017] FIG4 is a schematic diagram showing an exemplary process of performing a multi-channel convolution operation according to an embodiment of the present disclosure.

[0018] FIG5 is a schematic diagram showing another exemplary process of performing a multi-channel convolution operation according to an embodiment of the present disclosure.

[0019] FIG6 shows a flowchart of an exemplary method for convolution operation according to an embodiment of the present disclosure.

[0020] FIG7 shows a schematic diagram of a computing chip according to an embodiment of the present disclosure.

[0021] FIG8 shows a schematic diagram of a computing device according to an embodiment of the present disclosure.

[0022] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0023] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0024] Convolutional network is a widely used model. When training or using a convolutional network, a large number of convolution operations need to be performed. For example, a convolutional network may include a convolution layer. A convolution layer may include one or more convolution kernels. Each convolution kernel may be represented by corresponding coefficient data. The convolution kernel of the convolution layer can be used to perform multi-channel convolution operations on input data provided by the input channel. In the multi-channel convolution operation, by performing a convolution operation on the input data from multiple input channels and the coefficient data of multiple convolution kernels, a result value associated with one or more features of the input data can be generated. These result values ​​can be provided to multiple output channels associated with the multiple convolution kernels as multi-channel output data.

[0025] 1 shows a schematic diagram of an exemplary embodiment 1000 for performing a multi-channel convolution operation. By way of example and not limitation, in embodiment 1000, multi-channel input data 1100, multi-channel coefficient data 1200, and multi-channel output data 1300 are shown. Optionally, multi-channel bias data 1400 is also shown in embodiment 1000.

[0026] The multi-channel input data 1100 may come from multiple input channels of a convolutional network. According to an embodiment of the present disclosure, the multi-channel input data 1100 may include various types of input data associated with the convolutional network without limitation. In some embodiments, the multi-channel input data 1100 may include the original input data of the convolutional network. Depending on the purpose of training or using the convolutional network, the original input data may include but is not limited to image data, audio data, video data, sensor data, etc. In other embodiments, the multi-channel input data 1100 may be result data generated by at least a portion of the convolutional network. For example, the result data may include feature data generated by one or more layers of the convolutional network based on the original input data. The feature data may be used as input to additional convolutional layers of the convolutional network. In some other embodiments, the multi-channel input data 1100 may be a combination of original input data and feature data. These data may be provided during training, testing, or use of the convolutional network.

[0027] The multi-channel input data 1100 can be represented as a multi-dimensional input array as a whole. The size of the multi-dimensional input array can be expressed as L×H×CIN, where CIN represents the number of input channels, L represents the width of the two-dimensional array corresponding to the input data of each input channel, and H represents the height of the two-dimensional array corresponding to the input data of each input channel. In example 1000, the multi-channel input data 1100 is represented as a multi-dimensional input array X, where CIN=3 and L=H=7. The input data from the first input channel is represented as X[:,:,0], which can be represented as X0 in this article. The input data from the second input channel is represented as X[:,:,1], which can be represented as X1 in this article. The input data from the third input channel is represented as X[:,:,2], which can be represented as X2 in this article. Note that, unless otherwise specified, the values ​​representing indexes in this disclosure generally start from 0. In addition, the input data of each input channel is represented as a two-dimensional array of size 7×7. Those skilled in the art will appreciate that the above values ​​of L, H, and CIN are merely exemplary. In other embodiments, the values ​​of L, H, and CIN may be other suitable positive integers (e.g., integers not less than 2) without limitation.

[0028] In some optional embodiments, the multi-channel input data 1100 from three input channels may include image data. In some scenarios, the image data may represent an RGB image. The three input channels may correspond to the R (red) channel, the G (green) channel, or the B (blue) channel of the image data, respectively. The value of each data point in the input array X may be associated with the corresponding pixel value in the corresponding channel. In some optional embodiments, the image data may include a padding value. For example, the periphery of the input data from each input channel in Figure 1 is filled with a "0" value. In some embodiments, the padding value may be any suitable specified value. In some embodiments, the periphery of the image data may not include a padding value.

[0029] The multi-channel coefficient data 1200 can be associated with multiple convolution kernels of a convolution network. A convolution kernel can also be called a filter. The result value generated by convolving the input data with the coefficient data of the convolution kernel can represent one or more features of the input data. As an example and not a limitation, the coefficient data can be associated with one or more parameters of the convolution network. For example, the coefficient data can be associated with one or more weight coefficients of the convolution network. In a scenario where the convolution network is a neural network, the weight coefficient can be a weight coefficient associated with a neuron or neural connection in a layer of the neural network. In some embodiments (e.g., during training of a neural network), the coefficient data of each convolution kernel can be changed dynamically. In some embodiments (e.g., during use of a trained neural network), the coefficient data of each convolution kernel can be fixed.

[0030] The multi-channel coefficient data 1200 may include a plurality of coefficient arrays corresponding to a plurality of convolution kernels. Each of the plurality of convolution kernels corresponds to a corresponding output channel of a plurality of output channels of the convolution network. Therefore, each of the plurality of coefficient arrays also corresponds to a corresponding output channel of the plurality of output channels. In the present disclosure, the number of the plurality of output channels may be represented as COUT. Therefore, the multi-channel coefficient data 1200 may include COUT coefficient arrays, which may be represented as w0, w1, ..., w COUT-1. Each coefficient array can be multidimensional. In some embodiments, each coefficient array can be represented as a multidimensional array of n×n×CIN, where CIN is the number of input channels and n is a parameter associated with the size of the convolution kernel. n is a positive integer not less than 2. For example, the size of the convolution kernel can generally be selected to be n×n. When n=3, a 3×3 convolution is adopted. Each coefficient array can have a portion corresponding to a corresponding input channel of a plurality of input channels. The portion can be represented as a two-dimensional array. In example 1000, the multi-channel coefficient data 1200 includes coefficient arrays w0 and w1 associated with two convolution kernels, respectively. The size of each coefficient array is 3×3×3. The coefficient array w0 includes a two-dimensional array w0[:,:,0] corresponding to the first input channel, a two-dimensional array w0[:,:,1] corresponding to the second input channel, and a two-dimensional array w0[:,:,2] corresponding to the third input channel. Similarly, the coefficient array w1 includes a two-dimensional array w1[:,:,0] corresponding to the first input channel, a two-dimensional array w1[:,:,1] corresponding to the second input channel, and a two-dimensional array w1[:,:,2] corresponding to the third input channel. Those skilled in the art will appreciate that the above values ​​of COUT, n, and CIN are merely exemplary. In other embodiments, the values ​​of COUT, n, and CIN may be other suitable positive integers without limitation.

[0031] Multi-channel output data 1300 may represent the result of a multi-channel convolution operation performed on multi-channel input data 1100 and multi-channel coefficient data 1200. The result of the multi-channel convolution operation may represent one or more features of the channel input data 1100. Multi-channel output data 1300 may include multiple output arrays corresponding to multiple output channels of the convolutional network. Each of the multiple output arrays may correspond to a corresponding convolution kernel from a plurality of convolution kernels. In example 1000, multi-channel output data 1300 may include two output arrays, namely, a first output array out[:,:,0] and a second output array out[:,:,1]. The first output array and the second output array are associated with the first output channel and the second output channel, respectively. The first output array and the second output array are associated with the first convolution kernel and the second convolution kernel, respectively. Each of the first and second output arrays has a size of 3×3. Those skilled in the art will appreciate that when the values ​​of L, H, CIN, COUT, and n change, the size of the multi-channel coefficient data 1300 will also change accordingly.

[0032] In an optional embodiment, multi-channel bias data 1400 is applied to a multi-channel convolution operation. The multi-channel bias data 1400 may include a bias value corresponding to each convolution kernel. The bias value may be added to the convolution result associated with each convolution kernel to provide additional correction. The corrected convolution result may be provided to the corresponding output array. In some embodiments (e.g., during training a neural network), the bias value of each convolution kernel may be changed dynamically. In some embodiments (e.g., during use of a trained neural network), the bias value of each convolution kernel may be fixed. In instance 1000, the multi-channel bias data 1400 includes bias values ​​bias0 and bias1 associated with the first convolution kernel and the second convolution kernel, respectively.

[0033] It should be understood that the values ​​of the various data points in the multi-channel input data 1100, the multi-channel coefficient data 1200, or the multi-channel bias data 1400 shown in example 1000 are merely exemplary and are not intended to be limiting. In other embodiments, at least some of the values ​​of these data points may differ from example 1000. Accordingly, at least some of the values ​​of the various data points in the multi-channel output data 1300 will also differ from example 1000.

[0034] In practical applications, hardware can be used to implement convolutional networks. For example, dedicated chips can be used to implement convolutional neural networks. Convolution operations are usually performed by convolution circuits in hardware. Multi-channel convolution operations are usually divided into multiple cycles. The convolution circuit can be configured to perform convolution operations on both a portion of the multi-channel input data 1100 and a portion of the multi-channel coefficient data 1200 in each cycle. Each convolution operation can include a multiplication-accumulation operation, which includes a set of multiplication operations and accumulation operations. The result of each convolution operation can correspond to a data point in the multi-channel output data 1300. Across multiple cycles, the convolution circuit can traverse multiple portions of the multi-channel input data 1100 and multiple portions of the multi-channel coefficient data 1200.

[0035] The following continues to describe an exemplary process S100 of a multi-channel convolution operation according to one method in conjunction with Fig. 1. As part of the multi-channel convolution operation, the process S100 may include steps S101-S106 performed in sequence.

[0036] Step S101 may occur in the first cycle. In this step, a portion of the input data X0 of the first input channel from the multi-channel input data 1100, namely X[0:2,0:2,0], is provided to the convolution circuit as a first data block for the convolution operation. X[0:2,0:2,0] is represented as shaded in FIG1 . A portion of the coefficient array w0 of the multi-channel coefficient data 1200 corresponding to the first input channel, namely w0[:,:,0], is provided to the convolution circuit as a second data block for the convolution operation. The convolution circuit may perform a convolution operation on the first data block and the second data block. That is, R=X[0:2,0:2,0]*w0[:,:,0]. The symbol “*” is used in this disclosure to represent a convolution operation between two data blocks. The convolution operation on the first data block and the second data block may include performing multiplication operations on corresponding pairs of data points in the two data blocks and accumulating the results of the respective multiplication operations, as shown below: R = X[0:2,0:2,0]*w0[:,:,0] = 0×1+0×1+0×(-1)+0×(-1)+0×0+1×1+0×(-1)+0×(-1)+1×0 = 1

[0037] The result R of the current convolution operation can be stored in the register temp.

[0038] Process S100 can then proceed to step S102. Step S102 can occur in a second cycle after the first cycle. In step S102, a portion of input data X1 from the second input channel of multi-channel input data 1100, namely X[0:2,0:2,1], is provided to the convolution circuit as a first data block. X[0:2,0:2,1] is represented as shaded in Figure 1. A portion of coefficient array w0 of multi-channel coefficient data 1200 corresponding to the second input channel, namely w0[:,:,1], is provided to the convolution circuit as a second data block. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R = X[0:2,0:2,1] * w0[:,:,1] = -1. The result R of the current convolution operation can be accumulated to the previous value (i.e., 1) stored in register temp. At this time, the accumulated value in register temp = 1 + (-1) = 0.

[0039] Process S100 can then proceed to step S103. Step S103 can occur in a third cycle after the second cycle. In step S103, a portion of input data X2 from the third input channel of multi-channel input data 1100, namely X[0:2,0:2,2], is provided to the convolution circuit as a first data block. X[0:2,0:2,2] is represented as shaded in Figure 1. A portion of coefficient array w0 of multi-channel coefficient data 1200 corresponding to the third input channel, namely w0[:,:,2], is provided to the convolution circuit as a second data block. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R = X[0:2,0:2,2] * w0[:,:,2] = 0. The result R of the current convolution operation can be added to the previous value (i.e., 0) stored in register temp. At this time, the accumulated value in register temp = 0 + 0 = 0.

[0040] After the coefficient array w0 associated with the first convolution kernel has been convolved with multiple input channels, the bias value associated with the first convolution kernel (i.e., bias0) can be added to the current accumulated value in register temp. The result can be used as the corresponding data point of the first output array in multi-channel output data 1300, i.e., out[0,0,0] = 0 + 1 = 1. This data point is indicated by shading in FIG1. ​​The accumulated value in register temp can be cleared.

[0041] Then, process S100 can proceed to step S104. Step S104 can occur in the fourth cycle after the third cycle. In step S104, a portion of the input data X0 of the first input channel from the multi-channel input data 1100, namely X[0:2,0:2,0], is again provided to the convolution circuit as the first data block. A portion of the coefficient array w1 of the multi-channel coefficient data 1200 corresponding to the first input channel, namely w1[:,:,0], is provided to the convolution circuit as the second data block. The convolution circuit can perform multiplication operations on corresponding pairs of data points in the first data block and the second data block, and accumulate the results of each multiplication operation. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R = X[0:2,0:2,0] * w1[:,:,0] = 0. The result R of the current convolution operation can be stored in the register temp.

[0042] Then, process S100 can proceed to step S105. Step S105 can occur in the fifth cycle after the fourth cycle. In step S105, a portion of the input data X1 of the second input channel from the multi-channel input data 1100, namely X[0:2,0:2,1], is again provided to the convolution circuit as a first data block. A portion of the coefficient array w1 of the multi-channel coefficient data 1200 corresponding to the second input channel, namely w1[:,:,1], is provided to the convolution circuit as a second data block. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,1]*w1[:,:,1]=-1. The result R of the current convolution operation can be added to the previous value (i.e., 0) stored in the register temp. At this time, the accumulated value in the register temp=0+(-1)=-1.

[0043] Then, process S100 can proceed to step S106. Step S106 can occur in the sixth cycle after the fifth cycle. In step S106, a portion of the input data X2 of the third input channel from the multi-channel input data 1100, namely X[0:2,0:2,2], is again provided to the convolution circuit as the first data block. A portion of the coefficient array w1 of the multi-channel coefficient data 1200 corresponding to the third input channel, namely w1[:,:,2], is provided to the convolution circuit as the second data block. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,2]*w1[:,:,2]=0. The result R of the current convolution operation can be added to the previous value (i.e., 0) stored in the register temp. At this time, the accumulated value in the register temp=(-1)+0=-1.

[0044] After the coefficient array w1 associated with the second convolution kernel has been calculated for the convolution operation of multiple input channels, the bias value associated with the second convolution kernel (i.e., bias1) can be added to the current accumulated value in register temp. The result can be used as the corresponding data point of the second output array in multi-channel output data 1300, i.e., out[0,0,1] = (-1) + 0 = -1. This data point is represented by shading in Figure 1. The accumulated value in register temp can be cleared.

[0045] Process S100 may include additional steps. In these additional steps, the input data of each input channel may be slid to obtain a first data block provided to the convolution circuit for the convolution operation. The slid operation traverses the input data X, thereby obtaining the remaining data points in the first and second output arrays of the multi-channel output data 1300.

[0046] The inventors have recognized that, in process S100, the first data block and the second data block provided to the convolution circuit to perform the convolution operation always change between the current cycle and the next cycle. For example, between the first cycle and the second cycle, the first data block changes from X[0:2,0:2,0] to X[0:2,0:2,1], and the second data block changes from w0[:,:,0] to w0[:,:,1]. For another example, between the second cycle and the third cycle, the first data block changes from X[0:2,0:2,1] to X[0:2,0:2,2], and the second data block changes from w0[:,:,1] to w0[:,:,2]. The same is true between any two adjacent cycles. For hardware circuits implemented using semiconductor elements (e.g., logic gate elements), frequent changes in the data provided to the semiconductor elements as inputs will disadvantageously increase the power consumption of the logic gate elements.

[0047] FIG2 shows a schematic diagram of a logic gate element 2000 according to an embodiment of the present disclosure. Logic gate element 2000 may be a basic hardware unit for implementing a convolution circuit. Logic gate element 2000 includes a PMOS transistor and an NMOS transistor connected to each other. It should be understood that the configuration of logic gate element 2000 shown in FIG2 is merely exemplary. Logic gate elements in actual use may include other configurations while still conforming to the general principles set forth in this disclosure.

[0048] The power consumption of the logic gate element 2000 includes static power consumption and dynamic power consumption. Static power consumption is also called leakage power consumption. Dynamic power consumption includes short-circuit power consumption and flip-flop power consumption. When the interconnect structure of the PMOS and NMOS tubes is turned on, a short-circuit current will be generated. The power consumption caused by this is called short-circuit power consumption. When the input VIN of the logic gate element 2000 flips, the load capacitor C LOAD Charging or discharging will occur, and the power consumption caused by it is called flip power consumption. switch can be calculated as: P switch =1 / 2×VDD 2 ×C LOAD ×T r

[0049] Where VDD represents the power supply voltage, C LOAD Tr represents the load capacitance of logic gate element 2000. Tr represents the toggle rate, which indicates the toggle frequency of the logic gate element's input. The toggle frequency can be expressed as the number of toggle cycles per unit time. Therefore, the toggle power consumption of logic gate element 2000 is related to the toggle frequency. The toggle power consumption of logic gate element 2000 can be reduced by reducing the toggle frequency.

[0050] The convolution circuit is composed of a large number of logic gate elements similar to logic gate element 2000. For example, these logic gate elements can be used to implement the multiplier or adder of the convolution circuit. These logic gate elements can also be used to implement registers, etc. The inventors have recognized that when the data blocks provided to the convolution circuit change frequently, the inputs of the logic gate elements that make up the convolution circuit will frequently flip. This may cause one or more outputs of these logic gate elements to also frequently flip. These outputs may be inputs to the logic gate elements of the next level. Accordingly, the frequent changes in the data blocks provided to the convolution circuit will adversely increase the flipping frequency of the logic gate elements of the convolution circuit, thereby increasing the flipping power consumption of the logic gate elements. The increased power consumption not only increases the computing cost, but also brings about heat dissipation problems. This is undesirable for hardware (e.g., a computing chip) that integrates a large number of convolution circuits.

[0051] Embodiments of the present disclosure provide improved circuits, chips, devices, and methods for convolution operations. In at least one aspect, embodiments of the present disclosure can reduce the flip power consumption of convolution circuits, thereby reducing the overall power consumption associated with convolution operations.

[0052] FIG3 shows a schematic diagram of a circuit 3000 for a convolution operation according to an embodiment of the present disclosure. The circuit 3000 may include a convolution circuit 3100. The convolution circuit 3100 may be configured to perform a convolution operation on the following items in each cycle: (1) at least a portion of input data from a plurality of input channels of a convolutional network, and (2) at least a portion of coefficient data of a plurality of convolution kernels of the convolutional network.

[0053] For example, the input data can be the multi-channel input data 1100 discussed with respect to FIG. 1 , and the coefficient data can be the multi-channel coefficient data 1200 discussed with respect to FIG. 1 . Each of the multiple convolution kernels can be associated with a corresponding output channel of the multiple output channels of the convolution network. For example, the first convolution kernel in FIG. 1 can be associated with the first output channel, and the second convolution kernel can be associated with the second output channel. At least a portion of the input data from the multiple input channels of the convolution network can be used as a first data block for the convolution operation. At least a portion of the coefficient data of the multiple convolution kernels of the convolution network can be used as a second data block for the convolution operation. In this cycle, the convolution operation can be performed on the entire first data block and the entire second data block.

[0054] It should be understood that although FIG3 shows input data 1100 and coefficient data 1200 as data sources external to circuit 3000, in some embodiments, input data 1100 and coefficient data 1200 may be data sources internal to circuit 3000. For example, circuit 3000 may have an additional storage device internally that can be used to receive and store input data 1100 and coefficient data 1200. In some scenarios, coefficient data 1200 is fixed for a given convolutional network. Therefore, coefficient data 1200 may be stored internally to circuit 3000.

[0055] To implement the convolution operation, convolution circuit 3100 may include a set of multipliers 3110 and adders 3120. Multipliers 3110 may be configured to perform n×n multiplication operations on corresponding pairs of data points in a first data block from input data 1100 and a second data block from coefficient data 1200. Adder 3120 may be configured to accumulate n×n result values ​​of these multiplication operations. In some embodiments, convolution circuit 3100 may include a set of n×n multipliers. In some embodiments, convolution circuit 3100 may include multiple sets of n×n multipliers.

[0056] The multiplier 3110 and the adder 3120 may include various logic gate elements. The logic gate elements may be configured to perform a convolution operation by the multiplication-accumulation operation as described above. Various suitable logic gate elements and combinations thereof may be used to implement the multiplier 3110 and the adder 3120 without departing from the scope of this disclosure. For the logic gate elements, the input and output of data are typically triggered by a periodic clock signal (not shown in the figure). In this disclosure, the period for the convolution operation may represent the time period required for the convolution circuit 3100 to complete the convolution operation of a pair of data blocks (i.e., the first data block and the second data block). This time period is typically substantially stable. This time period may span one or more clock cycles of the clock signal.

[0057] According to an embodiment of the present disclosure, circuit 3000 may optionally include control circuit 3200. For each cycle, control circuit 3200 may be configured to select a first data block from input data 1100 for the convolution operation of the current cycle, and to select a second data block from coefficient data 1200 for the convolution operation of the current cycle. In some embodiments, control circuit 3200 may be implemented as hardwired logic. In some embodiments, control circuit 3200 may be implemented as a hardware circuit controlled by software logic, where the software may be executable code instructions. In some embodiments, control circuit 3200 may be omitted.

[0058] According to an embodiment of the present disclosure, circuit 3000 may optionally include one or more registers 3300. Register 3300 may be used to store one or more results of one or more convolution operations, or the accumulated value of the results of multiple convolution operations. Although FIG3 shows that register 3300 is part of circuit 3000, those skilled in the art will appreciate that register 3300 may also be located outside circuit 3000.

[0059] According to an embodiment of the present disclosure, circuit 3000 may be configured such that at least one data block provided to convolution circuit 3100 for performing a convolution operation remains unchanged across multiple consecutive cycles. This may be performed, for example, by control circuit 3200. In some embodiments, the at least one data block that remains unchanged comprises a first data block provided to the convolution circuit from input data 1100. In some embodiments, the at least one data block that remains unchanged comprises a second data block provided to the convolution circuit from coefficient data 1200.

[0060] In some embodiments, circuit 3000 can be configured such that a first block of data from input data 1100 provided to the convolution circuit remains constant across multiple consecutive cycles, while a second block of data from coefficient data 1200 provided to the convolution circuit can vary during these cycles. For example, for a multi-channel convolution operation with CIN input channels and COUT output channels, circuit 3000 can be configured to perform CIN rounds of convolution operations. Each round of convolution operation can include COUT consecutive cycles, wherein the first block of data from input data 1100 provided to convolution circuit 3100 remains constant during these COUT consecutive cycles.

[0061] Specifically, during each of the COUT cycles of a convolution operation, circuit 3000 can be configured to provide the same input data from the same specific input channel to convolution circuit 3100 as a first data block. In other words, the same input data remains unchanged across the COUT cycles of the convolution operation. In each cycle, circuit 3000 can be configured to provide the corresponding coefficient data of a corresponding convolution kernel from a plurality of convolution kernels to convolution circuit 3100 as a second data block. In some embodiments, the corresponding convolution kernel associated with each cycle is determined based on at least the current cycle. For example, any method can be used to traverse the COUT convolution kernels during the COUT cycles, such that the second data blocks provided in different cycles during the COUT cycles are derived from coefficient data associated with different convolution kernels. After determining the first and second data blocks for each cycle in the manner described above, convolution circuit 3100 can perform a convolution operation on the determined first and second data blocks to obtain corresponding convolution results. The corresponding convolution results can be accumulated into corresponding registers among the plurality of registers 3300.

[0062] In some embodiments, further, the specific input channel from which the first data block is obtained can be changed across each of the CIN rounds of convolution operations. In other words, the specific input channel associated with each round of convolution operations can be different. The first data block used in each round of convolution operations can originate from a different input channel. In this way, CIN input channels can be traversed in a CIN round of convolution operations.

[0063] In some embodiments, further, multiple result values ​​associated with multiple output channels can be determined based at least on the multiple accumulated values ​​in the multiple registers 3300. Alternatively, corresponding bias values ​​from the multiple bias values ​​included in the bias data 1400 can be added to the corresponding accumulated values ​​in the corresponding registers in the multiple registers 3300 to determine corresponding result values ​​associated with the corresponding output channels in the multiple output channels. These corresponding result values ​​can represent multiple result values ​​associated with the multiple output channels. These multiple result values ​​can be output as part of the multi-channel output data 1300. It should be understood that the use of the bias values ​​is merely to provide additional correction to the convolution result. In some scenarios, this additional correction is optional. In some scenarios, additional correction may not be provided. Accordingly, the addition of any bias values ​​can be omitted.

[0064] FIG4 shows a schematic diagram of an exemplary process S400 for performing a multi-channel convolution operation according to an embodiment of the present disclosure. Process S400 is performed in the same instance 1000 as the aforementioned process S100. Therefore, process S400 is performed for the same multi-channel input data 1100, multi-channel coefficient data 1200, and multi-channel bias data 1400. Accordingly, process S400 produces the same convolution result (i.e., multi-channel output data 1300) as process S100. However, compared to process S100, process S400 has a different schedule such that the first data block provided to the convolution circuit from the input data 1100 remains unchanged across multiple consecutive cycles.

[0065] As part of a multi-channel convolution operation, process S400 may include steps S401-S406 performed sequentially. Steps S401-S406 may be divided into three rounds (CIN=3), each round including two cycles of convolution operations (COUT=2). Specifically, the first round includes steps S401-S402, the second round includes steps S403-S404, and the third round includes steps S405-S406. Each round may be associated with a corresponding input channel from a plurality of input channels. As an example, the first round, the second round, and the third round may be associated with the first input channel, the second input channel, and the third input channel, respectively.

[0066] Step S401 in the first round can occur in the first cycle. In this step, a portion of the input data X0 of the first input channel from the multi-channel input data 1100, namely X[0:2,0:2,0], is provided to the convolution circuit as the first data block. A portion of the coefficient array w0 of the multi-channel coefficient data 1200 corresponding to the first input channel, namely w0[:,:,0], is provided to the convolution circuit as the second data block. Accordingly, the convolution operation can be calculated as: R = X[0:2,0:2,0] * w0[:,:,0] = 1. The result R of the current convolution operation can be stored in the register temp0 corresponding to the first output channel.

[0067] Then, process S400 can proceed to step S402 in the first round. Step S402 can occur in the second cycle after the first cycle. In step S402, the first data block provided to the convolution circuit remains unchanged, that is, remains X[0:2,0:2,0]. The second data block is changed to a portion of the coefficient array w1 of the multi-channel coefficient data 1200 corresponding to the second input channel, that is, w1[:,:,0]. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R = X[0:2,0:2,0] * w1[:,:,0] = 0. The result R of the current convolution operation can be stored in the register temp1 corresponding to the second output channel.

[0068] Then, process S400 can proceed to the second round. The second round can start from step S403. Step S403 can occur in the third cycle after the second cycle. In step S403, the first data block is changed to a portion of the input data X1 of the second input channel from the multi-channel input data 1100, namely X[0:2,0:2,1]. The second data block is changed to a portion of the coefficient array w0 of the multi-channel coefficient data 1200 corresponding to the second input channel, namely w0[:,:,1]. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,1]*w0[:,:,1]=-1. The result R of the current convolution operation can be added to the previous value (i.e., 1) in the register temp0 corresponding to the first output channel. At this time, the accumulated value in the register temp0=1+(-1)=0.

[0069] Then, process S400 can proceed to step S404 of the second round. Step S404 can occur in the fourth cycle after the third cycle. In step S404, the first data block remains X[0:2,0:2,1]. The second data block is changed to a portion of the coefficient array w1 of the multi-channel coefficient data 1200 corresponding to the second input channel, namely w1[:,:,1]. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,1]*w1[:,:,1]=-1. The result R of the current convolution operation can be added to the previous value (i.e., 0) stored in the register temp1 corresponding to the second output channel. At this time, the accumulated value in the register temp1=0+(-1)=-1.

[0070] Then, process S400 can proceed to the third round. The third round can start from step S405. Step S405 can occur in the fifth cycle after the fourth cycle. In step S405, the first data block can be changed to a portion of the input data X2 of the third input channel from the multi-channel input data 1100, namely X[0:2,0:2,2]. The second data block can be changed to a portion of the coefficient array w0 of the multi-channel coefficient data 1200 corresponding to the third input channel, namely w0[:,:,2]. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,2]*w0[:,:,2]=0. The result R of the current convolution operation can be added to the previous value (i.e., 0) stored in the register temp0 corresponding to the first output channel. At this time, the accumulated value in the register temp0=0+0=0.

[0071] After the convolution operation for multiple input channels has been calculated with respect to coefficient array w0, the bias value associated with the first convolution kernel (i.e., bias0) can be added to the current accumulated value in register temp0. The result can be used as the corresponding data point of the first output array in multi-channel output data 1300, i.e., out[0,0,0] = 0 + 1 = 1. The accumulated value in register temp0 can be cleared.

[0072] Then, process S400 can proceed to step S406 of the third round. Step S406 can occur in the sixth cycle after the fifth cycle. In step S406, the first data block remains X[0:2,0:2,2]. The second data block is changed to a portion of the coefficient array w1 of the multi-channel coefficient data 1200 corresponding to the third input channel, namely w1[:,:,2]. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,2]*w1[:,:,2]=0. The result R of the current convolution operation can be added to the previous value (i.e., -1) stored in register temp1. At this time, the accumulated value in register temp1=(-1)+0=-1.

[0073] After the convolution operation for multiple input channels has been calculated with respect to coefficient array w1, the bias value associated with the second convolution kernel (i.e., bias1) can be added to the current accumulated value in register temp1. The result can be used as the corresponding data point of the second output array in multi-channel output data 1300. That is, out[0,0,1] = (-1) + 0 = -1. This data point is indicated by shading in FIG4. The accumulated value in register temp1 can be cleared.

[0074] In process S400, the first data block from the multi-channel input data 1100 changes across different rounds. For two calculation cycles in the same round, the first data block remains unchanged. Therefore, compared with process S100, process S400 can reduce the overall change frequency of the first data block and the second data block of the convolution circuit. For example, in the aforementioned six cycles of process S100, the first data block changed six times and the second data block changed six times, with the total number of changes of the two being 12. In comparison, in the aforementioned six cycles of process S400, the first data block only changed three times and the second data block changed six times, with the total number of changes of the two being nine times. By reducing the overall change frequency of the first data block and the second data block, the flip frequency of the various logic gate circuits that constitute the convolution circuit can be advantageously reduced, thereby reducing the flip power consumption of these logic gate circuits.

[0075] It should be understood that the execution order of steps S401-S406 of process S400 is merely exemplary. In other embodiments, the execution order of steps S401-S406 can be changed to achieve similar technical effects. For example, the order of steps within the same round can be exchanged, as long as the same first data block is used in each step of the round. Furthermore, the order in which the three rounds are executed can also be changed. For example, the second round (S403-S404) can be executed first, then the third round (S405-S406), and then the first round (S401-S402). The three rounds can also be executed in other suitable orders.

[0076] It should be understood that process S400 may include additional rounds. In these additional rounds, the input data of each input channel may be slid to obtain a first data block provided to the convolution circuit for the convolution operation. By sliding, the multi-channel input data 1100 may be traversed to obtain the remaining data points in the first output array and the second output array of the multi-channel output data 1300. The sliding may be based on a predetermined sliding step size. The predetermined sliding step size may be expressed as the number of data points slid through each time.

[0077] By way of example and not limitation, process S400 may perform three additional rounds for instance 1000: a fourth round, a fifth round, and a sixth round. By way of example, the fourth, fifth, and sixth rounds may be associated with the first, second, and third input channels, respectively, of the three input channels. In the fourth round, the first data block may remain as part of the input data X0 of the first input channel, e.g., X[0:2,2:4,0]. X[0:2,2:4,0] slides to the right by a predetermined sliding step of 2 relative to X[0:2,0:2,0] in the first round. In the two cycles of this round, the second data block may be w0[:,:,0] and w1[:,:,0], respectively. In the fifth round, the first data block may remain as part of the input data X1 of the second input channel, e.g., X[0:2,2:4,1]. X[0:2,2:4,1] slides to the right by a predetermined sliding step of 2 relative to X[0:2,0:2,1] in the second round. In the two cycles of this round, the second data blocks can be w0[:,:,1] and w1[:,:,1] respectively. In the sixth round, the first data block can remain as part of the input data X2 of the third input channel, for example, X[0:2,2:4,2]. X[0:2,2:4,2] slides to the right by a predetermined sliding step of 2 relative to X[0:2,0:2,2] in the second round. In the two cycles of this round, the second data blocks can be w0[:,:,2] and w1[:,:,2] respectively. A similar sliding operation can be performed to traverse all input data, and one or more rounds can be performed accordingly (where the sliding direction can be rightward or downward). In other embodiments, the predetermined sliding step can be other suitable positive integer values.

[0078] The following describes more general multi-channel input data 1100 and multi-channel coefficient data 1200. As described above, the multi-channel input data 1100 can be represented as a multi-dimensional array of size L×H×CIN, where CIN represents the number of input channels, L represents the width of the two-dimensional array corresponding to the input data of each input channel, and H represents the height of the two-dimensional array corresponding to the input data of each input channel. The multi-channel coefficient data 1200 can be represented as COUT coefficient arrays w0, w1, ..., w COUT-1 Each coefficient array can be represented as a multidimensional array of size n×n×CIN. In this case, the first data block and the second data block provided to the convolution circuit in each cycle can be selected as shown in Table 1.

[0079] Table 1

[0080] Specifically, the convolution circuit can be configured to perform CIN rounds of convolution operations. Each round of convolution operations can include COUT cycles. Accordingly, a total of CIN×COUT cycles are shown in Table 1. In the first round of the CIN round of convolution operations, the first data block remains X[0:n-1,0:n-1,0], and the second data block traverses COUT coefficient arrays w0, w1, ..., w COUT-1 . In the second round, the first data block remains X[0:n-1,0:n-1,1], and the second data block traverses the COUT coefficient arrays. And so on, until the CIN round. In the CIN round, the first data block remains X[0:n-1,0:n-1,CIN-1], and the second data block traverses the COUT coefficient arrays. The coefficient array used in the Kth cycle of each round can be determined based on the count K of the cycle (1≤K≤COUT). In the example of Table 1, the coefficient array can be w K-1 In addition, the convolution result obtained in this cycle can be accumulated into the corresponding register in the COUT registers. In the example of Table 1, the corresponding register can be Temp K-1 .

[0081] Optionally, a corresponding bias value in the COUT bias values ​​may be added to a corresponding accumulated value in a corresponding register in the COUT registers to determine a corresponding result value associated with a corresponding output channel in the COUT output channels. Specifically, the bias value Bias associated with the Kth output channel may be K-1 Add to register Temp K-1 The accumulated value in .

[0082] Through the CIN×COUT cycles shown in Table 1, a result of calculating one point on each of the COUT output channels can be obtained. In this process, the number of changes in the first data block is only 1 / COUT of the method shown in process S100.

[0083] It should be understood that the execution order shown in Table 1 is merely exemplary. In other embodiments, the order in which the CIN rounds are executed may also be changed. Furthermore, the order of the COUT steps within the same round may be changed while ensuring that the first data block used by the COUT steps remains unchanged.

[0084] In alternative embodiments, circuit 3000 can be configured such that, rather than maintaining the first data block constant, the second data block from coefficient data 1200 provided to the convolution circuit remains constant across multiple consecutive cycles. In these embodiments, the first data block from input data 1100 provided to the convolution circuit can vary during these cycles. For example, for a multi-channel convolution operation with CIN input channels, circuit 3000 can be configured to perform CIN rounds of convolution operations. Each round of convolution operation can include P consecutive cycles, wherein the second data block from coefficient data 1200 provided to convolution circuit 3100 remains constant during these P consecutive cycles. P can be an integer not less than 2.

[0085] In some embodiments, the value of P can be determined based on the size of the input data of each input channel and a predetermined sliding step size. As previously described, the input data of each input channel can be represented as a two-dimensional array of size L×H, where L represents the width of the two-dimensional array and H represents the height of the two-dimensional array. If the sliding in each round of convolution operation is performed horizontally on the two-dimensional array (for example, sliding to the left or right), the maximum value of P is P max1 It can indicate the maximum number of horizontal sliding allowed. For example, P max1 The value of can be determined based on the size parameter n, width L and predetermined horizontal sliding step size D1 of the convolution kernel. If the sliding in each round of convolution operation is performed vertically on the two-dimensional array (for example, sliding up or down), the maximum value P of P is max2 It can indicate the maximum number of vertical slides allowed. For example, P max2 The value of can be determined based on the size parameter n, height H and predetermined vertical sliding step size D2 of the convolution kernel. If the sliding in each round of convolution operation is performed horizontally and vertically on the two-dimensional array (for example, a combination of sliding to the right and sliding downward), the maximum value P of P is max3 It can indicate the maximum number of slides allowed. For example, P max3 The value of P can be determined based on the size parameter n, width L, predetermined horizontal sliding step D1, height H and predetermined vertical sliding step D2 of the convolution kernel. In some embodiments, the predetermined horizontal sliding step D1 can be the same as the predetermined vertical sliding step D2. In other embodiments, the predetermined horizontal sliding step D1 can be different from the predetermined vertical sliding step D2. A suitable value of P can be selected as needed, as long as the selected value does not exceed the corresponding maximum value allowed (P max1 、P max2 or P max3 ).

[0086] For each round of convolution operations in the CIN round of convolution operations, in each of the P cycles of the round of convolution operations, the circuit 3000 may be configured to provide a corresponding portion of input data from a specific input channel among the multiple input channels to the convolution circuit 3100 as the first data block, wherein the provided corresponding portion is determined based on at least a predetermined sliding step size and the cycle. In other words, the corresponding portion may vary with the cycle.

[0087] Furthermore, in each of the P cycles of the convolution operation, the circuit 3000 can be configured to provide the same coefficient data of the same specific convolution kernel among the multiple convolution kernels to the convolution circuit 3100 as the second data block. In other words, the same coefficient data remains unchanged across the P cycles of the convolution operation. When the first data block and the second data block used in each cycle are determined in the above manner, the convolution circuit 3100 can perform a convolution operation on the determined first data block and the second data block to obtain a corresponding convolution result. The corresponding convolution result can be accumulated in a corresponding register among the plurality of registers 3300.

[0088] In some embodiments, during a convolution operation, the input data for a particular input channel associated with that round can be slid based on an incrementing cycle count, thereby obtaining a corresponding portion used as the first data block in each of the P cycles of that round. Each cycle can be slid by a predetermined sliding step size. In this way, in two adjacent cycles, the first data blocks provided to the convolution circuit are two adjacent portions of input data from the particular input channel, with the second portion offset from the first portion by a predetermined sliding step size. The inventors have recognized that some input data exhibits local similarity. Accordingly, two spatially adjacent portions of the input data are likely to have small differences. This makes the difference between the first and second portions obtained by sliding relatively small. As a result, the first and second portions provided to the convolution circuit 3100 as the first data blocks for two adjacent cycles may not cause significant flipping of various components of the convolution circuit 3100. This helps reduce flipping power consumption in the convolution circuit. Examples of input data exhibiting significant local similarity include, but are not limited to, image data. For example, some image data may contain large areas of identical or similar patterns. In some embodiments, each pixel of an image is represented by 8 bits of data, so two data values ​​representing two adjacent pixels in the same image generally will not differ in all 8 bits. Instead, only a few of the 8 bits may differ, while the remaining bits are the same.

[0089] In some embodiments, further, across each round of convolution operations in CIN rounds of convolution operations, the second data block provided to the convolution circuit is changed from the coefficient data of the specific convolution kernel. In other words, the second data block used in different rounds of the CIN round of convolution operations can be a different portion of the coefficient data of the specific convolution kernel. Specifically, the second data block used in each round of convolution operations can be derived from a portion of the coefficient data of the specific convolution kernel corresponding to a different input channel. In this way, different portions of the coefficient data of the specific convolution kernel corresponding to CIN input channels can be traversed in the CIN round of convolution operations.

[0090] In some embodiments, further, in a round of convolution operation, multiple result values ​​of a specific output channel associated with a specific convolution kernel in multiple output channels can be determined based on at least multiple accumulated values ​​in multiple registers 3300. Optionally, the same bias value can be added to the multiple accumulated values ​​in the multiple registers respectively to determine the multiple result values ​​of the specific output channel. The same bias value can be a bias value associated with the specific convolution kernel (i.e., associated with the specific output channel) in the bias data 1400. These corresponding result values ​​can represent multiple result values ​​associated with the same specific output channel. The multiple result values ​​can be output as part of the multi-channel output data 1300. The use of the bias value is optional and not required.

[0091] FIG5 shows a schematic diagram of an exemplary process S500 for performing a multi-channel convolution operation according to an embodiment of the present disclosure. For ease of comparison, process S500 is performed in the same instance 1000 as the aforementioned process S100 and process S400. Therefore, process S500 is performed for the same multi-channel input data 1100, multi-channel coefficient data 1200, and multi-channel bias data 1400. Accordingly, process S500 produces the same convolution result (i.e., multi-channel output data 1300) as process S100 and process S400. However, compared to process S100 and process S400, process S500 has a different schedule.

[0092] As part of a multi-channel convolution operation, process S500 may include steps S501-S506 performed sequentially. Steps S501-S506 may be divided into three rounds (CIN=3), each round including two cycles of convolution operations (P=2). In the exemplary process S500, P is selected to be 2 to facilitate comparison of process S500 with the aforementioned processes S100 and S400. It will be appreciated that in alternative embodiments, P may be selected to be other suitable values. In process S500, the first round includes steps S501-S502, the second round includes steps S503-S504, and the third round includes steps S505-S506. As an example, the first, second, and third rounds may be associated with the coefficient array w0 of the same convolution kernel (e.g., the first convolution kernel). Specifically, the first, second, and third rounds may be associated with three different portions of the coefficient array w0, respectively. For example, a first round can be associated with a portion of the coefficient array w0 corresponding to the first input channel (i.e., w0[:,:,0]), a second round can be associated with a portion of the coefficient array w0 corresponding to the second input channel (i.e., w0[:,:,1]), and a third round can be associated with a portion of the coefficient array w0 corresponding to the third input channel (i.e., w0[:,:,2]).

[0093] Step S501 in the first round can occur in the first cycle. In this step, a portion of input data X0 from the first input channel of multi-channel input data 1100, namely X[0:2,0:2,0], is provided to the convolution circuit as the first data block. X[0:2,0:2,0] is shaded. A portion of coefficient array w0 corresponding to the first input channel, namely w0[:,:,0], is provided to the convolution circuit as the second data block. Accordingly, the convolution operation can be calculated as: R = X[0:2,0:2,0] * w0[:,:,0] = 1. The result R of the current convolution operation can be stored in register temp0.

[0094] Process S500 can then proceed to step S502 in the first round. Step S502 can occur in the second cycle after the first cycle. In step S502, the second data block provided to the convolution circuit remains unchanged, i.e., remains w0[:,:,0]. The first data block is changed to another portion of the input data X0 of the first input channel. This other portion can be obtained by sliding the previous first data block (i.e., X[0:2,0:2,0]) in the input data X0 by a predetermined sliding step size. In the example of Figure 5, the predetermined sliding step size is 2 (i.e., 2 data points), and the sliding direction is to the right. Therefore, the obtained other portion can be represented as X[0:2,2:4,0], which is used as the first data block in step S502, as shown in the bold box in Figure 5. Accordingly, the convolution operation can be calculated as: R = X[0:2,2:4,0]*w0[:,:,0] = -1. The result R of the current convolution operation may be stored in register temp1.

[0095] Then, process S500 can proceed to the second round. The second round can start from step S503. Step S503 can occur in the third cycle after the second cycle. In step S503, the first data block is changed to a portion of the input data X1 of the second input channel from the multi-channel input data 1100, namely X[0:2,0:2,1]. The second data block is changed to a portion of the coefficient array w0 of the multi-channel coefficient data 1200 corresponding to the second input channel, namely w0[:,:,1]. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,1]*w0[:,:,1]=-1. The result R of the current convolution operation can be added to the previous value (i.e., 1) in the register temp0. At this time, the accumulated value in the register temp0=1+(-1)=0.

[0096] Process S500 can then proceed to step S504 of the second round. Step S504 can occur in the fourth cycle after the third cycle. In step S504, the second data block provided to the convolution circuit remains unchanged, i.e., remains w0[:,:,1]. The first data block is changed to another portion of the input data X1 of the second input channel. This other portion can be obtained by sliding the previous first data block (i.e., X[0:2,0:2,1]) in the input data X1 by a predetermined sliding step size. In the example of Figure 5, the obtained other portion can be represented as X[0:2,2:4,1], which is used as the first data block in step S504, as shown in the bold box in Figure 5. Accordingly, the convolution operation can be calculated as: R = X[0:2,2:4,1] * w0[:,:,1] = -1. The result R of the current convolution operation can be added to the previous value (i.e., -1) stored in register temp1. At this time, the accumulated value in the register temp1 = (-1) + (-1) = -2.

[0097] Then, process S500 can proceed to the third round. The third round can start from step S505. Step S505 can occur in the fifth cycle after the fourth cycle. In step S505, the first data block can be changed to a portion of the input data X2 from the third input channel, namely X[0:2,0:2,2]. The second data block can be changed to a portion of the coefficient array w0 corresponding to the third input channel, namely w0[:,:,2]. At this time, the result R of the convolution operation of the convolution circuit can be calculated as: R=X[0:2,0:2,2]*w0[:,:,2]=0. The result R of the current convolution operation can be added to the previous value (i.e., 0) stored in register temp0. At this time, the accumulated value in register temp0=1+(-1)+0=0.

[0098] Process S500 can then proceed to step S506 of the third round. Step S506 can occur in the sixth cycle after the fifth cycle. In step S506, the second data block provided to the convolution circuit remains unchanged, i.e., remains w0[:,:,2]. The first data block is changed to another portion of the input data X2 of the third input channel. This other portion can be obtained by sliding the previous first data block (i.e., X[0:2,0:2,2]) in the input data X2 by a predetermined sliding step size. In the example of Figure 5, the obtained other portion can be represented as X[0:2,2:4,2], which is used as the first data block in step S506, as shown in the bold box in Figure 5. Accordingly, the convolution operation can be calculated as: R = X[0:2,2:4,2] * w0[:,:,2] = 1. The result R of the current convolution operation can be added to the previous value (i.e., -2) stored in register temp1. At this time, the accumulated value in the register temp1 is 1+(-2)=-1.

[0099] Additionally, the bias value associated with the first convolution kernel (i.e., bias0) can be added to the current accumulated values ​​in registers temp0 and temp1. Accordingly, corresponding data points of the first output array in multi-channel output data 1300 can be obtained, i.e., out[0,0,0]=0+1=1, out[0,1,0]=0+1=(-1)+1=0, as shown in the shaded areas. The accumulated values ​​in registers temp0 and temp1 can be cleared.

[0100] In process S500, the second data block from the multi-channel coefficient data 1200 can change across different rounds. For two calculation cycles in the same round, the second data block remains unchanged. Therefore, compared with process S100, process S500 can reduce the overall change frequency of the first data block and the second data block of the convolution circuit. For example, in the aforementioned six cycles of process S100, the first data block changed six times and the second data block changed six times, and the total number of changes of the two is 12. In comparison, in the aforementioned six cycles of process S500, the first data block changed six times and the second data block changed three times, and the total number of changes of the two is 9 times. By reducing the overall change frequency of the first data block and the second data block, the flip frequency of the various logic gate circuits constituting the convolution circuit can be advantageously reduced, thereby reducing the flip power consumption of these logic gate circuits.

[0101] It should be understood that the value of P selected in process S500 (i.e., P=2) is exemplary. In other embodiments, P may take different values ​​so that each round of convolution operations spans a greater number of cycles. For example, in another embodiment of example 1000, P may be selected as 3. In this case, each of the three rounds of convolution operations in process S500 may span three cycles. Accordingly, the first round of convolution operations may also include an additional step after steps S501 and S502. In this additional step, the second data block provided to the convolution circuit remains unchanged, i.e., remains as w0[:,:,0]. The first data block is changed to another portion of the input data X0 of the first input channel. This other portion may be obtained by sliding the previous first data block (i.e., X[0:2,2:4,0]) in the input data X0 to the right by a predetermined sliding step of 2. The obtained other portion can be represented as X[0:2,4:6,0], which is used as the first data block in this additional step. The convolution operation can be calculated as: R=X[0:2,4:6,0]*w0[:,:,0]. The result R of the current convolution operation can be stored in register temp2. ​​It can be understood that the second and third rounds of convolution operations in process S500 can each have similar additional steps.

[0102] It should be understood that the starting point (i.e., X[0:2,0:2,0]) and direction (i.e., rightward) of the sliding shown in process S500 are exemplary. In other embodiments, the sliding may have a different starting point and / or a different direction. In some embodiments, the first data block may slide from X[0:2,4:6,0] to the left. In some embodiments, the first data block may slide from X[0:2,0:2,0] to the downward direction. In some embodiments where P is greater than 3, the first data block may slide from X[0:2,0:2,0] to the right and continue to slide downward after reaching X[0:2,4:6,0]. Depending on the value of P, the direction of the sliding, and the step size of the sliding, there are various ways to slide on the input data.

[0103] Furthermore, the first data blocks used in two adjacent cycles within the same round are two adjacent parts of the input data of the same input channel. For input data with local similarity, the difference between these two parts is likely to be small. Therefore, although the first data blocks change between two adjacent cycles, this change may be small enough. A sufficiently small change may not cause a large number of flips in the various components of the convolution circuit 3100. This can advantageously further reduce the flip power consumption of the convolution circuit.

[0104] It should be understood that process S500 may include additional rounds. For example, additional rounds may be performed on the first data block obtained by further sliding, as described above. For another example, additional rounds may be performed on the coefficient array w1 of the second convolution kernel. Additional rounds may be performed until the multi-channel input data 1100 is traversed, thereby obtaining the remaining data points in the first output array and the second output array of the multi-channel output data 1300.

[0105] The following describes more general multi-channel input data 1100 and multi-channel coefficient data 1200. As described above, the multi-channel input data 1100 can be represented as a multi-dimensional array of size L×H×CIN, where CIN represents the number of input channels, L represents the width of the two-dimensional array corresponding to the input data of each input channel, and H represents the height of the two-dimensional array corresponding to the input data of each input channel. The multi-channel coefficient data 1200 can be represented as COUT coefficient arrays w0, w1, ..., w COUT-1 Each coefficient array can be represented as a multidimensional array of size n×n×CIN. In this case, the first data block and the second data block provided to the convolution circuit in each cycle can be selected as shown in Table 2, where D can be a positive integer representing a predetermined sliding step size.

[0106] Table 2

[0107] Specifically, the convolution circuit can be configured to perform CIN rounds of convolution operations. Each round of convolution operations may include P cycles. Accordingly, a total of CIN×P cycles are shown in Table 2. In the first round, the second data block remains at w0[:,:,0], and the first data block traverses the P parts of the first input data in a sliding manner. In the second round, the second data block remains at w0[:,:,1], and the first data block traverses the P parts of the second input data in a sliding manner. And so on, until the CINth round. In the CINth round, the second data block remains at w0[:,:,CIN-1], and the first data block traverses the P parts of the CINth input data in a sliding manner. The corresponding part of the input data used in the Kth cycle of each round can be determined based on the count K of the cycle (1≤K≤P). In addition, the convolution result obtained in the cycle can be accumulated to the corresponding register among the P registers. In the example of Table 2, the corresponding register can be Temp K-1 .

[0108] Optionally, the same offset value from among the COUT offset values ​​associated with the COUT output channels can be added to the corresponding accumulated value in the corresponding register among the P registers to determine P result values ​​associated with the same output channel among the COUT output channels. Through the CIN × P cycles shown in Table 2, P point results can be obtained for one output channel. In this process, the rate of change of the second data block is only 1 / P of that in the method shown in process S100. Furthermore, due to the local similarity of the input data, the flipping of logic gate elements caused by changes in the first data block can also be reduced, further reducing the flipping power consumption of the convolution circuit.

[0109] It should be understood that the execution order shown in Table 2 is merely exemplary. In other embodiments, the order in which the CIN rounds are executed may also be changed. Furthermore, while ensuring that the second data blocks used by the P steps within the same round remain unchanged, the order of the P steps may be changed. Furthermore, the sliding shown in Table 2 is a rightward slide. As previously mentioned, different sliding directions may be used in other embodiments.

[0110] Figure 6 shows a flowchart of an exemplary method 6000 for a convolution operation according to an embodiment of the present disclosure. Method 6000 may include steps S601-S602. Step S601 may include providing a convolution circuit. The convolution circuit may be configured to perform a convolution operation on the following two items in each cycle: (1) at least a portion of input data from multiple input channels of a convolution network, and (2) at least a portion of coefficient data of multiple convolution kernels of the convolution network. Each convolution kernel of the multiple convolution kernels of the convolution network may be associated with a corresponding output channel of the multiple output channels of the convolution network. An example of a convolution circuit may include the convolution circuit 3100 described above. Step S602 may include causing the following item provided to the convolution circuit to perform the convolution operation to remain unchanged across multiple consecutive cycles: (1) a first data block of the input data provided to the convolution circuit, or (2) a second data block of the coefficient data provided to the convolution circuit. In some embodiments, step S602 may be performed, for example, by the control circuit 3200 described above.

[0111] In optional embodiments, method 6000 may include one or more additional steps. In some embodiments, the number of the plurality of input channels is CIN, the number of the plurality of output channels is COUT, and method 6000 may include: configuring the convolution circuit to perform CIN rounds of convolution operations, each round of convolution operations comprising a plurality of consecutive cycles, wherein: a first data block of the input data provided to the convolution circuit remains unchanged during the plurality of consecutive cycles; or a second data block of the coefficient data provided to the convolution circuit remains unchanged during the plurality of consecutive cycles.

[0112] In some embodiments, the plurality of consecutive cycles is COUT cycles. Method 6000 may include: in each of the COUT consecutive cycles: providing the same input data from the same specific input channel to the convolution circuit as a first data block; providing the convolution circuit with corresponding coefficient data of a corresponding convolution kernel from a plurality of convolution kernels as a second data block, wherein the corresponding convolution kernel is determined based on at least the cycle; performing a convolution operation on the first data block and the second data block by the convolution circuit to obtain a corresponding convolution result; and accumulating the corresponding convolution result into a corresponding register from a plurality of registers.

[0113] In some of the aforementioned embodiments, the method 6000 may further include changing the particular input channel from which the first data block is obtained across each of the CIN rounds of convolution operations.

[0114] In some of the foregoing embodiments, the method 6000 may further include determining a plurality of result values ​​associated with the plurality of output channels based at least on the plurality of accumulated values ​​in the plurality of registers. Specifically, the method may include adding corresponding bias values ​​from the plurality of bias values ​​to corresponding accumulated values ​​in corresponding registers from the plurality of registers to determine corresponding result values ​​associated with corresponding output channels from the plurality of output channels.

[0115] In some other embodiments, the plurality of consecutive cycles is P cycles. Method 6000 may include: in each of the P consecutive cycles: providing a corresponding portion of input data from a specific input channel among a plurality of input channels to a convolution circuit as a first data block, wherein the corresponding portion is determined based on at least a predetermined sliding step size and a cycle; providing the same coefficient data of a specific convolution kernel among a plurality of convolution kernels to the convolution circuit as a second data block; performing a convolution operation on the first data block and the second data block by the convolution circuit to obtain a corresponding convolution result; and accumulating the corresponding convolution result into a corresponding register among a plurality of registers.

[0116] In some of the above embodiments, method 6000 may further include providing a first part and a second part of the input data from a specific input channel to the convolution circuit in two adjacent cycles of the consecutive P cycles, respectively, wherein the second part is offset with respect to the first part by a predetermined sliding step size.

[0117] In a preferred embodiment, the input data used by method 6000 may be image data.

[0118] In some of the above embodiments, method 6000 may further include changing the second data block provided to the convolution circuit from coefficient data of a particular convolution kernel across each of the CIN rounds of convolution operations.

[0119] In some of the foregoing embodiments, method 6000 may further include determining, based at least on the multiple accumulated values ​​in the multiple registers, multiple result values ​​for a specific output channel associated with the specific convolution kernel among the multiple output channels. For example, the same bias value may be added to the multiple accumulated values ​​in the multiple registers to determine the multiple result values ​​for the specific output channel.

[0120] In some embodiments, the input data used by method 6000 is associated with at least one of: original input data of the convolutional network; feature data generated by one or more layers of the convolutional network based on the original input data; or a combination of the two.

[0121] In some embodiments, the coefficient data used by method 6000 is associated with one or more weight coefficients of a convolutional network.

[0122] FIG7 shows a schematic diagram of a computing chip 7000 according to an embodiment of the present disclosure. The computing chip 7000 may include one or more convolution calculation circuits 7100. Examples of the convolution calculation circuit 7100 may include the circuit 3000 described above with respect to FIG3 . The computing chip 7000 may be used to perform one or more functions associated with convolution operations. In some embodiments, the computing chip 7000 may be implemented as a dedicated CNN chip. Those skilled in the art will appreciate that the computing chip 7000 may include other components not shown.

[0123] FIG8 shows a schematic diagram of a computing device 8000 according to an embodiment of the present disclosure. The computing device 8000 may include a computing chip 8100. Examples of the computing chip 8100 may include the computing chip 7000 described above with respect to FIG7 . The computing device 8000 may be used to perform one or more functions associated with convolution operations. In some embodiments, the computing device 8000 may be implemented as a dedicated CNN server. In some embodiments, the computing device 8000 may be a general-purpose computing device loaded with the computing chip 8100. Those skilled in the art will appreciate that the computing device 8000 may include other components not shown.

[0124] The present disclosure may also provide a computing device, which may include one or more processors and a memory storing computer executable instructions, which, when executed by one or more processors, cause one or more processors to perform the method described in any of the foregoing embodiments of the present disclosure. The computing device may include (one or more) processors and a memory storing computer executable instructions, which, when executed by (one or more) processors, cause (one or more) processors to perform the method described in any of the foregoing embodiments of the present disclosure. For example, the processor may control the operation of circuit 3000. (One or more) processors may, for example, be a central processing unit (CPU) of the computing device. (One or more) processors may be any type of general-purpose processor, or may be a processor specifically designed for data transmission type conversion of a SOC chip, such as an application-specific integrated circuit ("ASIC"). The memory may include various computer-readable media accessible by (one or more) processors. In various embodiments, the memory described herein may include volatile and non-volatile media, removable and non-removable media. For example, the memory may include any combination of the following: random access memory ("RAM"), dynamic RAM ("DRAM"), static RAM ("SRAM"), read-only memory ("ROM"), flash memory, cache memory, and / or any other type of non-transitory computer-readable medium. The memory may store instructions that, when executed by the processor, cause the processor to perform the data transmission type conversion method described in any of the aforementioned embodiments of the present disclosure.

[0125] In addition, the present disclosure may also provide a non-volatile storage medium having computer-executable instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to execute the method according to any of the aforementioned embodiments of the present disclosure.

[0126] The words "left," "right," "front," "back," "top," "bottom," "up," "down," "high," "low," and the like, if any, in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein, for example, are capable of operation in orientations other than those illustrated or otherwise described herein. For example, features previously described as "above" other features could be described as "below" the other features when the apparatus in the accompanying drawings is turned over. The apparatus can also be otherwise oriented (rotated 90 degrees or in other orientations) and relative spatial relationships will be interpreted accordingly.

[0127] In the specification and claims, when an element is referred to as being "on," "attached," "connected," "coupled," or "in contact with," another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly in contact with, another element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly attached," "directly connected," "directly coupled," or "in direct contact with," another element, there may be no intervening elements. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that the feature has a portion that overlaps with the adjacent feature or a portion that is located above or below the adjacent feature.

[0128] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not to be bound by any expressed or implied theory presented in the technical field, background, summary, or detailed description.

[0129] As used herein, the term "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0130] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0131] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0132] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0133] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0134] Those skilled in the art will appreciate that the boundaries between the above-mentioned operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are also possible. Aspects and elements of all embodiments disclosed above can be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative, not restrictive.

[0135] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art will appreciate that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A circuit for convolution operation, wherein: The circuit comprises: A convolution circuit configured to perform a convolution operation on: (1) at least a portion of input data from a plurality of input channels of a convolutional network, and (2) at least a portion of coefficient data of a plurality of convolutional kernels of the convolutional network, wherein each convolutional kernel of the plurality of convolutional kernels is associated with a corresponding output channel of a plurality of output channels of the convolutional network, in each cycle; The circuit is configured such that one of the following provided to the convolution circuit to perform a convolution operation remains unchanged across multiple consecutive cycles: (1) a first data block of the input data provided to the convolution circuit, or (2) a second data block of the coefficient data provided to the convolution circuit.

2. The circuit of claim 1, wherein: The number of the plurality of input channels is CIN, the number of the plurality of output channels is COUT, and the circuit is configured as follows: CIN rounds of convolution operations are performed, each round of convolution operations includes COUT consecutive cycles, wherein the first data block in the input data provided to the convolution circuit remains unchanged during the COUT consecutive cycles.

3. The circuit of claim 2, wherein: The circuit is configured as: In each of the consecutive COUT cycles: providing the convolution circuit with the same input data from the same specific input channel as a first data block; providing the convolution circuit with corresponding coefficient data of a corresponding convolution kernel among the plurality of convolution kernels as a second data block, wherein the corresponding convolution kernel is determined based on at least the period; Performing a convolution operation on the first data block and the second data block by the convolution circuit to obtain a corresponding convolution result; and The corresponding convolution result is accumulated into a corresponding register in a plurality of registers.

4. The circuit of claim 3, wherein: The circuit is configured as: The particular input channel from which the first data block is obtained is changed across each of the CIN rounds of convolution operations.

5. The circuit of claim 4, wherein: The circuit is also configured to: A plurality of result values ​​associated with the plurality of output channels are determined based at least on the plurality of accumulated values ​​in the plurality of registers.

6. The circuit of claim 5, wherein: The circuit is also configured to: A respective bias value of the plurality of bias values ​​is added to a respective accumulated value in a respective register of the plurality of registers to determine a respective result value associated with a respective output channel of the plurality of output channels.

7. The circuit of claim 1, wherein: The number of the plurality of input channels is CIN, and the circuit is configured as follows: CIN rounds of convolution operations are performed, each round of convolution operations includes P consecutive cycles, wherein the second data block in the coefficient data provided to the convolution circuit remains unchanged during the P consecutive cycles, wherein P is an integer not less than 2.

8. The circuit of claim 7, wherein: The circuit is configured as: In each of the P consecutive cycles: providing a corresponding portion of input data from a same specific input channel of the plurality of input channels to the convolution circuit as a first data block, wherein the corresponding portion is determined based on at least a predetermined sliding step size and the period; providing the convolution circuit with the same coefficient data of the same specific convolution kernel among the plurality of convolution kernels as a second data block; Performing a convolution operation on the first data block and the second data block by the convolution circuit to obtain a corresponding convolution result; and The corresponding convolution result is accumulated into a corresponding register in a plurality of registers.

9. The circuit of claim 8, wherein: The circuit is configured as: In two adjacent cycles among the consecutive P cycles, a first part and a second part of the input data from the specific input channel are respectively provided to the convolution circuit, wherein the second part is offset from the first part by the predetermined sliding step size.

10. The circuit of claim 9, wherein the input data is image data.

11. The circuit of claim 8, wherein: The circuit is also configured to: Across each of the CIN rounds of convolution operations, the second data block provided to the convolution circuit is changed from the coefficient data of the particular convolution kernel.

12. The circuit of claim 8, wherein: The circuit is configured as: Based at least on the plurality of accumulated values ​​in the plurality of registers, a plurality of result values ​​of a particular output channel in the plurality of output channels associated with the particular convolution kernel are determined.

13. The circuit of claim 12, wherein: The circuit is configured as: The same offset value is added to the plurality of accumulated values ​​in the plurality of registers, respectively, to determine the plurality of result values ​​of the specific output channel.

14. The circuit of claim 1, wherein: The convolution circuit includes a multiplier and an adder, and the multiplier and the adder include logic gate elements, and the logic gate elements are configured to perform the convolution operation through a multiply-accumulate operation.

15. The circuit of claim 1, wherein the input data is associated with at least one of: The raw input data to the convolutional network; or One or more layers of a convolutional network generate feature data based on the original input data.

16. The circuit of claim 1, wherein: The coefficient data is associated with one or more weight coefficients of the convolutional network.

17. A computing chip, comprising a circuit for convolution operation as claimed in any one of claims 1 to 16.

18. A computing device comprising the computing chip according to claim 17.

19. A method for convolution operation, comprising: A convolution circuit is provided, the convolution circuit being configured to perform a convolution operation on the following two items in each cycle: (1) at least a portion of input data from a plurality of input channels of a convolutional network, and (2) at least a portion of coefficient data of a plurality of convolutional kernels of the convolutional network, each convolutional kernel of the plurality of convolutional kernels being associated with a corresponding output channel of a plurality of output channels of the convolutional network; Causes one of the following provided to the convolution circuit to perform a convolution operation to remain constant across multiple consecutive cycles: (1) a first data block of the input data provided to the convolution circuit, or (2) a second data block of the coefficient data provided to the convolution circuit.

20. The method of claim 19, wherein: The number of the plurality of input channels is CIN, and the method comprises: The convolution circuit is configured to perform CIN rounds of convolution operations, each round of convolution operations comprising a plurality of consecutive cycles, wherein: The first data block of the input data provided to the convolution circuit remains unchanged during the plurality of consecutive cycles; or The second data block of the coefficient data provided to the convolution circuit remains unchanged during the plurality of consecutive cycles.

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