System and method for substrate disturbance minimization, and lithographic apparatus including the system

Abstract

The present disclosure provides a lithographic process for handling two substrates in parallel, the process comprising the steps of: - exposing a first substrate on a first substrate table; - determining an available delay time for executing a second substrate sequence for measuring of a second substrate, and - optimizing the second substrate sequence taking into account the available delay time by delaying at least a part of the second substrate sequence. The second substrate is a closing wafer and the second substrate sequence is a closing wafer sequence. The process comprises the steps of determining whether the second substrate sequence is production critical; and if the second substrate sequence is production critical, executing the second substrate sequence without delay.

Description

SYSTEM AND METHOD FOR SUBSTRATE DISTURBANCE MINIMIZATION, ANDLITHOGRAPHIC APPARATUS INCLUDING THE SYSTEMCROSS-REFERENCE TO RELATED APPLICATION

[0001] The application claims priority of EP application 23195470.2 which was filed on 05 September, 2023 and which is incorporated herein in its entirety by reference.FIELD

[0002] The present invention relates to a system and method for substrate disturbance minimization. The substrate herein may be a wafer or other type of substrate suitable for lithographic processing. In particular, the system and method relate to the minimization of disturbance of a substrate handled in one part of a lithographic apparatus on processing of another substrate in the same apparatus.BACKGROUND

[0003] A lithographic apparatus is a machine constructed to apply a desired pattern onto a substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A lithographic apparatus may, for example, project a pattern (also often referred to as “design layout” or “design”) of a patterning device (e.g., a mask) onto a layer of radiation- sensitive material (resist) provided on a substrate (e.g., a wafer).

[0004] As semiconductor manufacturing processes continue to advance, the dimensions of circuit elements have continually been reduced while the amount of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as ‘Moore’s law’. To keep up with Moore’s law the semiconductor industry is chasing technologies that enable to create increasingly smaller features. To project a pattern on a substrate a lithographic apparatus may use electromagnetic radiation. The wavelength of this radiation determines the minimum size of features which are patterned on the substrate. Typical wavelengths currently in use are 365 nm (i-line), 248 nm, 193 nm and 13.5 nm. A lithographic apparatus, which uses extreme ultraviolet (EUV) radiation, having a wavelength within a range of 4 nm to 20 nm, for example 6.7 nm or 13.5 nm, may be used to form smaller features on a substrate than a lithographic apparatus which uses, for example, radiation with a wavelength of 193 nm.

[0005] In an everlasting effort to speed up production, substrate handling is streamlined into utmost detail. Typically, a wafer stage of a lithography apparatus has at least two substrate tables. A first substrate table may allow to perform preparatory measurements at the measure side, while a second substrate table enables exposure of another substrate in parallel at the exposure side. However, the movements of the first substrate table may negatively impact the performance of the second substrate table. Often, the negative impact can be predicted and mitigated by compensatory movements.However, in some instances this is not possible, or at least insufficiently so. If so, substrate movements at the measurement side may introduce overlay issues at the exposure side.

[0006] The present disclosure aims to provide an alternative system and method to mitigate or obviate overlay disturbances.SUMMARY

[0007] The disclosure provides a lithographic process for handling two substrates in parallel, the process comprising the steps of:- exposing a first substrate on a first substrate table;- determining an available delay time for executing a second substrate sequence for measuring of a second substrate, and- optimizing the second substrate sequence taking into account the available delay time by delaying at least a part of the second substrate sequence.

[0008] In an embodiment, the second substrate is a closing wafer and wherein the second substrate sequence is a closing wafer sequence.

[0009] In an embodiment, the process comprises the steps of:- determining whether the second substrate sequence is production critical; and- if the second substrate sequence is production critical, executing the second substrate sequence without delay.

[0010] In an embodiment, the step of optimizing the second substrate sequence comprises shifting a start of the second substrate sequence until the step of exposing the first substrate is finished, if the available delay time exceeds a time left to finalize the step of exposing the first substrate.

[0011] In an embodiment, the step of optimizing the second substrate sequence comprises using the available delay time to minimize impact on the step of exposing the first substrate.

[0012] In an embodiment, the step of optimizing the second substrate sequence comprises one or more of:- slowing down one or more steps included in the second substrate sequence;- delaying one or more steps included in the second substrate sequence; or- introducing delays in between one or more steps included in the second substrate sequence.

[0013] According to another aspect, the disclosure provides a lithographic apparatus for handling two substrates in parallel, the apparatus comprising: a substrate stage comprising at least a first substrate table and a second substrate table; at least one substrate handler for moving substrates onto the first or second substrate table; an exposure system for exposing a substrate positioned on the first substrate table or the second substrate table; and a measurement system for executing a second substrate sequence on the first substrate table or the second substrate table; anda control system adapted to determine an available delay time for executing the second substrate sequence, and to optimize the second substrate sequence taking into account the available delay time.

[0014] In an embodiment, the control system is adapted to:- determine whether the second substrate sequence is production critical; and- if the second substrate sequence is production critical, to execute the second substrate sequence without delay.

[0015] In an embodiment, the control system is adapted to shift the second substrate sequence until the step of exposing the first substrate is finished, if the available delay time exceeds a time left to expose the first substrate.

[0016] In an embodiment, the control system is adapted to optimize the second substrate sequence, by one or more of:- slowing down one or more steps included in the second substrate sequence;- delaying one or more steps included in the second substrate sequence; or- introducing delays in between one or more steps included in the second substrate sequence.BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:Figure 1 depicts a schematic overview of a lithographic apparatus;Figure 2 depicts a top view of an exemplary substrate stage of a lithographic apparatus;Figure 3 depicts a side view of an exemplary substrate stage of a lithographic apparatus;Figure 4 depicts a diagram indicating exemplary moves of two substrate tables (on the vertical axis) with respect to time t (horizontal axis), wherein one substrate table is on the expose side and the other substrate table executes a measurement sequence;Figure 5 depicts steps in an embodiment of a method according to the disclosure;Figure 6A depicts exemplary overlay disturbances in exposure in a conventional system;Figure 6B depicts exemplary reduced overlay disturbance in exposure when using the method of the disclosure; andFigures 7A to 7F schematically depict examples of overlay disturbances on the expose side due to a closing wafer sequence on the measure side.DETAILED DESCRIPTION

[0018] In the present document, the terms “radiation” and “beam” are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g. having a wavelength in the range of about 5-100 nm).

[0019] The term “reticle”, “mask” or “patterning device” as employed in this text may be broadly interpreted as referring to a generic patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. The term “light valve” can also be used in this context. Besides the classic mask (transmissive or reflective, binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include a programmable mirror array and a programmable LCD array.

[0020] The term "overlay error" as used herein refers to horizontal placement error between respective layers of a lithographic process. Said horizontal error may typically impact the quality of a chip. One key task of a lithography apparatus is the ability to image dense lines and spaces from the mask to the wafer. Here, the critical dimension (the width of a line), the pitch (the distance between lines) and the straightness of each of the lines are important, as well as overlay error.

[0021] Figure 1 schematically depicts a lithographic apparatus LA. The lithographic apparatus LA includes an illumination system (also referred to as illuminator) IL configured to condition a radiation beam B (e.g., UV radiation, DUV radiation or EUV radiation), a mask support (e.g., a mask table) MT constructed to support a patterning device (e.g., a mask) MA and connected to a first positioner PM configured to accurately position the patterning device MA in accordance with certain parameters, a substrate support (e.g., a wafer table) WT constructed to hold a substrate (e.g., a resist coated wafer) W and connected to a second positioner PW configured to accurately position the substrate support in accordance with certain parameters, and a projection system (e.g., a refractive projection lens system) PS configured to project a pattern imparted to the radiation beam B by patterning device MA onto a target portion C (e.g., comprising one or more dies) of the substrate W.

[0022] In operation, the illumination system IL receives a radiation beam from a radiation source SO, e.g. via a beam delivery system BD. The illumination system IL may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic, and / or other types of optical components, or any combination thereof, for directing, shaping, and / or controlling radiation. The illuminator IL may be used to condition the radiation beam B to have a desired spatial and angular intensity distribution in its cross section at a plane of the patterning device MA.

[0023] The term “projection system” PS used herein should be broadly interpreted as encompassing various types of projection system, including refractive, reflective, catadioptric, anamorphic, magnetic, electromagnetic and / or electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation being used, and / or for other factors such as the use of an immersion liquid or the use of a vacuum. Any use of the term “projection lens” herein may be considered as synonymous with the more general term “projection system” PS.

[0024] As depicted in Figure 1, the lithographic apparatus is of a transmissive type (e.g. employing a transmissive mask). Alternatively, the apparatus may be of a reflective type (e.g. employing a programmable mirror array of a type as referred to above, or employing a reflective mask).

[0025] The lithographic apparatus LA may be of a type wherein at least a portion of the substrate may be covered by a liquid having a relatively high refractive index, e.g., water, so as to fill a space between the projection system PS and the substrate W - which is also referred to as immersion lithography. More information on immersion techniques is given in US6952253, which is incorporated herein by reference.

[0026] The lithographic apparatus LA may also be of a type having two or more substrate supports WT (also named “dual stage”). In such “multiple stage” machine, the substrate supports WT may be used in parallel, and / or steps in preparation of a subsequent exposure of the substrate W may be carried out on the substrate W located on one of the substrate support WT while another substrate W on the other substrate support WT is being used for exposing a pattern on the other substrate W.

[0027] In addition to the substrate support WT, the lithographic apparatus LA may comprise a measurement stage. The measurement stage is arranged to hold a sensor and / or a cleaning device. The sensor may be arranged to measure a property of the projection system PS or a property of the radiation beam B. The measurement stage may hold multiple sensors. The cleaning device may be arranged to clean part of the lithographic apparatus, for example a part of the projection system PS or a part of a system that provides the immersion liquid. The measurement stage may move beneath the projection system PS when the substrate support WT is away from the projection system PS.

[0028] In operation, the radiation beam B is incident on the patterning device, e.g. mask, MA which is held on the mask support MT, and is patterned by the pattern (design layout) present on patterning device MA. Having traversed the mask MA, the radiation beam B passes through the projection system PS, which focuses the beam onto a target portion C of the substrate W. With the aid of the second positioner PW and a position measurement system IF, the substrate support WT can be moved accurately, e.g., so as to position different target portions C in the path of the radiation beam B at a focused and aligned position. Similarly, the first positioner PM and possibly another position sensor (which is not explicitly depicted in Figure 1) may be used to accurately position the patterning device MA with respect to the path of the radiation beam B. Patterning device MA and substrate W may be aligned using mask alignment marks Ml, M2 and substrate alignment marks Pl, P2. Although the substrate alignment marks Pl, P2 as illustrated occupy dedicated target portions, they may be located in spaces between target portions. Substrate alignment marks Pl, P2 are known as scribe-lane alignment marks when these are located between the target portions C.

[0029] To clarify the invention, a Cartesian coordinate system is used. The Cartesian coordinate system has three axes, i.e., an x-axis, a y-axis and a z-axis. Each of the three axes is orthogonal to the other two axes. A rotation around the x-axis is referred to as an Rx-rotation. A rotation around the y- axis is referred to as an Ry-rotation. A rotation around about the z-axis is referred to as an Rz-rotation. The x-axis and the y-axis define a horizontal plane, whereas the z-axis is in a vertical direction. The Cartesian coordinate system is not limiting the invention and is used for clarification only. Instead, another coordinate system, such as a cylindrical coordinate system, may be used to clarify the invention.The orientation of the Cartesian coordinate system may be different, for example, such that the z-axis has a component along the horizontal plane.

[0030] Figures 2 and 3 show an exemplary overview of a substrate stage WS. The substrate stage comprises a base frame BF having a substantially flat and planar top surface PAM. The substrate stage comprises two or more substrate tables WT1, WT2, WT3. The substrate tables are moveable with respect to the planar surface PAM. For instance, one or more guide rails LG1, LG2 may be provided at or near, for instance adjacent to the planar surface. Each positioning module PW1, PW2, PW3 may be connected to one of the guide rails, allowing planar movement of the respective modules with respect to the planar surface PAM. Other drive means for moving the substrate modules with respect to the planar surface are also conceivable, such as electromagnetic drives.

[0031] The respective substrate tables WT1, WT2, WT3 may typically be able to move with respect to their respective positioning modules PW1, PW2, PW3. Herein, the positioning modules PW1, PW2, PW3 may typically enable relatively fast movement, whereas movement of the substrate tables WT1, WT2, WT3 may enable very accurate movements. In the field of lithography, the positioning modules PW1, PW2, PW3 may also be referred to as a "long stroke module". The corresponding substrate tables WT1, WT2, WT3 may also be referred to as a "short stroke module".

[0032] One or more substrate handlers SHI, SH2 may be arranged adjacent to the substrate stage WS. The respective substrate handler typically comprises one or more storage positions WSL for holding a stack of substrates. The stack of substrates may also be referred to as a substrate lot WL. A substrate lot herein typically comprises a number of substrates each intended for a specific step in a lithographic process. Each substrate handler may be provided with one or more robot arms RAI, RA2 for transferring substrates W from one of the storage locations WSL to one of the substrate tables, or vice versa.

[0033] The substrate stage may be provided with an exposure station EST. The exposure station may refer to a location or area where a substrate W on one of the substrate tables can be exposed to radiation for patterning resist on said substrate. See also Figure 1 and the related description above. The substrate stage may be provided with another location or area intended for executing certain measurements. Said location or area may be referred to as measurement station MST. The measurements herein may include, but are not limited to, pre-expose measurements - such as surface, height, and topography mapping, and accurate positioning- and post-expose measurements such as control of exposed patterns. The measurement station MST, see Fig. 3, may include one or more sensors and related control equipment intended for the measurements as referenced. However, said sensors may also be included in or on the respective substrate tables or at any other viable position.

[0034] Please note that Figures 2 and 3 serve as a generic reference. Many other setups for a substrate stage setup are conceivable. Basically, the figures exemplify how a single substrate stage may comprise multiple substrate tables which may move individually with respect to each other and be involved in different steps in the lithographic process in parallel.

[0035] One particular problem may arise with closing substrates, basically the last substrate of a particular substrate stack. Herein, lithography machines are typically programmed to execute a particular closing substrate sequence. Said sequence may, however, be relatively course and elaborate, so much so that its related substrate table moves may negatively influence exposure of another substrate located at the expose station EST.

[0036] For instance in immersion lithography systems, at the end of a substrate lot, without a new streamed lot in the lot queue, the system will load the closing substrate on one of the substrate tables. The closing wafer needs to be “approved for immersion” in order to be allowed to go to the expose side, which in case of an immersion system has an Immersion Hood providing relatively limited vertical headroom. Also, in some situations with lot streaming, a closing wafer is loaded in-between lots. Practically this means that in many situations the last wafer exposure in a lot is done in parallel with the load of the closing wafer and its subsequent approve wafer sequence.

[0037] Figure 4 shows a diagram wherein the vertical axis indicates an example of positioning tracings in x-direction and y-direction of respective positioning modules PW 1 and PW2 versus time t on the horizontal axis. The tracings relate to the exposure of a last substrate of a lot positioned on the second substrate table WT2. Meanwhile, a closing wafer has been loaded on the first substrate table WT1 positioned on the first positioning module PW1 and is being approved for immersion. The latter may be referred to as an approve wafer sequence.

[0038] As can be seen in Figure 4, the approve wafer sequence comprises several specific moves on the measure side, for instance at times tl to t5.

[0039] Figures 7A to 7F show respective examples of overlay errors for the exposure cycle of the last wafer of a lot. The plots 7A to 7F indicate, see the square markings, overlay errors on the expose side which exceed overlay errors for other fields. The respective fields having said increased overlay errors correspond, in their time of exposure, with wafer table and associated positioning module moves on the measure side. Therefore, the increased overlay errors are probably caused by the approve closing wafer moves on the measure side. The individual movements of the first substrate table on the measure side negatively affect the substrate exposure on the expose side, resulting in an overlay error in some fields, corresponding to wafer table moves on the measure side.

[0040] However, it is not only the movements of the substrate table related to the approve wafer sequence which can disturb the exposure. Also pressure waves from the wafer load sequence itself can induce disturbances, for instance onto grid plates on the measure side and / or the expose side, as can be seen from, for instance, grid plate active stiffness tracings. Variations in grid plate excitations will also affect performance.

[0041] The idea of the present disclosure is the creation of an inline closing wafer sequence optimization mechanism. See Figure 5 for exemplary method steps. These steps are described in more detail below.

[0042] In a first step 10, the system WS prepares the loading of a closing wafer from a storage location WSL onto one of the substrate tables. A control system is instructed to load and execute the approve wafer sequence for the respective closing wafer.

[0043] In a second step, the method of the disclosure may derive how critical the closing wafer sequence is with respect to productivity. In some situations the closing wafer load and its actions might be production critical. If so, at the second step 12 the method will select yes (y). At a third step 14, the method will instruct the substrate stage WS to execute a predefined closing wafer sequence as fast as possible, in other words taking minimal time. The third step 14 may include a command such as "execute time critical closing wafer sequence".

[0044] However, for certain cases there will be additional time available exceeding a minimum threshold. For example, there is no new substrate lot queued or due to the exposure layout of the operator of the lithographic apparatus LA there is some additional time (typically in the order of seconds) available before the start of the next lot of substrates to be exposed. The latter will bring the closing wafer from the measure side MST to the expose side EST. If so, the step 12 will indicate that the closing wafer sequence is not production critical, selecting no (n).

[0045] After having determined how much time there is available this extra time can be used to optimize the closing wafer sequence to minimize impact to exposure of the last wafer of the lot, which is done in parallel. Impact to the last wafer exposure is minimal in case it possible to delay, or shift the start of the closing wafer sequence until the exposure of the last wafer of the lot is completed. Thus, in fourth step 16, the method determines available delay time. Subsequently, the method checks whether the delay time exceeds a threshold, i.e. the time left until the exposure of the substrate currently on the expose side EST will be finished. If said delay time exceeds said time left, the method will select yes (y) at step 16 and proceed to a fifth step 18.

[0046] In step 18, the method instructs the substrate stage WS to delay the start of the closing wafer sequence until the substrate exposure of the substrate at the expose side EST is finished. When the substrate exposure at the expose station EST has finished, see sixth step 20, the method instructs the substrate stage to execute the closing wafer sequence in a time-critical manner, meaning as fast as possible.

[0047] In case the shift in time is not possible, i.e. the available delay time is below the threshold of time left for the substrate exposure, step 16 will select no (n) and refer to step 22. In seventh step 22, the method determines potential extra optimization time available.

[0048] Next, see step 24, the method checks whether the sequence itself can be optimized. Basically, step 24 optimizes the closing wafer sequence using the available delay time. Optimization herein is defined as minimizing impact of the measurement sequence on the expose sequence which is executed in parallel.

[0049] A few parameters which could be beneficial for optimization in step 24 may be fixed, for instance pre-selected or unchangeable due to boundary constraints. However, other parameters mayleave room for change. To limit impact of the measurement side MST to the expose side EST, several positioning module moves may be reduced in velocity, for instance. For instance, Wafer Unload to Load moves (step 26), or the approve wafer moves (step 28), may be reduced in their velocity, acceleration and / or jerk. The wafer load settings (step 30) of the closing wafer may be added in the optimization of step 24. Velocity and acceleration reduction will provide more time available, allowing a longer and “gentler” wafer load, which limits or reduces associated pressure waves. For instance, an aggressive setting for substrate load (step 30) may be expressed as the required suction flow to keep substrates in their correct position on the substrate tables, wherein an aggressive setting may correspond to at least a factor 2 or even a factor 4 increased suction flow. Additional parameters (step 32) may be added, for instance. Many additional settings can be added to reduce the number of substrates loaded per minute, resulting in softer and more gentle wafer load .

[0050] For the optimization of step 24, a few predefined sequence settings are conceivable, for instance. Constraints depend on, for instance, the total delay time available when a given sequence is chosen, as determined in step 22. However it would also be possible to scale down two or more settings. The latter allows a wider variation of optimization using multiple up to all available parameters. Thus, the method of the disclosure may take maximum advantage of the available delay time as determined in step 22.

[0051] Finally, see step 34, the method instructs to execute the optimized substrate sequence as determined during step 24 (instead of the original substrate sequence).

[0052] For production wafers, the principle of “scaling”, i.e. reducing velocity or other move settings on the measure side can also be done more generic for all wafers in a lot in case there is additional time available on the measure side. Figure 6A shows overlay errors without the method of the disclosure. Figure 6B shows an example of performance when measure moves are delayed until exposure is finished, so there is no measure-to-expose disturbance anymore. Any overlay errors in Fig. 6B are (fully) due to other unrelated physical effects.

[0053] The exact performance improvement which can be achieved will be determined by the available time, see steps 16 and 22. In the most optimal scenario, see step 16, the step of loading a substrate on the measure side can be delayed until the wafer exposure on the expose side EST has been finished. In that case there will be no induced disturbances anymore, and overlay error will be minimized. In theory, any disturbances of the fields as indicated in Figure 6A due to crosstalk with the measurement side will be entirely obviated, as exemplified in Figure 6B. If the measure side substrate must be loaded while another substrate is being processed on the expose side, the method of the disclosure allows to delay or slow down certain parts or movements of a measurement cycle, providing at least a certain amount of reduction of the crosstalk and related overlay errors.

[0054] Herein, the load of a closing wafer may obviate thermal or wafer clamping grid requirements. The latter means that a closing wafer does not have to obey thermal stability requirements which are typically required for substrate exposure. Also, the substrate load sequence may differ from the loadingof production wafers in the lot. For production substrates, for example, timing variations on the load robot are typically minimized. For loading the closing wafer timing variations may be ignored, so slowing down moves from Wafer unload to load is allowed for the closing wafer.

[0055] Figure 6A shows an exemplary plot of overlay errors of a production substrate, as caused by movements of the positioning module and substrate table on the measure side. Figure 6B shows an example of reduced overlay errors on the expose station EST when the method of the disclosure is used to shift, slow down or delay at least certain steps of movements of the measurement sequence, which is conducted in parallel to irradiating the production substrate. As indicated in Figure 6B, even for a regular measurement cycle the method of the disclosure enables to significantly reduce overlay errors on the expose side. As an example, the maximum overlay error can be reduced from up to 0.74 nm originally (Fig. 6A) to a maximum of about 0.56 nm when using the method of the disclosure.

[0056] An alternative solution to the problem would be to make the system design less sensitivity for crosstalk. However, that will require costly hardware redesigns and it is not sure if it will be feasible. It is also unclear whether it will be possible to apply any hardware solutions to lithographic systems already in the field. The system and method of the disclosure on the other hand can be applied to new as well as to existing lithographic systems.

[0057] Although the embodiments above have been described with reference to, in particular, lithographic immersion systems, the system and method may be equally applicable to other lithography apparatuses. For instance, also DUV dry systems and EUV systems use closing wafers and their load sequence and actions to approve the substrate performance may be improved, using the embodiments described above.

[0058] Although specific reference may be made in this text to the use of a lithographic apparatus in the manufacture of ICs, it should be understood that the lithographic apparatus described herein may have other applications. Possible other applications include the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, flat-panel displays, liquidcrystal displays (LCDs), thin-film magnetic heads, etc.

[0059] Although specific reference may be made in this text to embodiments of the invention in the context of a lithographic apparatus, embodiments of the invention may be used in other apparatus. Embodiments of the invention may form part of a mask inspection apparatus, a metrology apparatus, or any apparatus that measures or processes an object such as a wafer (or other substrate) or mask (or other patterning device). These apparatus may be generally referred to as lithographic tools. Such a lithographic tool may use vacuum conditions or ambient (non-vacuum) conditions.

[0060] Although specific reference may have been made above to the use of embodiments of the invention in the context of optical lithography, it will be appreciated that the invention, where the context allows, is not limited to optical lithography and may be used in other applications, for example imprint lithography.

[0061] While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. The descriptions above are intended to be illustrative, not limiting. Thus it will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below. For instance, features of various embodiments as described above may be combined.

Claims

CLAIMS1. Lithographic process for handling two substrates in parallel, the process comprising the steps of:- exposing a first substrate on a first substrate table;- determining an available delay time for executing a second substrate sequence for measuring of a second substrate, and- optimizing the second substrate sequence taking into account the available delay time by delaying at least a part of the second substrate sequence.

2. The process of claim 1, wherein the second substrate is a closing wafer and wherein the second substrate sequence is a closing wafer sequence.

3. The process of claim 1 or 2, comprising the steps of:- determining whether the second substrate sequence is production critical; and- if the second substrate sequence is production critical, executing the second substrate sequence without delay.

4. The process of one of the previous claims, the step of optimizing the second substrate sequence comprising shifting a start of the second substrate sequence until the step of exposing the first substrate is finished, if the available delay time exceeds a time left to finalize the step of exposing the first substrate.

5. The process of one of the previous claims, the step of optimizing the second substrate sequence comprising using the available delay time to minimize impact on the step of exposing the first substrate.

6. The process of claim 5, the step of optimizing the second substrate sequence comprising one or more of:- slowing down one or more steps included in the second substrate sequence;- delaying one or more steps included in the second substrate sequence; or- introducing delays in between one or more steps included in the second substrate sequence.

7. A lithographic apparatus for handling two substrates in parallel, the apparatus comprising: a substrate stage comprising at least a first substrate table and a second substrate table; at least one substrate handler for moving substrates onto the first or second substrate table; an exposure system for exposing a substrate positioned on the first substrate table or the second substrate table; anda measurement system for executing a second substrate sequence on the first substrate table or the second substrate table; and a control system adapted to determine an available delay time for executing the second substrate sequence, and to optimize the second substrate sequence taking into account the available delay time.

8. The apparatus of claim 7, wherein the control system is adapted to:- determine whether the second substrate sequence is production critical; and- if the second substrate sequence is production critical, to execute the second substrate sequence without delay.

9. The apparatus of claim 7 or 8, wherein the control system is adapted to shift the second substrate sequence until the step of exposing the first substrate is finished, if the available delay time exceeds a time left to expose the first substrate.

10. The apparatus of one of claims 7 to 9, wherein the control system is adapted to optimize the second substrate sequence, by one or more of:- slowing down one or more steps included in the second substrate sequence;- delaying one or more steps included in the second substrate sequence; or- introducing delays in between one or more steps included in the second substrate sequence.

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