Simulation device, method, program, material selection method, manufacturing method, and photosensitive insulating material

Abstract

A setting unit (32) sets an adhesion state of the interface between materials in a simulation model (40) representing a semiconductor package including a plurality of materials, and a simulation unit (34) uses the simulation model (40) in which the adhesion state of the interface between materials has been set to simulate whether delamination occurs between the materials when force or heat is applied to the semiconductor package.

Description

Simulation device, method, program, material selection method, manufacturing method, and photosensitive insulating material

[0001] The present disclosure relates to a simulation device, a simulation method, a simulation program, a material selection method, a semiconductor package manufacturing method, and a photosensitive insulating material.

[0002] Conventionally, simulations using simulation models have been performed to evaluate the characteristics of semiconductor packages. For example, a technology has been proposed that provides customers with simulation data that takes into account bonding materials used when mounting a semiconductor package on a mounting substrate (see Patent Document 1). In this technology, simulation data is input into a simulation device to generate a simulation model. The simulation data has a structure including first data elements for modeling the thermal conduction of the semiconductor package and second data elements for modeling the thermal conduction of the bonding materials when mounting the semiconductor package on a mounting substrate. Furthermore, when this simulation data is input into a simulation device, it is integrated with a simulation program included in the simulation device to generate a thermal analysis model based on the first data elements and the second data elements. Simulation results using this thermal analysis model are then output.

[0003] Furthermore, a simulation analysis device capable of performing simulation analysis of cracks occurring in a bonded structure has been proposed (see Patent Document 2). This device performs structural analysis of a semiconductor package in which a first member surface-bonded to the top surface of a bonded structure and a second member surface-bonded to the bottom surface of the bonded structure are stacked in a direction perpendicular to the bonding surface and encapsulated in a sealant. The device also reads physical property information, dimensional information, and shape information of the first member, the second member, and the bonded structure, and calculates the maximum principal stress acting on the bonded structure when heated to a predetermined temperature. The device also calculates the amount of displacement occurring in the direction perpendicular to the bonding surface of the bonded structure when heated to the predetermined temperature, and evaluates that no cracks will occur in the bonded structure if the maximum principal stress is equal to or less than a first threshold and the amount of displacement is equal to or less than a second threshold.

[0004] JP 2022-033586 A JP 2014-174927 A

[0005] Semiconductor packages contain protective materials, such as insulating films and encapsulants, to protect surrounding materials. Mismatches in the thermal expansion coefficients of these protective materials and the materials they protect can cause the protective materials to peel off from the materials they protect. Because this peeling can cause semiconductor package failures, it is necessary to reduce the stress on the protective materials and prevent peeling.

[0006] The present disclosure has been made in consideration of the above points, and aims to accurately simulate peeling between materials that constitute a semiconductor package.

[0007] The simulation device according to the first aspect includes a setting unit that sets the adhesive state at the interface between each material for a simulation model representing a semiconductor package including a plurality of materials, and a simulation unit that uses the simulation model in which the adhesive state at the interface between each material has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

[0008] The simulation method according to the second aspect is a simulation method executed by a simulation device including a setting unit and a simulation unit, in which the setting unit sets the adhesive state at the interface between each material for a simulation model representing a semiconductor package including multiple materials, and the simulation unit uses the simulation model in which the adhesive state at the interface between each material has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

[0009] The simulation program according to the third aspect is a program for causing a computer to function as a setting unit that sets the adhesive state at the interface between each material for a simulation model representing a semiconductor package including multiple materials, and a simulation unit that uses the simulation model in which the adhesive state at the interface between each material has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

[0010] The material selection method according to the fourth aspect is a method for selecting a material to be used for a semiconductor package based on the results of a simulation performed by the above-mentioned simulation device.

[0011] A method for manufacturing a semiconductor package according to a fifth aspect is a method for manufacturing a semiconductor package using a material selected by the above-described material selection method.

[0012] The photosensitive insulating material according to the sixth aspect is a photosensitive insulating material in which the magnitude of the stress, which is a result of simulation by the above-mentioned simulation device, is 0 to 100 MPa.

[0013] The simulation device, method, and program according to the present disclosure can accurately simulate peeling between materials that make up a semiconductor package.

[0014] 1 is a block diagram showing a hardware configuration of a simulation device according to an embodiment of the present invention; FIG. 2 is a functional block diagram of a simulation device according to an embodiment of the present invention; FIG. 3 is a side view and a partial enlarged view showing a schematic configuration of a semiconductor package; FIG. 4 is a schematic image of a simulation model; FIG. 5 is a diagram for explaining setting of an adhesive state in a simulation model; FIG. 6 is a diagram for explaining setting of an adhesive state in a simulation model; FIG. 7 is a diagram for explaining setting of an adhesive state in a simulation model; FIG. 8 is a diagram showing an example of a simulation result; FIG. 9 is a flowchart showing the flow of a simulation process; FIG. 10 is a functional block diagram of a simulation device according to a modified example of the present invention;

[0015] An example of this embodiment will be described below with reference to the drawings.

[0016] <Simulation Apparatus> Fig. 1 is a block diagram showing the hardware configuration of a simulation apparatus 10 according to this embodiment. As shown in Fig. 1, the simulation apparatus 10 has a CPU (Central Processing Unit) 12, a memory 14, a storage device 16, an input device 18, an output device 20, a storage medium reader 22, and a communication I / F (Interface) 24. Each component is connected to each other via a bus 26 so as to be able to communicate with each other.

[0017] The storage device 16 stores a simulation program for executing the simulation process described below. The CPU 12 is a central processing unit that executes various programs and controls each component. That is, the CPU 12 reads the program from the storage device 16 and executes the program using the memory 14 as a work area. The CPU 12 controls each component and performs various arithmetic processes in accordance with the program stored in the storage device 16.

[0018] The memory 14 is configured with RAM (Random Access Memory) and serves as a working area for temporarily storing programs and data. The storage device 16 is configured with ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), etc., and stores various programs including the operating system and various data.

[0019] The input device 18 is a device for performing various inputs, such as a keyboard, a mouse, etc. The output device 20 is a device for outputting various information, such as a display, a printer, etc. A touch panel display may be used as the output device 20 to function as the input device 18.

[0020] The storage medium reader 22 reads data stored in various storage media such as CD (Compact Disc)-ROM, DVD (Digital Versatile Disc)-ROM, Blu-ray Disc, USB (Universal Serial Bus) memory, etc., and writes data to the storage media. The communication I / F 24 is an interface for communicating with other devices, and uses standards such as Ethernet (registered trademark), FDDI, or Wi-Fi (registered trademark).

[0021] Next, the functional configuration of the simulation device 10 according to this embodiment will be described.

[0022] Fig. 2 is a block diagram showing an example of the functional configuration of the simulation device 10. As shown in Fig. 2, the simulation device 10 includes, as its functional configuration, a setting unit 32 and a simulation unit 34. A simulation model 40 is also stored in a predetermined storage area of ​​the simulation device 10. Each functional configuration is realized when the CPU 12 reads out a simulation program stored in the storage device 16, loads it into the memory 14, and executes it.

[0023] The simulation model 40 represents a semiconductor package including a plurality of materials, and is a model for simulating phenomena occurring in the semiconductor package, such as stress of each material.

[0024] Here, the schematic configuration of a semiconductor package will be described. The left diagram of FIG. 3 is a side view showing the schematic configuration of a semiconductor package 50, and the right diagram of FIG. 3 is an enlarged partial view of the semiconductor package 50. The semiconductor package 50, which encloses a semiconductor chip 52 made of silicon (Si) or the like on which a circuit is formed, includes a package substrate 54, solder balls 56, and the like, and is mounted on a mounting substrate 90. The portion of the semiconductor package 50 shown in an enlarged view in the right diagram of FIG. 3 (the portion enclosed by the dashed line in the left diagram of FIG. 3) includes an interlayer insulating layer 58, a printed circuit board 60 including a circuit pattern made of copper foil (Cu) or the like, solder 62, and the semiconductor chip 52. This portion also includes a protective material 64 that covers the joint between the printed circuit board 60 and the solder 62, and an encapsulant (UF) 66 that is injected between the protective material 64 and the semiconductor chip 52.

[0025] The interlayer insulating layer 58 is, for example, a build-up (BU) film, etc. The protective material 64 is, for example, a solder resist (SR), a photosensitive insulating material, a build-up film, etc. The sealing material 66 is, for example, a liquid sealing material, a non-conductive adhesive film, etc.

[0026] In this embodiment, a case will be described in which the protective material 64 is a solder resist. Hereinafter, the protective material 64 will also be referred to as the solder resist 64.

[0027] Solder resist 64, in film or liquid form, is attached or applied to the surface of a substrate or other object to be protected to protect it. As shown in the right diagram of Figure 3, when solder resist 64 is attached to protect the joint between a printed circuit board 60 and solder 62, if the solder resist 64 layer is removed alone, the area corresponding to the solder 62 becomes an opening. There is a problem in that the solder resist 64 peels off near this opening (the area indicated by the thick line in the right diagram of Figure 3). Peeling of materials in a semiconductor package 50 occurs when the stress on the material increases due to factors such as a mismatch in the thermal expansion coefficients of the materials being joined. Therefore, it is necessary to analyze the range of stress that will not cause peeling by simulating the stress on the material through structural analysis of the semiconductor package.

[0028] The simulation model 40 is a model that represents the openings in the solder resist 64 in the configuration of the semiconductor package when analyzing the above-mentioned stress. Fig. 4 is a schematic image of the simulation model 40. In Fig. 4, each part of the simulation model 40 is represented by a different color (by using different shades) depending on the material that constitutes the semiconductor package 50.

[0029] As shown in Fig. 4, the simulation model 40 is represented by a three-dimensional mesh structure. In Fig. 4, horizontal planes are divided radially, and vertical planes are divided into grids to form meshes. In the example of Fig. 4, the size of each mesh varies depending on the part of the semiconductor package 50. For example, the mesh may be set finer for parts where particularly detailed analysis is desired, such as interfaces between materials, and larger for other parts.

[0030] The mesh configuration of the simulation model 40 is not limited to the example shown in Fig. 4. For example, it may be a cube-shaped mesh, or may be a mesh with different shapes depending on the part of the semiconductor package 50. Furthermore, the size of each mesh may be uniform.

[0031] Generally, a simulation model of the semiconductor package 50 is created in which all interfaces of each material are bonded. In the simulation model 40 of this embodiment, the bond state of the interfaces between each material can be set.

[0032] Specifically, as shown in FIG. 5 , the corners of each mesh are nodes. In this case, "bonded" is represented by setting adjacent meshes to share nodes, and "unbonded" is represented by setting them not to share nodes. The example in FIG. 5 is a diagram showing a portion of the mesh where material A and material B are adjacent. In FIG. 5 , the mesh representing material A is mesh 42A, and the mesh representing material B is mesh 42B. The black circles represent nodes 44 of each mesh. If meshes 42A and 42B share a node (a node indicated by a dashed line in FIG. 5 ) at the contact point between meshes 42A and 42B, this indicates that material A and material B are bonded. On the other hand, if meshes 42A and 42B do not share the node at that point but retain it as their own node, this indicates that material A and material B are unbonded (contacting but not bonded).

[0033] For ease of explanation, the mesh is shown in two dimensions in Fig. 5. The same applies to Fig. 7 below.

[0034] The adhesive state of the interface between materials in the simulation model 40 is not limited to either adhesive or non-adhesive, and the degree of adhesiveness may be configurable. For example, non-adhesive may be set to 0, adhesive may be set to 1, and the degree of adhesiveness may be a value between 0 and 1. As a method for setting the degree of adhesiveness in the simulation model 40, for example, as shown in FIG. 6 , shared nodes 44 and non-shared nodes 44 are set among consecutive nodes 44 at adjacent locations between a mesh 42A of material A and a mesh 42B of material B. The degree of adhesiveness between material A and material B can be set by changing the ratio of shared nodes 44 to non-shared nodes 44 at adjacent locations between meshes 42A and 42B.

[0035] The setting unit 32 receives setting values ​​including the shape, physical properties, and adhesive instructions of each material constituting the semiconductor package 50. The shape is, for example, information such as the vertical and horizontal dimensions and thickness of each material. The physical properties are, for example, information necessary for stress simulation, such as the thermal expansion coefficient and Young's modulus. For example, if solder resist is used as the protective material 64, the physical properties included in the setting values ​​of the protective material 64 are information on the physical properties of the solder resist. The adhesive instructions are information that indicates which portions between which materials should be bonded or not bonded. The adhesive instructions may also be instructions indicating the degree of adhesion at the interface between the materials.

[0036] The setting unit 32 sets the received setting value in the simulation model 40. Specifically, the setting unit 32 adjusts the spacing of the mesh structure, etc., so that the shape of the portion corresponding to each material in the simulation model 40 becomes the shape of each material included in the setting value. In addition, the setting unit 32 causes each mesh corresponding to each material in the simulation model 40 to hold information on physical properties as parameters.

[0037] Furthermore, the setting unit 32 sets the adhesive state of the interface between each material for the simulation model 40. For example, assume that the setting values ​​include an adhesive instruction indicating that the interface between the solder resist 64 and the solder 62 is not adhesive and that the interfaces between other materials are adhesive. In this case, as shown in FIG. 7 , the setting unit 32 sets the meshes constituting the simulation model 40 so that adjacent meshes corresponding to the interface between the solder resist 64 and the solder 62 (thick line portion in FIG. 7 ) do not share nodes. The setting unit 32 also sets the meshes corresponding to the interfaces between the other materials so that they share nodes. This allows the simulation model 40 to be constructed so that the interface between the solder resist 64 and the solder 62 is not adhesive.

[0038] Furthermore, for an interface between materials that have been set to be unbonded, the setting unit 32 may set whether the materials will penetrate each other or will push against each other when a pushing force acts on the interface.

[0039] The simulation unit 34 uses the simulation model 40 in which the shape, physical properties, and adhesive state at the interface between the materials indicated by the setting values ​​are set by the setting unit 32, to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package 50. For example, the simulation unit 34 calculates, for each mesh, the magnitude and direction of stress in each material caused by the action of a pressing force that occurs between the materials due to thermal expansion or the like.

[0040] Furthermore, the simulation unit 34 simulates whether or not peeling will occur at the interface between the materials based on the calculated magnitude and direction of the stress of each material. For example, the simulation unit 34 calculates the magnitude and direction of the stress at a predetermined position (e.g., an opening) at the interface between the materials from the magnitude and direction of the stress for each mesh, and simulates whether or not peeling will occur. Note that existing technologies can be applied to the simulation of stress and peeling, so detailed explanations will be omitted.

[0041] The simulation unit 34 outputs the stress simulation results and a failure mode indicating the peeling location. FIG. 8 shows an example of the stress simulation results and a failure mode. The "Unbonded Case" in FIG. 8 is an example in which the interface between the solder resist 64 and the solder 62 is set to "unbonded" as shown in FIG. 7 using the method of this embodiment (hereinafter referred to as "this method"). The "Bonded Case" in FIG. 8 is a comparative example of the method in which all interfaces between the materials are set to "bonded" and other settings are the same as in the method. In FIG. 8, the stress simulation results for a portion including the opening of the solder resist 64 are represented by different colors (densities) to indicate the magnitude of stress calculated for each mesh, and also indicate the direction of stress occurring at a predetermined position of the opening of the solder resist 64.

[0042] The simulation using this method predicted a failure mode in which peeling occurs on the top surface of the printed circuit board 60 at the interface between the printed circuit board 60 and the solder resist 64, as shown by the bold line in A of Figure 8. On the other hand, the simulation using the comparative method predicted a failure mode in which peeling occurs on the side surface of the printed circuit board, as shown by the bold line in B of Figure 8, as shown by the bold line in B of Figure 8. The failure mode identified by experiments on an actual semiconductor package 50 was consistent with the failure mode obtained by this method. Therefore, compared to the comparative method, this method produced simulation results that were closer to reality.

[0043] Next, the operation of the simulation device 10 according to this embodiment will be described.

[0044] Fig. 9 is a flowchart showing the flow of a simulation process executed by the CPU 12 of the simulation device 10. The CPU 12 reads a simulation program from the storage device 16, loads it into the memory 14, and executes it, causing the CPU 12 to function as each functional component of the simulation device 10 and execute the simulation process shown in Fig. 9. Note that the simulation process is an example of a simulation method of the present disclosure.

[0045] In step S10, the setting unit 32 receives setting values ​​including the shape, physical properties, and adhesion instructions of each material constituting the semiconductor package 50. Next, in step S12, the setting unit 32 adjusts the spacing of the mesh structure, etc., in the simulation model 40 so that the shape of the portion corresponding to each material matches the shape of each material included in the setting values. Furthermore, the setting unit 32 causes each mesh corresponding to each material in the simulation model 40 to hold information on physical properties as a parameter. Next, in step S14, the setting unit 32 sets the adhesion state (bonded or unbonded) of the interface between each material for the simulation model 40 based on the adhesion instructions.

[0046] Next, in step S16, the simulation model 40, in which the shape, physical properties, and adhesive state of the interfaces between the materials are set, is used to simulate the magnitude and direction of stress for each mesh when force or heat is applied to the semiconductor package 50. Next, in step S18, the simulation unit 34 simulates the presence or absence of peeling at the interfaces between the materials, i.e., the failure mode indicating the peeling location, based on the magnitude and direction of the stress of each simulated material.

[0047] Next, in step S20, the simulation unit 34 outputs the simulation results of the stress and failure mode, and the simulation process ends.

[0048] As described above, the simulation device according to this embodiment sets the adhesive state of the interfaces between the materials in a simulation model representing a semiconductor package including multiple materials. The simulation device then uses the simulation model in which the adhesive state of the interfaces between the materials is set to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package. This allows for accurate simulation of peeling between the materials that make up the semiconductor package.

[0049] Furthermore, the simulation process executed by the CPU in the above embodiment by loading software (programs) may be executed by various processors other than the CPU. Examples of such processors include dedicated electrical circuits, such as programmable logic devices (PLDs) (such as field-programmable gate arrays (FPGAs)) whose circuit configuration can be changed after manufacture, and application-specific integrated circuits (ASICs) that are processors with circuit configurations specifically designed to execute specific processes. The simulation process may be executed by one of these various processors, or by a combination of two or more processors of the same or different types (e.g., multiple FPGAs, or a combination of a CPU and an FPGA). The hardware structure of these various processors is, more specifically, an electrical circuit that combines circuit elements such as semiconductor devices.

[0050] In the above embodiment, the simulation program is pre-stored (installed) in a storage device, but this is not limiting. The program may be provided in a form stored in a storage medium such as a CD-ROM, DVD-ROM, or USB memory. The program may also be downloaded from an external device via a network.

[0051] <Modification of Simulation Apparatus> A functional block diagram of a simulation apparatus 10A according to a modification is shown in Fig. 10. As shown in Fig. 10, the simulation apparatus 10A includes an estimation unit 36 ​​in addition to the functional units of the simulation apparatus 10 of the above embodiment.

[0052] The setting unit 32 receives setting values ​​for a plurality of patterns each having a different adhesion instruction, and sets the setting values ​​for each pattern in the simulation model 40. That is, a plurality of patterns of the simulation model 40 each having a different adhesion state are constructed.

[0053] The estimation unit 36 ​​receives information on failure modes previously identified through experiments for the actual semiconductor package 50. The estimation unit 36 ​​then compares the failure modes simulated using the simulation model 40 for each pattern with the actual failure modes. The estimation unit 36 ​​estimates the adhesive state indicated by the pattern for the simulation result that most closely matches the actual failure mode as the adhesive state of the interfaces between the materials of the actual semiconductor package, and outputs the estimation result.

[0054] The simulation device according to this modified example makes it possible to estimate the adhesive state at the interface between materials of an actual semiconductor package in which the adhesive state at the interface between the materials is unknown.

[0055] <Material Selection Method> The material selection method according to this embodiment is a method for selecting a material to be used for a semiconductor package based on the results of simulation by the simulation device 10. Specifically, in this material selection method, based on the results of simulation by the simulation device 10, materials are selected whose stress values ​​fall within a range in which no deviation occurs between materials.

[0056] For example, when selecting the protective material 64 to be used in the semiconductor package 50, if a simulation confirms that peeling does not occur when the stress is 0 to 100 MPa, an insulating material with a stress in the range of 0 to 100 MPa is selected. Examples of such insulating materials include solder resist, photosensitive insulating materials, and build-up films.

[0057] <Method for Manufacturing Semiconductor Package> The method for manufacturing a semiconductor package according to this embodiment is a method for manufacturing a semiconductor package 50 using materials selected by the above-described material selection method. Specifically, the semiconductor package is manufactured by sequentially stacking materials selected based on the simulation results of the simulation device 10 according to the setting values ​​set during the simulation. Since existing technologies can be applied to more specific methods for manufacturing a semiconductor package, detailed explanations will be omitted.

[0058] <Additional Notes> The additional notes are disclosed below.

[0059] (Addendum 1) A simulation device including: a setting unit that sets an adhesive state at an interface between each material for a simulation model representing a semiconductor package including a plurality of materials; and a simulation unit that uses the simulation model in which the adhesive state at the interface between each material has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

[0060] (Supplementary Item 2) The simulation device according to Supplementary Item 1, wherein the simulation model includes, as the material, a solder and an insulating material that protects the solder.

[0061] (Supplementary Item 3) The simulation device according to Supplementary Item 2, wherein the insulating material is a photosensitive insulating material.

[0062] (Supplementary Item 4) The simulation device according to Supplementary Item 3, wherein the photosensitive insulating material is a solder resist.

[0063] (Supplementary Item 5) The simulation device according to any one of Supplementary Items 1 to 4, wherein the setting unit sets the degree of adhesion at the interface between the materials as the adhesion state.

[0064] (Supplementary Item 6) The simulation device according to Supplementary Item 5, wherein the setting unit sets, as the degree of adhesion, whether the interface between the materials is adhered or not adhered.

[0065] (Supplementary Item 7) The simulation device according to any one of Supplementary Items 1 to 6, wherein the simulation unit calculates a magnitude and a direction of stress in the material, and simulates whether or not peeling occurs at an interface between the materials based on the calculated magnitude and direction of the stress.

[0066] (Supplementary Item 8) The simulation device according to any one of Supplementary Items 1 to 7, wherein the setting unit sets a plurality of patterns as the adhesive state of the interface between the materials, and includes an estimation unit that compares information indicating which materials in the actual semiconductor package have peeled at which position with simulation results for each of the plurality of patterns, and estimates the adhesive state corresponding to the pattern that most closely matches the state of peeling in the actual semiconductor package as the adhesive state of the interface between the materials in the actual semiconductor package.

[0067] (Supplementary Item 9) A simulation method executed by a simulation device including a setting unit and a simulation unit, wherein the setting unit sets an adhesive state at an interface between each material for a simulation model representing a semiconductor package including a plurality of materials, and the simulation unit uses the simulation model in which the adhesive state at the interface between each material has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

[0068] (Addendum 10) A simulation program for causing a computer to function as: a setting unit that sets the adhesive state at the interface between each material for a simulation model representing a semiconductor package including multiple materials; and a simulation unit that uses the simulation model in which the adhesive state at the interface between each material has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

[0069] (Supplementary Item 11) A material selection method for selecting a material to be used in a semiconductor package based on a simulation result obtained by the simulation device according to any one of Supplementary Items 1 to 8.

[0070] (Supplementary Item 12) A material selection method for selecting materials whose stress values ​​fall within a range in which no deviation occurs between materials, based on a simulation result obtained by the simulation device according to Supplementary Item 7.

[0071] (Supplementary Item 13) A manufacturing method for manufacturing a semiconductor package using a material selected by the material selection method according to Supplementary Item 11 or Supplementary Item 12.

[0072] (Supplementary Item 14) A photosensitive insulating material in which the magnitude of the stress, which is a simulation result obtained by the simulation device according to Supplementary Item 7, is 0 to 100 MPa.

[0073] REFERENCE SIGNS LIST 10, 10A Simulation device 12 CPU 14 Memory 16 Storage device 18 Input device 20 Output device 22 Storage medium reading device 24 Communication I / F 26 Bus 32 Setting unit 34 Simulation unit 36 ​​Estimation unit 40 Simulation model 42A, 42B Mesh 44 Node 50 Semiconductor package 52 Semiconductor chip 54 Package substrate 56 Solder ball 58 Interlayer insulating layer 60 Printed circuit board 64 Protective material (solder resist) 66 Sealing material 90 Mounting substrate

Claims

1. A simulation device including: a setting unit that sets the adhesive state of the interface between each material for a simulation model representing a semiconductor package including a plurality of materials; and a simulation unit that uses the simulation model in which the adhesive state of the interface between each of the materials has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

2. The simulation device according to claim 1, wherein the simulation model includes, as the materials, solder and an insulating material for protecting the solder.

3. The simulation device according to claim 2, wherein the insulating material is a photosensitive insulating material.

4. The simulation device according to claim 3, wherein the photosensitive insulating material is a solder resist.

5. A simulation device according to any one of claims 1 to 4, wherein the setting unit sets the degree of adhesion at the interface between the materials as the adhesion state.

6. The simulation device according to claim 5, wherein said setting unit sets, as said degree of adhesion, whether the interface between said materials is bonded or not bonded.

7. A simulation device according to any one of claims 1 to 4, wherein the simulation unit calculates the magnitude and direction of stress in the material, and simulates the presence or absence of peeling at the interface between the materials based on the calculated magnitude and direction of the stress.

8. A simulation device according to any one of claims 1 to 4, wherein the setting unit sets a plurality of patterns as the adhesive state of the interface between each of the materials, and includes an estimation unit that compares information indicating at which position between which materials in the actual semiconductor package peeling has occurred with simulation results for each of the plurality of patterns, and estimates the adhesive state corresponding to the pattern that most closely matches the peeling state of the actual semiconductor package as the adhesive state of the interface between each of the materials in the actual semiconductor package.

9. A simulation method executed by a simulation device including a setting unit and a simulation unit, wherein the setting unit sets an interfacial adhesion state between each material for a simulation model representing a semiconductor package including a plurality of materials, and the simulation unit uses the simulation model in which the interfacial adhesion state between each of the materials has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

10. A simulation program for causing a computer to function as: a setting unit that sets the adhesive state of the interface between each material for a simulation model representing a semiconductor package including a plurality of materials; and a simulation unit that uses the simulation model in which the adhesive state of the interface between each of the materials has been set by the setting unit to simulate whether or not peeling occurs between the materials when force or heat is applied to the semiconductor package.

11. A material selection method for selecting a material to be used in a semiconductor package based on the results of a simulation performed by the simulation device according to claim 1.

12. A material selection method for selecting materials whose stress values ​​fall within a range in which no deviation occurs between materials, based on the results of a simulation performed by the simulation device described in claim 7.

13. A method for manufacturing a semiconductor package using a material selected by the material selection method according to claim 11 or 12.

14. A photosensitive insulating material in which the magnitude of the stress, which is a result of simulation by the simulation device according to claim 7, is 0 to 100 MPa.

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