Video signal processing device, video signal processing method, and program

Abstract

A processing device (10A) comprises: a reception interface (11) that receives a video signal indicating a moving image; a video processing circuit (13) that generates a first signal by performing video processing of one pattern on the video signal; a capture circuit (17) that generates a second signal by capturing the video signal received by the reception interface (11); a synthesis circuit (14A) that outputs a synthesized signal obtained by synthesizing the first signal and the second signal; and a processor that (a) controls the synthesis circuit (14A) such that the first signal is outputted as the synthesized signal in a first period, (b) controls the video processing circuit (13) such that the pattern of the video processing performed by the video processing unit (13) is changed in a second period, and (c) controls the capture circuit (17) such that the second signal is generated in the period of the change and controls the synthesis circuit (14A) such that the second signal is outputted as the synthesized signal.

Description

Video signal processing device, video signal processing method, and program

[0001] The present disclosure relates to a video signal processing device, a video signal processing method, and a program.

[0002] There is a video signal processing device that performs video processing on a video signal including a moving image and displays the result as a video. When the video signal processing device switches the video signal, there is a control technique that reads out a video signal that was written into a memory immediately before the switching (see, for example, Patent Document 1).

[0003] Japanese Patent Application Publication No. 3-242095

[0004] When a video signal processing device switches the video processing to be performed on a video signal, the video signal may be muted, which can cause a problem that the video signal may be muted at a timing contrary to the user's intention.

[0005] The present disclosure provides a video signal processing device, a video signal processing method, and a program that suppress muting of a video signal during a video processing switching period.

[0006] The video signal processing device of the present disclosure is a video signal processing device comprising: a receiving interface that receives a video signal indicating a moving image; a video processing circuit that generates a first signal by applying one of a plurality of patterns of video processing that the video processing circuit can apply to the video signal received by the receiving interface; a capture circuit that generates a second signal by capturing the video signal received by the receiving interface; a synthesis circuit that outputs a synthesized signal that combines the first signal and the second signal; and a processor that (a) controls the synthesis circuit to output the first signal as the synthesized signal during a first period, (b) controls the video processing circuit to change the pattern of the video processing applied by the video processing circuit during a second period that is not included in the first period, and (c) controls the capture circuit to generate the second signal during the change period and controls the synthesis circuit to output the second signal as the synthesized signal.

[0007] The video signal processing device according to the present disclosure can suppress muting of the video signal during the video processing switching period.

[0008] FIG. 1 is an explanatory diagram showing the configuration of a system in an embodiment, and the configuration of a display device having a processing device. FIG. 2 is an explanatory diagram showing a pattern table showing a plurality of video processing patterns in an embodiment. FIG. 3 is an explanatory diagram showing a time table showing the time required to change the video processing settings in an embodiment. FIG. 4 is a first explanatory diagram showing a compositing process by an adder circuit in an embodiment. FIG. 5 is a second explanatory diagram showing a compositing process by an adder circuit in an embodiment. FIG. 6 is a third explanatory diagram showing a compositing process by an adder circuit in an embodiment. FIG. 7 is a flow diagram showing the processing of a processor when changing video processing in an embodiment. FIG. 8 is an explanatory diagram showing an example of the processing of a processing device in an embodiment. FIG. 9 is a flow diagram showing the processing of a processor when changing video processing in a second modification of an embodiment. FIG. 10 is an explanatory diagram showing an example of the processing of a processing device in a second modification of an embodiment.

[0009] (Findings that Form the Basis of the Present Disclosure) The present inventors have found that the following problems arise with the video signal processing device described in the "Background Art" section.

[0010] There is a technology that changes the video processing that a video signal processing device applies to a video signal based on a signal received from a transmitting device. For example, in the HDMI (registered trademark) (High-Definition Multimedia Interface) 2.1 standard, the ALLM (Auto Low Latency Mode) function enables the video processing that a video signal processing device applies to a video signal to be changed based on the signal received from the transmitting device.

[0011] When switching the video processing applied to a video signal, noise may be included in the video signal output by the video signal processing device. The video signal processing device may mute the video signal during a video processing switching period to suppress display of the video signal including noise. When the video signal processing device changes the video processing in response to receiving a signal instructing a change in video processing from a transmitting device, the timing of the change in video processing may not be based on a user instruction. As a result, the video signal may be muted at a timing contrary to the user's intention, which may cause discomfort to the user.

[0012] If the video signal is muted at a timing contrary to the user's intention, this may be perceived as a deterioration in the quality of the video signal provided to the user or as a malfunction of the video signal processing device.

[0013] The present disclosure provides a video signal processing device, a video signal processing method, and a program that suppress muting of a video signal during a video processing switching period.

[0014] Below, examples of inventions that can be obtained from the disclosure of this specification will be given, and the effects and the like that can be obtained from these inventions will be explained.

[0015] (1) A video signal processing device comprising: a receiving interface that receives a video signal representing a moving image; a video processing circuit that generates a first signal by applying one of a plurality of video processing patterns that the video processing circuit can apply to the video signal received by the receiving interface; a capture circuit that generates a second signal by capturing the video signal received by the receiving interface; a synthesis circuit that outputs a synthesized signal that combines the first signal and the second signal; and a processor that (a) controls the synthesis circuit to output the first signal as the synthesized signal during a first period, (b) controls the video processing circuit to change the pattern of the video processing applied by the video processing circuit during a second period that is not included in the first period, and (c) controls the capture circuit to generate the second signal during the change period and controls the synthesis circuit to output the second signal as the synthesized signal.

[0016] According to the above aspect, the video signal processing device outputs the signal captured by the capture circuit during the period when the video processing circuit switches video processing, thereby maintaining the output of the video signal even during the period when the video processing circuit switches video processing. Since the signal output by the video processing circuit is not output during the period when the video processing circuit switches video processing, it is possible to avoid outputting a video signal containing noise. Therefore, the video signal processing device can suppress muting of the video signal during the period when the video processing is switched.

[0017] (2) The video signal processing device according to (1), further comprising a memory, wherein the processor controls the capture circuit to store the second signal generated by the capture circuit in the memory, and, if a first time corresponding to a first delay caused in the video signal by video processing of a first pattern among the plurality of patterns before the change and a second time corresponding to a second delay caused in the video signal by video processing of a second pattern among the plurality of patterns after the change are different, controls the synthesis circuit to output, within the period of the change, the second signal whose elapsed time since storage in the memory is a time length between the first time and the second time.

[0018] According to the above aspect, when the delay of the video processing before the change (first delay) is different from the delay of the video processing after the change (second delay), the video signal processing device can output a composite signal so as to reduce the difference in delay between the second signal and the first signal before and after the change. Thus, the video signal processing device can appropriately change the delay associated with switching of the video processing while suppressing muting of the video signal during the video processing switching period. Furthermore, the video signal processing device can also achieve the effect of reducing the discomfort that the user may experience if the video signal is muted at a timing contrary to the user's intention.

[0019] (3) The video signal processing device described in (2), wherein the processor controls the synthesis circuit so that the elapsed time since the second signal output by the synthesis circuit during the change period was stored in the memory changes from the first time to the second time.

[0020] According to the above aspect, when the delay of the video processing before the change (first delay) is different from the delay of the video processing after the change (second delay), the video signal processing device can output the composite signal while gradually changing the delay time before and after the change by changing the elapsed time of the second signal read during the change period from the first time to the second time. Thus, the video signal processing device can appropriately change the delay associated with the change of the video processing while suppressing muting of the video signal during the change period of the video processing.

[0021] (4) A video signal processing device described in any of (1) to (3), wherein the receiving interface receives an instruction to change the video processing that the video processing circuit applies to the video signal to video processing with lower latency, and the processor, when the receiving interface receives the instruction, controls in (b) to change the video processing that the video processing circuit applies to the video signal to video processing with lower latency.

[0022] According to the above aspect, the video signal processing device can suppress muting of the video signal during the video processing switching period when the video processing circuit changes the video processing applied to the video signal to video processing with lower delay.

[0023] (5) A video signal processing device described in any of (1) to (4), wherein the processor controls the synthesis circuit to generate and output the synthetic signal by mixing pixel values ​​contained in the first signal and pixel values ​​contained in the second signal immediately before or after the change period.

[0024] According to the above aspect, when switching the signal to be output as a composite signal from one of the first signal and the second signal to the other, the video signal processing device uses a pixel value obtained by mixing the pixel values ​​of the respective signals, thereby suppressing a sudden change in image quality. Thus, the video signal processing device can suppress a sudden change in image quality that accompanies switching of the video processing while suppressing muting of the video signal during the switching period of the video processing.

[0025] (6) The video signal processing device according to any one of (1) to (5), wherein the synthesis circuit includes an OSD (On-Screen Display) synthesis circuit that synthesizes the second signal as an OSD signal with the first signal.

[0026] According to the above aspect, the video signal processing device uses an OSD synthesis circuit to synthesize the first signal and the second signal, which makes it easier to synthesize the first signal and the second signal, and therefore the video signal processing device can more easily suppress muting of the video signal during the video processing switching period.

[0027] (7) A video signal processing device described in any of (1) to (6), wherein the synthesis circuit further includes a mute circuit that switches whether or not to mute the first signal generated by the video processing circuit, and the processor controls the mute circuit to mute the first signal during the change period.

[0028] According to the above aspect, the video signal processing device mutes the first signal during the change period, thereby preventing the first signal, which may contain noise, from being output as a composite signal. During the change period, the second signal is output as a composite signal in principle, and the first signal is not output as a composite signal. However, if the combining circuit operates contrary to the above principle for some reason, the first signal, which may contain noise, may be output as a composite signal. By including the mute circuit in the combining circuit, it is possible to prevent the first signal, which may contain noise, from being output as a composite signal, as described above. Therefore, the video signal processing device can suppress the muting of the video signal during the video processing switching period, while suppressing the output of the video signal, which may contain noise.

[0029] (8) A video signal processing method executed by a video signal processing device, the video signal processing device comprising: a receiving interface that receives a video signal indicating a moving image; a video processing circuit that generates a first signal by applying one of a plurality of patterns of video processing that the video processing circuit can apply to the video signal received by the receiving interface; a capture circuit that generates a second signal by capturing the video signal received by the receiving interface; a synthesis circuit that outputs a synthesized signal that combines the first signal and the second signal; and a processor, the video signal processing method comprising the steps of: (a) controlling the synthesis circuit to output the first signal as the synthesized signal during a first period; (b) controlling the video processing circuit to change the pattern of the video processing applied by the video processing circuit during a second period that is not included in the first period; and (c) controlling the capture circuit to generate the second signal and the synthesis circuit to output the second signal as the synthesized signal during the change period.

[0030] According to the above aspect, the same effects as those of the above video signal processing device are achieved.

[0031] (9) A program for causing a computer to execute the video signal processing method according to (8).

[0032] According to the above aspect, the same effects as those of the above video signal processing device are achieved.

[0033] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, more detailed explanation than necessary may be omitted. For example, detailed explanation of well-known matters or redundant explanation of substantially the same configuration may be omitted. This is to avoid unnecessary redundancy in the following explanation and to facilitate understanding by those skilled in the art.

[0034] The inventor(s) provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present disclosure, and do not intend for them to limit the subject matter described in the claims.

[0035] (Embodiment) In this embodiment, a video signal processing device (also referred to as a processing device) that suppresses muting of a video signal during a switching period of video processing will be described.

[0036] [1 Configuration of System 1] FIG. 1 is an explanatory diagram showing the configuration of a system 1 according to the present embodiment and the configuration of a display device 10 having a processing device 10A.

[0037] 1, the system 1 includes a transmitting device 5 and a display device 10. It can also be said that the system 1 includes the transmitting device 5 and a processing device 10A.

[0038] The transmitting device 5 is a device that transmits a video signal including a moving image to the display device 10. The communication standard of the video signal transmitted by the transmitting device 5 is, for example, the HDMI (registered trademark) 2.1 standard. The transmitting device 5 may transmit an audio signal to the display device 10 together with the video signal.

[0039] Furthermore, the transmitting device 5 can transmit to the display device 10 an instruction (also referred to as a change instruction) for changing the video processing that the display device 10 (more specifically, the processing device 10A) applies to the video signal. The transmitting device 5 can transmit the change instruction as a communication packet (also referred to as a change instruction packet).

[0040] The change command may include, for example, a command to change the video processing that the display device 10 applies to the video signal to video processing with lower latency, or a command to change to video processing with higher latency. Here, a case will be described as an example in which the change command is a command to change the video processing that the display device 10 applies to the video signal to video processing with lower latency.

[0041] In other words, "lower latency video processing" refers to video processing that is performed with a delay lower than the standard latency and in a processing time shorter than the standard latency. Similarly, "higher latency video processing" refers to video processing that is performed with a delay higher than the standard latency and in a processing time longer than the standard latency.

[0042] The command to change the video processing applied to the video signal by the display device 10 to video processing with lower latency is realized, for example, by the ALLM function of the HDMI (registered trademark) 2.1 standard. The timing at which the transmitter 5 transmits the change command is, for example, the timing at which the content of the moving image included in the video signal transmitted by the transmitter 5 is switched.

[0043] The transmitting device 5 is, for example, a game machine. In this case, the transmitting device 5, which is a game machine, transmits a change command when switching from a normal video signal to a video signal in which a delay in the user's response to the progression of the moving image is determined to have a relatively large impact on the progress of the game (for example, a video signal for a fighting game, etc.).

[0044] The display device 10 is a device that displays, as a moving image, the video signal transmitted by the transmission device 5. The display device 10 has a processing device 10A that performs video processing on the video signal transmitted by the transmission device 5.

[0045] The processing device 10A is a video signal processing device that suppresses muting of a video signal during a video processing switching period. The processing device 10A performs video processing on a video signal and displays the processed video signal as an image on the display 16. The processing device 10A can change the video processing to be performed on the video signal, and the period during which the change is made is also referred to as a change period.

[0046] [2 Configuration of Display Device 10] The display device 10 includes a receiving interface 11, a processor 12, a video processing circuit 13, a synthesis circuit 14A, a display 16, a capture circuit 17, memories 18 and 20, an audio processing circuit 21, and a speaker 22.

[0047] The synthesis circuit 14A is configured to include, for example, a mute circuit 14, an adder circuit 15, and a readout circuit 19 as shown in FIG.

[0048] The processing device 10A corresponds to the part of the components of the display device 10 that includes the receiving interface 11, the processor 12, the video processing circuit 13, the mute circuit 14, the addition circuit 15, the capture circuit 17, the memories 18 and 20, the readout circuit 19, and the audio processing circuit 21.

[0049] Of the components of the display device 10, some or all of the processor 12, video processing circuit 13, mute circuit 14, adder circuit 15, capture circuit 17, readout circuit 19, and audio processing circuit 21 may be configured as a single-chip LSI (Large Scale Integration) or the like.

[0050] [2-1 Receiving Interface 11] The receiving interface 11 is an interface device that receives a video signal representing a moving image transmitted by the transmitting device 5. The video signal representing a moving image is a signal in which a plurality of still images (also called frames) that make up the moving image are arranged in the time direction. The receiving interface 11 provides the received video signal to the video processing circuit 13. Note that the components included in the display device 10 process the video signal on a frame-by-frame basis.

[0051] When the transmitting device 5 transmits an audio signal, the receiving interface 11 receives the audio signal transmitted by the transmitting device 5 together with the video signal. The receiving interface 11 provides the received audio signal to the audio processing circuit 21.

[0052] The receiving interface 11 also receives a change command packet transmitted by the transmitting device 5. The change command packet is a command to change the video processing performed by the video processing circuit 13 on the video signal to video processing with lower latency. The transmitting device 5 provides the received change command packet to the processor 12.

[0053] [2-2 Processor 12] The processor 12 is a circuit that controls the circuits included in the display device 10. The processor 12 is, for example, a CPU (Central Processing Unit). The processor 12 is connected to the circuits included as components of the display device 10 via control lines. Note that the control lines connecting the processor 12 and the circuits included as components of the display device 10 are omitted for the sake of convenience of explanation.

[0054] The processor 12 executes a predetermined program to control the circuits included in the display device 10. The program may be stored in the memory 20 or in another storage device. Examples of circuit control performed by the processor 12 are listed and described below.

[0055] (1) Determination of Signal to be Output as Composite Signal The processor 12 determines the output signal to be output as the composite signal by the composite circuit 14A. Specifically, during a first period, the processor 12 controls the composite circuit 14A to output, as the composite signal, a signal (also referred to as a first signal or a main path signal) generated by the video processing circuit 13 performing video processing. The first period is a period not included in the second period described below.

[0056] Furthermore, the processor 12 controls the video processing circuit 13 to change the pattern of video processing applied by the video processing circuit 13 during a period not included in the first period (also referred to as a second period). The period during which the video processing circuit 13 changes the pattern of video processing corresponds to the change period. The change period is included in the second period.

[0057] Then, during the second period, the processor 12 controls the capture circuit 17 to generate a signal (also referred to as a second signal or a sub-path signal) by capturing the video signal, and controls the combining circuit 14A to output the sub-path signal as a combined signal. As described above, within the second period, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so it can be said that during the change period, the processor 12 controls the capture circuit 17 to generate a signal (also referred to as a second signal or a sub-path signal) by capturing the video signal, and controls the combining circuit 14A to output the sub-path signal as a combined signal.

[0058] (2) Identifying Frames to be Played During the Second Period The processor 12 controls the capture circuit 17 to store the subpath signals generated by the capture circuit 17 in the memory 18. In this case, if the time (also referred to as the first time) corresponding to the delay (also referred to as the first delay) caused in the video signal by video processing of a pre-change pattern (also referred to as the first pattern) among the multiple video processing patterns is different from the time (also referred to as the second time) corresponding to the delay (also referred to as the second delay) caused in the video signal by video processing of a post-change pattern (also referred to as the second pattern) among the multiple video processing patterns, the processor 12 controls the combining circuit 14A to read out from the memory 18 and output, during the second period, a subpath signal whose elapsed time since storage in the memory 18 is between the first time and the second time. As described above, the period during the second period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so in the above case, the processor 12 can also be said to control the synthesis circuit 14A to read out and output from memory 18, within the change period, a subpath signal whose elapsed time since being stored in memory 18 is between the first time and the second time.

[0059] At this time, the processor 12 can control the readout circuit 19 so that the elapsed time since the subpath signal that the readout circuit 19 reads from the memory 18 during the change period (in other words, the second period) was stored in the memory 18 changes from the first time to the second time. More specifically, the processor 12 can determine the frame that the readout circuit 19 will read so that the playback speed multiplier when the frame that the readout circuit 19 reads during the second period is equal to the playback speed multiplier P, and control the readout circuit 19 to read the determined frame.

[0060] More specifically, the frames that the processor 12 plays back during the second period are identified as follows.

[0061] First, the processor 12 uses the first delay Dpre, the second delay Dpost, and the time Tc required for the setting change to calculate the time Td from when the synthesis circuit 14A starts to output the subpath signal to when it finishes (in other words, the time during which the synthesis circuit 14A outputs the subpath signal) using the following (Equation 1).

[0062] Td=Tc+Dpost (Formula 1)

[0063] The time Td is the time during which the synthesis circuit 14A outputs the sub-path signal in the case where no upper or lower limit is set for the playback speed multiplier P, which will be described later.

[0064] Then, the processor 12 calculates the playback speed magnification P of the video signal in the second period (also simply referred to as magnification) using the time Td according to the following (Equation 2).

[0065] P=1+(Dpre-Dpost) / Td (Formula 2)

[0066] Then, the processor 12 identifies the number Fr(n) of the nth (where n≧1) frame of the subpath signal that the readout circuit 19 reads from the memory 18 during the second period using the following (Equation 3): In (Equation 3), ROUND() is a function that rounds off the value in parentheses, and F0 is the number of the frame output by the adder circuit 15 immediately before the second period.

[0067] Fr(n)=F0+ROUND(P×n) (Formula 3)

[0068] If an upper or lower limit value is set for the playback speed multiplier P, the processor 12 can recalculate the playback speed multiplier P as follows.

[0069] That is, if the playback speed multiplier P calculated by (Equation 2) exceeds the upper limit value Pmax, the playback speed multiplier P is set to the upper limit value Pmax, and the time Td is calculated by the following (Equation 4). The time Td is the time from when the output of the sub-path signal starts to when it ends.

[0070] Td=(Dpre-Dpost) / (Pmax-1) (Formula 4)

[0071] By using the time Td shown in (Equation 4), it is possible to reduce the discomfort that the user may experience. The time Td calculated by (Equation 1) above is the minimum necessary time calculated from the time Tc required for the change process and the delay Dpost after the change. If the playback speed multiplier P calculated from this time Td becomes too high (for example, the playback speed multiplier P exceeds Pmax), a time Td longer than the time Td calculated by (Equation 1) can be obtained by calculating the time Td so as to suppress the playback speed multiplier P to Pmax as in (Equation 4) above. Using the time Td calculated in this way has the effect of preventing the playback speed from increasing excessively, although it takes some time before the playback speed can be switched back to the main path.

[0072] Furthermore, if the playback speed multiplier P calculated by (Equation 2) is below the lower limit value Pmin, the playback speed multiplier P is set to the lower limit value Pmin, and the time Td is calculated by the following (Equation 5). As above, the time Td is the time from when the output of the sub-path signal starts to when it ends.

[0073] Td=(Dpre-Dpost) / (Pmin-1) (Formula 5)

[0074] By using the time Td shown in (Equation 5), it is possible to reduce the discomfort that the user may feel, similar to the above.

[0075] For example, the upper limit value Pmax can be set to about 1.1 to 1.2, and the lower limit value Pmin can be set to about 0.8 to 0.9.

[0076] Furthermore, when there is a constraint that the length of the second period must be a predetermined fixed time Tf, the upper limit value Pmax and the lower limit value Pmin shown in the following (Equation 6) and (Equation 7) can be used. Here, Dmax is the maximum difference between the delay Dpre of the pre-change video processing and the delay Dpost of the post-change video processing, when various combinations of the pre-change video processing and the post-change video processing are taken into consideration. The time Tf can be, for example, about 1 second.

[0077] Pmax=1+Dmax / Tf (Formula 6) Pmin=1−Dmax / Tf (Formula 7)

[0078] (3) Changing the Setting of the Video Processing Pattern The processor 12 changes the setting of the video processing pattern that the video processing circuit 13 applies to the video signal. Specifically, when the receiving interface 11 receives a change command packet, the processor 12 controls the video processing circuit 13 to change the video processing that the video processing circuit 13 applies to the video signal to lower-latency video processing or higher-latency video processing. Here, an example will be described in which the processor 12 controls the video processing circuit 13 to change the video processing that the video processing circuit 13 applies to the video signal to lower-latency video processing when the receiving interface 11 receives a change command packet.

[0079] Furthermore, the processor 12 can control the adder circuit 15 to generate and output a frame having pixel values ​​obtained by mixing pixel values ​​included in a frame of the main path signal and pixel values ​​included in a frame of the sub path signal immediately before or after the second period. The generation of a composite signal by mixing pixel values ​​will be described in the following modified example.

[0080] (4) Muting of the Main Path Signal The processor 12 controls the muting circuit 14 so that the muting circuit 14 mutes the main path signal during the second period.

[0081] [2-3 Video Processing Circuit 13] The video processing circuit 13 performs video processing on the video signal received by the receiving interface 11. The video processing circuit 13 provides the processed video signal to the mute circuit 14. The video processing performed by the video processing circuit 13 on the video signal will be described in detail later.

[0082] Specifically, the video processing circuit 13 generates a first signal (corresponding to a main path signal) by applying one of a plurality of patterns of video processing that the video processing circuit 13 can apply to the video signal received by the receiving interface 11. The one pattern of video processing that the video processing circuit 13 applies to the video signal can be set by the processor 12.

[0083] When the reception interface 11 receives the change command packet, the video processing circuit 13 changes the video processing to be performed by the video processing circuit 13 to video processing with lower delay under the control of the processor 12 .

[0084] [2-4 Combining Circuit 14A] The combining circuit 14A outputs a combined signal obtained by combining the main path signal and the sub path signal. Specifically, the combining circuit 14A generates a combined signal by combining the main path signal provided by the video processing circuit 13 with the sub path signal read out from the memory 18. The combining circuit 14A then provides the generated combined signal to the display 16.

[0085] The combining circuit 14A outputs a main path signal in a first period under the control of the processor 12. The combining circuit 14A also outputs a sub path signal in a second period under the control of the processor 12. Since the second period includes a modification period, it can also be said that the combining circuit 14A outputs a sub path signal in the modification period.

[0086] As an example, the synthesis circuit 14A is configured to include a mute circuit 14, an adder circuit 15, and a readout circuit 19 as shown in FIG. 1, and this case will be described as an example here.

[0087] When the combining circuit 14A outputs a main path signal, the muting circuit 14, the adding circuit 15 and the reading circuit 19 operate as follows.

[0088] The muting circuit 14 outputs the main path signal without muting it.

[0089] The read circuit 19 does not read out the subpath signal.

[0090] The adder circuit 15 outputs the main path signal as a composite signal (the opacity r of the sub path signal, which will be described later, is set to 0).

[0091] When the combining circuit 14A outputs a subpath signal, the muting circuit 14, the adding circuit 15 and the reading circuit 19 operate as follows.

[0092] The mute circuit 14 mutes the main path signal.

[0093] The read circuit 19 reads out the subpath signals.

[0094] The adder circuit 15 outputs the subpath signal as a composite signal (the opacity r of the subpath signal, which will be described later, is set to 1).

[0095] As another example of the configuration of the combining circuit 14A, the combining circuit 14A may be configured to include a memory and a readout circuit instead of the mute circuit 14. In this case, the video signal provided from the video processing circuit 13 is stored in the memory 18, and the readout circuit reads out the video signal stored in the memory and provides it to the adding circuit 15.

[0096] [2-5 Mute Circuit 14] Under the control of the processor 12, the mute circuit 14 switches whether to mute the main path signal input to the mute circuit 14. When the mute circuit 14 does not mute the input main path signal, it outputs the input main path signal as is. When the mute circuit 14 mutes the input main path signal, it outputs a video signal in which all pixels are black as the main path signal.

[0097] The mute circuit 14 mutes the main path signal during the second period under the control of the processor 12, thereby providing a video signal in which all pixels are black as a main path signal to the adder circuit 15. As described above, within the second period, the period in which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so it can be said that the mute circuit 14 mutes the main path signal during the change period under the control of the processor 12, thereby providing a video signal in which all pixels are black as a main path signal to the adder circuit 15.

[0098] The mute circuit 14 is not essential to the display device 10. If the display device 10 does not include the mute circuit 14, the video processing circuit 13 is connected to the adder circuit 15. By setting the opacity r of the sub-path signal (more specifically, the OSD signal) to 1 in the adder circuit 15 (described later), the main-path signal and the sub-path signal can be combined in the same way as when the mute circuit 14 mutes the main-path signal.

[0099] [2-6 Addition Circuit 15] The addition circuit 15 outputs a composite signal obtained by combining the main path signal and the sub path signal. Specifically, the addition circuit 15 generates a composite signal by combining the main path signal provided by the mute circuit 14 and the sub path signal provided by the readout circuit 19. The addition circuit 15 then provides the generated composite signal to the display 16.

[0100] Under the control of processor 12, when a first time corresponding to a first delay caused in a video signal by video processing of a first pattern and a second time corresponding to a second delay caused in a video signal by video processing of a second pattern are different, adder circuit 15 outputs, within a second period, a subpath signal whose elapsed time since storage in memory 18 is the length of time between the first time and the second time. As described above, within the second period, the period during which video processing circuit 13 changes the video processing pattern corresponds to the change period, and therefore, in the above case, adder circuit 15 can also be said to output, within the change period, a subpath signal whose elapsed time since storage in memory 18 is the length of time between the first time and the second time.

[0101] The subpath signal output by the adder circuit 15 is a subpath signal that is stored in the memory 18 and read out from the memory 18 by the read circuit 19 .

[0102] Furthermore, the time that has elapsed since the subpath signal that is output by the adder circuit 15 within the second period was stored in the memory 18 is controlled by the processor 12 so as to change from the first time to the second time. As described above, within the second period, the period during which the video processing circuit 13 is changing the video processing pattern corresponds to the change period, so it can be said that the time that has elapsed since the subpath signal that is output by the adder circuit 15 within the change period was stored in the memory 18 is controlled by the processor 12 so as to change from the first time to the second time.

[0103] This is based on the fact that the read circuit 19 reads the subpath signals from the memory 18 in such a way that the elapsed time since the subpath signals that the read circuit 19 reads from the memory 18 within the second period change from the first time to the second time.

[0104] The adder circuit 15 can generate and output a composite signal that mixes pixel values ​​included in the main path signal and pixel values ​​included in the sub path signal immediately before or immediately after the second period under the control of the processor 12. As described above, within the second period, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so it can also be said that the adder circuit 15 can generate and output a composite signal that mixes pixel values ​​included in the main path signal and pixel values ​​included in the sub path signal immediately before or immediately after the change period.

[0105] The adder circuit 15 can be realized by an OSD (On-Screen Display) synthesizing circuit. In this case, the OSD synthesizing circuit, which is the adder circuit 15, synthesizes the sub-path signal as an OSD (On-Screen Display) signal with the main-path signal. An OSD synthesizing circuit is generally a circuit that superimposes a signal (also called an OSD signal) indicating an image such as a channel number or volume on a video signal to be displayed. When the OSD signal is superimposed on the video signal, the opacity of the OSD signal can be controlled within a range of 0% to 100%.

[0106] In the display device 10, the main path signal is used as the "video signal to be displayed" and the sub path signal is used as the OSD signal, so that the OSD synthesis circuit functions as the adder circuit 15. The pixel value D included in the frame of the synthesis signal output by the adder circuit 15 is a pixel value obtained by mixing the pixel value Sm included in the frame of the main path signal and the pixel value Ss included in the frame of the sub path signal according to the following (Equation 8). In (Equation 8), r is the opacity of the OSD signal. The pixel value D can also be said to be a weighted average, with the weight of the pixel value Sm being (1-r) and the weight of the pixel value Ss being r.

[0107] D=Sm×(1-r)+Ss×r (Formula 8)

[0108] For example, if the opacity of the sub-path signal, which is an OSD signal, is 0%, the composite signal output by the adder circuit 15 will be the same as the main-path signal. This corresponds to the following (Equation 9) when r=0 in (Equation 8).

[0109] D=Sm (Formula 9)

[0110] Furthermore, for example, if the opacity of the subpath signal, which is an OSD signal, is 100%, the composite signal output by the adder circuit 15 will be the same as the subpath signal. This corresponds to the fact that, when r=1 in (Equation 8), the following (Equation 10) is obtained.

[0111] D=Ss (Formula 10)

[0112] Furthermore, for example, if the opacity of the Subpath signal, which is an OSD signal, is 50%, the pixel value of the frame of the composite signal output by the adder circuit 15 is the average value of the pixel values ​​contained in the frame of the Mainpath signal and the pixel values ​​contained in the frame of the Subpath signal. This corresponds to the following (Equation 11) when r = 0.5 in (Equation 8).

[0113] D=0.5×Sm+0.5×Ss (Formula 11)

[0114] [2-7 Display 16] The display 16 displays the composite signal provided from the addition circuit 15 as an image. The display 16 may be, for example, a liquid crystal panel or an organic electroluminescence (EL) panel. It is expected that the image displayed by the display 16 will be viewed by a user.

[0115] [2-8 Capture Circuit 17] The capture circuit 17 generates a subpath signal by capturing a video signal received by the receiving interface 11. The capture circuit 17 stores the generated subpath signal in the memory 18. Under the control of the processor 12, the capture circuit 17 stores the generated subpath signal in the memory 18.

[0116] [2-9 Memory 18] Memory 18 is a storage device capable of storing video signals. Memory 18 may be a volatile storage device such as a dynamic random access memory (DRAM), or a non-volatile storage device such as a hard disk drive (HDD) or a solid state drive (SSD). The subpath signals generated by capture circuit 17 are stored in memory 18 by capture circuit 17, and the stored subpath signals are read out by read circuit 19.

[0117] [2-10 Read Circuit 19] The read circuit 19 reads out the subpath signals stored in the memory 18. The read circuit 19 provides the read out subpath signals to the adder circuit 15.

[0118] Under the control of the processor 12, the readout circuit 19 sequentially reads out frames determined by the processor 12 as frames to be read out by the readout circuit 19.

[0119] Under the control of processor 12, when a first time corresponding to a first delay caused in a video signal by video processing of a first pattern and a second time corresponding to a second delay caused in a video signal by video processing of a second pattern are different, readout circuit 19 can read from memory 18, within the second period, a subpath signal whose elapsed time since storage in memory 18 is between the first and second times, and provide the subpath signal to adder circuit 15. As described above, within the second period, the period during which video processing circuit 13 changes the video processing pattern corresponds to the change period. Therefore, in the above case, it can also be said that readout circuit 19 can read from memory 18, within the change period, a subpath signal whose elapsed time since storage in memory 18 is between the first and second times, and provide the subpath signal to adder circuit 15.

[0120] Furthermore, under the control of the processor 12, the readout circuit 19 can read the subpath signals from the memory 18 during the second period so that the time that has elapsed since the subpath signals were stored in the memory 18 changes from the first time to the second time. As described above, within the second period, the period during which the video processing circuit 13 is changing the video processing pattern corresponds to the change period. Therefore, it can be said that the readout circuit 19 can read the subpath signals from the memory 18 during the change period so that the time that has elapsed since the subpath signals were stored in the memory 18 changes from the first time to the second time.

[0121] The number specifying the frame that the readout circuit 19 reads out from the memory 18 is calculated using the above (Equation 3). When the readout circuit 19 does not read out a frame, the readout circuit 19 does not provide anything to the adder circuit 15. In this case, the readout circuit 19 may provide an image in which all pixels are black to the adder circuit 15.

[0122] The readout circuit 19 may also perform video decompression processing on the readout frames. This is on the assumption that the capture circuit 17 has performed video compression processing on the frames before storing them in the memory 18. By doing so, the amount of video signal data stored in the memory 18 can be reduced, and therefore the capacity of the memory 18 can be reduced.

[0123] The read circuit 19 may be included in the adder circuit 15 as one function of the adder circuit 15. In other words, the adder circuit 15 may read out the subpath signals stored in the memory 18.

[0124] [2-11 Memory 20] The memory 20 is a storage device that can store various types of information. The memory 20 is a non-volatile storage device, and may be, for example, a flash memory. The memory 20 stores programs read by the processor 12, information indicating video processing patterns (see FIG. 2), and information indicating the time required to change the video processing settings (see FIG. 3).

[0125] [2-12 Audio Processing Circuit 21] The audio processing circuit 21 performs audio processing on the audio signal received by the receiving interface 11. The audio processing circuit 21 provides the processed audio signal to the speaker 22.

[0126] The audio processing circuit 21 may include a buffer (not shown). In this case, the audio processing circuit 21 temporarily stores the audio signal in the buffer, thereby adjusting the timing at which the processed audio signal is provided to the speaker 22.

[0127] Specifically, the audio processing circuit 21 determines the number Sr(n) of the nth audio signal to be read from the buffer during the second period using the following equation (12): In equation (12), S0 is the number of the audio signal output by the audio processing circuit 21 immediately before the second period.

[0128] Sr(n)=S0+ROUND(P×n) (Formula 12)

[0129] The audio signal output from the audio processing circuit 21 to the speaker 22 during the second period may be an audio signal having a timestamp T shown in the following (Equation 13): In (Equation 13), Tn is the elapsed time from the start of playback of the audio signal, and Tpast is the elapsed time from the start of the second period to the current time.

[0130] T = Tn + Dpre + Tpast × P (Equation 13)

[0131] It is assumed that a timestamp is previously assigned to the audio signal received by the receiving interface 11. For example, if the video signal standard is MPEG2-TS, a PTS (Presentation Time Stamp) can be used as the timestamp.

[0132] [2-13 Speaker 22] The speaker 22 outputs, as sound, the audio signal provided from the audio processing circuit 21. It is assumed that the sound output by the speaker 22 is listened to by the user.

[0133] [3. Video Processing] The video processing that the video processing circuit 13 applies to the video signal will be described in detail with reference to FIG.

[0134] FIG. 2 is an explanatory diagram showing a pattern table showing a plurality of video processing patterns in this embodiment.

[0135] The pattern table shown in Fig. 2 shows a plurality of video processing patterns, each associated with a type of video processing and a delay. The pattern table shown in Fig. 2 is stored in, for example, the memory 20, and can be read and used by the processor 12 as needed.

[0136] The video processing patterns are patterns of video processing that can be applied to a video signal by the video processing circuit 13. Each pattern indicates whether or not the video processing that the video processing circuit 13 can apply to a video signal is applied to the video signal.

[0137] Specifically, the pattern table indicates whether the video processing circuit 13 applies video processing to the video signal in the pattern (denoted as "ON") or not (denoted as "OFF").

[0138] FIG. 2 shows high-quality image processing (denoted as "high quality") as an example of image processing that the image processing circuit 13 can perform on the image signal.

[0139] The video processing circuit 13 generally includes a plurality of types of video processing means for improving the quality of the video image, such as noise reduction, sharpness correction, gradation correction, and gamma correction.

[0140] In the video processing of pattern 1 shown in Fig. 2 (i.e., video processing in which high-quality video processing is turned off), by not applying some of the multiple types of video processing means to the video signal, the time required for video processing is shorter than when all of the multiple types of video processing means are applied to the video signal. In this way, low-delay video processing is achieved.

[0141] On the other hand, in the image processing of pattern 2 shown in Fig. 2 (i.e., image processing in which high-quality image processing is on), image processing using all of the above image processing means is performed on the image signal, thereby realizing high-quality image processing.

[0142] The video processing that the video processing circuit 13 can perform on the video signal is not limited to high-quality video processing, and may include other video processing.

[0143] Low-latency video processing may be video processing for games, in other words, video processing designed specifically for gameplay, and is sometimes commonly referred to as a "game mode," etc. On the other hand, high-quality video processing may be video processing for applications that do not require low latency.

[0144] The "delay" column indicates the delay that occurs in the video signal when the video processing circuit 13 applies the video processing pattern to the video signal. The delay is expressed in units of time, for example, but is not limited to this and may be expressed in units of frames. A delay expressed in units of time and a delay expressed in units of frames can be mutually converted by multiplication or division using the frame rate (fps) of the video signal. Specifically, a delay expressed in units of frames is calculated by multiplying a delay expressed in units of time by the frame rate. Conversely, a delay expressed in units of time is calculated by dividing a delay expressed in units of frames by the frame rate.

[0145] 2, pattern 1 is a video processing pattern in which high-quality video processing is not applied to the video signal (off). Pattern 1 is a video processing pattern in which video processing with lower delay is applied than when high-quality video processing is applied (pattern 2). The delay caused in the video signal when video processing circuit 13 applies pattern 1 video processing is D1.

[0146] Pattern 2 is a video processing pattern in which high-quality video processing is performed (ON) on the video signal. Pattern 2 is a video processing pattern in which video processing with a higher delay is performed than when low-delay video processing is performed (in the case of pattern 1). The delay caused in the video signal when video processing circuit 13 performs video processing of pattern 2 is D2, which is greater than D1.

[0147] 3 is an explanatory diagram showing a time table indicating the time Tc required to change the video processing settings in this embodiment. The time table shown in FIG. 3 is stored in, for example, the memory 20, and can be read and used by the processor 12 as needed.

[0148] 3, the time Tc required for changing the settings is associated with each type of video processing. The time required for changing the settings is the time required to set the video processing of that type as the video processing to be performed by the video processing circuit 13.

[0149] FIG. 3 shows that the time required for setting the video processing circuit 13 to perform low-latency video processing is T1, and the time required for setting the video processing circuit 13 to perform high-quality video processing is T2.

[0150] [4. Combining Process] The combining process performed by the adder circuit 15 on the main path signal and the subpath signal will be described in detail with reference to FIGS.

[0151] FIG. 4 is a first explanatory diagram showing the synthesis process by the adder circuit 15 in this embodiment.

[0152] FIG. 4 shows the concept of the synthesis process when the adder circuit 15 outputs the main path signal as the synthesis signal.

[0153] The adder circuit 15 combines the subpath signal with the mainpath signal with an opacity of 0% (see (a) in FIG. 4). In this case, r=0 in (Equation 8), and the pixel value D included in the frame of the combined signal is equal to the pixel value Sm included in the frame of the mainpath signal (see (Equation 9)).

[0154] For example, if the main path signal contains a character image of "A" and the sub path signal contains a character image of "B," the combined signal will contain the character image of "A" (see FIG. 4(b)).

[0155] FIG. 5 is a second explanatory diagram showing the synthesis process by the adder circuit 15 in this embodiment.

[0156] FIG. 5 shows the concept of the combining process when the adder circuit 15 outputs a subpath signal as a combined signal.

[0157] The adder circuit 15 combines the subpath signal with the mainpath signal with an opacity of 100% (see (a) of FIG. 5). In this case, r=1 in (Equation 8), and the pixel value D included in the frame of the combined signal is equal to the pixel value Ss included in the frame of the subpath signal (see (Equation 10)).

[0158] For example, if the main path signal contains a character image of "A" and the sub path signal contains a character image of "B," the combined signal will contain the character image of "B" (see FIG. 5(b)).

[0159] FIG. 6 is a third explanatory diagram showing the synthesis process by the adder circuit 15 in this embodiment.

[0160] FIG. 6 shows the concept of the synthesis process in which the adder circuit 15 outputs a frame having pixel values ​​that are a mixture of pixel values ​​contained in a frame of the main path signal and pixel values ​​contained in a frame of the sub path signal as a synthesized signal.

[0161] The adder circuit 15 combines the sub-path signal with the main-path signal at an opacity of 50% (see (a) in FIG. 6). In this case, by setting r=0.5 in (Equation 8), the pixel value D included in the frame of the combined signal becomes the average value of the pixel value Sm included in the frame of the main-path signal and the pixel value Ss included in the frame of the sub-path signal (see (Equation 11)).

[0162] For example, if the main path signal contains a character image of "A" and the sub path signal contains a character image of "B," the composite signal will contain an image in which the character image of "A" and the character image of "B" are superimposed (see (b) of Figure 6).

[0163] [5. Processing] The processing of the system 1 configured as above will be described.

[0164] FIG. 7 is a flowchart showing the processing of the processor 12 when changing the video processing in this embodiment.

[0165] In step S101, the processor 12 determines whether the receiving interface 11 has received a change command packet. If it is determined that the receiving interface 11 has received a change command packet (Yes in step S101), the processor 12 proceeds to step S102. If not (No in step S101), the processor 12 executes step S101 again. In other words, the processor 12 waits in step S101 until the receiving interface 11 receives a change command packet.

[0166] In step S102, the processor 12 calculates a reproduction speed multiplier P for the subpath signal. The reproduction speed multiplier P for the subpath signal calculated by the processor 12 is used in step S105, which will be described later.

[0167] In step S103, the processor 12 controls the capture circuit 17 to start capturing the received signal and storing the captured received signal in the memory 18. The capture circuit 17 starts capturing the received signal and storing the captured received signal in the memory 18 under the control of the processor 12.

[0168] In step S104, the processor 12 waits for a time period corresponding to the delay Dpre. During this waiting time, the capture circuit 17 captures a number of frames corresponding to the delay Dpre and stores them in the memory 18.

[0169] In step S105, the processor 12 controls the read circuit 19 to change the playback speed multiplier P of the subpath signal. The read circuit 19 changes the playback speed multiplier P of the subpath signal under the control of the processor 12. Changing the playback speed multiplier P of the subpath signal by the read circuit 19 means that the read circuit 19 starts sequentially determining frames to read so that the playback speed multiplier when the frames read by the read circuit 19 are played back will be the playback speed multiplier P calculated in step S102.

[0170] In step S106, the processor 12 controls the read circuit 19 to start reading out the frames stored in the memory 18 as subpath signals. Under the control of the processor 12, the read circuit 19 starts reading out the frames determined in step S105 from the frames stored in the memory 18 as subpath signals. The read circuit 19 provides the read out subpath signals to the adder circuit 15.

[0171] In step S106A, the processor 12 controls the summing circuit 15 to start outputting the subpath signals as a combined signal. The summing circuit 15, under the control of the processor 12, starts outputting the subpath signals as a combined signal.

[0172] In step S107, the processor 12 controls the muting circuit 14 to start muting the main path signal. The muting circuit 14 starts muting the main path signal (i.e., the signal output by the video processing circuit 13) under the control of the processor 12.

[0173] Steps S105, S106, S106A and S107 may be performed in any order as long as they are performed between immediately after the completion of the waiting period in step S104 and the time when the adder circuit 15 actually outputs the subpath signal as a combined signal (time t7 in the specific example described below).

[0174] In step S108, the processor 12 changes the settings of the video processing circuit 13. The time required to change the settings of the video processing circuit 13 is as shown in FIG.

[0175] In step S109, the processor 12 controls the muting circuit 14 to stop muting the main path signal. The muting circuit 14 stops muting the main path signal (i.e., the signal output by the video processing circuit 13) under the control of the processor 12. The muting of the main path signal is stopped after waiting for a time Td from the start of the setting change of the video processing circuit 13 (step S108).

[0176] In step S110, the processor 12 controls the adder circuit 15 to start outputting the main path signal as a composite signal. Under the control of the processor 12, the adder circuit 15 starts outputting the main path signal (i.e., the signal output by the mute circuit 14) as a composite signal.

[0177] In step S111, the processor 12 controls the capture circuit 17 to stop capturing the received signal. The capture circuit 17 stops capturing the received signal under the control of the processor 12. The processor 12 also controls the read circuit 19 to stop reading out the frames stored in the memory 18. The read circuit 19 stops reading out the frames stored in the memory 18 under the control of the processor 12.

[0178] Steps S109, S110, and S111 may be performed in any order as long as they are performed between immediately after the setting change in step S108 is completed and the time when the adder circuit 15 actually outputs the main path signal as a combined signal (time t11 in the specific example described later).

[0179] By the series of processes shown in FIG. 7, the display device 10 can suppress muting of the video signal during the video processing switching period.

[0180] An example of the processing performed by the system 1 will be described using a specific example of a video signal.

[0181] FIG. 8 is an explanatory diagram showing an example of processing by the display device 10 in this embodiment.

[0182] Fig. 8 shows an example of processing by display device 10 when video processing circuit 13 changes the setting from a state in which it is performing video processing of pattern 2 on a video signal to a state in which it is performing video processing of pattern 1. The processing shown in Fig. 8 is, for example, a series of processes shown in the flowchart of Fig. 7, which are executed by display device 10 using a pattern table (see Fig. 2) and a time table (see Fig. 3).

[0183] 8 shows, from top to bottom, frames received by the receiving interface 11, frames output by the video processing circuit 13, frames output by the mute circuit 14, frames captured by the capture circuit 17, frames read by the readout circuit 19, and frames output by the adder circuit 15. In FIG. 8, the right direction indicates the direction of time passage.

[0184] Here, the delays Dpre and Dpost are expressed in units of frames. That is, the delay Dpre is the delay D1 of pattern 1, specifically 3 frames. The delay Dpost is the delay D2 of pattern 2, specifically 1 frame.

[0185] Furthermore, it is assumed that the time Tc required to change the settings is a time equivalent to 3 frames (i.e., 3 / frame rate). The time Td is calculated as a time equivalent to 4 frames using the above (Equation 1) as follows:

[0186] Td = 3 + 1 = 4

[0187] Further, the playback speed multiplier P is calculated as 1.5 using the above (Equation 2) as follows:

[0188] P=1+(3-1) / 4=1.5

[0189] Furthermore, each frame of the video signal is assigned a sequential number (..., -2, -1, 0, 1, 2, ...). The sequential number assigned to each frame of the video signal indicates the playback order of the frame or the reception order of the receiving interface 11, and has no other meaning.

[0190] At time t0 shown in Figure 8, the receiving interface 11 receives frame #0. Because the delay Dpre is 3, the video processing circuit 13 outputs frame #-3 at time t0. The muting circuit 14 acquires frame #-3 output by the video processing circuit 13 and outputs the acquired frame #-3 as is without muting it. The frame output by the adding circuit 15 at time t0 is frame #-3, the same as the frame that is the main path signal output by the muting circuit 14. Note that at time t0, the capture circuit 17 and readout circuit 19 are not operating and therefore do not output anything.

[0191] When the receiving interface 11 receives the change command packet at time t3 (Yes in step S101), the capture circuit 17 starts capturing the received signal and storing it in the memory 18 at time t4 (step S103). The frames stored in the memory 18 are frames #4, #5, and #6.

[0192] Then, after waiting for a time equivalent to the delay Dpre (step S104), at time t7, the display device 10 performs a process of switching the signal output by the adder circuit 15 from the main path signal to the sub path signal.

[0193] Specifically, the processor 12 sets the playback speed multiplier for the subpath signal (step S105), the readout circuit 19 starts reading frames from the memory 18 and providing them to the adder circuit 15 under the control of the processor 12 (step S106), and the adder circuit 15 starts outputting the subpath signal as a composite signal under the control of the processor 12 (step S106A). At this time, the processor 12 sets the opacity r of the OSD signal for the adder circuit 15 to 1, allowing the adder circuit 15 to output the frame of the subpath signal as a composite signal. The frame output by the adder circuit 15 is the subpath signal provided by the readout circuit 19, and is frame #5. At time t7, the mute circuit 14 starts muting under the control of the processor 12 (step S107).

[0194] The fact that the frame output by the adder circuit 15 is frame #5 can be derived as follows using the above (Equation 3).

[0195] In the above (Equation 3), the frame output by the adder circuit 15 immediately before the second period is frame #3, so F0 = 3. Furthermore, the frame read out from the memory 18 by the readout circuit 19 at time t7 is the first frame in the second period, so n = 1. As a result, the frame Fr(1) read out from the memory 18 by the readout circuit 19 at time t7 is calculated to be frame #5 as follows:

[0196] Fr(1)=3+ROUND(1.5×1)=5

[0197] Thereafter, after the mute circuit 14 starts muting under the control of the processor 12, the processor 12 instructs the video processing circuit 13 to change the setting (step S108). The video processing circuit 13 changes the setting under the control of the processor 12 during the time Tc.

[0198] During the second period (times t7 to t11), from time t8 onwards, the read circuit 19 reads frames #6, #8 and #9 from the memory 18 in accordance with the playback speed multiplier P and provides them to the adder circuit 15, which then outputs the frames.

[0199] The fact that the frames output by the adder circuit 15 are frames #6, #8, and #9 can be derived using the above (Equation 3) as follows:

[0200] In the above (Equation 3), the frames read out by the readout circuit 19 from the memory 18 at times t8, t9, and t10 are the second, third, and fourth frames in the second period. As a result, frames Fr(2), Fr(3), and Fr(4) read out by the readout circuit 19 from the memory 18 at times t8, t9, and t10, respectively, are calculated as frames #6, #8, and #9 as follows:

[0201] Fr(2)=3+ROUND(1.5×2)=6 Fr(3)=3+ROUND(1.5×3)=8 Fr(4)=3+ROUND(1.5×4)=9

[0202] Thereafter, at time t10, when the time Tc required for changing the settings has elapsed since the muting circuit 14 started muting, the processor 12 instructs the video processing circuit 13 to start video processing after the settings have been changed. Under the control of the processor 12, the video processing circuit 13 starts video processing after the settings have been changed for a frame (specifically, frame #10) at time t10.

[0203] At time t11, the display device 10 performs a process of switching the signal output by the addition circuit 15 from the sub-path signal to the main-path signal.

[0204] Specifically, the muting circuit 14 stops muting under the control of the processor 12 (step S109), and the adding circuit 15 starts outputting frames of the main path signal as a composite signal under the control of the processor 12 (step S110). At this time, the processor 12 sets the opacity r of the OSD signal of the adding circuit 15 to 0, so that the adding circuit 15 can output frames of the main path signal as a composite signal. Also, the reading circuit 19 stops reading frames under the control of the processor 12 (step S111).

[0205] After time t11, the video processing circuit 13 outputs frames (frames #10 and #11) that have been subjected to the changed video processing. As described above, the video processing circuit 13 starts video processing after the setting change at time t10, and since Dpost=1, the video processing circuit 13 completes video processing of frame #10 at time t11 and outputs it.

[0206] As described above, the display device 10 plays back frames at the playback speed multiplier P during the second period, and further outputs a composite signal that is delayed by one frame relative to the received frame after the second period (i.e., after time t11). In this way, the display device 10 can continue to output a video signal even during the video processing switching period, thereby preventing the video signal from being muted.

[0207] (First Modification of the Embodiment) In this modification, a processing device and the like that suppresses muting of a video signal during a switching period of video processing will be described.

[0208] In the above embodiment, the display device 10 (more specifically, the processing device 10A) changed the video processing of the video processing circuit 13 in response to a change command from the transmitting device 5, but it can also change the processing of the video processing circuit 13 even if there is no change command from the transmitting device 5.

[0209] For example, the display device 10 can change the video processing of the video processing circuit 13 when a user instructs the display device 10 to change the video processing using an operation menu provided by the display device 10. For example, the operation menu includes a selection of whether to turn low-latency video processing on or off. It is assumed that the user refers to the provided operation menu and performs an operation on the display device 10 to select whether to turn low-latency video processing on or off. The display device 10 can accept the user's operation and change the processing of the video processing circuit 13 in accordance with the operation. In this case, the processor 12 can execute the processes from step S102 onward when it accepts a user operation using a remote control light receiving unit or a touch panel detection unit instead of receiving a change command packet in step S101 (see FIG. 7 ).

[0210] In this way, the change command in the present invention can be realized by the user operating the operation menu even in a configuration with only the display device 10 (in other words, a configuration without the transmission device 5).

[0211] Furthermore, when the user instructs a change in video processing using the operation menu, the change command may be a command to change to video processing for RGB video signals in addition to a command to change to low-delay video processing.

[0212] Generally, image quality improvement means such as noise reduction, sharpness correction, or gradation correction are image processes for YUV image signals expressed using color difference signals, but the required capacity of memory 18 may be reduced by reducing the UV signal portion, which is color information. In order to prevent such reduction of color information when receiving RGB image signals output by a personal computer or the like, a mode may be provided to bypass image quality improvement means such as noise reduction, sharpness correction, or gradation correction. When a user issues a command using an operation menu to change the image processing to that for RGB image signals, the image quality improvement means are bypassed, which results in a change in the delay time of image processing circuit 13.

[0213] In this case, to prevent the display device 10 from muting the video signal during the video processing switching period, RGB processing may be added to the video processing types in Figures 2 and 3. Specifically, in the pattern table shown in Figure 2, new video processing patterns are added that indicate combinations of on / off states of video processing for RGB video signals and on / off states of high-quality video processing, and a delay Dx is added to each of the added new video processing patterns. Also, in the time table shown in Figure 3, a time T3 is added during which the video signal is changed so that video processing for the RGB video signal is performed.

[0214] In this way, the change command in the present invention also applies to a command that results in a change in the delay time of the video processing circuit 13, and does not necessarily have to be a change command that instructs low-delay video processing.

[0215] (Second Modification of the Embodiment) In this modification, a processing device or the like that suppresses muting of a video signal during a switching period of video processing will be described. The processing device in this modification more appropriately suppresses muting of a video signal during a switching period of video processing by using an adder circuit that generates a composite signal by mixing pixel values.

[0216] The configuration of the display device 10 in this modification is similar to that of the display device 10 in the above embodiment.

[0217] However, the difference from the display device 10 in the above embodiment is that the adder circuit 15 generates and outputs a composite signal by mixing pixel values ​​included in a frame of the main path signal and pixel values ​​included in a frame of the sub path signal immediately before or immediately after the second period. Note that the adder circuit 15 may also generate and output a composite signal by mixing pixel values ​​included in a frame of the main path signal and pixel values ​​included in a frame of the sub path signal both immediately before and immediately after the second period.

[0218] Specifically, the adder circuit 15 can convert the N frames before the second period into a composite signal having pixel values ​​obtained by mixing pixel values ​​included in the frames of the main path signal and pixel values ​​included in the frames of the sub path signal. N is, for example, an integer between 1 and 30, but is not limited thereto. In this case, the opacity r of the sub path signal may be set to a constant value (e.g., 50%) for the N frames. Alternatively, the opacity r may be gradually changed from a relatively low value to a relatively high value for the N frames. For example, if N is 3, the opacity of the first, second, and third frames may be changed to 25%, 50%, and 75%, respectively.

[0219] Furthermore, the adder circuit 15 may convert the M frames after the second period into a composite signal having pixel values ​​obtained by mixing pixel values ​​included in the frames of the main path signal and pixel values ​​included in the frames of the sub-path signal. M is, for example, an integer between 1 and 30, but is not limited thereto. M may be the same as or different from N, the number of frames before the second period. The opacity r of the sub-path signal may be set to a constant value (e.g., 50%) for the M frames. Alternatively, the opacity r may be gradually changed from a relatively high value to a lower value for the M frames. For example, if M is 3, the opacity of the first, second, and third frames may be changed to 75%, 50%, and 25%, respectively.

[0220] Furthermore, the processor 12 uses the following (Equation 14) to identify the number Fr(n) of the nth (where n≧1) frame of the subpath signal that the readout circuit 19 reads from the memory 18 during the second period. (Equation 14) is used in place of (Equation 3). In (Equation 14), N is the number of frames that are output by the adder circuit 15 before the second period and that constitute a composite signal having pixel values ​​obtained by mixing pixel values ​​included in the frame of the mainpath signal and pixel values ​​included in the frame of the subpath signal. The other variables are the same as those in (Equation 3).

[0221] Fr(n)=F0+N+ROUND(P×n) (Formula 14)

[0222] The processing of the display device 10 in this modified example will be described. Here, the case where the number of frames before the second period and the number of frames after the second period are the same, N, will be described as an example. Also, the case where the opacity r for the N frames is set to a constant value of 50% will be described as an example.

[0223] 9 is a flow diagram showing the processing of the processor 12 when changing the video processing in this modified example. In FIG. 9, the same processes as those of the display device 10 in the above embodiment (see FIG. 7) are denoted by the same reference numerals as those in the above embodiment, and detailed descriptions thereof may be omitted.

[0224] When the receiving interface 11 receives the change command packet sent by the transmitting device 5, the processor 12 controls the interface 11 to calculate the playback speed multiplier P of the subpath signal, start capturing the received signal and storing it in the memory 18, and wait for a time equivalent to the delay Dpre (steps S101 to S104).

[0225] In step S104A, the processor 12 controls the adder circuit 15 to output a composite signal obtained by combining N frames of the subpath signal with the mainpath signal at an opacity of 50%.

[0226] Thereafter, the processor 12 starts outputting the subpath signal as a composite signal, and controls the video processing circuit 13 to change its settings, similar to the processor 12 in the above embodiment (steps S105 to S109).

[0227] In step S109A, the processor 12 changes the reproduction speed multiplier P of the sub-path signal to 1 (i.e., 1x speed).

[0228] In step S109B, the processor 12 controls the adder circuit 15 to output a composite signal obtained by combining N frames of the subpath signal with the mainpath signal at an opacity of 50%.

[0229] Thereafter, the processor 12 starts outputting the main path signal as a composite signal, and stops the capture by the capture circuit 17, in the same manner as the processor 12 in the above embodiment (steps S110 to S111).

[0230] By the series of processes shown in FIG. 9, the display device 10 suppresses muting of the video signal during the video processing switching period.

[0231] FIG. 10 is an explanatory diagram showing an example of processing by the display device 10 in a modified example of the present embodiment.

[0232] As with Figure 8, Figure 10 shows an example of the processing of the display device 10 when the setting is changed from a state in which the video processing circuit 13 is performing video processing of pattern 2 on the video signal to a state in which the video processing circuit 13 is performing video processing of pattern 1.

[0233] The frame display mode, delay Dpre, delay Dpost, times Tc and Td, playback speed magnification P, etc. in Fig. 10 are the same as those in Fig. 8. Also, the number N of frames that form a composite signal having pixel values ​​obtained by mixing pixel values ​​contained in frames of the Main Path signal and pixel values ​​contained in frames of the Sub Path signal is set to 1.

[0234] When the receiving interface 11 receives the change command packet at time t3 (Yes in step S101), the capture circuit 17 starts capturing the received signal and storing it in the memory 18 under the control of the processor 12 at time t4 (step S103). The frames stored in the memory 18 are frames #4, #5, and #6.

[0235] After that, after waiting for a time equivalent to the delay Dpre (step S104), the adder circuit 15, under the control of the processor 12, outputs a combined signal (frame #4) by combining one frame of the subpath signal with the mainpath signal from time t7 (step S104A).

[0236] Thereafter, read circuit 19, under the control of processor 12, begins reading frames from memory 18 and provides them to summing circuit 15. The frame output by summing circuit 15 is frame #6 (i.e., the subpath signal) provided by read circuit 19.

[0237] Thereafter, the muting circuit 14 starts muting (step S107), and then the video processing circuit 13 changes the setting (step S108) under the control of the processor 12. The setting change requires Tc (i.e., the time equivalent to three frames).

[0238] During the second period (times t8 to t12), the read circuit 19 reads frames #6, #7, #9 and #10 from the memory 18 in accordance with the playback speed multiplier P and provides them to the adder circuit 15, which outputs the frames.

[0239] The fact that the frames output by the adder circuit 15 are frames #6, #7, #9 and #10 can be derived as follows using the above (Equation 14).

[0240] In the above (Equation 14), the frames read out by the readout circuit 19 from the memory 18 at times t8, t9, t10, and t11 are the first, second, third, and fourth frames in the second period, respectively. Also, N = 1. As a result, the frames Fr(1), Fr(2), Fr(3), and Fr(4) read out by the readout circuit 19 from the memory 18 at times t8, t9, t10, and t11, respectively, are calculated as frames #6, #7, #9, and #10, as follows:

[0241] Fr(1)=3+1+ROUND(1.5×1)=6 Fr(2)=3+1+ROUND(1.5×2)=7 Fr(3)=3+1+ROUND(1.5×3)=9 Fr(4)=3+1+ROUND(1.5×4)=10

[0242] Thereafter, under the control of the processor 12, the adder circuit 15 outputs a combined signal (frame #11) obtained by combining one frame of the subpath signal with the mainpath signal from time t12 (step S109B). After that, the video processing circuit 13 performs the changed video processing on the received frame from time t13 onward, and the adder circuit 15 outputs the processed frame (frame #12).

[0243] At time t12, the muting circuit 14 stops muting under the control of the processor 12 (step S109). At time t13, the capture circuit 17 stops capturing under the control of the processor 12, and the readout circuit 19 stops reading under the control of the processor 12 (step S111).

[0244] As described above, the display device 10 plays back frames at the playback speed multiplier P during the second period, and further outputs a composite signal that is delayed by one frame relative to the received frame after the second period (i.e., after time t12). Furthermore, because the display device 10 outputs a frame having pixel values ​​that are a mixture of pixel values ​​included in the frame of the Main Path signal and pixel values ​​included in the frame of the Sub Path signal before and after the second period as a composite signal, even if the video signal formats of the Main Path signal and the Sub Path signal are different (for example, if the resolution is reduced during capture), a sudden change in image quality when switching the composite signal can be suppressed.

[0245] In this way, the display device 10 can suppress muting of the video signal during the video processing switching period.

[0246] As described above, the embodiments and modifications have been described as examples of the technology in this disclosure, and for that purpose, the accompanying drawings and detailed descriptions have been provided.

[0247] Therefore, the components shown in the accompanying drawings and detailed description may include not only essential components for solving the problem, but also components that are not essential for solving the problem in order to illustrate the above implementation. Therefore, the fact that these non-essential components are shown in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential.

[0248] Furthermore, since the above-described embodiments are intended to illustrate the technology of the present disclosure, various modifications, substitutions, additions, omissions, etc. may be made within the scope of the claims or their equivalents.

[0249] The present disclosure can be used as a video signal processing device that applies video processing selected from a plurality of video processing methods to a video signal and outputs the processed signal.

[0250] REFERENCE SIGNS LIST 1 System 5 Transmitting device 10 Display device 10A Processing device 11 Receiving interface 12 Processor 13 Video processing circuit 14 Mute circuit 14A Combining circuit 15 Adding circuit 16 Display 17 Capture circuit 18, 20 Memory 19 Readout circuit 21 Audio processing circuit 22 Speaker

Claims

1. A video signal processing device comprising: a receiving interface that receives a video signal indicating a moving image; a video processing circuit that generates a first signal by applying one of a plurality of video processing patterns that the video processing circuit can apply to the video signal received by the receiving interface; a capture circuit that generates a second signal by capturing the video signal received by the receiving interface; a synthesis circuit that outputs a synthesis signal by combining the first signal and the second signal; and a processor that (a) controls the synthesis circuit to output the first signal as the synthesis signal during a first period; (b) controls the video processing circuit to change the pattern of the video processing applied by the video processing circuit during a second period that is not included in the first period; and (c) controls the capture circuit to generate the second signal and controls the synthesis circuit to output the second signal as the synthesis signal during the period of change.

2. The video signal processing device according to claim 1, further comprising a memory, wherein the processor controls the capture circuit to store the second signal generated by the capture circuit in the memory, and when a first time corresponding to a first delay caused in the video signal by video processing of a first pattern of the plurality of patterns before the change is different from a second time corresponding to a second delay caused in the video signal by video processing of a second pattern of the plurality of patterns after the change, controls the synthesis circuit to output, within the period of the change, the second signal whose elapsed time since storage in the memory is a time length between the first time and the second time.

3. The video signal processing device according to claim 2, wherein the processor controls the synthesis circuit so that the elapsed time since the second signal output by the synthesis circuit during the change period was stored in the memory changes from the first time to the second time.

4. A video signal processing device as described in any one of claims 1 to 3, wherein the receiving interface receives an instruction to change the video processing applied to the video signal by the video processing circuit to lower latency video processing, and the processor, when the receiving interface receives the instruction, controls in (b) to change the video processing applied to the video signal by the video processing circuit to lower latency video processing.

5. A video signal processing device as claimed in any one of claims 1 to 3, wherein the processor controls the synthesis circuit to generate and output the synthesis signal by mixing pixel values ​​contained in the first signal and pixel values ​​contained in the second signal immediately before or after the change period.

6. A video signal processing device according to any one of claims 1 to 3, wherein the synthesis circuit includes an OSD (On-Screen Display) synthesis circuit that synthesizes the second signal as an OSD signal with the first signal.

7. A video signal processing device as claimed in any one of claims 1 to 3, wherein the synthesis circuit further comprises a mute circuit which switches whether or not the first signal generated by the video processing circuit is muted, and the processor controls the mute circuit so as to mute the first signal during the change period.

8. A video signal processing method executed by a video signal processing device, comprising: a receiving interface that receives a video signal indicating a moving image; a video processing circuit that generates a first signal by applying one of a plurality of patterns of video processing that the video processing circuit can apply to the video signal received by the receiving interface; a capture circuit that generates a second signal by capturing the video signal received by the receiving interface; a synthesis circuit that outputs a synthetic signal by synthesizing the first signal and the second signal; and a processor, wherein the video signal processing method comprises the processor: (a) controlling the synthesis circuit to output the first signal as the synthetic signal during a first period; (b) controlling the video processing circuit to change the pattern of the video processing applied by the video processing circuit during a second period that is not included in the first period; and (c) controlling the capture circuit to generate the second signal and controlling the synthesis circuit to output the second signal as the synthetic signal during the period of change.

9. A program for causing a computer to execute the video signal processing method according to claim 8.

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